A data compression method and system for ssd

Abstract

The application discloses a data compression method and system for an SSD, and relates to the technical field of SSD data compression. The method comprises write IO path processing and read IO path processing. The write IO path processing comprises the following steps: after receiving host data, processing the data in 4K units, judging compressibility, performing compressed storage according to the remaining space of the cache, synchronously updating metadata, and when the data volume of the cache reaches a threshold, allocating NAND space to encode and write data and updating address mapping. The read IO path processing comprises the following steps: receiving a read command, searching for a mapping to obtain a NAND physical address, judging whether data is compressed through metadata after reading and decoding the data, transmitting compressed data and uncompressed data to a cache after decompressing the compressed data, and transmitting the data to a host after passing a PI check. The application effectively avoids the problem that the current compression technology causes an increase in meta data, thereby excessively occupying LDPC parity space, leading to an increase in LDPC code rate and causing a decrease in LDPC error correction capability.

Description

Technical Field

[0001] This invention relates to the field of SSD data compression technology, and specifically to a data compression method and system for SSDs. Background Technology

[0002] Data compression is currently the only SSD technology that has been theoretically and practically proven to reduce the write amplification factor to below 1. SSDs employing data compression can significantly increase their total bytes written (TBW). For example, with a compression ratio of 2:1, the physical space occupied by the same amount of data written to the host is directly halved, while overprovisioning (OP) space can be directly increased by 50% in usable capacity. Compared to incompressible products, the combined benefits of halved write data volume and a 50% increase in OP space can increase TBW by more than 4 times. If the compression ratio is even higher, the lifespan improvement will be even greater, resulting in even greater benefits.

[0003] The current mainstream compression schemes used in the SSD industry primarily involve compressing multiple host units (4K) of data into a single 4K space, and can only handle data written by the host in 4K unit sizes. Simultaneously, an additional 32 bytes are used to record the logical address of the compressed host unit corresponding to this 4K space, such as... Figure 1 As shown, in this scheme, the 32B meta is mainly used to record the logical address of the compressed data unit. Figure 1 The proposed scheme allows a maximum of four compression units (X, Y, Z, M) to be stored in a single 4K space, corresponding to 32 bytes of meta data (recording LAA_x, LAA_y, LAA_z, LAA_m). If a higher compression ratio is desired, and more compression units are desired within the 4K space, such as eight, the corresponding meta data size will double to 64 bytes. The compressed data in the 4K space, along with the meta data and LDPC parity data, constitute an LDPC codeword. These four LDPC codewords are stored together on a single flash page, with the total size not exceeding the flash page size.

[0004] However, existing compression schemes have technical drawbacks in the following aspects:

[0005] 1) The meta tag occupies too much LDPC information bit length (up to 32 bytes), affecting LDPC error correction capabilities. Flash Page Size limits the codeword length (code length) that LDPC can use. Currently, a typical flash page size is 16384 + 2048 bytes, which can hold four 4K LDPC codeword units. Therefore, the code length of each codeword unit cannot exceed (16384 + 2048) / 4 = 4608 bytes. With the same code length, a longer LDPC information bit length leads to a higher code rate and a decrease in error correction capability. Furthermore, in existing data compression schemes, the size and space of the meta data are strongly correlated with the number of compression units stored. To support more compression units, the meta data will be larger, further lengthening the LDPC information bit length and reducing error correction capability. If we consider adding PI information meta data, each compression unit will add an extra 8B of data (8B for NVMe 1.x; 16B for PI in NVMe 2.x). The 8 compression units will add at least 64B of information bits, further compressing the LDPC parity space and further reducing error correction capability, which will seriously affect product reliability.

[0006] 2) It does not support the processing of end-to-end data protection PI information. The meta structure of the current compression technology does not support PI (if it were to support it, the PI information corresponding to multiple compression units would cause the LDPC bit rate to increase sharply, and the LDPC error correction capability would drop to an unacceptable level); there is also no PI-specific processing on the IO path, which cannot support enterprise-level scenarios with higher requirements for data reliability.

[0007] 3) It does not support host writes of data smaller than 4K. Although some hosts and PCIe SSDs can negotiate an LBA unit of 4K, the vast majority of hosts still use a 512B LBA unit. Existing compression solutions require the host to write only in 4K unit sizes, which greatly limits their use cases. Summary of the Invention

[0008] The purpose of this invention is to overcome the shortcomings of the prior art and provide a data compression method and system for SSDs.

[0009] The objective of this invention is achieved through the following technical solution:

[0010] In a first aspect, this application discloses a data compression method for SSDs, including write I / O path processing and read I / O path processing;

[0011] The write I / O path processing includes the following steps:

[0012] S11. Receive data written by the host through the host interface and cache it in the buffer FIFO module. At the same time, calculate the PI information of the data in the buffer FIFO module through the PI module.

[0013] S12. If the data cached in the buffer FIFO module reaches the size of 4K data units, or if data larger than 4K is sliced ​​into 4K data units, then the 4K data units are submitted to the compression module; if the data written by the host is less than 4K, then it is padded with 4K unit sizes.

[0014] S13. The compression module performs a compressibility judgment on the 4K data unit through the compression judgment module, and performs corresponding compression and storage operations based on the judgment result and the remaining space size of the 4K data storage space in the current Data Cache Buffer module.

[0015] S14. When storing compressed data in the 4K storage data space of the Data Cache Buffer module, the compress meta is updated synchronously to record the PI information, LAA information and compressed size information corresponding to the 4K data unit, and the number of compressed units is updated; if the 4K storage data space stores the first compressed data unit, the PI information in the normal meta is updated to 0 to indicate that the 4K storage data space stores compressed data.

[0016] S15. If the amount of data stored in the Data Cache Buffer module reaches the preset threshold, then allocate physical space of the corresponding size of NAND for the data, and write it into NAND after encoding by the LDPC engine; after the data is written, update the mapping relationship between the corresponding data unit and the NAND physical space in the L2P table, so that the corresponding logical address in the L2P table is associated with the NAND physical address where the data is stored.

[0017] The read I / O path processing includes the following steps:

[0018] S21. After the host interface of the SSD receives the read command from the host, it extracts the first logical address of the data from the read command, queries the L2P table according to the first logical address, and obtains the corresponding NAND physical address.

[0019] S22. Read the LDPC codeword of the 4K data corresponding to the NAND physical address through the NAND interface, submit it to LDPC for decoding, and store the data after LDPC decoding into the Data Cache Buffer module, including 4K data and normal meta.

[0020] S23. Check the validity of the PI position information in the normal meta file through the compression module; if the PI position information is valid, determine that the corresponding 4K data is uncompressed data; if the PI position information is invalid, determine that the corresponding 4K data is compressed data.

[0021] S24. If the corresponding 4K data is compressed data, based on the second logical address corresponding to the 4K data, the compression module finds the corresponding compressed data unit from the compress meta and submits it to the compression engine for decompression. The decompressed 4K unit data is then transferred to the Buffer FIFO module, and the corresponding PI information in the compress meta is transferred to the PI module. If the corresponding 4K data is uncompressed data, it is directly transferred to the Buffer FIFO module, and the PI information in the normal meta is transferred to the PI module.

[0022] S25. Verify the matching between the PI information and the data in the buffer FIFO module through the PI module, including verifying the consistency between the data CRC and the logical address and the PI information; after the verification is successful, the host interface transmits the data in the buffer FIFO module to the host; if the data read by the host is within 4K, then identify the offset within 4K of the data according to the 4K offset of the LBA corresponding to the LAA, and then transmit the corresponding data to the host.

[0023] Based on the first aspect, the 4K cell size read filling and padding described in step S12 specifically includes: reading the insufficient data from NAND into the buffer FIFO module, merging it with the host-written data to fill the 4K data cell, and then submitting it to the compression module.

[0024] Based on the first aspect, the specific steps of performing the corresponding compression and storage operations in step S13 include:

[0025] If the 4K unit data is compressible, then the compression engine is used to compress the 4K unit data; if the length after compression is less than the remaining space, then the compressed 4K unit data is stored adjacent to the remaining space; if the length after compression is greater than the remaining space, then the compressed 4K unit data is stored in the new 4K space of the next Data Cache Buffer module.

[0026] If the 4K cell data is not compressible, it will be stored in a new 4K space in the next Data Cache Buffer module.

[0027] Based on the first aspect, the step S24 in which the compression module searches for the corresponding compressed data unit in the compress meta specifically includes: comparing the second logical address with the LAA information recorded in the compress meta, and simultaneously calculating the total size of the compressed 4K data to obtain the offset of the compressed data unit corresponding to the second logical address within 4K.

[0028] Secondly, this application discloses a data compression system for SSDs, employing the aforementioned data compression method for SSDs, including:

[0029] The PI module is used to calculate and verify PI information for the data before compression in the write direction and the data after decompression in the read direction.

[0030] The Buffer FIFO module is used to cache block data from the host in the write direction;

[0031] The compression module includes a compression judgment module and a compression engine. The compression judgment module is used to determine whether the data is compressible, the compression engine compresses the compressible data, and the compressed data is merged in the Data CacheBuffer module.

[0032] The Data Cache Buffer module is used to merge compressed or incompressible data.

[0033] Based on the second aspect, in the Buffer FIFO module, if the block data is less than 4K, or if the beginning and end are not aligned to 4K, then the part of the block data that is less than 4K will be read, padded, and merged.

[0034] Based on the second aspect, the compression module further includes a transmission module for placing the PI information generated by the PI module in the corresponding meta position, including the compress meta structure corresponding to compressible data and the normal meta structure corresponding to incompressible data.

[0035] Based on the second aspect, in the Data Cache Buffer module, if the amount of data written reaches the amount of data that can be programmed in the NAND Flash at one time, the merged data is transmitted to the LDPC engine as LDPC information bits for encoding, and the encoded data is then transmitted to the NAND through the NAND interface.

[0036] The beneficial effects of this invention are:

[0037] 1) The online real-time data compression and decompression method for SSDs proposed in this invention can greatly reduce the write amplification of SSDs and extend the usable lifespan of SSDs to the greatest extent.

[0038] 2) The data compression method of the present invention can solve the problem that the existing SSD compression technology does not support end-to-end data protection PI (protect information) information recording and inspection.

[0039] 3) The data compression technology of the present invention can effectively avoid the problem that the current compression technology causes an increase in meta data due to the increase in the number of compressed data units stored in a unit storage space, which in turn excessively occupies the LDPC parity space, leading to an increase in the LDPC bit rate and a decrease in the LDPC error correction capability. Attached Figure Description

[0040] Figure 1 This is a schematic diagram illustrating how a 4K space stores 32B of meta data corresponding to four compression units.

[0041] Figure 2 This is a schematic diagram of the LDPC data layout structure according to an embodiment of the present invention, wherein, Figure 2 (A) in the diagram represents the structure of the LDPC codeword standard. Figure 2 (B) in the diagram represents the structure of an LDPC codeword containing multiple compressed data. Figure 2 (C) in the diagram represents the Normal Meta structure. Figure 2 (D) in the diagram represents the Compress Meta structure;

[0042] Figure 3 This is a schematic diagram of the write I / O path according to an embodiment of the present invention;

[0043] Figure 4 This is a schematic diagram of the read I / O path according to an embodiment of the present invention. Detailed Implementation

[0044] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0045] This invention proposes a data compression method and system for SSDs. On one hand, it controls the excessive use of LDPC parity space by meta data; on the other hand, it supports end-to-end data protection (PI) information recording and inspection. Furthermore, supporting PI functionality does not affect the LDPC bitrate or error correction capability. Additionally, this invention supports compression processing in host environments with LBA values ​​less than 4KB, and can receive and read data smaller than 4KB.

[0046] Here, the relevant technical terms used in this application are explained:

[0047] LDPC codeword: An LDPC codeword is the output sequence after LDPC encoding, including information bits and parity data. Assuming an LDPC codeword length of N bits and information bits of K bits, the LDPC code rate R = K / N. A higher code rate indicates a lower proportion of redundant parity bits, resulting in lower error correction capability for the same code length.

[0048] LBA: The basic logical unit address for data blocks transferred between the host and the hard drive, usually 512 bytes in size; some hosts and hard drives capable of supporting 4K logical block sizes can negotiate an LBA size of 4KB (4096B).

[0049] Read filling: When the host writes less than 4K of data, such as when the LBA size is 512B, the host writes one sector of data to LBA0. When processing internally, the hard drive will consider 4K granularity mapping, read the other sector data (LBA1-LBA7) corresponding to LBA0, and merge them with the newly written LBA0 data to form a new 4K of data.

[0050] LAA: A 4K logical address, aligned to 4K. One LAA address represents a 4K data block. For 512B LBAs, one LAA corresponds to 8 consecutive LBAs. The offset of the data within 4K can be found through the 4K offset of the LBA.

[0051] The L2P table records the mapping between the host logical address and the NAND physical address. When the host reads data at the corresponding logical address, the hard drive retrieves the location of the corresponding NAND by consulting the L2P table, and then reads the data from the NAND and returns it to the host.

[0052] PI: Protection Information, is a protection mechanism in end-to-end data protection that ensures data integrity. In NVMe 1.x, the PI information is 8 bytes long, including a 2-byte Guard field, a 2-byte Application Tag, and a 4-byte Reference Tag. The Guard field typically contains the CRC checksum of the data, and the Reference Tag is the logical address corresponding to the data. In NVMe 2.x and later versions, the length has been extended to 16 bytes, supporting stronger error detection capabilities. The specific length used can be determined by the protection information configuration.

[0053] For example, the data compression method for SSD described in this application includes write I / O path processing and read I / O path processing. A schematic diagram of the write I / O path is shown below. Figure 3 As shown in the diagram, the read I / O path is illustrated below. Figure 4 As shown, there are two data buffers before and after the compression engine in the IO processing path. The buffer closer to the host interface is mainly used to cache data before compression or after decompression, while the buffer closer to the NAND interface is used to cache compressed data or data that cannot be compressed. The buffer closer to the host interface can also be used for 4K padding.

[0054] The write I / O path processing includes the following steps:

[0055] S11. Receive data written by the host through the host interface and cache it in the buffer FIFO module. At the same time, calculate the PI information of the data in the buffer FIFO module through the PI module (refer to the NVMe PI standard).

[0056] S12. If the data cached in the buffer FIFO module reaches the size of 4K data units, or if data larger than 4K is sliced ​​into 4K data units, then the 4K data units are submitted to the compression module; if the data written by the host is less than 4K, then it is padded with 4K unit sizes.

[0057] S13. The compression module performs a compressibility judgment on the 4K data unit through the compression judgment module, and performs corresponding compression and storage operations based on the judgment result and the remaining space size of the 4K data storage space in the current Data Cache Buffer module.

[0058] S14. When storing compressed data in the 4K storage space of the Data Cache Buffer module, the compress meta is updated synchronously to record the PI information, LAA information and compressed size information corresponding to the 4K data unit, and the number of compressed units is updated (refer to the composition of compress meta); if the 4K storage space stores the first compressed data unit, the PI information in the normal meta is updated to 0 to indicate that the 4K storage space stores compressed data.

[0059] S15. If the amount of data (including compressible and incompressible data) stored in the Data Cache Buffer module reaches a preset threshold (usually the amount of data in a NAND Flash multi-plane program), then the data is allocated physical space of the corresponding size in NAND, encoded by the LDPC engine, and written to NAND; after the data is written, the mapping relationship between the corresponding data unit and the NAND physical space in the L2P table is updated, so that the corresponding logical address in the L2P table is associated with the NAND physical address where the data is stored;

[0060] The read I / O path processing includes the following steps:

[0061] S21. After the host interface of the SSD receives the read command from the host, it extracts the first logical address of the data from the read command, queries the L2P table according to the first logical address, and obtains the corresponding NAND physical address.

[0062] S22. Read the LDPC codeword of the 4K data corresponding to the NAND physical address through the NAND interface, submit it to LDPC for decoding, and store the data after LDPC decoding into the Data Cache Buffer module, including 4K data and normal meta.

[0063] S23. Check the validity of the PI position information in the normal meta file through the compression module; if the PI position information is valid, determine that the corresponding 4K data is uncompressed data; if the PI position information is invalid, determine that the corresponding 4K data is compressed data.

[0064] S24. If the corresponding 4K data is compressed data, based on the second logical address corresponding to the 4K data, the compression module finds the corresponding compressed data unit from the compress meta and submits it to the compression engine for decompression. The decompressed 4K unit data is then transferred to the Buffer FIFO module, and the corresponding PI information in the compress meta is transferred to the PI module. If the corresponding 4K data is uncompressed data, it is directly transferred to the Buffer FIFO module, and the PI information in the normal meta is transferred to the PI module.

[0065] S25. Verify the matching between the PI information and the data in the buffer FIFO module through the PI module, including verifying the consistency between the data CRC and the logical address and the PI information; after the verification is successful, the host interface transmits the data in the buffer FIFO module to the host; if the data read by the host is within 4K, then identify the offset within 4K of the data according to the 4K offset of the LBA corresponding to the LAA, and then transmit the corresponding data to the host.

[0066] For example, the 4K cell size read filling padding described in step S12 specifically includes: reading the insufficient data from NAND into the buffer FIFO module, merging it with the host-written data to fill the 4K data cell, and then submitting it to the compression module.

[0067] For example, the execution of the corresponding compression and storage operations in step S13 specifically includes:

[0068] If the 4K unit data is compressible, then the compression engine will be used to compress the 4K unit data; if the length after compression is less than the remaining space, then the compressed 4K unit data will be stored adjacent to the remaining space (see reference). Figure 1 (Compression unit merging section); If the length after compression is greater than the remaining space, the compressed 4K unit data will be stored in the new 4K space of the next DataCache Buffer module;

[0069] If the 4K cell data is not compressible, it will be stored in a new 4K space in the next Data Cache Buffer module.

[0070] For example, in step S24, the compression module finds the corresponding compressed data unit from the compress meta, which specifically includes: comparing the second logical address with the LAA information recorded in the compress meta, and calculating the total size of the compressed 4K data to obtain the offset of the compressed data unit corresponding to the second logical address within 4K.

[0071] For example, a schematic diagram of the LDPC data layout structure of the present invention is shown below. Figure 2 As shown, where, Figure 2 (A) in the diagram represents the structure of the LDPC codeword standard. Figure 2 (B) in the diagram represents the structure of an LDPC codeword containing multiple compressed data. Figure 2 (C) in the diagram represents the Normal Meta structure. Figure 2 (D) in the diagram represents the Compress Meta structure. The LDPC codeword consists of LDPC information bits and parity check bits, where the LDPC information bits include 4K data and NormalMeta. When the 4K space stores incompressible 4K data units, the PI information, LAA address, etc., corresponding to the data unit are recorded in Normal Meta. When the 4K space stores compressed data units, multiple compressed data units are stored sequentially, and the PI information, LAA information, etc., corresponding to multiple compressed data units are recorded in Compress Meta. The total length of multiple compressed data units plus the length of the Compress Meta structure does not exceed 4K. In this case, the corresponding PI position in Normal Meta is filled with 0 (or other values, to distinguish valid PI values). Normal Meta is stored immediately after the tail boundary of 4K space and does not occupy the internal space of 4K space; Compress Meta is stored immediately before the tail boundary of 4K space and occupies the internal space of 4K space (only valid when the internal space stores compressible data units).

[0072] For example, this application discloses a data compression system for SSDs, which utilizes the data compression method for SSDs described above, including:

[0073] The PI module is used to calculate and verify PI information for the data before compression in the write direction and the data after decompression in the read direction.

[0074] The Buffer FIFO module is used to cache block data from the host in the write direction;

[0075] The compression module includes a compression judgment module and a compression engine. The compression judgment module is used to determine whether the data is compressible, the compression engine compresses the compressible data, and the compressed data is merged in the Data CacheBuffer module.

[0076] The Data Cache Buffer module is used to merge compressed or incompressible data.

[0077] For example, in the Buffer FIFO module, if the block data is less than 4K, or if the beginning and end are not aligned to 4K, the part of the block data that is less than 4K will be read, padded, and merged.

[0078] For example, the compression module further includes a transmission module for placing the PI information generated by the PI module in the corresponding meta position, including the compress meta structure corresponding to compressible data and the normal meta structure corresponding to incompressible data.

[0079] For example, in the Data Cache Buffer module, if the amount of data written reaches the amount of data that can be programmed in the NAND Flash at one time, the merged data is transmitted to the LDPC engine as LDPC information bits for encoding, and the encoded data is then transmitted to the NAND through the NAND interface.

[0080] The above description is merely a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and environments, and can be altered within the scope of the concept described herein through the above teachings or related technologies or knowledge. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention should be within the protection scope of the appended claims.

Claims

1. A data compression method for SSDs, characterized in that, This includes write I / O path processing and read I / O path processing; The write I / O path processing includes the following steps: S11. Receive data written by the host through the host interface and cache it in the buffer FIFO module. At the same time, calculate the PI information of the data in the buffer FIFO module through the PI module. S12. If the data cached in the buffer FIFO module reaches the size of 4K data units, or if data larger than 4K is sliced ​​into 4K data units, then the 4K data units are submitted to the compression module; if the data written by the host is less than 4K, then it is padded with 4K unit sizes. S13. The compression module performs a compressibility judgment on the 4K data unit through the compression judgment module, and performs corresponding compression and storage operations based on the judgment result and the remaining space size of the 4K data storage space in the current Data Cache Buffer module. S14. When storing compressed data in the 4K storage data space of the Data Cache Buffer module, the compress meta is updated synchronously to record the PI information, LAA information and compressed size information corresponding to the 4K data unit, and the number of compressed units is updated; if the 4K storage data space stores the first compressed data unit, the PI information in the normal meta is updated to 0 to indicate that the 4K storage data space stores compressed data. S15. If the amount of data stored in the Data Cache Buffer module reaches the preset threshold, then allocate physical space of the corresponding size of NAND for the data, and write it into NAND after encoding by the LDPC engine; after the data is written, update the mapping relationship between the corresponding data unit and the NAND physical space in the L2P table, so that the corresponding logical address in the L2P table is associated with the NAND physical address where the data is stored. The read I / O path processing includes the following steps: S21. After the host interface of the SSD receives the read command from the host, it extracts the first logical address of the data from the read command, queries the L2P table according to the first logical address, and obtains the corresponding NAND physical address. S22. Read the LDPC codeword of the 4K data corresponding to the NAND physical address through the NAND interface, submit it to LDPC for decoding, and store the data after LDPC decoding into the Data Cache Buffer module, including 4K data and normalmeta; S23. Check the validity of the PI position information in the normal meta file through the compression module; if the PI position information is valid, determine that the corresponding 4K data is uncompressed data; if the PI position information is invalid, determine that the corresponding 4K data is compressed data. S24. If the corresponding 4K data is compressed data, based on the second logical address corresponding to the 4K data, the compression module finds the corresponding compressed data unit from the compress meta and submits it to the compression engine for decompression. The decompressed 4K unit data is then transferred to the Buffer FIFO module, and the corresponding PI information in the compress meta is transferred to the PI module. If the corresponding 4K data is uncompressed data, it is directly transferred to the Buffer FIFO module, and the PI information in the normal meta is transferred to the PI module. S25. Verify the matching between the PI information and the data in the buffer FIFO module through the PI module, including verifying the consistency between the data CRC and the logical address and the PI information; after the verification is successful, the host interface transmits the data in the buffer FIFO module to the host; if the data read by the host is within 4K, then identify the offset within 4K of the data according to the 4K offset of the LBA corresponding to the LAA, and then transmit the corresponding data to the host.

2. The data compression method for SSD according to claim 1, characterized in that, The 4K cell size read filling and padding described in step S12 specifically includes: reading the insufficient data from NAND into the buffer FIFO module, merging it with the host-written data to fill the 4K data cell, and then submitting it to the compression module.

3. The data compression method for SSDs according to claim 1, characterized in that, The specific compression and storage operations described in step S13 include: If the 4K unit data is compressible, then the compression engine is used to compress the 4K unit data; if the length after compression is less than the remaining space, then the compressed 4K unit data is stored adjacent to the remaining space; if the length after compression is greater than the remaining space, then the compressed 4K unit data is stored in the new 4K space of the next Data Cache Buffer module. If the 4K cell data is not compressible, it will be stored in a new 4K space in the next Data Cache Buffer module.

4. The data compression method for SSD according to claim 1, characterized in that, In step S24, the compression module searches for the corresponding compressed data unit in the compress meta, which specifically includes: comparing the second logical address with the LAA information recorded in the compress meta, and calculating the total size of the compressed 4K data to obtain the offset of the compressed data unit corresponding to the second logical address within 4K.

5. A data compression system for SSDs, employing the data compression method for SSDs according to any one of claims 1-4, characterized in that, include: The PI module is used to calculate and verify PI information for the data before compression in the write direction and the data after decompression in the read direction. The Buffer FIFO module is used to cache block data from the host in the write direction; The compression module includes a compression judgment module and a compression engine. The compression judgment module is used to determine whether the data is compressible, the compression engine compresses the compressible data, and the compressed data is merged in the Data Cache Buffer module. The Data Cache Buffer module is used to merge compressed or incompressible data.

6. A data compression system for SSDs according to claim 5, characterized in that: In the Buffer FIFO module, if the block data is less than 4K, or if the beginning and end are not aligned to 4K, the part of the block data that is less than 4K will be read, padded, and merged.

7. A data compression system for SSDs according to claim 5, characterized in that: The compression module also includes a transmission module, which is used to place the PI information generated by the PI module in the corresponding meta position, including the compress meta structure corresponding to compressible data and the normal meta structure corresponding to incompressible data.

8. A data compression system for SSDs according to claim 5, characterized in that: In the Data CacheBuffer module, if the amount of data written reaches the amount of data that can be programmed in the NAND Flash at one time, the merged data is transmitted to the LDPC engine as LDPC information bits for encoding, and the encoded data is then transmitted to the NAND through the NAND interface.

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