A decoding method and device of a product code, a storage medium and an electronic device

Abstract

The application discloses a decoding method and device of product code, a storage medium and an electronic device, and comprises the following steps: step S1: obtaining a product code word to be decoded and performing iterative decoding; step S2: detecting whether the iterative decoding process enters a stagnation state; step S3: when it is detected that the stagnation state is entered, determining a candidate bit set corresponding to the current stagnation state and storing a code word corresponding to the current stagnation state as a reference code word; step S4: performing a plurality of retry decoding operations on the basis of the step S3 until decoding is successful or a preset termination condition is met; wherein, before each retry, the current working code word is first restored to the reference code word, and a flip operation is performed on the reference code word by using different flip bit selection schemes to obtain a perturbed code word, which is used as a starting point of the retry decoding operation.

Description

Technical Field

[0001] This invention relates to the field of error correction coding and decoding technology, and in particular to a product code decoding method, apparatus, storage medium and electronic device. Background Technology

[0002] Product codes are a type of block code based on a two-dimensional matrix structure. They are constructed by arranging information bits into a matrix and applying component codes in both the row and column directions. Due to their regular structure and controllable encoding / decoding complexity, product codes have attracted widespread attention in data storage and communication systems. In particular, when component codes such as BCH codes or RS codes are used, which enable hard-decision bounded-distance decoding, product code decoders can obtain the hard-decision input with only a single read, eliminating the need for additional soft information acquisition steps, thus offering advantages in terms of decoding latency and hardware area.

[0003] In practical applications, a typical decoding method for product codes is iterative bounded-distance decoding. This method alternately performs component code decoding on the row-direction and column-direction component codewords: in one row-direction or column-direction traversal, for codewords with an error count not exceeding the error correction capability of the component code, the component code decoder can completely correct them; after multiple rounds of alternating row and column decoding, most error patterns can be gradually eliminated.

[0004] However, iterative bounded-distance decoding has an inherent limitation: when residual errors form a specific structured pattern in the matrix, the number of errors in each row component codeword exceeds the error correction capability of the row component code, and simultaneously, the number of errors in each column component codeword also exceeds the error correction capability of the column component code, causing neither the row nor column component code decoders to make any progress in error correction. This state, where the decoding process stops making new progress in error correction, is usually called the decoding stagnation state. Once in the stagnation state, continuing iterative decoding will not change the error pattern of the codewords, and the decoding process falls into a convergence trap.

[0005] Decoding failures caused by stagnation are one of the main factors affecting the performance of product code decoders in the low bit error rate (BER) region. This typically manifests as the error floor phenomenon—that is, after the original BER decreases to a certain level, the frame error probability no longer continues to decrease with increasing signal-to-noise ratio (SNR). For applications requiring extremely low uncorrected BER, the error floor problem restricts the further application of product codes.

[0006] To improve this situation, some post-processing methods have been proposed to attempt to break the stagnation. For example, when iterative decoding is detected to have entered a stagnation state, the sub-matrix regions corresponding to the uncorrected rows and columns are identified, and certain post-processing operations (such as overall flipping) are performed on the bits in that sub-matrix before iterative decoding continues. In some cases, such post-processing methods can change the original error pattern, thereby enabling the decoding process to regain error correction progress and thus reducing the error floor.

[0007] However, in practical applications, existing post-processing methods still struggle to effectively reduce the decoding failure probability in certain scenarios. For example, when the post-processed error pattern remains uncorrectable in the component code, the decoding process may still fail to converge successfully. Furthermore, the impact of post-processing operations on the decoding result may differ depending on the error pattern, thus there is still room for improvement in further enhancing the decoding success rate.

[0008] Therefore, given the shortcomings of existing technologies, it is necessary to propose a technical solution to address the technical problems existing in the current technologies. Summary of the Invention

[0009] In view of this, it is indeed necessary to provide a decoding method, apparatus, storage medium and electronic device for product codes. When the iterative decoding of product codes enters a stagnant state, the decoding failure can be effectively reduced by performing diversified perturbation operations on some bits in the stagnant related region and making multiple independent attempts based on the same reference state when a single perturbation fails.

[0010] To address the technical problems existing in the prior art, the technical solution of the present invention is as follows: A decoding method for product codes includes the following steps: Step S1: Obtain the product codeword to be decoded and perform iterative decoding; Step S2: Detect whether the iterative decoding process has entered a stalled state; Step S3: When entering a stagnation state is detected, determine the candidate bit set corresponding to the current stagnation state and completely store the codeword corresponding to the current stagnation state as the reference codeword; Step S4: Based on step S3, perform multiple retry decoding operations until decoding is successful or a preset termination condition is met; wherein, before each retry, the current working codeword is restored to the reference codeword and different flip bit selection schemes are used to perform flip operations on the reference codeword to obtain a perturbed codeword, which serves as the starting point for the retry decoding operation.

[0011] As a further improvement, the candidate bit set is determined based on the uncorrected row component codeword set and the uncorrected column component codeword set, wherein the bits in the submatrix defined by the uncorrected row component codeword set and the uncorrected column component codeword set are determined as the candidate bit set.

[0012] As a further improvement, step S4 includes: Each time a retry decoding operation is performed, the flip bit selection scheme is random or pseudo-random. According to the flip bit selection scheme, the set of bits to be flipped is determined from the candidate bit set. The bits in the reference codeword that correspond to the set of bits to be flipped are flipped to obtain the perturbation codeword. Perform decoding processing on the perturbation codeword; If the decoding of the perturbation codeword fails, the codeword is restored to the reference codeword, and a different next flip bit selection scheme than the previous attempt is adopted. The above steps are repeated until the decoding is successful or the preset termination condition is met.

[0013] As a further improvement, the number of bits in the set of bits to be flipped is less than the total number of bits in the candidate set of bits.

[0014] As a further improvement, the bit-flipping selection scheme uses different random seeds, different pseudo-random sequences, or different random sources for each retry, so that different attempts correspond to different sets of bits to be flipped.

[0015] As a further improvement, the stagnant state includes at least one of the following: No new errors were corrected after a predetermined number of consecutive row and column component codeword decodings; and The decoding process cycles between two codeword states.

[0016] As a further improvement, before determining the candidate bit set, the following steps are also included: Perform a global flip operation on the submatrix defined by the uncorrected row component codeword set and the uncorrected column component codeword set, and continue decoding the flipped codewords; If the codeword remains stagnant after the overall flip, the candidate bit set is determined and subsequent retries are performed.

[0017] As a further improvement, the reference codeword is obtained by completely copying the current working codeword when a stagnation state is detected, and the current working codeword is replaced with a copy of the reference codeword before each new attempt.

[0018] As a further improvement, the number of bits to be flipped in each attempt is odd.

[0019] The present invention also discloses a decoding apparatus for product codes, comprising: The iterative decoding module is used to obtain the product code codeword to be decoded and perform iterative decoding; The stall detection module is used to detect whether the iterative decoding process has entered a stall state; The candidate bit determination module is used to determine the set of candidate bits corresponding to the current stagnation state and to completely store the codeword corresponding to the current stagnation state as the reference codeword when the stagnation state is detected. The flip and retry control module is used to perform multiple retry decoding operations based on the output information of the candidate bit determination module until decoding is successful or a preset termination condition is met. Before each retry, the current working codeword is restored to the reference codeword and a different flip bit selection scheme is used to perform a flip operation on the reference codeword to obtain a perturbed codeword, which serves as the starting point for the retry decoding operation.

[0020] The present invention also discloses a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the above-described method.

[0021] The present invention also discloses an electronic device, characterized in that it includes a processor and a memory, wherein the memory stores computer-executable instructions, and the processor executes the computer-executable instructions to implement the above-described method.

[0022] As a further improvement, the electronic device is a storage controller connected to a NAND Flash memory chip, used to perform the method described above on data read from the NAND Flash memory chip.

[0023] Compared with existing technologies, this invention constructs a reference codeword after detecting a decoding stall state, and generates multiple perturbation codewords based on the reference codeword for decoding attempts. This allows the decoding process to explore multiple different error modes starting from the same stall state, thereby increasing the probability of successful decoding and effectively avoiding the problem of decoding failure due to a single post-processing operation. Attached Figure Description

[0024] Figure 1 This is a flowchart illustrating a product code decoding method provided by the present invention.

[0025] Figure 2 This is a flowchart of the product code decoding method provided in a preferred embodiment of the present invention; Figure 3This is a schematic diagram of the product code codeword matrix structure provided in an embodiment of the present invention; Figure 4 This is a flowchart of decoding stall detection and candidate bit set determination provided in an embodiment of the present invention; Figure 5 This is a flowchart of the single-flip retry processing provided in an embodiment of the present invention; Figure 6 This is a flowchart of the multiple retry control provided in an embodiment of the present invention, illustrating the process of saving and restoring the reference codeword; Figure 7 This is a schematic diagram of the reference codeword storage and recovery provided in an embodiment of the present invention, wherein... Figure 7 (a) shows when the reference codeword is saved. Figure 7 (b) illustrates the recovery operation prior to each retry; Figure 8 This is a schematic diagram illustrating two methods for determining the candidate bit set provided in embodiments of the present invention, wherein... Figure 8 (a) shows the submatrix layout defined by uncorrected rows and uncorrected columns. Figure 8 (b) illustrates a way to make moderate extensions based on the submatrix; Figure 9 This is a block diagram of the product code decoding device provided in an embodiment of the present invention; Figure 10 This is a schematic diagram of the structure of the electronic device provided in an embodiment of the present invention; Figure 11 This is a schematic diagram comparing the process differences between the method of the present invention and the overall flipping method provided in the embodiments of the present invention.

[0026] Figure 12 This is a schematic diagram showing the FER comparison curves of method A and method B in the 16 KiB product code system of this invention.

[0027] The following specific embodiments will further illustrate the present invention in conjunction with the above-described accompanying drawings. Detailed Implementation

[0028] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are merely some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0029] In the description of this invention, it should be understood that terms such as "first" and "second" are used only for descriptive purposes and should not be construed as indicating or implying relative importance or order.

[0030] See Figure 1 The diagram shows a flowchart of a product code decoding method provided by the present invention, which includes the following steps: Step S1: Obtain the product codeword to be decoded and perform iterative decoding; Step S2: Detect whether the iterative decoding process has entered a stalled state; Step S3: When entering a stagnation state is detected, determine the candidate bit set corresponding to the current stagnation state and completely store the codeword corresponding to the current stagnation state as the reference codeword; Step S4: Based on step S3, perform multiple retry decoding operations until decoding is successful or a preset termination condition is met; wherein, before each retry, the current working codeword is restored to the reference codeword and different flip bit selection schemes are used to perform flip operations on the reference codeword to obtain a perturbed codeword, which serves as the starting point for the retry decoding operation.

[0031] In the above technical solution, iterative decoding refers to performing iterative bounded-distance decoding on the product codeword to be decoded, alternately performing component code decoding on the row-direction component codeword and the column-direction component codeword. If the iterative decoding successfully corrects all errors, the result is output and the process ends.

[0032] Simultaneously, the error correction progress is monitored during the iterative decoding process. When it is detected that multiple consecutive row and column decodings have failed to correct any new errors, or when the decoding process cycles between two codeword states, it is determined to enter a stagnant state.

[0033] When entering a stagnant state, a candidate bit set is determined based on the uncorrected row component codeword set and the uncorrected column component codeword set corresponding to the stagnant state. The candidate bit set can be all bits in the submatrix defined by the uncorrected rows and columns, or it can be appropriately expanded based on this.

[0034] At the same time, the reference codeword is saved; the codeword corresponding to the current stalled state is stored completely as the reference codeword. The reference codeword remains unchanged throughout the multiple retries and serves as the unified starting point for each retry.

[0035] Each retry selects a different bit-flipping scheme to perform bit flipping. Based on the selected scheme, a subset of bits (less than the total number of bits in the candidate set) are selected for flipping to obtain the perturbed codeword. The bit-flipping scheme can be random, pseudo-random, or deterministic based on predetermined rules.

[0036] The obtained perturbation codeword is then decoded. This decoding process can involve continuing iterative decoding, restarting the entire iterative decoding process, or including post-processing steps such as flipping the entire submatrix. If decoding is successful, the result is output, and the process ends. If decoding fails and the termination condition is not met, the codeword is restored to the base codeword, and a different flip bit selection scheme is used to re-execute the process. This process is repeated until decoding is successful or the preset termination condition is met (such as reaching the maximum number of attempts k).

[0037] In the above steps, the recovery of the base codeword is the key step—ensuring that each retry starts from the same base state and that each attempt does not affect the others.

[0038] The technical solution of this invention can be applied to the following scenarios: SSD Controller: As the error correction engine of NAND Flash memory, the SSD controller performs product code decoding on the data read from the storage chip to meet the reliability requirements of enterprise-grade and consumer-grade SSDs.

[0039] NAND Flash data error correction: Provides effective hard-decision error correction capability for high-density storage media such as 3D TLC / QLC NAND under the condition of high original bit error rate.

[0040] Communication systems: In communication systems that use product codes (such as fiber optic communication and satellite communication), it is used to improve the error correction performance of hard-decision decoders.

[0041] Data storage system: More broadly applicable to any data storage system that uses product codes for hard-decision decoding, including magnetic storage, optical storage, etc.

[0042] The following detailed description is provided in conjunction with more specific embodiments. Example 1: Basic Method Example

[0043] This embodiment provides a decoding method for product codes, referring to... Figure 2 The overall process of Embodiment 1 of the present invention, as shown, includes the following steps: Step S100: Obtain the product codeword to be decoded.

[0044] Product code codewords have a two-dimensional matrix structure. (See reference...) Figure 3 The diagram shows the structure of a product code codeword matrix. The encoding process of a product code involves arranging the information bits into an m×n data matrix, applying component codes in both the row and column directions to obtain the encoded codeword matrix. Each component codeword in the row direction is a row codeword, and each component codeword in the column direction is a column codeword. The row and column component codes can be the same type or different types of error correction codes.

[0045] In a specific example, both the row-direction component code and the column-direction component code are BCH codes. The error correction capability of the row-direction component code is t_r, and the error correction capability of the column-direction component code is t_c. Those skilled in the art will understand that the component codes can also be RS codes or other component codes suitable for hard-decision decoding; this invention does not limit the type of component code.

[0046] Step S200: Perform iterative decoding on the product codeword.

[0047] The iterative decoding process involves alternately performing component code decoding on row-direction and column-direction component codewords. Specifically, in one row-direction traversal, component code decoding is performed on all row-direction component codewords one by one. If the number of errors in a row-direction component codeword does not exceed the error correction capability t_r of the row component code, then the component code decoder corrects all errors in that codeword; otherwise, the codeword is not corrected in this traversal. The column-direction traversal is handled similarly, using the error correction capability t_c of the column component code as the criterion. Row-direction and column-direction traversals are performed alternately until all errors are corrected or no new errors are corrected.

[0048] It should be noted that the bounded distance decoding described above is a typical implementation of component code decoding in iterative decoding. In other implementations, component code decoding can also be performed using other hard-decision decoding processes, as long as it can output the error correction result for the corresponding component codeword and participate in the row-column alternation iteration.

[0049] In this invention, a complete row traversal or a complete column traversal is referred to as a half-iteration process.

[0050] Step S300: Detect whether the iterative decoding has entered a stagnant state.

[0051] Reference Figure 4 The diagram shows the flowchart for stall detection and candidate bit set determination in this invention. During iterative decoding, the error correction progress of each half-iteration is monitored. Iterative decoding is determined to have entered a stall state when one of the following conditions is met: Condition 1: After a predetermined number of consecutive row-direction component codeword decodings and column-direction component codeword decodings (e.g., twice), no new errors are corrected. That is, after at least one complete row-direction traversal and column-direction traversal, the error pattern in the codeword remains unchanged.

[0052] Condition 2: The decoding process cycles between two codeword states. That is, the current codeword state is the same as a previously recorded codeword state, and the decoding process forms a periodic oscillation.

[0053] Those skilled in the art will understand that the above-mentioned criteria for determining a stagnant state are not exhaustive, and other criteria that can indicate that iterative decoding no longer makes progress in error correction are also applicable.

[0054] If the iterative decoding successfully corrects all errors, the decoding result is output, and the process ends.

[0055] Step S400: Determine the candidate bit set and store the reference codeword.

[0056] When a stalled state is detected, the set of uncorrected row component codewords R and the set of uncorrected column component codewords C corresponding to that stalled state are first determined. Uncorrected row component codewords refer to row direction component codewords that still contain errors in the stalled state; uncorrected column component codewords refer to column direction component codewords that still contain errors in the stalled state.

[0057] Based on the aforementioned uncorrected row component codeword set R and uncorrected column component codeword set C, a candidate bit set is determined. The method for determining the candidate bit set will be described in detail in Example 2.

[0058] Simultaneously, the codeword corresponding to the current stalled state is stored as the baseline codeword. The baseline codeword is a complete copy of the codeword state at the time the stalled state was detected. Each subsequent retry operation starts from this baseline codeword, rather than from the result of the previous attempt. Saving the baseline codeword is fundamental to the correct operation of the multiple retry mechanism.

[0059] Step S500: Based on the flip bit selection scheme, determine the set of bits to be flipped from the candidate bit set and perform the flip operation.

[0060] See Figure 5 and 6 The diagram shows the retry process flow chart of this invention. Figure 5 To perform a flip and decode process starting from the reference codeword, Figure 6 The core of the multiple retry control process is the saving of the reference codeword and the recovery operation before each retry.

[0061] In the first attempt, a first flip bit selection scheme is used to determine a first set of bits to be flipped from the candidate bit set. The number of bits in the first set of bits to be flipped is less than the total number of bits in the candidate bit set, that is, only some bits in the candidate bit set are flipped, not all bits.

[0062] Perform a flipping operation on the bit positions corresponding to the first set of bits to be flipped in the reference codeword, that is, invert the bit values ​​at these positions (0 becomes 1, 1 becomes 0), to obtain the first perturbation codeword.

[0063] Step S600: Perform decoding processing on the perturbation codeword.

[0064] Decoding is performed on the first perturbation codeword. The specific method of the decoding process will be described in detail in Example 6.

[0065] If the decoding process is successful (all errors are corrected), the decoding result is output and the process ends.

[0066] Step S700: Retry multiple times.

[0067] Reference Figure 7 The diagram illustrates the specific process of saving and restoring the reference codeword in this invention, showing the timing of saving and the data flow for each restoration operation. (Refer to...) Figure 7 (a) When decoding enters a stalled state, the current codeword is completely copied as the reference codeword and stored in the memory area. This reference codeword remains unchanged throughout the retry process. If the decoding of the first perturbation codeword fails, the following operations are performed: (a) Restore the codeword to the reference codeword. That is, discard the perturbation codeword and intermediate results generated by the current attempt, and start again from the previously saved reference codeword. See [reference] Figure 7 (b) Before each new attempt, the current input codeword is a copy of the base codeword, not the output codeword of the previous attempt.

[0068] (b) Using a different next-flip bit selection scheme than the previous attempt, determine the next set of bits to be flipped from the candidate bit set.

[0069] (c) Perform a flipping operation on the bits corresponding to the next set of bits to be flipped in the reference codeword to obtain the next perturbation codeword.

[0070] (d) Decode the next perturbation codeword.

[0071] (e) If decoding is successful, output the result and the process ends. If decoding is unsuccessful and the preset termination condition has not yet been met (e.g., the preset maximum number of attempts k has not been reached), return to step (a) and continue to the next retry.

[0072] (f) If the preset termination condition has been met (e.g., the maximum number of attempts k has been reached), then the decoding of the frame is determined to have failed.

[0073] In the aforementioned multiple retries, before each new attempt, the codeword is restored to the same base codeword, and then a new flip and decoding process is performed starting from the base codeword. Therefore, the starting state of each attempt is the same (all are base codewords), only the flip bit selection scheme is different, thus providing multiple distinct attempts for successful decoding.

[0074] The preset termination condition may include, but is not limited to, one or a combination of the following: reaching a preset maximum number of attempts k; reaching a preset maximum processing time or clock cycles. The maximum number of attempts k can be selected according to the reliability requirements and latency constraints of the application scenario.

[0075] The above technical solution effectively overcomes the deficiency of existing methods in lacking a systematic multiple-trial mechanism. When decoding reaches a standstill, it can start from the same standstill state and try different post-processing schemes, effectively improving the decoding success rate. Example 2: Method for determining the candidate bit set

[0076] This embodiment describes in detail the method for determining the candidate bit set, as a refinement of step S400 in embodiment 1.

[0077] Method 1: Submatrix Method Reference Figure 8 (a) The candidate bit set is determined by identifying all bits in the submatrix defined by the rows corresponding to the uncorrected row component codeword set R and the columns corresponding to the uncorrected column component codeword set C. That is, the candidate bit set is all bits at the intersection of the rows in set R and the columns in set C.

[0078] For example, if there are r uncorrected row component codewords and c uncorrected column component codewords in the stagnant state, then the candidate bit set contains r×c bits.

[0079] This method directly corresponds to the determination method described in claim 2.

[0080] Method 2: Expanding the candidate region Reference Figure 8 (b) Based on method one, the candidate bit set can be appropriately expanded. For example: (a) Extend the row or column range of the submatrix to several adjacent rows or columns, and include the bits in the extended region into the candidate bit set.

[0081] (b) In addition to the bits in the submatrix, other positions on the uncorrected row component codeword (not limited to the intersection with the uncorrected column) or other positions on the uncorrected column component codeword are included in the candidate bit set.

[0082] (c) In some extended implementations, the candidate bit set can be further extended based on the submatrix defined by the uncorrected row component codeword set and the uncorrected column component codeword set, and the extended range can cover the entire codeword in extreme cases.

[0083] The above-described extension methods can increase the coverage of the flipping operation to a certain extent, adapting to certain specific application scenarios. However, since the submatrix method (method one) most directly corresponds to the position information of the stagnant structure, it is the preferred embodiment of the present invention.

[0084] Regardless of the determination method used, the subsequent flipping operation selects a portion of the bits (rather than all the bits) from the candidate bit set for flipping. This feature is the core of the method of this invention. Example 3: Flip Bit Selection Scheme

[0085] This embodiment describes in detail various implementation methods of the flip bit selection scheme as a refinement of step S500 in embodiment 1.

[0086] In each attempt, the set of bits to be flipped needs to be determined from the candidate bit set. This set can be determined using one of the following bit selection schemes: Option 1: Random selection A true random method is used to uniformly and randomly select a predetermined number of bits, t, from the candidate bit set as the set of bits to be flipped. Each attempt uses an independent random source, ensuring that different attempts almost always select different combinations of bit positions.

[0087] Option 2: Pseudo-random selection A pseudo-random sequence generator (e.g., a linear feedback shift register, LFSR) is used to generate a pseudo-random sequence, and a predetermined number of bits, t, are selected from a set of candidate bits based on this pseudo-random sequence. Different attempts are made to initialize the pseudo-random sequence generator with different random seed values, so that different attempts correspond to different sets of bits to be flipped.

[0088] Pseudo-random selection schemes are particularly useful in hardware implementations because pseudo-random sequence generators have low hardware overhead and are fast to generate.

[0089] Option 3: Deterministic selection based on predetermined rules The bits to be flipped are selected using predefined deterministic rules. For example: (a) Selection by checkerboard pattern: Select the positions in the candidate bit set where the sum of the row number and column number is odd (or even).

[0090] (b) Selection by diagonal pattern: Select positions along the main diagonal or the secondary diagonal in the candidate bit set.

[0091] (c) Selecting according to the periodic jump pattern: Selecting a position at fixed intervals.

[0092] When using a deterministic selection scheme, different attempts can use different deterministic rules, or different parameters of the same rule (such as different starting positions, different interval steps, etc.) to ensure that different attempts correspond to different sets of bits to be flipped.

[0093] During a single retries, different attempts can employ the same or different types of flip-bit selection schemes. For example, the first attempt can use Scheme 1 (random selection), the second attempt can use Scheme 2 (pseudo-random selection), and the third attempt can use Scheme 3 (deterministic selection). A combination of these methods is also feasible.

[0094] Furthermore, the size of the set of bits to be flipped (i.e., the number of bits to be flipped, t) can be the same or different in different attempts. For example, a smaller number of flips can be used in the first few attempts, and a larger number of flips can be used in subsequent attempts, or vice versa. The choice of the number of bits to be flipped can be flexibly adjusted according to actual needs, as long as the number of bits to be flipped in each attempt is less than the total number of bits in the candidate bit set. Example 4: Multiple Retry Mechanism

[0095] This embodiment further describes in detail the implementation details of the multiple retry mechanism.

[0096] Storage of base codewords Reference Figure 7 (a) When step S300 detects a stall state, a complete copy of the current codeword is made and stored as a reference codeword. The storage of the reference codeword can be achieved in the following way: (a) Store a complete copy of the reference codeword in a dedicated storage area (such as SRAM or register file); (b) Allocate a buffer in the existing storage resources to store the reference codeword and reuse the existing transposed memory or data buffer.

[0097] Once the reference codeword is saved, it remains unchanged throughout the multiple retries until the decoding of that frame is finally successful or determined to be a failure.

[0098] Recovery of the base codeword Reference Figure 7 (b) Before each new attempt, replace the current working codeword with a copy of the base codeword. Specifically: If the decoding attempt fails (i≥1) and the termination condition has not yet been met, perform the following operation: (1) Restore all bits in the current working codeword to their corresponding values ​​in the reference codeword. This step ensures that the starting state of the (i+1)th attempt is exactly the same as the starting state of the first attempt.

[0099] (2) Use a new flip bit selection scheme (e.g., use a new random seed to initialize the pseudo-random generator) to determine the set of bits to be flipped for the (i+1)th time from the candidate bit set.

[0100] (3) Perform a flipping operation on the bits to be flipped in the recovered reference codeword to obtain the (i+1)th perturbation codeword.

[0101] (4) Decode the perturbation codeword.

[0102] The above process ensures that the input codeword for each attempt is the same base codeword, rather than the output of the previous attempt. Therefore, the results of each attempt do not affect each other. Each attempt starts from the same base state but uses a different flip bit selection scheme, which helps to reduce the overall decoding failure probability.

[0103] The meaning of "different flip bit selection schemes" In this invention, "different flip bit selection schemes" means that different attempts result in different sets of bits to be flipped. Methods to achieve different sets of bits to be flipped include, but are not limited to: (a) Initialize the same pseudo-random generator using different random seeds; (b) Use different pseudo-random sequences; (c) Use different random sources; (d) Using different deterministic selection rules or different parameters of the same rule; (e) Different numbers of flipped bits t were used in different attempts.

[0104] Termination conditions Preset termination conditions may include one or a combination of the following: (a) The number of attempts has reached the preset maximum number of attempts k. The maximum number of attempts k can be set according to the target reliability requirements, such as k=2, k=3, k=5, k=7 or k=10, etc.

[0105] (b) The total processing time or number of clock cycles consumed has reached the preset limit.

[0106] (c) Other termination criteria defined according to application requirements.

[0107] Successful judgment In any attempt, if the decoding process shows that all errors have been corrected, the decoding is considered successful, the corrected codeword is output, and the retry process is terminated early. Example 5: Preferred Implementation of Flip Quantity and Odd Flipping

[0108] This embodiment describes the strategy for selecting the number of flipped bits and the technical considerations for using odd-number flips as the preferred method.

[0109] Choice of the number of flipped bits In each attempt, the number of bits t to be flipped can be determined using one of the following strategies: (a) Preset fixed value: The value of t is determined during the system design phase based on codeword parameters and performance requirements, and all attempts are made to use the same t.

[0110] (b) Values ​​related to the size of the candidate bit set: Set t to a certain proportion of the total number of bits in the candidate bit set. For example, if the candidate bit set contains N_cand bits, t can be set to a value in the range of approximately 20% to 80% of N_cand. In some implementation scenarios, setting t in the range of approximately 40% to 60% of N_cand yields good results.

[0111] (c) Dynamic adjustment of the value: Different t values ​​can be used for different attempts. For example, try with a smaller t first, and if it is unsuccessful, gradually increase t, or vice versa.

[0112] The only constraint on the number of bits to be flipped, t, is that t must be less than the total number of bits in the candidate bit set, meaning that each attempt to flip is to flip only a portion of the bits in the candidate bit set.

[0113] Preferred implementation of odd number flipping In a preferred embodiment, the number of flipped bits t is selected to be an odd number.

[0114] The advantage of selecting an odd number of flipped bits is that, for the smallest stagnant structure (i.e., the smallest stagnant error pattern determined by the component code's error correction capability) that appears in product code iterative decoding, the total number of errors in this stagnant structure has a definite parity. When an odd number of bits are flipped, the parity of the total number of errors in the flipped submatrix changes, no longer satisfying the specific quantity constraint of the stagnant structure, thus destroying the stagnant structure. In other words, under the condition that the number of flips is odd, the stagnant structure cannot continue to exist after flipping.

[0115] This property is particularly effective for the smallest stagnant structures, because the row and column constraints of such structures completely lock the total number of errors, and changes in parity directly disrupt the satisfaction of these constraints. For larger stagnant structures, odd-number flips can also reduce their survival probability, but they do not necessarily guarantee complete elimination.

[0116] It should be noted that the method of this invention can also be implemented by selecting an even number of flip bits. Although an even number of flips does not have the aforementioned mathematical guarantee regarding the minimum stall structure, it can still effectively reduce the probability of decoding failure under the multiple-trial mechanism. Therefore, an odd number of flips is the preferred method, but not the only method. Example 6: Implementation of Decoding Processing

[0117] This embodiment describes in detail various implementation methods of the decoding process in step S600.

[0118] After performing a flip operation on the perturbed codeword, it is necessary to perform decoding on the perturbed codeword to attempt to correct any remaining errors. The decoding process can be performed in one of the following ways: Method 1: Continue iterative decoding Continue performing iterative bounded distance decoding on the perturbed codeword, that is, alternately perform component code decoding on the row direction component codeword and the column direction component codeword of the perturbed codeword until all errors are corrected or the system enters a stagnant state again.

[0119] This method is the simplest to implement; it only requires sending the perturbation codeword into the same iterative decoding process.

[0120] Method 2: Restart a complete round of iterative decoding The perturbed codeword is subjected to a complete iterative decoding process starting from the beginning, including resetting the iteration counter and intermediate states. This method is suitable for situations where flipping operations may change the positions of many bits, allowing the iterative decoder to fully utilize its iterative error correction capabilities from the initial state.

[0121] Method 3: Decoding process including overall submatrix flipping The perturbed codeword is first subjected to iterative bounded distance decoding. If a stall occurs again during the iterative decoding process, the currently stalled submatrix is ​​flipped, and then the iterative decoding continues. This method treats the overall flip post-processing as a link in the perturbed post-decoding processing chain.

[0122] The three methods described above correspond to different implementations of the decoding process described in claims 9, 10, and 11, respectively. In practical implementation, a suitable method can be selected based on the decoder architecture and performance requirements, or different methods can be chosen in different trials. A combination of overall flipping priority attempt and partial flipping retry.

[0123] In one implementation, when it is detected that the iterative decoding has entered a stalled state, before determining the candidate bit set and performing a partial bit flip retry, a global flip operation is first performed on the submatrix defined by the uncorrected row component codeword set and the uncorrected column component codeword set, that is, all bits in the submatrix are inverted, and then iterative decoding continues on the codewords after the global flip.

[0124] If the codeword after the overall flip can be successfully decoded through iterative decoding, the decoding process ends. Since the overall flip is a deterministic operation with low computational cost and predictable results, it can directly resolve stagnant states in certain error modes, making it a practically viable approach as a preferred method.

[0125] Global flipping is a deterministic operation—given the same stalled state, the result of global flipping is uniquely determined. If decoding still fails after global flipping, since the flipping result remains unchanged, performing global flipping again on the same stalled state will not yield different results, thus preventing further reduction of the failure probability through repeated attempts. Furthermore, global flipping inverts all bits in the stalled region. When not all positions in the stalled region are erroneous, the flipping can introduce new errors into some previously correct positions, potentially causing the error pattern after global flipping to remain in an uncorrectable state.

[0126] If the codeword after the overall flip remains in a stagnant state after iterative decoding (i.e., the overall flip fails to resolve the stagnant problem), then the partial bit flip retry process proposed in this invention is entered: a candidate bit set is determined based on the uncorrected row component codeword and the uncorrected column component codeword corresponding to the current stagnant state, the codeword corresponding to the current stagnant state is stored as the reference codeword, and then, in accordance with the method described in the aforementioned embodiments, a portion of bits are selected from the candidate bit set to perform the flip operation, the perturbed codeword is decoded, and if unsuccessful, the codeword is restored to the reference codeword, and a different flip bit selection scheme is used for the next attempt.

[0127] In the above combination method, preferably, the reference codeword used in the partial bit flip retry process is the codeword when the entire bit flip re-enters the stagnant state again, that is, the stagnant state after the entire bit flip is used as the starting point for subsequent partial bit flip retry. Regardless of which reference codeword is used, the codeword is restored to the selected reference codeword before each new partial bit flip attempt to ensure mutual differentiation between attempts.

[0128] In another implementation, the reference codeword used in the partial bit flip retry procedure can also be the original codeword when the stall state was initially detected (i.e., the codeword before the overall flip). The specific choice depends on the design of the implementation scheme.

[0129] The above combination method combines deterministic overall flipping with nondeterministic partial bit flipping retry: first, overall flipping is used to try to solve the stall problem with low overhead; if overall flipping fails, the diversified selection capability of partial bit flipping is used to perform multiple independent retries, thereby maximizing the probability of successful decoding while taking efficiency into account. Example 7: Additional parity bit gating and error correction suppression

[0130] This embodiment describes an implementation method for detecting and rejecting error correction outputs from a component code decoder by adding a parity bit to each component codeword.

[0131] Currently, in bounded-distance decoding of component codes (such as BCH codes), when the actual number of errors in a component codeword exceeds the error correction capability t, the component code decoder may fail to decode correctly, and in some cases may output an incorrect correction result (i.e., miscorrection). Miscorrection is relatively rare in ordinary iterative decoding, but when the flip operation changes some bits in the codeword, the error weight distribution of some component codewords may change, thus altering the probability of miscorrection.

[0132] Check bit gating mechanism To mitigate the impact of miscorrection, a parity bit can be added to each component codeword of the product code. Specifically: During the encoding phase, a parity bit is added to each row-direction component codeword and / or each column-direction component codeword. During the decoding phase, when the component code decoder provides an error correction result, the parity bit is used to verify the error correction result. If the verification passes, the error correction result is accepted; if the verification fails, the error correction result is rejected, and the component codeword remains unchanged.

[0133] Optimal implementation of overall parity check bit As a preferred implementation, the parity bit is an overall parity bit, that is, each component codeword is appended with a bit such that the modulo-2 sum of all bits in the component codeword (including the parity bit) is a definite value (e.g., 0).

[0134] The implementation methods of the overall parity check bit include: (a) Two-step method: First, encode according to the standard encoding method of component code, and then add an extra parity check bit.

[0135] (b) One-step method: Multiply the generator polynomial of the component code with the factor (x+1) to form an extended generator polynomial, and directly generate codewords including parity bits during encoding.

[0136] The two methods are mathematically equivalent, and the added parity bits have the same function and effect.

[0137] A beneficial characteristic of global parity bits is that they can completely detect certain most common error correction patterns (i.e., cases where the actual number of errors is exactly one more than the component code's error correction capability). This is because, in these specific cases, the relationship between the error correction output codeword and the actual error pattern ensures that parity checking will inevitably fail.

[0138] Of course, the parity bit can also take other forms, such as cyclic redundancy check (CRC) or multi-bit check codes. The overall parity bit is the implementation with the lowest check overhead (only one bit is added to each component codeword), and is the preferred embodiment of this invention. Example 8: Device and Electronic Equipment Example

[0139] This embodiment provides a product code decoding device, referring to... Figure 9 The module block diagram shown indicates that the decoding device includes: The iterative decoding module 810 is used to alternately perform component code decoding on the row-direction and column-direction component codewords of the product codeword to be decoded, forming an iterative decoding process. The iterative decoding module 810 includes a row-direction component code decoder and a column-direction component code decoder. In one implementation, the row-direction and column-direction component code decoders can share the same hardware decoding engine, and the row-direction and column-direction codewords can be processed alternately using time-division multiplexing.

[0140] Stagnation detection module 820 is used to monitor the error correction progress of the iterative decoding process and determine whether the iterative decoding has entered a stagnant state. Stagnation detection module 820 can detect periodic oscillations by comparing whether the number of error bits corrected in adjacent half-iterations is zero, or by recording and comparing codeword states.

[0141] The candidate bit determination module 830 is used to determine a set of candidate bits based on the uncorrected row component codeword and uncorrected column component codeword corresponding to the stagnation state when a stagnation state is detected, and to store the codeword corresponding to the stagnation state as a reference codeword. This module includes: (a) Row and column status recording unit, used to record whether each row direction component codeword and column direction component codeword has been successfully corrected, thereby determining the set of uncorrected row component codewords and the set of uncorrected column component codewords.

[0142] (b) A reference codeword storage unit, used to completely copy and store the current codeword as a reference codeword when a stagnant state is detected. The reference codeword storage unit may be implemented by a dedicated SRAM or a register file.

[0143] The flip and retry control module 840 is used to control the flip operation and multiple retries. The functions of this module include: (a) Determine the set of bits to be flipped from the candidate bit set according to the flip bit selection scheme. This module may include a pseudo-random sequence generator (such as an LFSR) to generate the flip positions.

[0144] (b) Perform a flipping operation on the bits to be flipped in the reference codeword to generate a perturbation codeword.

[0145] (c) The control iterative decoding module 810 performs decoding processing on the perturbation codeword.

[0146] (d) If the decoding process fails, the control restores the codeword to the reference codeword (reads a copy of the reference codeword from the reference codeword storage unit), and then generates a new set of bits to be flipped using a new flip bit selection scheme (e.g., using a new LFSR seed), and repeats the flipping and decoding process.

[0147] (e) Maintain an attempt counter and terminate the retry process when the number of attempts reaches the maximum number of attempts k or the decoding is successful.

[0148] In the flip and retry control module 840, the function of saving and restoring the reference codeword is a core component. Before each new attempt, the module ensures that the current working codeword is restored to the reference codeword, rather than retaining the perturbation result of the previous attempt.

[0149] Electronic device examples Reference Figure 10 The present invention also provides an electronic device 900, including a processor 910 and a memory 920. The memory 920 stores computer-executable instructions, and when the processor 910 executes the computer-executable instructions, it implements the method as described in any one of Embodiments 1 to 7.

[0150] Processor 910 may be a general-purpose processor (such as a CPU), a special-purpose processor (such as a DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices. Memory 920 may be random access memory (RAM), read-only memory (ROM), flash memory, or a combination thereof.

[0151] In a preferred embodiment, the electronic device 900 is a storage controller connected to a NAND Flash memory chip, used to perform the product code decoding method described above on data read from the NAND Flash memory chip. In the storage system, data stored in the NAND Flash memory chip is encoded and written, and decoded by an error correction engine in the storage controller during reading. The method of this invention is applicable to the decoding algorithm used as the error correction engine. Example 9: Storage System Application Example

[0152] This embodiment describes a typical application scenario of the present invention in a storage system. It is only an example and does not constitute a limitation on the scope of protection of the present invention.

[0153] In solid-state drive (SSD) systems, data undergoes error correction encoding (including product code encoding) before being written to NAND Flash memory chips. During reading, the error correction engine in the memory controller performs iterative decoding. With the evolution of NAND Flash memory chip manufacturing processes and the increase in storage density, the raw bit error rate (RBER) tends to rise. Under high RBER conditions, traditional iterative decoding may encounter stalls more frequently.

[0154] The decoding method of this invention can be applied to the error correction engine in an SSD controller. When iterative decoding enters a stall state, the error correction engine performs operations such as determining the candidate bit set, saving the reference codeword, flipping some bits, and multiple retries. Since the stall event occurs only with a very low probability (corresponding to the error floor region), the multiple retries have little impact on the average throughput of the system.

[0155] It should be noted that the method of the present invention is not limited to NAND Flash storage systems, but is also applicable to other data storage or data transmission scenarios that use product codes, including but not limited to NOR Flash storage systems, magnetic storage systems, and optical fiber communication systems.

[0156] See Figure 11 The diagram shows a comparison of the process differences between the method of the present invention and the overall flipping method, and it has at least the following technical effects: (1) By storing the reference codeword corresponding to the stalled state and restoring the codeword to the reference codeword before each new attempt, a mechanism is realized that multiple attempts are made starting from the same reference state and using different flip bit selection schemes. Each attempt is based on the same reference codeword but uses a different flip bit selection scheme, providing multiple distinct attempts for successful decoding. When different attempts correspond to different sets of bits to be flipped, it helps to reduce the overall decoding failure probability.

[0157] (2) By performing a flip operation on a subset of bits (rather than all bits) in the candidate bit set, the result of each flip operation depends on the specific bit position selected, thus producing a variety of perturbation effects. Compared to a global flip, partial bit flipping maintains the perturbation effect on the stagnant structure while avoiding indiscriminate changes to all bits in the stagnant region.

[0158] (3) The above-mentioned partial bit flipping and multiple retry mechanism work together: It is precisely because each flip is of a portion of the candidate bit set rather than all the bits that different flipping bit selection schemes can produce different perturbation codewords, making multiple attempts a meaningful operation. If the entire bit is flipped, different flipping bit selection schemes cannot produce different results, and multiple attempts will lose their effect. Therefore, partial bit flipping is the technical prerequisite for the effective operation of the multiple retry mechanism.

[0159] To further verify the performance improvement effect of the product code decoding method described in the above embodiments on actual flash memory storage systems, the differences in error floor suppression between the existing single-bit single-flip method and the partial bit flip and multiple independent trial method described in this invention are quantitatively evaluated by comparing them. This verifies that the technical solution of this invention can meet the reliability requirements of enterprise-level solid-state drives. Experimental setup

[0160] The experiment used two sets of product code system configurations for testing: Configuration 1 (16 KiB system): The data matrix size is 313 rows × 420 columns. The row direction uses BCH component code with error correction capability t=3 (code length 447, information bit length 420, with an additional 1-bit overall parity check, extended code length 448), and the column direction uses BCH component code with error correction capability t=2 (code length 331, information bit length 313, with an additional 1-bit overall parity check, extended code length 332). After encoding, the matrix size is 332 × 448, and the system code rate is approximately 0.884.

[0161] Configuration 2 (8 KiB system): The data matrix size is 288 rows × 228 columns. The row direction uses BCH component codes with error correction capability t=2 (code length 246, information bit length 228, with an additional 1-bit overall parity check, extended code length 247), and the column direction uses BCH component codes with error correction capability t=3 (code length 315, information bit length 288, with an additional 1-bit overall parity check, extended code length 316). The encoded matrix size is 316 × 247, and the system code rate is approximately 0.841.

[0162] In both of the above configurations, the BCH component codes are in Constructing over a finite field, the primitive polynomial is: The overall parity check bit is used to assist in detecting miscorrection events in the BCH decoder. The test channel model uses a binary symmetric channel (BSC), and the raw bit error rate (RBER) is set to α=0.01, corresponding to the typical operating conditions of 3D TLC NAND flash memory near the end of its life.

[0163] Comparison Method Explanation

[0164] Method A (Single-bit Single-Flip Method): When a stall is detected during the iterative decoding process, a set of candidate bits is determined based on the stall region. One bit position is randomly selected from this set for flipping, and then iterative decoding continues. This method performs only a single flip attempt each time the post-processing is triggered, with a fixed number of flipped bits (1), and does not support multiple retries after recovery from the reference codeword.

[0165] Method B (the method of this invention): When a stalled state is detected in the iterative decoding process, the received codeword at the current moment is first saved as the reference codeword. Then, a candidate bit set is determined based on the stalled region, and a preset number of bit positions are randomly selected from it and flipped, followed by continued iterative decoding. If the decoding attempt fails, the received codeword state is restored from the saved reference codeword, and bit positions are randomly selected independently from the candidate bit set again for flipping, and iterative decoding is attempted again. The above process is repeated for a preset number of independent attempts.

[0166] Both methods use the same iterative decoder, employing a row-column alternating bounded-distance decoding (BDD) strategy, combined with a submatrix flipping mechanism to handle 2-cycle stall structures. Both methods preserve the reference codeword at the stall point; the differences lie in the number of flipped bits (1 bit for method A, a preset number for method B) and whether multiple independent attempts are supported after recovery from the reference codeword.

[0167] Experimental results

[0168] Table 1 lists the comparison results of key performance indicators of Method A and Method B under the above two configurations.

[0169] Table 1. Comparison of performance indicators between Method A and Method B

[0170] See Figure 11 The figure shows the frame error rate (FER) comparison curves of method A and method B under different raw bit error rates for configuration 1 (16 KiB system).

[0171] From Table 1 and Figure 12 The experimental results show that the method of the present invention (Method B) achieves a significant improvement in error floor suppression compared to the single-bit single-flip method (Method A). The following analysis examines this from multiple perspectives.

[0172] (1) The error floor is significantly reduced. In configuration one (16 KiB), the error floor of method A is approximately Method B reduced the error floor to approximately [value missing] through 7 independent attempts. The improvement is more than three orders of magnitude. In configuration two (8 KiB), the error floor of method A is approximately Method B reduces the error floor to approximately [value missing] through two independent attempts. The improvement is about one order of magnitude.

[0173] (2) Meets the reliability requirements of the storage system. Enterprise-grade solid-state drives typically require an uncorrectable bit error rate (UBER) of less than [value missing]. Method A configures the following error floor as follows: This is approximately three orders of magnitude higher than the target value, failing to meet the aforementioned reliability requirements. Method B achieves a fault floor lower than [value missing] in both configurations. This meets the reliability requirements of the storage system. This demonstrates that the partial bit flipping combined with multiple independent attempts described in this invention can effectively overcome the error floor bottleneck of the single bit flipping method.

[0174] (3) The crucial role of the reference codeword saving and recovery mechanism. Each attempt in Method B is re-executed after being recovered from the saved reference codeword, and each attempt is independent of the others. This independence ensures that with each additional attempt, the overall failure probability decreases approximately exponentially. In contrast, Method A can only perform a single flip operation and lacks the ability to make multiple independent attempts, so it cannot further reduce the failure probability by increasing the number of attempts.

[0175] (4) Advantages of optimizing the number of flipped bits. Method A only flips 1 bit, which has limited effect on disrupting the balanced error structure that causes decoding stall. Method B adopts a strategy of randomly selecting a preset number of bits from the candidate bit set for flipping. By optimizing the number of flips, it can disrupt the balanced error structure that causes decoding stall with a higher probability. Experimental data shows that when 41 flipped bits are selected in configuration one and 3 flipped bits are selected in configuration two, the survival probability of the stalled structure in a single attempt can be reduced to a low level.

[0176] (5) Controllable hardware implementation overhead. Both methods require a reference codeword storage buffer, which requires approximately 148,736 bits of SRAM storage space for a 16 KiB codeword. The additional hardware overhead of method B compared to method A is mainly due to the control logic and recovery path for multiple attempts, which is negligible. Under 28nm CMOS technology, the decoder logic area is approximately 0.120mm², and a decoding throughput of approximately 15.4 Gb / s can be achieved at an operating frequency of 500MHz. Multiple independent attempts only introduce additional delay on the post-processing path, since the post-processing trigger probability is extremely low (approximately...). (on the order of magnitude), its impact on the average decoding throughput of the system is less than It can be ignored.

[0177] (6) Error correction detection function of the parity bit. In both configurations, each BCH component code is supplemented with a 1-bit overall parity bit. When the BCH decoder performs a miscorrection (correcting the received codeword to an incorrect codeword), the overall parity bit can detect the miscorrection event of a specific weight pattern. Experiments show that for a BCH code with error correction capability t, the undetected error correction rate of the error pattern with weight t+1 is zero, thus effectively reducing the impact of miscorrection on the error floor.

[0178] in conclusion

[0179] The experimental results above demonstrate that the product code decoding method described in this invention, by saving the reference codeword after iterative decoding stalls, randomly selecting a preset number of bits from the candidate bit set for flipping, and supporting multiple independent attempts after recovery from the reference codeword, can reduce the error floor by more than one to three orders of magnitude, meeting the reliability requirements of storage systems in both 16 KiB and 8 KiB system configurations. This technical solution effectively solves the error floor problem of traditional product code iterative decoding while maintaining the advantages of low complexity and low latency in hard-decision decoding, making it suitable for the error correction needs of high-density NAND flash memory storage systems. Terminology and Description of Alternative Implementations

[0180] To ensure a correct understanding of the scope of protection of this invention, the terminology and alternative embodiments used in this specification are explained below: (1) Regarding "flipping". In this specification and claims, "flipping" means inverting the current value of a bit (0 becomes 1, 1 becomes 0). Flipping is a preferred bit modification method in the embodiments of this invention. Those skilled in the art will understand that performing other forms of state modification operations on bits (such as setting all selected bits to preset values, XORing with a preset mask, etc.) may also achieve the effect of perturbing the stagnant structure, but the flipping operation is the most direct and effective method.

[0181] (2) Regarding the flip bit selection method. The flip bit selection scheme of the present invention includes random selection, pseudo-random selection, and deterministic selection based on predetermined rules. This specification mainly describes random and pseudo-random selection, but this does not exclude deterministic selection. Unless otherwise specified in the claims, all of the above selection methods are within the protection scope of the present invention.

[0182] (3) Regarding the candidate bit set. The candidate bit set can be a precise submatrix defined by uncorrected rows and columns (as in Embodiment 2, Method 1), or it can be a region that is moderately extended based on the submatrix (as in Embodiment 2, Method 2). In extreme cases, the extended range can cover the entire codeword. Different determination methods will affect the coverage range of the flipped bits, but will not change the core feature of this invention: "selecting a portion of bits from the candidate bit set for flipping".

[0183] (4) Regarding component codes. This specification uses BCH codes as a specific example of component codes, but the invention does not limit the type of component codes. Component codes can be BCH codes, RS codes, or other component codes capable of hard-decision decoding. The error correction capabilities of row-direction component codes and column-direction component codes can be the same or different.

[0184] (5) Regarding the reference codeword. The "reference codeword" refers to the complete copy of the codeword saved when a stalled state is detected. During multiple retries, the reference codeword is recovered before each new attempt, and each attempt uses the reference codeword as the starting point for the flip operation. The reference codeword remains unchanged throughout the multiple retries.

[0185] (6) Regarding the non-limiting nature of the parameters. The specific matrix size (such as the specific value of m×n), component code parameters (such as the specific values ​​of error correction capability t_r and t_c), number of flipped bits t, maximum number of attempts k, etc., appearing in this specification are specific examples in the embodiments and do not constitute a limitation on the present invention. The present invention is applicable to product code systems with different sizes and different component code parameters.

[0186] The above description of the embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. It should be noted that those skilled in the art can make several improvements and modifications to the present invention without departing from the principles of the present invention, and these improvements and modifications also fall within the protection scope of the claims of the present invention.

[0187] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined in this invention may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A decoding method for product codes, characterized in that, Includes the following steps: Step S1: Obtain the product codeword to be decoded and perform iterative decoding; Step S2: Detect whether the iterative decoding process has entered a stalled state; Step S3: When entering a stagnation state is detected, determine the candidate bit set corresponding to the current stagnation state and completely store the codeword corresponding to the current stagnation state as the reference codeword; Step S4: Based on step S3, perform multiple retry decoding operations until decoding is successful or a preset termination condition is met; wherein, before each retry, the current working codeword is restored to the reference codeword and different flip bit selection schemes are used to perform flip operations on the reference codeword to obtain a perturbed codeword, which serves as the starting point for the retry decoding operation.

2. The decoding method for product codes according to claim 1, characterized in that, The candidate bit set is determined based on the uncorrected row component codeword set and the uncorrected column component codeword set, wherein the bits in the submatrix defined by the uncorrected row component codeword set and the uncorrected column component codeword set are determined as the candidate bit set.

3. The decoding method for product codes according to claim 1, characterized in that, Step S4 includes: Each time a retry decoding operation is performed, the flip bit selection scheme is random or pseudo-random. According to the flip bit selection scheme, the set of bits to be flipped is determined from the candidate bit set. The bits in the reference codeword that correspond to the set of bits to be flipped are flipped to obtain the perturbation codeword. Perform decoding processing on the perturbation codeword; If the decoding of the perturbation codeword fails, the codeword is restored to the reference codeword, and a different next flip bit selection scheme than the previous attempt is adopted. The above steps are repeated until the decoding is successful or the preset termination condition is met.

4. The decoding method for product codes according to claim 3, characterized in that, The number of bits in the set of bits to be flipped is less than the total number of bits in the set of candidate bits.

5. The decoding method for product codes according to claim 3, characterized in that, Each time a retry is made, the bit-flipping selection scheme uses a different random seed, a different pseudo-random sequence, or a different random source so that different attempts correspond to different sets of bits to be flipped.

6. The decoding method for product codes according to claim 1, characterized in that, The stagnant state includes at least one of the following: No new errors were corrected after a predetermined number of consecutive row and column component codeword decodings; and The decoding process cycles between two codeword states.

7. The decoding method for product codes according to claim 1, characterized in that, Before determining the candidate bit set, the process also includes: Perform a global flip operation on the submatrix defined by the uncorrected row component codeword set and the uncorrected column component codeword set, and continue decoding the flipped codewords; If the codeword remains stagnant after the overall flip, the candidate bit set is determined and subsequent retries are performed.

8. The decoding method for product codes according to claim 1, characterized in that, The reference codeword is obtained by completely copying the current working codeword when a stagnation state is detected, and the current working codeword is replaced with the copy of the reference codeword before each new attempt.

9. The decoding method for product codes according to claim 1, characterized in that, In each attempt, the set of bits to be flipped contains an odd number of bits.

10. A decoding apparatus for a product code that implements any one of the methods described in claims 1-9, characterized in that, include: The iterative decoding module is used to obtain the product code codeword to be decoded and perform iterative decoding; The stall detection module is used to detect whether the iterative decoding process has entered a stall state; The candidate bit determination module is used to determine the set of candidate bits corresponding to the current stagnation state and to completely store the codeword corresponding to the current stagnation state as the reference codeword when the stagnation state is detected. The flip and retry control module is used to perform multiple retry decoding operations based on the output information of the candidate bit determination module until decoding is successful or a preset termination condition is met. Before each retry, the current working codeword is restored to the reference codeword and a different flip bit selection scheme is used to perform a flip operation on the reference codeword to obtain a perturbed codeword, which serves as the starting point for the retry decoding operation.

11. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the method as described in any one of claims 1 to 9.

12. An electronic device, characterized in that, It includes a processor and a memory, wherein the memory stores computer-executable instructions, and the processor executes the computer-executable instructions to implement the method as described in any one of claims 1 to 9.

13. The electronic device according to claim 12, characterized in that, The electronic device is a storage controller connected to a NAND Flash memory chip, used to perform the method as described in any one of claims 1 to 9 on data read from the NAND Flash memory chip.

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