A kind of 128 / 256 channel scalable multi-beam phased array radio frequency transceiver chip is supported

Abstract

The application belongs to the technical field of wireless communication, and specifically relates to a multi-beam phased array radio frequency transceiver chip supporting 128 and 256 channels and being extensible. The chip adopts a tile type extensible architecture and is composed of a phased array subarray module, an extensible interconnection interface, a central beam processor and a dynamic channel management unit. Each subarray module contains 16 transceiver channels, supports Ka or Ku band switching, and realizes 128 to 256 channel extension through 8 to 16 subarray cascades. The central beam processor can simultaneously generate at least 8 independent beams, and the dynamic channel management unit realizes four-stage intelligent power switching. The application solves the problems of channel expansion limitation, insufficient multi-beam capacity and excessively high power consumption of traditional chips, reduces standby power consumption by more than 90%, and realizes switching time less than 50 ms, and is suitable for low-orbit satellite communication terminals, mobile phone direct satellite equipment and attachable satellite communication accessories.

Description

[0001] This invention belongs to the field of wireless communication technology, specifically relating to the design of phased array radio frequency transceiver chips. It focuses on core technologies such as large-scale channel scalability and multi-beam parallel processing, and is applicable to low-Earth orbit satellite communication terminals, mobile phone-to-satellite direct connection devices, and attachable satellite communication accessories. This chip addresses the application requirements of high gain, low power consumption, and flexible expansion in the Ka or Ku bands, solving the technical pain points of traditional phased array chips, such as limited channel expansion, insufficient multi-beam capability, and the contradiction between power consumption and integration. It provides core hardware support for high-speed satellite communication and can be widely used in civilian satellite communication, 5G millimeter-wave extension, and other scenarios, adapting to the miniaturization and low power consumption requirements of consumer electronics terminals. Background Technology

[0002] Low-Earth orbit (LEO) satellite communication, with its advantages of low latency and wide coverage, has become a key technology for achieving seamless global communication. Phased array RF transceiver chips, as the core component of terminal-satellite communication, directly determine communication quality and user experience. Currently, consumer electronics-grade phased array chips face three major technological bottlenecks: First, limited channel size. Traditional chips typically support 32 to 64 channels, which is insufficient to meet the high-gain requirements of Ka or Ku bands. High-bandwidth services such as video calls require large-scale arrays of 128 or even 256 channels, but existing architectures lack linear scalability, requiring chip redesign for expansion, resulting in high R&D costs and long development cycles. Second, insufficient multi-beam capability. Traditional chips only support single-beam formation and cannot simultaneously track multiple LEO satellites. The transit window for a single LEO satellite is only about 7 minutes, leading to easy communication interruptions and difficulty in ensuring real-time service continuity. Third, a contradiction between power consumption and integration. Large-scale channels cause a surge in chip power consumption, while consumer electronics terminals have stringent requirements for battery life. Existing architectures lack refined power management mechanisms, failing to achieve a balance between high performance and low power consumption.

[0003] Furthermore, the fixed interconnect topology of traditional chips cannot adapt to the expansion needs of different channel scales, resulting in high signal transmission loss; beamforming uses a real-time computing architecture, leading to high weight calculation latency and affecting satellite tracking response speed. These problems severely restrict the popularization of low-Earth orbit satellite communication in the consumer electronics field, urgently requiring a phased array RF transceiver chip with scalable channels, low power consumption with multiple beams, and stable switching to meet the market demand for high-performance, low-cost satellite communication terminals. Summary of the Invention

[0004] The purpose of this invention is to solve the technical problems of limited channel expansion, insufficient multi-beam capability, and excessive power consumption of existing phased array RF transceiver chips. It provides a multi-beam phased array RF transceiver chip that supports 128 or 256 scalable channels. Through the collaborative design of tile-type scalable architecture, time-division multiplexing multi-beam generation, and dynamic power management, it achieves the technical goals of flexible channel expansion, simultaneous tracking of multiple satellites, and stable operation with low power consumption.

[0005] The chip of this invention comprises four core components, each with optimized synergistic functions: 1. Phased array subarray module: As the basic unit for channel expansion, each module integrates 16 complete transmit and receive channels. Each channel includes a low-noise amplifier, power amplifier, phase shifter, attenuator, and reconfigurable matching network. The reconfigurable matching network supports fast switching between Ku or Ka bands to adapt to different low-Earth orbit satellite communication needs. The number of subarray modules can be flexibly configured to 8 or 16, corresponding to a scale of 128 channels or 256 channels to meet the performance requirements of different terminals.

[0006] 2. Expandable interconnect interface: Located at the edge of the subarray module, it adopts the LVDS high-speed serial bus protocol with a data transmission rate of no less than 10 Gbps. It supports automatic switching between star and daisy chain topologies. When there are 8 or fewer subarray modules, the star topology is used to ensure low-latency transmission; when there are more than 8, it automatically switches to daisy chain topology to reduce the burden on the central processing unit interface and realize efficient cascading expansion of subarray modules.

[0007] 3. Central beam processor: It is connected to each subarray module in a star topology. The core includes a multi-beamforming matrix and a weight calculation unit. It adopts a time-division multiplexing architecture, with multiple beams sharing the weight calculation unit. The weight calculation speed is linearly related to the number of beams. It can generate at least 8 independent and controllable beams at the same time, supporting the simultaneous tracking of multiple low-orbit satellites and achieving seamless switching between pre-construction and post-disconnection.

[0008] 4. Dynamic Channel Management Unit: Composed of a service identification module and a power state machine. The service identification module analyzes the service type identifier issued by the baseband processor to accurately determine whether the current service is a video call, file transfer, or standby. The power state machine divides the power consumption into four levels: working, standby, hibernation, and deep hibernation. It automatically switches according to the service identification result, dynamically activating or deactivating the sub-array module. Idle modules enter a zero-power state, which greatly reduces the chip power consumption. The standby power consumption is reduced by more than 90% compared with traditional chips.

[0009] This invention achieves linear channel expansion through a tile-based architecture, enabling switching from 128 to 256 channels without redesigning the chip; its multi-beam parallel processing capability allows simultaneous tracking of multiple satellites, solving the communication interruption problem caused by short satellite transit windows; and its dynamic power management mechanism solves the power consumption problem of large-scale channels, balancing high performance and low power consumption, and adapting to the application needs of consumer electronics terminals. Attached Figure Description

[0010] Figure 1 Chip overall architecture diagram Note: This section demonstrates the core components and interconnections of the chip, showcasing a tile-based scalable architecture.

[0011] Drawing requirements: Draw the outline of a rectangular chip from a top-down perspective. Inside, draw 16 phased array sub-modules in a 4×4 array (labeled 101). Label the edges of the modules with expandable interconnect interfaces (labeled 102). Draw the central beam processor (labeled 103) at the center of the chip, connecting it to all sub-modules with star-shaped lines labeled "Star Connection". Draw the dynamic channel management unit (labeled 104) on one side of the chip, connecting it to the central beam processor with bidirectional arrows labeled "Command or Status Interaction". The overall layout should be clear, the dimensions of each module should be proportionate, and the labeling text should be concise and clear.

[0012] Figure 2 Internal structure block diagram of phased array sub-array module Description: This section shows the internal composition, channel layout, and signal transmission path of the subarray module.

[0013] Drawing requirements: Draw the outline of the rectangular subarray module, with 16 transceiver channels arranged in a 4×4 array (labeled 201). Channels are represented by small rectangles and evenly distributed. Within each transceiver channel, draw the low-noise amplifier (labeled 202), phase shifter (labeled 203), attenuator (labeled 204), power amplifier (labeled 205), and reconfigurable matching network (labeled 206) in series. Use arrowed lines to indicate the signal transmission direction. Draw the local control unit (labeled 207) in the corner of the module and connect it to all transceiver channels with lines, labeled "Channel Calibration or Weight Loading". All components should be clearly labeled, and the signal flow should be intuitive.

[0014] Figure 3 Dynamic Channel Management Unit Power Consumption State Transition Diagram Note: This demonstrates the division of the four power consumption states and the relationship between them.

[0015] Drawing requirements: Use four independent rectangles to label the working state (label 301), standby state (label 302), hibernation state (label 303), and deep hibernation state (label 304), respectively. The rectangles should be of the same size and evenly distributed. Use arrowed lines to indicate the transition relationships between the states, and indicate the transition conditions next to the arrows, such as "reduced service traffic", "no service requests", "long period of no service", and "wake-up command". Below each state box, indicate the number of activated sub-modules and their power consumption characteristics, such as "all activated (high power consumption)", "2 activated (low power consumption)", "0 activated (core low power consumption)", and "wake-up listening only (lowest power consumption)". The lines should be smooth, and the labels should not obscure the core content.

[0016] Figure 4 Schematic diagram of two topologies for scalable interconnect interfaces Note: This section demonstrates the composition and applicable scenarios of two topologies: star and daisy chain.

[0017] Drawing requirements: The diagrams are divided into Figure 4a (star topology) and Figure 4b (daisy-chain topology), arranged side-by-side. In Figure 4a, the central beam processor (labeled 401) is drawn in the center, surrounded by 8 phased array sub-modules (labeled 402). Each module is connected to the central beam processor by a straight line. The diagrams are labeled "8 or fewer sub-modules" and "star topology." In Figure 4b, 16 phased array sub-modules (labeled 402) are drawn in series to form a chain structure. The first and last modules are connected to the central beam processor (labeled 401). The diagrams are labeled "more than 8 sub-modules" and "daisy-chain topology." Both topologies are labeled with scalable interconnect interfaces (labeled 403), indicated by small circles distributed along the edges of the sub-modules. The overall structure should be symmetrical, with clear lines and accurate labeling. Detailed Implementation

[0018] The invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, certain well-known parts may not be shown in the drawings. Many specific details of the invention, such as the structure of the device, materials, process parameters, etc., are described below to provide a clearer understanding of the invention. However, as those skilled in the art will understand, the invention can be implemented without following these specific details.

[0019] This embodiment takes a 256-channel multi-beam phased array RF transceiver chip as an example to describe the specific implementation of the present invention in detail. The 128-channel implementation can be achieved by reducing the number of phased array subarray modules, and its core architecture and working principle are the same as those in this embodiment.

[0020] like Figure 1 As shown, the chip in this embodiment is manufactured using a 28nm CMOS process, with an overall size of 12 mm × 12 mm. It operates at 1.2V or 2.5V, has a maximum transmit power of +10 dBm / channel, a receive noise figure of 3.5 dB, and consumes 4.8 W when all 256 channels are operating, while consuming only 0.3 W in standby mode, representing a standby power reduction of over 90%. The chip includes 16 phased array sub-modules 101, an expandable interconnect interface 102, a central beam processor 103, and a dynamic channel management unit 104. The 16 sub-modules are arranged in a 4×4 tile array. The expandable interconnect interface 102 is distributed at the edges of each sub-module. The central beam processor 103 is located at the center of the chip and is connected to all sub-modules in a star topology. The dynamic channel management unit 104 communicates bidirectionally with the central beam processor to enable command issuance and status feedback.

[0021] like Figure 2As shown, each phased array subarray module 101 contains 16 transceiver channels 201, arranged in a 4×4 array. Within each transceiver channel 201, a low-noise amplifier 202, a phase shifter 203, an attenuator 204, a power amplifier 205, and a reconfigurable matching network 206 are connected in series. The reconfigurable matching network 206 can quickly switch between the Ka band (28GHz) and the Ku band (12GHz) to adapt to the communication needs of different low-Earth orbit satellites. The local control unit 207 in the subarray module is connected to all 16 transceiver channels and is responsible for real-time calibration and beam weight loading for each channel to ensure the consistency and accuracy of signal processing for each channel, with calibration errors controlled within ±0.1dB.

[0022] like Figure 3 As shown, the power state machine of the dynamic channel management unit 104 is divided into four states: In working state 301, all 16 subarray modules are activated, and all 256 channels operate at full load, suitable for high-bandwidth, high-demand services such as video calls; in standby state 302, only 2 subarray modules (32 channels) are activated, scanning satellite signals in turn, while the remaining 14 subarray modules enter a zero-power state, suitable for standby scenarios without real-time data transmission; in hibernation state 303, all transceiver channels are shut down, retaining only the low-power monitoring function of the central beam processor and the expandable interconnect interface, suitable for scenarios with short-term no service requests; in deep hibernation state 304, except for the wake-up monitoring module of the expandable interconnect interface, the rest of the chip is shut down, minimizing power consumption, suitable for scenarios with long-term no satellite communication needs; the states automatically transition based on the judgment result of the service identification module, with a transition delay of less than 10 ms, ensuring precise matching of power consumption and service requirements.

[0023] like Figure 4 As shown, in this embodiment, the number of subarray modules exceeds 8. The expandable interconnect interface 102 automatically switches to a daisy-chain topology (Figure 4b). The 16 subarray modules are connected in series to form a chain network. The first and last subarray modules are connected to the central beam processor 103 to ensure efficient transmission of signals and commands, with a data transmission rate stable at 10 Gbps. If the number of subarray modules is reduced to 8, the interface will automatically switch to a star topology (Figure 4a). All 8 subarray modules are directly connected to the central beam processor, further reducing signal transmission delay to less than 5 ns.

[0024] The central beam processor 103 includes a multi-beamforming matrix, a weight calculation unit, and a beam weight buffer. The beam weight buffer pre-stores beam weight coefficients calculated based on satellite ephemeris, eliminating the need for real-time calculation and reducing beam switching latency. The multi-beamforming matrix adopts a time-division multiplexing architecture, calculating the weights of 8 beams sequentially within a single clock cycle at a clock frequency of 100 MHz. The beam weight update rate reaches 390 kHz, enabling the simultaneous generation of 8 independently controllable beams and simultaneous tracking of 8 low-Earth orbit satellites. The switching time is less than 50 ms, ensuring seamless switching for real-time services such as video calls, with a data packet loss rate of less than 0.01%.

[0025] The scope of protection of this invention is not limited to the above embodiments. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A scalable multi-beam phased array radio frequency transceiver chip supporting 128 and 256 channels, characterized in that, It includes phased array subarray modules, scalable interconnect interfaces, a central beam processor, and a dynamic channel management unit; the number of phased array subarray modules is 8 or 16, corresponding to a total number of channels of 128 or 256. Each subarray module contains 16 transmit and receive channels, and the channels integrate low-noise amplifiers, power amplifiers, phase shifters, attenuators, and reconfigurable matching networks, which can switch between Ka or Ku frequency bands.

2. The multi-beam phased array radio frequency transceiver chip according to claim 1, characterized in that, The scalable interconnect interface adopts the LVDS high-speed serial bus with a data rate of ≥10 Gbps. It supports automatic switching between star and daisy-chain topologies. When there are 8 or fewer subarray modules, it uses a star topology, and when there are more than 8, it uses a daisy-chain topology, enabling subarray cascading expansion.

3. The multi-beam phased array radio frequency transceiver chip according to claim 1, characterized in that, The central beam processor is connected to the subarray module in a star topography. It contains a multi-beamforming matrix and a weight calculation unit. It adopts a time-division multiplexing architecture and can generate at least 8 independent and controllable beams at the same time, supporting the simultaneous tracking of multiple low-orbit satellites.

4. The multi-beam phased array radio frequency transceiver chip according to claim 1, characterized in that, The dynamic channel management unit includes a service identification module and a four-level power consumption state machine. It can dynamically activate or deactivate sub-array modules according to service requirements. Idle modules enter a zero-power state, reducing standby power consumption by more than 90%.

5. The multi-beam phased array radio frequency transceiver chip according to any one of claims 1 to 4, characterized in that, The chip is manufactured using 28 nm CMOS or 22 nm FD-SOI processes, with a maximum transmit power of +10 dBm / channel and a receive noise figure of 3.5 dB. It is suitable for low-Earth orbit satellite communication terminals, mobile phone direct satellite connection equipment, and attachable satellite communication accessories.

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