A si-ge anti-radiation beamforming chip for 256-beam full-digital phased array

Abstract

This invention belongs to the field of phased array chip technology, specifically a SiGe radiation-hardened beamforming chip for a 256-beam all-digital phased array. This chip is integrated using SiGe BiCMOS technology and includes a transceiver channel array, a beam weighting calculation unit, a beamforming network, a control interface, and a radiation-hardening module. The transceiver channel integrates an LNA, PA, phase shifter, attenuator, and T / R switch. The beam weighting calculation unit generates amplitude and phase weighting coefficients, the beamforming network achieves parallel synthesis of 256 beams, and the radiation-hardening module improves adaptability to the space radiation environment through triple-mode redundancy and ring oscillator monitoring technology. This chip has high single-chip integration and supports multi-chip cascading expansion, significantly reducing the size, weight, and power consumption of spaceborne phased arrays, and adapting to the application requirements of satellite communication payloads.

Description

Technical Field

[0001] This invention belongs to the field of phased array integrated circuit technology, specifically relating to the design of a beamforming chip for a spaceborne all-digital phased array, particularly suitable for satellite communication payloads. This chip focuses on the requirement for large-scale multi-beamforming with 256 beams, employing SiGe BiCMOS technology and radiation-hardened design to address the weaknesses of traditional CMOS chips in radiation resistance and the limited beam count of existing SiGe phased array chips. It achieves high integration, high reliability, and low power consumption beamforming functionality, adapting to Ku / Ka band spaceborne phased array applications. Background Technology

[0002] Spaceborne phased array antennas need to operate stably in the harsh space radiation environment, which includes total dose effect and single-event effect. Traditional CMOS chips are sensitive to radiation and prone to functional failure, making it difficult to meet the reliability requirements of spaceborne applications. SiGe BiCMOS technology has the advantages of natural radiation resistance and excellent high-frequency performance, making it the preferred technology for spaceborne phased array chips. However, most existing SiGe phased array chips only support small-scale formation of 4 or 8 beams. For large-scale all-digital phased arrays with 256 beams, multiple chips need to be combined, resulting in complex system architecture, large size, heavy weight, and high power consumption, which contradicts the requirements of miniaturization, lightweight, and low power consumption of spaceborne equipment.

[0003] Meanwhile, large-scale phased arrays place higher demands on the integration, beam parallel processing capability, and radiation resistance of beamforming chips. Existing chips lack efficient architecture design for 256-beam parallel synthesis, and their radiation hardening measures are not comprehensive enough. They cannot balance beamforming performance with space environment adaptability, which has become a key technical bottleneck restricting the development of spaceborne 256-beam all-digital phased arrays. Summary of the Invention

[0004] The purpose of this invention is to propose a SiGe radiation-resistant beamforming chip for a 256-beam all-digital phased array, which solves the technical problems of weak radiation resistance of traditional CMOS chips, small number of beams and low system integration of existing SiGe phased array chips, and achieves reliable adaptation of single-chip 256-beam parallel formation to the space radiation environment.

[0005] This chip is manufactured using SiGe BiCMOS technology. Its core technology combines a highly integrated architecture with a radiation-hardened design: the transceiver channel array contains 64 or 128 independent transceiver channels, each channel integrating an LNA, PA, phase shifter, attenuator, and T / R switch. It supports time-division multiplexing or analog beamforming extension to meet the application requirements of phased arrays of different sizes. The phase shifter and attenuator are controlled by 6-bit digital control to ensure the accuracy of phase and amplitude control.

[0006] The beamweighting calculation unit consists of an ARM Cortex-M0 processor and a dedicated hardware accelerator. It receives beam pointing commands from an external SPI interface and calculates the amplitude and phase weighting coefficients of each channel in real time. The weights are stored in on-chip triple-modulus redundant hardened SRAM to ensure data reliability. The beamforming network adopts a butterfly FFT architecture or a matrix multiplication architecture, implementing complex weighted summation with 64 inputs and 256 outputs in three stages. It can complete the real-time synthesis of 256 beams at a 500MHz clock with a delay of less than 1μs.

[0007] The radiation hardening module employs a dual hardening strategy: all configuration registers utilize a triple-modulus redundancy design, with a majority voter set every three D flip-flops to resist single-event upsets; the clock network integrates a ring oscillator monitoring circuit, automatically switching to the backup clock when clock glitches caused by single-event transients are detected, ensuring clock signal stability. The chip supports multi-chip cascading, exchanging beam data via high-speed serial interfaces such as JESD204B to achieve larger-scale phased array expansion. Built-in self-test circuitry enables on-orbit self-testing and calibration, with total power consumption less than 5W in 256-beam mode.

[0008] This chip integrates 256 beamforming functions on a single chip, significantly reducing the system complexity, size, and power consumption of spaceborne phased arrays. The SiGe process and radiation-hardened design ensure operational reliability in the space environment, meeting the application requirements of satellite communication payloads. Attached Figure Description

[0009] Figure 1 shows the functional block diagram of the SiGe radiation-resistant beamforming chip; Figure 2 is a schematic diagram of the transceiver channel circuit. Figure 3 is a schematic diagram of the beamforming network architecture. Explanation of reference numerals in the attached figures

[0010] 101: Transceiver Channel Array 102: Beam Weighting Calculation Unit 103: Beamforming Network 104: Control Interface 105: Radiation Hardening Module 106: Built-in Self-Test Circuit 201: Antenna Interface; 202: T / R Switch; 203: Low Noise Amplifier (LNA); 204: Phase Shifter; 205: Attenuator; 206: Power Amplifier (PA); 207: Signal Interface 301: 64 signal inputs; 302: First-stage butterfly FFT module; 303: Second-stage matrix multiplication module; 304: Third-stage accumulation module; 305: 256 beam outputs. Detailed Implementation

[0011] The invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are indicated by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown in the drawings.

[0012] Many specific details of the invention, such as process parameters, hardware selection, and performance indicators, are described below to provide a clearer understanding of the invention. However, as those skilled in the art will understand, the invention may be implemented without following these specific details.

[0013] Figure 1 shows a functional block diagram of the SiGe radiation-resistant beamforming chip. As shown in Figure 1, the beamforming chip of this invention includes a transceiver channel array 101, a beam weighting calculation unit 102, a beamforming network 103, a control interface 104, a radiation hardening module 105, and a built-in self-test circuit 106. The transceiver channel array 101 is an array of 64 transceiver channels, each channel integrating an LNA, PA, phase shifter, attenuator, and T / R switch, covering the 17-31GHz Ka band. The beam weighting calculation unit 102 includes an ARM Cortex-M0 processor and a dedicated hardware accelerator to calculate the weighting coefficients of each channel in real time. The beamforming network 103 is a 64-input, 256-output complex matrix multiplier, supporting parallel synthesis of 256 beams. The control interface 104 is an SPI interface that receives external control commands and configuration parameters. The radiation hardening module 105 includes a triple-modulus redundant register and a ring oscillator monitoring circuit to achieve radiation hardening. The built-in self-test circuit 106 is used for on-orbit self-testing and calibration. The modules work together to achieve efficient and reliable formation of 256 beams, with a total chip power consumption of less than 5W.

[0014] Figure 2 shows a schematic diagram of the transceiver channel circuit. As shown in Figure 2, the transceiver channel in this invention adopts a half-duplex mode, including an antenna interface 201, a T / R switch 202, an LNA (low-noise amplifier) ​​203, a phase shifter 204, an attenuator 205, a PA (power amplifier) ​​206, and a signal interface 207. In the receive mode, the antenna interface 201 receives the radio frequency signal, which is switched to the receive branch by the T / R switch 202. After low-noise amplification by the LNA 203, the signal amplitude and phase are adjusted sequentially by the phase shifter 204 (6-bit phase control) and the attenuator 205 (6-bit amplitude control), and then output to the beamforming network through the signal interface 207. In the transmit mode, the signal output by the beamforming network is input through the signal interface 207, adjusted sequentially by the attenuator 205 and the phase shifter 204, and then amplified by the PA 206. Finally, it is switched to the antenna interface 201 for transmission by the T / R switch 202. This channel achieves transmit / receive function switching through integrated design, and 6-bit digital control ensures amplitude and phase adjustment accuracy.

[0015] Figure 3 shows a schematic diagram of the beamforming network architecture. As shown in Figure 3, the beamforming network in this invention adopts a butterfly FFT architecture, including 64 signal inputs 301, a first-stage butterfly FFT module 302, a second-stage matrix multiplication module 303, a third-stage accumulation module 304, and 256 beam outputs 305. The 64 signal inputs 301 come from the adjusted signals of the transceiver channel array; the first-stage butterfly FFT module 302 performs FFT transformation on the 64 input signals to achieve frequency domain decomposition of the signals; the second-stage matrix multiplication module 303 adopts a 64×256 complex matrix multiplication architecture to multiply the frequency domain signals with the beam weighting coefficient matrix; the third-stage accumulation module 304 performs accumulation operation on the multiplication results to generate 256 independent beam signals; and the 256 beam outputs 305 output the synthesized beam signals to the subsequent processing unit. This architecture can perform real-time synthesis at a 500MHz clock with a delay of less than 1μs, meeting the requirements for parallel formation of 256 beams.

[0016] In this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that the included set of elements (such as a process, method, article, or apparatus) includes not only those elements but also other elements not expressly listed. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements besides those included.

[0017] In this invention, the embodiments do not exhaustively describe all details, nor are they limited to the specific embodiments described. Many variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to make good use of the invention and modifications based on it. The invention is limited only by the claims and their full scope and equivalents. The invention will now be described in more detail with reference to the accompanying drawings. In the various drawings, the same elements are represented by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. Furthermore, some well-known parts may not be shown in the drawings.

Claims

1. A SiGe radiation-hardened beamforming chip for a 256-beam all-digital phased array, characterized in that, It includes a transceiver channel array, a beam weighting calculation unit, a beamforming network, a control interface, and a radiation hardening module. The transceiver channel array contains multiple transceiver channels, each integrating an LNA, PA, phase shifter, attenuator, and T / R switch. The beam weighting calculation unit generates amplitude and phase weighting coefficients for each channel. The beamforming network weights and sums the signals from multiple channels, outputting 256 beams. The control interface receives external control commands and configuration parameters. The radiation hardening module enhances the chip's radiation resistance.

2. The chip according to claim 1, characterized in that, The number of transmit and receive channels is 64 or 128, supporting time-division multiplexing or analog beamforming extension. The phase shifter and attenuator are digitally controlled, with 6-bit phase control accuracy and 6-bit amplitude control accuracy.

3. The chip according to claim 1, characterized in that, The beamforming network employs a butterfly FFT architecture or a matrix multiplication architecture, supports parallel computation of 256 beams, and has a latency of less than 1μs.

4. The chip according to claim 1, characterized in that, The radiation hardening module includes a triple-mode redundancy register and a ring oscillator monitoring circuit, providing triple-mode redundancy protection for critical registers and monitoring single-particle transients for the clock tree.

5. The chip according to claim 1, characterized in that, It adopts SiGe BiCMOS process, with HBT characteristic frequency fT≥200GHz, CMOS gate length≤180nm, and operating frequency covering Ku / Ka band (10-30GHz).

6. The chip according to claim 1, characterized in that, It supports multi-chip cascading and exchanges beam data through a high-speed serial interface to achieve larger-scale phased array expansion. The total power consumption in 256-beam mode is less than 5W.

7. The chip according to claim 1, characterized in that, It also includes a built-in self-test circuit for on-orbit self-testing and calibration, ensuring the reliability of the chip's on-orbit operation.

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