Hybrid rate optical input / output interface and co-pack structure

Abstract

The application provides a mixed rate optical input and output interface and a co-encapsulation structure, and relates to the technical field of optical communication. The mixed rate optical input and output interface comprises an electrical interface unit, which is used for connecting with an external chip and adopts a low-speed interface protocol; and an optical engine unit, which is used for connecting with an external optical fiber array unit and adopts a high-speed serial interface rate. The electrical interface unit comprises a rate conversion module, which is used for converting multi-channel electrical signals of the low-speed interface into multi-channel electrical signals of the high-speed serial interface, or converting multi-channel electrical signals of the high-speed serial interface into multi-channel electrical signals of the low-speed interface. The electrical interface unit and the optical engine unit are connected through high-speed serial interface signal lines. The mixed rate optical input and output interface and the co-encapsulation structure provided by the application have the advantages of high bandwidth density, high yield and high optical integration.

Description

Technical Field

[0001] This application relates to the field of optical communication technology, and more specifically, to a mixed-rate optical input / output interface and co-package structure. Background Technology

[0002] Optical interconnect is a key technology for data centers and computing clusters. It enables a large number of servers and computing units to work together to build high-performance, large-scale computing clusters. With the rapid development of artificial intelligence (AI), the demand for AI computing power is growing exponentially, placing extremely high demands on the interconnect capabilities of AI computing clusters, especially in front-end network interconnect, back-end scale-out network interconnect, and back-end scale-up network interconnect.

[0003] Scale-up networks primarily enable direct interconnection between GPU chips, supporting pooling and resource sharing between computing and storage chips. Expanding the scale-up network using optical interconnect technology can significantly enhance the computing power of AI computing clusters. Optical input and output (OIO) interfaces are widely considered a key technology for scale-up network interconnection, and improving OIO bandwidth density has become a hot research topic in the industry.

[0004] However, existing OIO technologies struggle to simultaneously meet the requirements of high bandwidth density, high yield, and low fiber count. Summary of the Invention

[0005] The purpose of this application is to provide a hybrid rate optical input / output interface and co-package structure to solve the problem that existing OIOs cannot simultaneously meet the requirements of high bandwidth density, high yield, and low fiber count.

[0006] To achieve the above objectives, the technical solutions adopted in the embodiments of this application are as follows: On one hand, embodiments of this application provide a hybrid rate optical input / output interface, the hybrid rate optical input / output interface comprising: The electrical interface unit is used to connect to external chips and uses a low-speed interface protocol. The optical engine unit is used to connect to the external fiber optic array unit and adopts a high-speed serial interface rate. The electrical interface unit includes a rate conversion module, which is used to convert multiple electrical signals from the low-speed interface into multiple electrical signals from the high-speed serial interface, or to convert multiple electrical signals from the high-speed serial interface into multiple electrical signals from the low-speed interface; the electrical interface unit and the optical engine unit are connected via a high-speed serial interface signal line.

[0007] Optionally, the electrical interface unit further includes: The UCIe interface is connected to the rate conversion module and is used to connect to external chips. A high-speed SerDes interface is connected to the rate conversion module and is also used to connect to the optical engine unit; The rate conversion module is also used to realize the data rate conversion between the UCIe interface and the high-speed SerDes interface.

[0008] Optionally, the electrical interface unit further includes a functional unit, which is connected to the UCIe interface and the high-speed SerDes interface respectively.

[0009] Optionally, the functional unit is a network protocol processing unit or a forward error correction unit.

[0010] Optionally, the optical engine unit includes an optical chip and an electrical chip. The optical chip integrates an electro-optic modulator and a photodetector, and the electrical chip includes a driver and a transimpedance amplifier. The signal transmitted by the optical engine unit is amplified by the driver and then drives the electro-optic modulator to convert it into an optical signal for output. The optical signal received by the optical engine unit is converted into an electrical signal by photoelectric detection, and then amplified by a transimpedance amplifier before being sent to the receiving end of the optical engine unit.

[0011] Optionally, the optical engine unit includes an optical chip and an electrical chip, wherein the optical chip integrates an electro-optic modulator and a photodetector, and the electrical chip includes a transimpedance amplifier; wherein, The transmitting signal of the optical engine unit is converted into an optical signal output by an optical modulator; The optical signal received by the optical engine unit is converted into an electrical signal by photoelectric detection, and then amplified by a transimpedance amplifier before being sent to the receiving end of the optical engine unit.

[0012] On the other hand, this application embodiment also provides a co-packaging structure, which includes an external chip and the above-mentioned mixed-rate optical input / output interface. The mixed-rate optical input / output interface and the external chip are co-packaged on the same substrate using optoelectronic co-packaging technology.

[0013] Optionally, the hybrid rate optical input / output interface adopts a 3D stacked package structure; The signal connection between the electrical interface unit and the external chip is achieved through substrate traces, TMV, and RDL; or the signal connection between the electrical interface unit and the external chip is achieved through substrate traces, TSV, and RDL.

[0014] Optionally, the bottom electrical interface of the mixed-rate optical input / output interface includes a first part and a second part. The first part is connected to the substrate and is used to transmit high-speed signals; the second part is used to connect to the power supply and transmit low-speed monitoring signals.

[0015] Optionally, the substrate covers only a first portion of the bottom area of ​​the package, and the second portion is connected to the PCB board.

[0016] Compared with the prior art, this application has the following advantages: This application provides a hybrid-rate optical input / output interface and co-package structure. The hybrid-rate optical input / output interface includes: an electrical interface unit for connecting to an external chip, employing a low-speed interface protocol; and an optical engine unit for connecting to an external fiber optic array unit, employing a high-speed serial interface rate. The electrical interface unit includes a rate conversion module, which converts multiple electrical signals from the low-speed interface into multiple electrical signals from the high-speed serial interface, or vice versa. The electrical interface unit and the optical engine unit are connected via a high-speed serial interface signal line.

[0017] This application uses a low-speed interface in the electrical interface unit and a high-speed serial interface in the optical engine unit, and performs rate conversion internally. This retains the advantages of high sideband density of the UCIe interface, and also leverages the advantages of fewer high-speed SerDes channels, fewer PIC integration channels, and high yield. It effectively overcomes the problems of low bandwidth density and high optical integration difficulty in the prior art.

[0018] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of the first application scenario of optical input / output interfaces in existing technology.

[0021] Figure 2 This is a schematic diagram of the first type of connection for optical input / output interfaces in the prior art.

[0022] Figure 3This is a schematic diagram of the second application scenario of optical input / output interfaces in existing technologies.

[0023] Figure 4 This is a schematic diagram of a second type of connection for optical input / output interfaces in the prior art.

[0024] Figure 5 This is a schematic diagram illustrating an application scenario for the hybrid rate optical input / output interface provided in this application embodiment.

[0025] Figure 6 This is a schematic diagram of a mixed-rate optical input / output interface provided in an embodiment of this application.

[0026] Figure 7 This is a schematic diagram of a light engine unit provided in an embodiment of this application.

[0027] Figure 8 This is another schematic diagram of the optical engine unit provided in an embodiment of this application.

[0028] Figure 9 This is a schematic diagram of a co-packaging structure provided in an embodiment of this application.

[0029] Figure 10 This is another schematic diagram of the co-packaging structure provided in the embodiments of this application.

[0030] In the picture: 100 - Mixed-rate optical input / output interface; 110 - Electrical interface unit; 111 - UCIe interface; 112 - Functional unit; 113 - Rate conversion module; 114 - High-speed SerDes interface; 120 - Optical engine unit; 121 - Optical chip; 122 - Electrical chip. Detailed Implementation

[0031] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0032] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0033] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, in the description of this application, terms such as "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0034] It should be noted that in this paper, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0035] As described in the background section, optical interconnect is a key technology for data centers and computing clusters. Optical interconnect enables a large number of servers to form a network, allowing servers and computing units to work collaboratively to build the high-performance, large-scale computing clusters required by society. Currently, optical interconnect in data centers and computing clusters mainly uses optical modules. Because optical modules are relatively large, their bandwidth density requirements are not high. However, with the emergence of AI (Artificial Intelligence) in recent years, the demand for AI computing power has grown rapidly, almost doubling every three to four months. This has driven a huge demand for AI infrastructure, namely AI computing clusters. AI computing is large-scale parallel computing based on GPU (Graphics Processing Unit) computing chips. AI computing clusters have large-scale, comprehensive interconnection needs, with extremely high requirements for interconnection, including interconnection of front-end networks, back-end scale-out networks, and back-end scale-up networks.

[0036] Scale-up networks are interconnect networks between chips, primarily between GPUs. They enable direct interconnection between GPU chips, facilitating pooling and resource sharing between computing chips (GPUs) and memory chips (especially HBM - High Bandwidth Memory). Expanding the scale of scale-up networks using optical interconnect technology can significantly enhance the computing power of AI computing clusters. Due to chip area limitations, scale-up networks have high bandwidth density requirements. Currently, scale-up networks use electrical interconnect technology, but are moving towards optical interconnect. Optical Input and Output (OIO) interfaces are widely considered a key technology for scale-up network interconnection. Improving the bandwidth density of OIO, including both electrical and optical bandwidth density, is a hot topic in industry technology and research.

[0037] like Figure 1The diagram illustrates what is commonly referred to in the industry as the Fast and Narrow solution. The core computing functions of AI acceleration computing chips (XPUs, including GPUs, TPUs, etc.) are provided by logic processing units, with external interfaces via high-speed SerDes (only the right side of the diagram shows SerDes; in actual applications, other sides may also have high-speed SerDes external interfaces). The current data rate of high-speed SerDes has reached 224Gb / s. The optical input / output interface interfaces with the SerDes on one side and converts electrical signals into optical signals via photoelectric conversion on the other, then interconnects with the external network through a fiber optic array unit (FAU), converting the electrical interface back into an optical interface. This optical input / output interface achieves transparent conversion between optical and electrical signals; that is, at the transmitting end, it converts N x R (N SerDes, each with a rate of R) electrical signals into optical signals, and at the receiving end, it converts N x R optical signals back into electrical signals, as shown below. Figure 2 As shown. Due to the high single-channel rate of high-speed SerDes, fewer channels are required within a given interface bandwidth, resulting in a relatively simple photonic integrated circuit (PIC) and a high yield. However, because SerDes occupy a relatively large space, the side bandwidth density of this scheme can only reach approximately 1Tb / s / mm.

[0038] Figure 3 Another approach is illustrated, commonly known in the industry as the Slow and Wide approach. In this approach, the AI ​​acceleration computing chip XPU uses a low-speed UCIe (Universal Chiplet Interconnect Express) interface (only the right side of the diagram shows UCIe; in reality, other sides may also have UCIe interfaces). The optical input / output interface of this approach interfaces with the UCIe on one side and converts electrical signals into optical signals via photoelectric conversion, then interconnects with the external network through a fiber optic array unit (FAU), converting the electrical interface back into an optical interface. This optical input / output interface achieves transparent conversion between optical and electrical signals; that is, at the transmitting end, it converts M x B (M UCIe channels, each with a rate of B) electrical signals into optical signals, and at the receiving end, it converts M x B optical signals back into electrical signals, such as... Figure 4 As shown, UCIe achieves a side bandwidth density more than 10 times higher than high-speed SerDes, reaching 10Tb / s / mm. Due to UCIe's relatively low rate, it requires fewer paths for the same bandwidth. Figure 1There are many more such methods, meaning M is much larger than N. Given the current difficulty in achieving large-scale integration of PICs, PIC yields are very low, making productization extremely challenging. Furthermore, the increased number of optical paths also creates significant difficulties for fiber optic cabling. Although WDM (Wavelength Division Multiplexing) technology can reduce the number of fibers, the MUX (multiplexer) and DEMUX (demultiplexer) of WDM introduce additional losses, resulting in significantly higher requirements for lasers.

[0039] In view of this, to resolve the above issues, please refer to Figure 5 and Figure 6 This application provides a hybrid rate optical input / output interface. As an optional implementation, the hybrid rate optical input / output interface 100 includes: The electrical interface unit 110 is used to connect to an external chip and adopts a low-speed interface protocol; the optical engine unit 120 is used to connect to an external fiber optic array unit and adopts a high-speed serial interface rate. The electrical interface unit 110 includes a rate conversion module 113, which is used to convert multiple electrical signals from the low-speed interface to multiple electrical signals from the high-speed serial interface, or to convert multiple electrical signals from the high-speed serial interface to multiple electrical signals from the low-speed interface. The electrical interface unit 110 and the optical engine unit 120 are connected through a high-speed serial interface signal line.

[0040] The external chips mentioned in this application include, but are not limited to, computing chips and switching chips. The low-speed interface mentioned in this application can be a parallel or serial interface, such as a UCIe interface.

[0041] This application employs two different rate-level interface protocols simultaneously in the same hybrid rate optical input / output interface 100. Specifically, the electrical interface unit 110 uses a low-speed interface protocol for external chips (such as GPUs, TPUs, and other AI acceleration chips), while the optical engine unit 120 uses a high-speed serial interface rate for external fiber array units. A rate conversion module 113 is then set up to achieve bidirectional and dynamic electrical signal rate mapping and adaptation between the two.

[0042] Understandably, in existing technologies, electrical and optical interfaces are forced to adopt the same rate strategy, resulting in a trade-off between high density and high yield: If both electrical and optical interfaces use high-speed serial methods (such as 224 Gb / s SerDes), although the number of optical paths can be reduced and the yield of photonic integrated circuits (PICs) can be improved, the side bandwidth density can only reach about 1 Tb / s / mm due to the physical pin size and wiring density of SerDes, which cannot meet the urgent requirement of AI chip scale-up networks for >5 Tb / s / mm. If both electrical and optical interfaces use low-speed parallel methods (such as UCIe), although a side bandwidth density of >10 Tb / s / mm can be achieved by leveraging high pin multiplexing, the number of optical paths increases dramatically (M paths are much larger than N paths), severely exceeding the current silicon photonics process's capacity to handle modulator array uniformity, waveguide coupling accuracy, and thermal management capabilities, causing a sharp drop in PIC yield and making system fiber optic cabling impractical. The hybrid rate optical input / output interface 100 provided in this application can significantly reduce the number of physical channels required for optical interconnects and the integration complexity of optical chips 121 without sacrificing side bandwidth density, thereby achieving both high interconnect bandwidth and high manufacturing yield.

[0043] It should be noted that the low-speed interface protocol described in this application may refer to the Universal Chiplet Interconnect Express (UCIe) protocol, whose single-channel rate is typically 16~64 Gb / s, but achieves ultra-high total bandwidth through hundreds to thousands of parallel channels. The high-speed serial interface rate refers to the rate level supported by the high-speed serializer / deserializer (SerDes), such as 112 Gb / s or 224 Gb / s pulse amplitude modulation signals. The function of the rate conversion module 113 can be manifested as converting M UCIe electrical signals (each with a rate of B) into N high-speed SerDes electrical signals (each with a rate of R), satisfying M*B=N*R, where M is much larger than N and B is much smaller than R. This mathematical relationship shows that by increasing the single-channel rate R and reducing the number of channels N, the channel size required in the optical domain can be significantly reduced while maintaining the total bandwidth.

[0044] In this process, since the electrical interface unit 110 adopts the UCIe interface 111, its side bandwidth density is determined by the physical width W of the interface, thus achieving a very high side bandwidth density. Meanwhile, the optical engine unit 120 uses a high-speed SerDes rate, significantly reducing the number of optical modulators and detectors that actually need to be integrated. This greatly reduces the integration complexity and manufacturing difficulty of photonic integrated circuits, improves PIC yield, and correspondingly reduces the number of optical fibers and wiring space required. Therefore, this embodiment is not simply a splicing of two interfaces, but rather a reconstruction of the data path structure internally through the rate conversion module 113. This allows the electrical domain to inherit the high-density wiring advantages of UCIe, while the optical domain enjoys the low channel complexity advantages of SerDes, ultimately achieving a synergistic breakthrough in side bandwidth density and optical integration feasibility within a single interface.

[0045] As one implementation, the electrical interface unit 110 provided in this application further includes: a UCIe interface 111, connected to the rate conversion module 113 and used for connecting to an external chip; a high-speed SerDes interface 114, connected to the rate conversion module 113 and used for connecting to the optical engine unit 120; the rate conversion module 113 is also used to realize the data rate conversion between the UCIe interface 111 and the high-speed SerDes interface 114.

[0046] To increase on-chip interconnect bandwidth density, AI computing chips generally adopt the Universal Chip Interconnect Express (UCIe) protocol. This protocol transmits data in parallel through a large number of low-speed channels (e.g., 16~64 Gb / s per channel). Although it can achieve ultra-high total bandwidth, if its electrical signals are directly sent to the optical engine unit 120, a large number of modulators and detector arrays need to be integrated on the optical chip 121, which far exceeds the current silicon photonics process's tolerance limits for yield, power consumption, and heat distribution. If a high-speed serial interface is forcibly used to directly connect to external chips, the chip I / O architecture needs to be reconstructed, which is not only costly but also violates the industry ecosystem's extensive reliance on the UCIe standard interface.

[0047] Therefore, this application simultaneously incorporates a UCIe interface 111, a high-speed SerDes interface 114, and a rate conversion module 113 within the electrical interface unit 110 of the mixed-rate optical input / output interface 100, and enables these three components to work collaboratively according to a specific connection relationship. This achieves structural adaptation of the electrical domain protocol and rate within the interface, accepting high-density parallel electrical signal input from external chips while outputting high-speed serial electrical signals adapted to the optical domain integration capabilities to the optical engine unit 120. Through this configuration, while maintaining compatibility with the native electrical interfaces of AI computing chips (such as GPUs), high-number, low-rate parallel electrical signals are efficiently and with low overhead mapped to low-number, high-rate serial electrical signals to match the optical engine unit 120, providing structurally consistent and timing-controllable drive signals for subsequent photoelectric conversion.

[0048] It should be noted that the UCIe interface 111 mentioned in this application refers to the Universal Chiplet Interconnect Express (UCIe) interface, which is used to receive M parallel electrical signals from an external chip, with each signal having a rate of B; the high-speed SerDes interface 114 refers to the high-speed serializer / deserializer interface (SerDes interface), which is used to output N serial electrical signals to the optical engine unit 120, with each signal having a rate of R; the function of the rate conversion module 113 is to convert M UCIe electrical signals into N high-speed SerDes electrical signals, or to convert N high-speed SerDes electrical signals into M UCIe electrical signals, and to satisfy the total bandwidth conservation relationship M*B = N*R, where M is much larger than N and B is much smaller than R; that is, the rate conversion is not a simple scaling, but rather a significant reduction in the physical channel size required by the downstream optical domain without sacrificing information throughput by increasing the single-channel rate and compressing the number of channels.

[0049] As one implementation, the electrical interface unit 110 also includes a functional unit 112, which is connected to both the UCIe interface 111 and the high-speed SerDes interface 114. Exemplarily, the functional unit 112 can be a Network Protocol Processing Unit (CPSU) or a Forward Error Correction Unit (FEC Unit). The CPSU can perform routing resolution, flow control management, or protocol encapsulation on the data received via the UCIe interface 111 to adapt to the requirements of the optical interconnect network layer. The FEC Unit can inject error correction codes before the data enters the high-speed SerDes interface 114, and decode and correct errors after the optical signal generates errors during fiber optic transmission, thereby improving link reliability. The functional unit 112 is optional and can be enabled or bypassed depending on the system's different requirements for deterministic delay, bit error rate, or protocol flexibility.

[0050] It is evident that this application does not change the original electrical interface form of the external chip, nor does it require the optical engine unit 120 to adapt to a large number of low-speed channels. Instead, by embedding structured rate conversion and optional function processing capabilities inside the electrical interface unit 110, the mixed-rate optical input / output interface 100 becomes a protocol-aware device. Without increasing the burden of chip-side modification or sacrificing the feasibility of optical-side integration, it substantially breaks down the technical gap between AI computing chips and high-density optical interconnects.

[0051] Because the optical engine unit 120 needs to perform two tasks involving opposite directions but coupled performance: at the transmitting end, the voltage swing of the electrical signal from the high-speed SerDes interface 114 is limited. If it directly drives the electro-optic modulator (MOD), insufficient driving strength may lead to insufficient modulation depth, eye diagram closure, and increased bit error rate. At the receiving end, the current signal output by the photodetector (PD) is extremely weak (usually in the microampere range). If it is sent to the SerDes receiving circuit without effective amplification, it will not meet its input sensitivity requirements, causing link failure. In the existing technology, the driver (DRV) and the transimpedance amplifier (TIA) are usually fixedly integrated in the same electrical chip 122 or must share a package. There is a lack of space for functional decoupling and layout optimization according to the actual signal strength, power budget, and thermal distribution, resulting in poor solution adaptability, limited yield, and high upgrade costs.

[0052] Therefore, in order to rationally allocate the position and form of electrical amplification function in the process of driving the optical modulator with high-speed serial electrical signals to achieve stable optical emission and recovering weak optical signals into usable electrical signals after detection, so as to adapt to the optical interconnection requirements under different process nodes, different laser types and different power consumption constraints, this application adopts a discrete architecture in the optical engine unit 120 of the mixed rate optical input / output interface 100, in which optical chip 121 and electrical chip 122 work together. According to the different requirements of the system for driving capability and power consumption, the driver can be flexibly configured to be integrated on the electrical chip 122, so as to ensure photoelectric conversion performance while taking into account the flexibility of circuit design and chip integration efficiency.

[0053] Specifically, this embodiment uses a hybrid rate optical input / output interface 100 as the implementation device. Please refer to [link to relevant documentation]. Figure 7 The optical engine unit 120 includes an optical chip 121 and an electrical chip 122. The optical chip 121 integrates an electro-optic modulator and a photodetector. The electrical chip 122 includes a driver and a transimpedance amplifier. The driver and transimpedance amplifier can be integrated into the same chip or are two separate chips; this is not limited here. The transmitting signal of the optical engine unit 120 is amplified by the driver and then drives the electro-optic modulator to convert it into an optical signal for output. The optical signal received by the optical engine unit 120 is converted into an electrical signal by the photodetector, amplified by the transimpedance amplifier, and then sent to the receiving end of the optical engine unit 120.

[0054] It should be noted that the optical chip refers to a photonic integrated circuit (PIC), which is manufactured based on silicon photonics technology. It integrates an electro-optic modulator (MOD) for modulating electrical signals into optical signals and a photodetector (PD) for converting incident light signals into current signals. The electrical chip refers to the linear electrical signal amplifier that, together with the optical chip 121, constitutes the optical engine unit 120, including a driver (DRV) and a transimpedance amplifier (TIA). The driver is used to enhance the voltage and current driving capability of the high-speed SerDes electrical signal at the transmitting end, making it sufficient to linearly and efficiently control the phase or intensity of the electro-optic modulator. The transimpedance amplifier is used to convert the weak current signal output by the photodetector into a voltage signal with sufficient amplitude and controllable noise, so that the subsequent SerDes circuit can reliably identify and sample it.

[0055] And, please see Figure 8Alternatively, the optical engine unit 120 can be implemented in another way: its optical chip 121 still integrates an electro-optic modulator and a photodetector, but the electrical chip 122 only includes a transimpedance amplifier and does not include a driver; in this case, the transmitting signal of the optical engine unit 120 can be directly driven by the high-speed SerDes interface 114 to convert the electro-optic modulator into an optical signal output without being amplified by the driver; this method is suitable for situations where the SerDes output swing is high enough and the driving voltage requirement of the electro-optic modulator is low, such as when a low-voltage swing type modulator or a high-efficiency vertical-cavity surface-emitting laser (VCSEL) is used as the light source; while the optical signal received by the optical engine unit 120 is still converted into an electrical signal by the photodetector, and then amplified by the transimpedance amplifier before being sent to the receiving end of the optical engine unit 120.

[0056] Therefore, this embodiment does not require the driver to be present, but rather sets it as an optional configuration, so that the optical engine unit 120 can choose whether to integrate the driver in the electrical chip 122 according to the actual light source type (such as an external continuous-wave laser (CWLaser) or VCSEL), modulator structure (such as a Mach-Zehnder modulator or a micro-ring modulator), SerDes output capability and system power consumption target, thereby achieving a balance between functional integrity and design simplicity.

[0057] In summary, the mixed-rate optical input / output interface 100 provided in this application adopts a UCIe interface 111 for its electrical interface and a high-speed SerDes rate for its optical interface. It combines the advantages of existing technologies, namely, the high side bandwidth density of UCIe and the advantages of high-speed channels with fewer channels and fewer PIC integrated channels, resulting in higher yield.

[0058] Based on the above implementation, this application embodiment also provides a co-packaging structure, which includes an external chip and a mixed-rate optical input / output interface 100 as described above. The mixed-rate optical input / output interface 100 and the external chip are co-packaged on the same substrate using optoelectronic co-packaging technology.

[0059] In traditional board-level optical module solutions (such as QSFP / OSFP optical modules plugged into server motherboards), high-speed electrical signals (such as UCIe or SerDes) need to be transmitted between external chips and optical engines via PCB traces several centimeters long, resulting in severe degradation of signal integrity, especially at speeds of 112 Gb / s and above, where eye diagram closure, jitter increases, and bit error rate soars. While simply placing the optical engine and external chips side by side on the same substrate (2D Co-Packaging) can shorten the distance to some extent, it is still difficult to meet the high-density fan-out requirements of hundreds of UCIe signals due to limitations in substrate wiring density and stack-up capabilities. Furthermore, power distribution network (PDN) noise is easily coupled to sensitive high-speed links. In addition, optical chips (such as silicon photonics PICs) and driver / amplifier electrical chips have vastly different requirements for process technology, coefficient of thermal expansion, and heat dissipation paths. Forcing homogeneous integration will sacrifice their respective performance or increase yield costs.

[0060] Therefore, please refer to Figure 9 and Figure 10 In this application, the external chip and the mixed-rate optical input / output interface 100 are co-packaged on the same substrate using optoelectronic co-packaging technology. Inside the mixed-rate optical input / output interface 100, the optical chip 121 and electrical chip 122 are arranged in a 3D stacked structure. Simultaneously, the bottom electrical interface is functionally partitioned, thereby achieving high-density, low-latency, and scalable optoelectronic co-integration at the physical level. Furthermore, without significantly increasing the package size and system cost, the electrical interconnection distance between the external chip and the optical interconnection interface is shortened, reducing high-frequency signal transmission loss and crosstalk, while also considering power supply stability, thermal management feasibility, and manufacturing process compatibility.

[0061] In this context, optoelectronic co-packaging technology refers to integrating the hybrid-rate optical input / output interface 100, which performs photoelectric signal conversion, and an external chip (such as a GPU, TPU, or other AI accelerator chip) that performs core computing tasks, onto the same interposer or organic substrate using advanced packaging processes. This allows the two to be physically adjacent, rather than connected via pluggable modules or long PCB traces. Furthermore, the hybrid-rate optical input / output interface 100 employs a 3D stacked packaging structure. For example, the optical chip 121 in the optical engine unit 120 is located above or below the electrical chip 122. This structure keeps the optical signal path (optical chip 121) as far away as possible from the digital logic area that generates heat and electromagnetic noise, while simultaneously shortening the micrometer-level interconnection distance between the electrical chip 122 (including the driver and transimpedance amplifier) ​​and the optical chip 121 (including the electro-optic modulator and photodetector). This significantly reduces parasitic capacitance and inductance, improving photoelectric conversion efficiency and bandwidth utilization.

[0062] In this process, the signal connection between the electrical interface unit 110 and the external chip can be optionally achieved through substrate traces, through-mold vias (TMV), and a re-distribution layer (RDL); or optionally through substrate traces, through-silicon vias (TSV), and a re-distribution layer (RDL). TMV is suitable for organic substrates or embedded substrates, while TSV is suitable for silicon interposers. Both provide higher density and lower loss vertical interconnect channels than traditional PCB traces. RDL is used to implement fine-width / spacing signal redistribution and fan-out on the chip surface or substrate surface to match the pad pitch of different devices.

[0063] As one implementation, the bottom electrical interface of the mixed-rate optical input / output interface 100 includes a first part and a second part. The first part is connected to the substrate and is used to transmit high-speed signals; the second part is used to connect power and transmit low-speed monitoring signals. This partitioned design stems from the inherent differences in the internal signal functions of the mixed-rate optical input / output interface 100: high-speed signals (such as UCIe data channels and SerDes channels) are extremely sensitive to impedance continuity, reference plane integrity, and power supply noise, and must be carried and shielded by a high-precision substrate; while power and low-speed monitoring signals (such as I²C, JTAG, temperature alarms, etc.) have high noise tolerance and low bandwidth requirements, and do not require expensive high-density substrate wiring resources. Therefore, the substrate only covers the first part of the bottom area of ​​the package, and the second part is directly connected to the printed circuit board (PCB). This method can significantly reduce the required substrate area. For example, the substrate that originally needed to cover the entire bottom of the rectangular package now only needs to cover the narrow strip area where high-speed signals are dense, and the rest is covered by a low-cost PCB, thereby effectively reducing the overall system packaging cost and supply chain complexity.

[0064] As can be seen, this embodiment does not simply place two chips together, but constructs a structurally optimized optoelectronic co-packaging structure for AI Scale-up scenarios through three-dimensional spatial layering (illustrated with optical chip 121 on top and electrical chip 122 on the bottom), multi-level interconnection path selection (TMV / TSV+RDL), and functional partitioning of the bottom electrical interface (separation of high-speed area and power / monitoring area). This achieves a synergistic breakthrough in cost, performance, and manufacturability while ensuring signal quality and system reliability.

[0065] Understandably, the co-package structure provided in this application includes the following key points: 1. The electrical and optical interfaces use different rates, and the mixed-rate optical input / output interface performs rate conversion internally. 2. The electrical interface uses a UCIe interface, and the optical interface uses a high-speed SerDes rate. 3. The mixed-rate optical input / output interface chip is implemented by multiple dies through packaging, including an electrical interface unit die, a driver die, a transimpedance amplifier die, and an optical chip die that realize the conversion between UCIe and high-speed SerDes. 4. The electrical interface of the mixed-rate optical input / output interface chip is divided into a first part of high-speed interface and a second part of low-speed and power interface. The first part is connected to the substrate, and the second part can be directly connected to the PCB.

[0066] In summary, this application provides a hybrid-rate optical input / output interface and co-package structure. The hybrid-rate optical input / output interface includes: an electrical interface unit for connecting to an external chip, employing a low-speed interface protocol; and an optical engine unit for connecting to an external fiber optic array unit, employing a high-speed serial interface rate. The electrical interface unit includes a rate conversion module, which converts multiple electrical signals from the low-speed interface to multiple electrical signals from the high-speed serial interface, or vice versa. The electrical interface unit and the optical engine unit are connected via a high-speed serial interface signal line. This application, by using a low-speed interface in the electrical interface unit and a high-speed serial interface rate in the optical engine unit, and performing rate conversion internally, retains the advantages of high sideband density of the UCIe interface while leveraging the advantages of fewer high-speed SerDes channels, fewer PIC integration channels, and higher yield, effectively overcoming the problems of low bandwidth density and high optical integration difficulty in the prior art.

[0067] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

[0068] It will be apparent to those skilled in the art that this application is not limited to the details of the exemplary embodiments described above, and that this application can be implemented in other specific forms without departing from the spirit or essential characteristics of this application. Therefore, the embodiments should be considered illustrative and non-limiting in all respects, and the scope of this application is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this application. No reference numerals in the claims should be construed as limiting the scope of the claims.

Claims

1. A hybrid rate optical input / output interface, characterized in that, The hybrid rate optical input / output interface includes: The electrical interface unit is used to connect to external chips and uses a low-speed interface protocol. The optical engine unit is used to connect to the external fiber optic array unit and adopts a high-speed serial interface rate. The electrical interface unit includes a rate conversion module, which is used to convert multiple electrical signals from the low-speed interface into multiple electrical signals from the high-speed serial interface, or to convert multiple electrical signals from the high-speed serial interface into multiple electrical signals from the low-speed interface; the electrical interface unit and the optical engine unit are connected via a high-speed serial interface signal line.

2. The hybrid rate optical input / output interface according to claim 1, characterized in that, The electrical interface unit further includes: The UCIe interface is connected to the rate conversion module and is used to connect to external chips. A high-speed SerDes interface is connected to the rate conversion module and is also used to connect to the optical engine unit; The rate conversion module is also used to realize the data rate conversion between the UCIe interface and the high-speed SerDes interface.

3. The hybrid rate optical input / output interface according to claim 2, characterized in that, The electrical interface unit also includes a functional unit, which is connected to the UCIe interface and the high-speed SerDes interface respectively.

4. The hybrid rate optical input / output interface according to claim 3, characterized in that, The functional unit is either a network protocol processing unit or a forward error correction unit.

5. The hybrid rate optical input / output interface according to claim 1, characterized in that, The optical engine unit includes an optical chip and an electrical chip. The optical chip integrates an electro-optic modulator and a photodetector, and the electrical chip includes a driver and a transimpedance amplifier. The signal transmitted by the optical engine unit is amplified by the driver and then drives the electro-optic modulator to convert it into an optical signal for output. The optical signal received by the optical engine unit is converted into an electrical signal by photoelectric detection, and then amplified by a transimpedance amplifier before being sent to the receiving end of the optical engine unit.

6. The hybrid rate optical input / output interface according to claim 1, characterized in that, The optical engine unit includes an optical chip and an electrical chip. The optical chip integrates an electro-optic modulator and a photodetector, and the electrical chip includes a transimpedance amplifier. The transmitting signal of the optical engine unit is converted into an optical signal output by an optical modulator; The optical signal received by the optical engine unit is converted into an electrical signal by photoelectric detection, and then amplified by a transimpedance amplifier before being sent to the receiving end of the optical engine unit.

7. A co-package structure, characterized in that, The co-package structure includes an external chip and a hybrid rate optical input / output interface as described in any one of claims 1 to 6, wherein the hybrid rate optical input / output interface and the external chip are co-packaged on the same substrate using optoelectronic co-packaging technology.

8. The co-packaging structure according to claim 7, characterized in that, The hybrid rate optical input / output interface adopts a 3D stacked packaging structure; The signal connection between the electrical interface unit and the external chip is achieved through substrate traces, TMV, and RDL; or the signal connection between the electrical interface unit and the external chip is achieved through substrate traces, TSV, and RDL.

9. The co-packaging structure according to claim 7, characterized in that, The bottom electrical interface of the mixed-rate optical input / output interface includes a first part and a second part. The first part is connected to the substrate and is used to transmit high-speed signals; the second part is used to connect to the power supply and transmit low-speed monitoring signals.

10. The co-packaging structure according to claim 9, characterized in that, The substrate covers only a first portion of the bottom area of ​​the package, while the second portion is connected to the PCB board.

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