A parallel NCO bit synchronization and timestamp solution method, system and device for high dynamic bidirectional ranging

Abstract

The present application relates to the technical field of synchronous demodulation, and particularly relates to a parallel NCO bit synchronization and timestamp solution method, system and device for high dynamic bidirectional ranging, comprising: S1: constructing a high time-geometry model, and establishing a mapping relationship among Doppler frequency offset, Doppler acceleration and sampling point phase increment; S2: based on the time-geometry model, constructing a parallel NCO optimal processing window architecture, and outputting high-precision time offset control parameters; S3: based on the time-geometry model, constructing a parallel NCO suboptimal processing window architecture, and outputting time offset control parameters; S4: establishing a mapping solution mechanism, and solving normalized values and serial number markers; S5: connecting the time offset control parameters to an interpolation filtering module to complete bit synchronization, and synchronously evaluating the timestamp stability and ranging accuracy of a receiver based on the solved timestamp information. The present application realizes an integrated design of bit synchronization and ranging timestamp processing in a high dynamic scene, has high precision and low complexity, and improves the dynamic adaptability and ranging accuracy of a bidirectional ranging receiver.

Description

Technical Field

[0001] This invention relates to the field of synchronous demodulation technology, and in particular to a parallel NCO bit synchronization and timestamp calculation method, system and device for high dynamic bidirectional ranging. Background Technology

[0002] With the continuous improvement of communication transmission rates, high-speed parallel demodulation has become the mainstream implementation scheme for high-bandwidth communication systems, and bit synchronization is the core component of high-speed parallel demodulation. The numerically controlled oscillator (NCO), as the core control unit of the bit synchronization loop, directly determines the bit synchronization accuracy and dynamic adaptability of the parallel demodulation system. Current design schemes for high-speed parallel demodulation bit synchronization NCOs mainly suffer from the following technical shortcomings: First, the adaptability to high-dynamic scenarios is insufficient. Most existing parallel NCO designs can only adapt to static scenarios with a fixed Doppler frequency offset, and have not established a linear recursive mechanism for Doppler acceleration, making it impossible to accurately reproduce the signal time-scaling effect caused by time-varying Doppler in high-dynamic scenarios. In high-dynamic extreme scenarios such as high-speed aircraft and low-orbit satellites, problems such as bit synchronization loss and a significant decrease in tracking accuracy are prone to occur.

[0003] Second, the architecture lacks compatibility and flexibility. Existing parallel NCO architectures are mostly designed for a fixed number of parallel paths (such as 8 paths), lacking a general-purpose architecture that can adapt to any number of parallel paths. At the same time, there is no design for a switchable high-precision optimal architecture and a low-complexity suboptimal architecture for different hardware resource constraints and dynamic scenarios, making it impossible to balance the accuracy requirements of highly dynamic scenarios with the implementation cost of low-resource scenarios.

[0004] Third, there is a lack of integrated timestamp calculation capabilities. Existing parallel bit synchronization NCO designs only focus on the estimation and control of bit synchronization timing deviations, without establishing a mapping and calculation mechanism between bidirectional ranging timestamps and NCO phases. This makes it impossible to synchronously complete accurate timestamp calculation during parallel bit synchronization processing, requiring the design of an additional independent hardware module to implement timestamp processing, which significantly increases the system complexity and hardware resource overhead of the bidirectional ranging receiver.

[0005] Fourth, the design of loop stability lacks theoretical support. Existing parallel NCO architectures have not completed the full z-domain discrete modeling after embedding the bit synchronization loop, making it impossible to accurately quantify the impact of loop delay caused by parallel processing. They also lack standardized loop stability criteria and parameter design methods, making it difficult to guarantee the long-term stable operation of the bit synchronization loop in high dynamic scenarios.

[0006] Therefore, there is an urgent need to develop a parallel NCO bit synchronization architecture for high dynamic bidirectional ranging that can accurately adapt to high dynamic scenarios with Doppler acceleration, has strong architectural compatibility, integrates timestamp synchronization calculation capabilities, and has a complete loop stability design. Summary of the Invention

[0007] The purpose of this invention is to overcome the shortcomings of existing technologies and provide a parallel NCO bit synchronization and timestamp calculation method for high-dynamic bidirectional ranging, comprising the following steps: S1: Construct a temporal geometric model of the signal time stretching effect in a high dynamic scene, and establish the mapping relationship between Doppler frequency offset, Doppler acceleration and sampling point phase increment; S2: Based on the aforementioned temporal geometry model, construct a parallel NCO optimal processing window architecture containing Doppler acceleration recursion, perform phase recursion calculation, state determination, and timing deviation estimation for several consecutive sampling points within the processing window, and output the timing deviation control parameters required for parallel interpolation; S3: Based on the aforementioned temporal geometry model, construct a parallel NCO suboptimal processing window architecture that ignores Doppler acceleration, perform phase calculation, scene branch determination, and timing deviation estimation with a fixed parallel processing window, and output timing deviation control parameters adapted to low-complexity scenarios. S4: Establish a mapping and solution mechanism between the bidirectional ranging timestamp and the parallel NCO phase. Based on the phase output of the optimal processing window architecture of the parallel NCO or the suboptimal processing window architecture of the parallel NCO, calculate the normalized value and sequence mark of the timestamp deviating from the zero point of the symbol phase. S5: Connect the time offset control parameters to the high-speed parallel demodulation interpolation filtering module to complete bit synchronization processing, synchronize the timestamp information based on the calculated timestamp information, and evaluate the timestamp stability and ranging accuracy of the two-way ranging receiver.

[0008] Preferably, in step S1, constructing a temporal geometric model includes: S11: with Using the normalized phase unit and the sampling interval as the normalized time unit, a two-dimensional geometric relationship between time and phase is established. S12: For scenarios with Doppler frequency offset, establish a mapping relationship between the normalized phase increment of sampling points and the Doppler frequency offset: , in, The normalized phase increment of the sampling point. For Doppler frequency shift, For carrier frequency; S13: For high-dynamic scenarios with Doppler acceleration, establish a normalized phase increment recursive relationship between adjacent sampling points based on the mapping relationship: , in, The normalized phase increment of the sampling point at time k+i. The rate of change of Doppler frequency deviation, is the sampling interval, and i is the offset of the sampling point number.

[0009] Preferably, in step S2, constructing the parallel NCO optimal processing window architecture includes: S21: Taking the k-th sampling point as the origin of the processing window, based on the phase increment recursive relationship, the phase value of m consecutive sampling points within the processing window is calculated using the phase accumulation formula. The phase recursive formula is as follows: , in, The cumulative phase value of the sampling point at time k+m. To process the initial phase value of the window, The normalized phase increment of the sampling point at time k+i; S22: Calculate the phase difference between adjacent sampling points. Based on the phase difference, compare it with the preset ideal signal point phase characteristic threshold, and divide the sampling points within the processing window into three states: containing 2 ideal signal points, containing 1 ideal signal point, and having no ideal signal point. Obtain the state determination result. The formula for calculating the phase difference is: ; S23: Based on the state determination result, and combined with the phase value of the sampling point, calculate the estimated value of the timing deviation under the corresponding state. The timing deviation estimation formula is as follows: , in, For the timing deviation estimate based on the (k+m)th sampling point, This is the timing deviation estimate based on the (k+m+1)th sampling point. This represents the normalized phase increment at the (k+m)th sampling point; S24: Based on pipelined timing logic design, phase calculation, state determination, and timing deviation estimation are decomposed into parallel processing branches. Each branch corresponds to the full-process calculation of a sampling point within the processing window. The results of each branch are summarized, and the timing deviation control parameters required for parallel interpolation filtering are output.

[0010] Preferably, in step S3, constructing a parallel NCO suboptimal processing window architecture that ignores Doppler acceleration includes: S31: Using 8 consecutive sampling points as a single processing window, based on the initial phase value of the processing window... With normalized phase increment Calculate the phase value at the end of the processing window: , in, This is the modulo 8 remainder operation. The phase value of the (k+8)th sampling point. This represents the normalized phase increment of the sampling point; S32: Based on the initial phase value of the processing window The value range is divided into 4 basic scenarios, and each basic scenario is based on the phase value at the end of the processing window. Further divide into sub-scenes; S33: For the sub-scenario, based on the preset scenario-deviation mapping table, calculate the candidate timing deviation estimate for the scenario, and determine the interpolation position corresponding to the best sampling point in the 8 parallel branches by comparing the matching degree between the candidate timing deviation estimate and the ideal deviation threshold, and output the timing deviation control parameters. S34: Set the processing window to end phase value This serves as the initial phase value for the next processing window, completing the pipeline iteration of successive processing windows.

[0011] Preferably, in step S32, the scenarios are divided into four basic categories, including: First scene segmentation: Initial phase value of the processing window satisfy ; Divide the second scene: process the initial phase value of the window satisfy ; Divide the third scene: process the initial phase value of the window satisfy ; Fourth scene segmentation: Initial phase value of the processing window satisfy or .

[0012] Preferably, in step S4, a mapping and calculation mechanism for bidirectional ranging timestamps and parallel NCO phases is established, including: bidirectional ranging timestamp Normalized to the sampling duration dimension, its value range is: , where n is the number of parallel paths in the currently enabled parallel NCO processing window; Based on the integer part Determine the sampling segment containing the timestamp, and calculate the offset of the timestamp within the corresponding segment: ; Based on the initial phase value of the sampling segment With phase increment Calculate the mapped phase value corresponding to the timestamp: ; Calculate the normalized value of the timestamp offset from the zero point of the symbol phase. : ; Calculate the phase zero-point sequence number corresponding to the timestamp : According to the normalized value and the phase zero point number mark Obtain the bidirectional ranging timestamp calculation results.

[0013] Preferably, step S5 further includes discrete modeling and stability analysis after the parallel NCO embedding bit synchronization loop: Establish the recurrence relation of parallel NCO in the discrete domain: , in, This represents the initial phase value of the k-th sampling point in the h-th processing. This represents the cumulative phase value of the (k+m)th sampling point in the (h+1)th processing iteration. is the average normalized phase increment of the h-th processing, and m is the number of parallel processing windows; The z-domain transfer function of the parallel NCO is derived based on the aforementioned recursive relationship: , in, The z-transform result of the parallel NCO phase adjustment cumulant. This is the z-transform result of the loop filter output error filtering value. For discrete-domain delay operators; The z-domain transfer function is embedded into a second-order bit synchronization loop architecture. Combined with the transfer function of the loop filter, the loop characteristic equation is constructed based on the loop open-loop transfer function, and the loop stability detection polynomial is derived. The coefficients of the stability detection polynomial are determined according to the Routh criterion or the Julius criterion: if the polynomial satisfies that the modulus of all roots is less than 1, the loop is considered stable; otherwise, the loop filter parameters are adjusted until the stability condition is met. The designed loop parameters are substituted into the phase recursion model of the high dynamic scenario. The phase adjustment convergence speed and steady-state error of the position synchronization loop are verified by simulation to ensure that the parameters are adapted to the real-time and accuracy requirements of high dynamic two-way ranging.

[0014] Preferably, the evaluation of timestamp stability and ranging accuracy in step S5 includes: Normalized value based on the timestamp offset from the zero point of the symbol phase obtained from the solution Calculate under different signal-to-noise ratio conditions Standard deviation; Build The mapping curve between standard deviation and signal-to-noise ratio is used to complete the quantitative evaluation of the timestamp stability of the two-way ranging receiver in a high dynamic environment. Simultaneously based on The mapping relationship between standard deviation and ranging error is used to complete the quantitative analysis of the receiver ranging accuracy.

[0015] Based on the same concept, this invention also provides a parallel NCO bit synchronization and timestamp calculation system for high dynamic bidirectional ranging, including: The temporal geometry modeling module constructs a temporal geometry model of the signal time stretching effect in high dynamic scenarios and establishes the mapping relationship between Doppler frequency offset, Doppler acceleration and sampling point phase increment. The optimal NCO processing module, based on the aforementioned temporal geometry model, constructs a parallel NCO optimal processing window architecture containing Doppler acceleration recursion, performs phase recursion calculation, state determination, and timing deviation estimation for several consecutive sampling points within the processing window, and outputs the timing deviation control parameters required for parallel interpolation. The suboptimal NCO processing module, based on the aforementioned temporal geometry model, constructs a parallel NCO suboptimal processing window architecture that ignores Doppler acceleration, performs phase calculation, scene branch determination, and timing deviation estimation within a fixed parallel processing window, and outputs timing deviation control parameters adapted to low-complexity scenarios. The timestamp calculation module establishes a mapping calculation mechanism between the bidirectional ranging timestamp and the parallel NCO phase. Based on the phase output of the optimal processing window architecture or the suboptimal processing window architecture of the parallel NCO, it calculates the normalized value and sequence mark of the timestamp deviation from the zero point of the symbol phase. The bit synchronization and performance evaluation module connects the time offset control parameters to the high-speed parallel demodulation interpolation filtering module to complete the bit synchronization process, synchronizes the timestamp information based on the calculated timestamp information, and evaluates the timestamp stability and ranging accuracy of the two-way ranging receiver.

[0016] Based on the same concept, the present invention also provides a computer device, including a memory and a processor, wherein the memory stores computer-readable instructions, which, when executed by the processor, cause the processor to perform the steps of the parallel NCO bit synchronization and timestamp calculation method for high dynamic bidirectional ranging as described in any one embodiment.

[0017] Compared with the prior art, the beneficial effects of the present invention are: (1) This invention constructs a temporal geometric model of the signal time stretching effect in a high dynamic scenario, establishes a precise mapping relationship between Doppler frequency offset, Doppler acceleration and sampling point phase increment, provides a theoretical basis for the core control parameters of the parallel NCO, and thus lays the mathematical foundation for accurate bit synchronization and timestamp calculation in a high dynamic scenario, ensuring that subsequent processing can accurately reproduce the signal time stretching effect, and fundamentally solves the problem of bit synchronization loss in a high dynamic environment.

[0018] (2) Based on the temporal geometric model, the present invention constructs a parallel NCO optimal processing window architecture with Doppler acceleration recursion. Through phase recursion calculation, state determination and timing deviation estimation of multiple sampling points in the processing window, high-precision time deviation control parameters are output, realizing accurate tracking of high dynamic signals with Doppler acceleration. This greatly improves the dynamic adaptability and tracking accuracy of the bit synchronization loop, meets the application requirements of extreme dynamic scenarios such as high-speed aircraft and low-orbit satellites, and has strong robustness.

[0019] (3) Based on the temporal geometric model, the present invention constructs a parallel NCO suboptimal processing window architecture that ignores Doppler acceleration. It adopts an 8-way fixed parallel processing and scene branching decision strategy to output time offset control parameters that are adapted to low-complexity scenarios. This enables low-cost bit synchronization processing in resource-constrained or low-dynamic scenarios, thus taking into account different application requirements of high precision and low complexity, enhancing the flexibility and compatibility of the architecture, and reducing hardware implementation costs.

[0020] (4) The present invention establishes a mapping and calculation mechanism between bidirectional ranging timestamp and parallel NCO phase. Based on the optimal or suboptimal architecture, the phase output synchronously calculates the normalized value and sequence mark of the timestamp deviation from the zero point of the symbol phase, realizing the integrated processing of bit synchronization and ranging timestamp, thereby eliminating the need for a separate timestamp processing module, greatly reducing the system complexity and hardware resource overhead of the bidirectional ranging receiver, and improving the system integration.

[0021] (5) This invention connects the time offset control parameters output by the parallel NCO to the interpolation filtering module of the high-speed parallel demodulation to complete the bit synchronization processing, and completes the quantitative evaluation of the receiver timestamp stability and ranging accuracy based on the calculated timestamp information. At the same time, by performing complete z-domain discrete modeling and stability analysis on the parallel NCO embedded in the loop, the long-term stable operation of the bit synchronization loop under high dynamic environment is guaranteed, thus providing a complete performance verification and design basis for the two-way ranging system, and ensuring ranging accuracy and reliability. Attached Figure Description

[0022] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention.

[0023] Figure 1 This is a flowchart of a parallel NCO bit synchronization and timestamp calculation method for high dynamic bidirectional ranging according to the present invention. Figure 2 This is a schematic diagram illustrating the interpretation of the deviation estimation under the geometric relationship of time and phase construction in this invention; Figure 3 This is a schematic diagram of the time-phase geometric relationship when the Doppler rate of change is not zero according to the present invention; Figure 4 This is a schematic diagram illustrating the phase vector change process of the 8 input sampling points under the Doppler acceleration effect in this invention; Figure 5 This is a schematic diagram illustrating the general temporal variation of sampling points within the optimal processing window under the Doppler acceleration effect of this invention. Figure 6 This is a schematic diagram illustrating all possible scenarios between sampling points under the optimal processing method in this invention, considering the Doppler acceleration effect. Figure 7 This is a schematic diagram illustrating the timing of the optimal processing window architecture implemented at 8 points in a single operation according to the present invention. Figure 8 This is a schematic diagram illustrating the possible boundary relationship between duration and phase in a single 8-point processing process under the suboptimal processing window architecture of the present invention. Figure 9 This is a schematic diagram illustrating the general timing of a single 8-point implementation of the suboptimal processing window architecture of the present invention. Figure 10 This is a schematic diagram illustrating the overall z-domain analysis of the algorithm architecture of this invention after equivalent embedding of loops; Figure 11 A schematic diagram illustrating the general timestamp processing for the optimal architecture of this invention; Figure 12 A schematic diagram illustrating the process of extracting the corresponding phase from a single 8-point time stamp to adapt to the suboptimal architecture of this invention. Figure 13 The figures show the I-channel and Q-channel numerical waveforms at the 0-phase and π-phase of the symbol duration after OQPSK demodulation in the experiment of this invention. Figure 14 This is the IQ constellation diagram at the 0 phase and π phase of the symbol duration after OQPSK demodulation in the experiment of this invention; Figure 15 This is a graph showing the test results of the normalized value of the symbol end after demodulation of the timestamp deviation in the experiment of this invention; Figure 16 This is a graph showing the change in the stability (standard deviation) of timestamps based on the signal-to-noise ratio in the experiments of this invention. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. Obviously, the described embodiments are only some, not all, of the embodiments described in this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without creative effort are within the scope of protection of this application.

[0025] Those skilled in the art will understand that, unless otherwise stated, the singular forms “a” and “an” used herein, and “the”, may also include the plural forms. It should be further understood that the term “comprising” as used in this specification means the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0026] First Embodiment Please see Figure 1 As shown, this embodiment provides a parallel NCO bit synchronization and timestamp calculation method for high dynamic bidirectional ranging, including the following steps: S1: Construct a temporal geometric model of the signal time stretching effect in a high dynamic scene, and establish the mapping relationship between Doppler frequency offset, Doppler acceleration and sampling point phase increment.

[0027] More preferably, for bit synchronization processing, the down-converted baseband received signal can be expressed as: in, It is symbolic information. It is the duration of the symbol. It is an unknown time deviation. It is an energy-normalized pulse waveform function. It is the equivalent link loss. It is additive white Gaussian noise. After the received signal is processed by matched filtering, the following is obtained: , in It is the autocorrelation function of the pulse waveform function. Under the condition that pulse shaping satisfies the Nyquist inter-symbol interference-free criterion, the synchronization algorithm provides an accurate time offset estimate. Can make At this point, the sum of the inter-symbol interference terms is 0. Accurate estimation of the time deviation requires simultaneously covering both the initial deviation estimate and the time-varying deviation estimate caused by the Doppler effect.

[0028] Preferably, in step S1, constructing a temporal geometric model includes: S11: with Normalized phase unit, with sampling interval as normalized time unit. A two-dimensional geometric relationship between time and phase is established. Specifically, in this embodiment, if the receiving system uses a sampling rate of 4 times to process the baseband received signal, and there is no Doppler effect, the sampling interval is equal to the ideal interval, i.e. When the Doppler effect is present, the sampling interval is stretched or compressed. ,in This is the Doppler equivalent duration compensation, corresponding to the electromagnetic wave phase change. Based on the above geometric relationship, the interval duration is 4 times the sampling rate. Corresponding phase change satisfy: ; S12: For scenarios with Doppler frequency offset, establish a mapping relationship between the normalized phase increment of sampling points and the Doppler frequency offset: , in, The normalized phase increment of the sampling point. For Doppler frequency shift, For carrier frequency; S13: For high-dynamic scenes with Doppler acceleration, where the Doppler frequency offset changes linearly with time, a recursive relationship of normalized phase increments for adjacent sampling points is established based on the aforementioned mapping relationship: , in, The normalized phase increment of the sampling point at time k+i. The rate of change of Doppler frequency deviation, Let i be the sampling interval and i be the sampling point index offset. Based on this recursive relationship, the signal time stretching effect caused by Doppler acceleration in high dynamic scenarios can be fully described. Figure 2 and Figure 3 The temporal geometric relationships are illustrated for the cases with and without acceleration.

[0029] S2: For high dynamic extreme scenarios, based on the aforementioned temporal geometry model, a parallel NCO optimal processing window architecture with Doppler acceleration recursion is constructed. The phase recursion calculation, state determination, and timing deviation estimation of several consecutive sampling points within the processing window are performed, and the timing deviation control parameters required for parallel interpolation are output.

[0030] Preferably, in step S2, constructing the parallel NCO optimal processing window architecture includes: S21: Taking the k-th sampling point as the origin of the processing window, based on the phase increment recursive relationship, the phase value of m consecutive sampling points within the processing window is calculated using the phase accumulation formula. The phase recursive formula is as follows: , in, The cumulative phase value of the sampling point at time k+m. To process the initial phase value of the window, The normalized phase increment of the sampling point at time k+i can be further simplified in this embodiment as follows: ; S22: Calculate the phase difference between adjacent sampling points. Based on the phase difference, compare it with the preset ideal signal point phase characteristic threshold, and divide the sampling points within the processing window into three states: containing 2 ideal signal points, containing 1 ideal signal point, and having no ideal signal point. Obtain the state determination result. The formula for calculating the phase difference is: , Specifically, in this embodiment, the sampling points within the processing window are divided into three states: containing 2 ideal signal points, containing 1 ideal signal point, and having no ideal signal points. The first state is a determination result of 2, corresponding to the presence of 2 ideal signal points within the sampling segment; the second state is a determination result of 1, corresponding to the presence of 1 ideal signal point within the sampling segment; and the third state is a determination result of 0, corresponding to the absence of any ideal signal points within the sampling segment. Figures 4 to 6 A geometric diagram illustrating the phase change and state division of sampling points under the Doppler acceleration effect is presented. S23: Based on the state determination result, and combined with the phase value of the sampling point, calculate the estimated value of the timing deviation under the corresponding state to provide control parameters for subsequent parallel interpolation filtering. The timing deviation estimation formula is: , in, For the timing deviation estimate based on the (k+m)th sampling point, This is the timing deviation estimate based on the (k+m+1)th sampling point. This represents the normalized phase increment at the (k+m)th sampling point; S24: Based on pipelined timing logic design, phase calculation, state determination, and timing deviation estimation are decomposed into parallel processing branches. Each branch corresponds to the full-process calculation of a sampling point within the processing window. The results of each branch are summarized, and the timing deviation control parameters required for parallel interpolation filtering are output. Figure 7 A timing description of the optimal processing window architecture for a single 8-point implementation is given.

[0031] S3: Based on the aforementioned temporal geometry model, a parallel NCO suboptimal processing window architecture ignoring Doppler acceleration is constructed. This architecture performs phase calculation, scene branch determination, and timing deviation estimation for a fixed parallel processing window, outputting timing deviation control parameters adapted to low-complexity scenarios. Specifically, in this embodiment, for scenarios with low to medium dynamics and limited hardware resources, an 8-way parallel NCO suboptimal processing window architecture ignoring Doppler acceleration is constructed. For a single 8-point processing window, a three-stage pipeline architecture is designed: First clock edge: latching the initial phase of the processing window. Normalized phase increment With Doppler acceleration The second clock edge: the phase values ​​of the 9 sampling points and the phase increments of the 8 sampling segments within the processing window are calculated in parallel by the DSP; the third clock edge: the sampling point status is determined, 16 alternative timing deviation estimates are calculated in parallel, and the timing deviation control parameters are output to the subsequent interpolation and filtering module.

[0032] Preferably, in step S3, constructing a parallel NCO suboptimal processing window architecture that ignores Doppler acceleration includes: S31: Using 8 consecutive sampling points as a single processing window, based on the initial phase value of the processing window... With normalized phase increment Calculate the phase value at the end of the processing window: , in, This is the modulo 8 remainder operation. The phase value of the (k+8)th sampling point. The normalized phase increment of the sampling points is, specifically, in this embodiment, when Doppler acceleration is ignored, the normalized phase increment of all sampling points within the processing window is constant. The phase value at the end of the processing window is used as the initial phase value of the next processing window to achieve iteration of continuous processing windows; S32: Based on the initial phase value of the processing window The value range is divided into 4 basic scenarios, and each basic scenario is based on the phase value at the end of the processing window. Further divide the scene into sub-scenes.

[0033] Preferably, in step S32, the scenarios are divided into four basic categories, including: First scene segmentation: Initial phase value of the processing window satisfy ,according to The values ​​of are further divided into , The remaining three sub-scenes; Divide the second scene: process the initial phase value of the window satisfy ,according to The values ​​of are further divided into , The remaining three sub-scenes; Divide the third scene: process the initial phase value of the window satisfy ,according to The values ​​of are further divided into , The remaining three sub-scenes; Fourth scene segmentation: Initial phase value of the processing window satisfy or ,according to The values ​​of are further divided into , The remaining three sub-scenes Figure 8 It demonstrates the possible boundary of the relationship between the duration and phase of a single 8-point processing step under a suboptimal processing window architecture.

[0034] S33: For the sub-scene, based on the preset scene-deviation mapping table, calculate the candidate timing deviation estimate for the scene. By comparing the matching degree between the candidate timing deviation estimate and the ideal deviation threshold, determine the interpolation position corresponding to the best sampling point in the 8 parallel branches, and output the timing deviation control parameter. Specifically, in this embodiment, a two-stage pipeline implementation architecture is designed for the 8 parallel processing windows. The second clock edge completes the scene branch determination, selects the matching timing deviation estimate, outputs the timing deviation control parameter, and simultaneously latches the initial phase value of the next processing window. S34: Set the processing window to end phase value This serves as the initial phase value for the next processing window, completing the pipeline iteration of successive processing windows. Figure 9 A general timing description of a single 8-point implementation of the suboptimal processing window architecture is given.

[0035] S4: Establish a mapping and solution mechanism between the bidirectional ranging timestamp and the parallel NCO phase. Based on the phase output of the optimal processing window architecture or the suboptimal processing window architecture of the parallel NCO, calculate the normalized value and sequence number of the timestamp deviating from the zero point of the symbol phase.

[0036] Preferably, in step S4, a mapping and calculation mechanism for bidirectional ranging timestamps and parallel NCO phases is established, including: bidirectional ranging timestamp Normalized to the sampling duration dimension, its value range is: , where n is the number of parallel paths in the currently enabled parallel NCO processing window; Based on the integer part Determine the sampling segment k+i-1 to k+i where the timestamp is located, and calculate the offset of the timestamp within the corresponding segment: ; Based on the initial phase value of the sampling segment With phase increment Calculate the mapped phase value corresponding to the timestamp: , in, For paragraph indexing; Calculate the normalized value of the timestamp offset from the zero point of the symbol phase. : ; Calculate the phase zero-point sequence number corresponding to the timestamp : According to the normalized value and the phase zero point number mark To obtain the bidirectional ranging timestamp calculation result, specifically, in this embodiment, for an 8-way parallel suboptimal processing window architecture, the specific calculation steps are as follows: calculate the initial phase offset of the timestamp mapping, Based on the scene segmentation results of the suboptimal processing window architecture, the phase zero point position of the corresponding scene is matched, and the normalized value of the timestamp deviation from the symbol phase zero point is calculated. Simultaneously complete the marking of phase zero point sequence numbers. . Figure 11 and Figure 12 The timestamp calculation process for adapting to the optimal architecture and the suboptimal architecture is illustrated in the diagrams.

[0037] S5: Connect the time offset control parameters to the high-speed parallel demodulation interpolation filtering module to complete bit synchronization processing, synchronize the timestamp information based on the calculated timestamp information, and evaluate the timestamp stability and ranging accuracy of the two-way ranging receiver.

[0038] Preferably, step S5 further includes discrete modeling and stability analysis after the parallel NCO embedding bit synchronization loop: Establish the recurrence relation of parallel NCO in the discrete domain: , in, This represents the initial phase value of the k-th sampling point in the h-th processing. This represents the cumulative phase value of the (k+m)th sampling point in the (h+1)th processing iteration. is the average normalized phase increment of the h-th processing, and m is the number of parallel processing windows; The z-domain transfer function of the parallel NCO is derived based on the aforementioned recursive relationship: , in, The z-transform result of the parallel NCO phase adjustment cumulant. This is the z-transform result of the loop filter output error filtering value. For discrete-domain delay operators; The z-domain transfer function is embedded into a second-order bit synchronization loop architecture. Combined with the transfer function of the loop filter, the loop characteristic equation is constructed based on the loop open-loop transfer function, and the loop stability detection polynomial is derived. More preferably, the transfer function of the loop filter is as follows: , in, Let d be the loop gain and d be the loop delay. , These are the coefficients of the second-order loop filter.

[0039] More preferably, the loop stability is determined based on the loop stability detection polynomial, while simultaneously optimizing the design of the loop parameters. The loop stability detection polynomial is shown below: .

[0040] The coefficients of the stability detection polynomial are determined according to the Routh criterion or the Julius criterion: if the polynomial satisfies that the modulus of all roots is less than 1, the loop is considered stable; otherwise, the loop filter parameters are adjusted until the stability condition is met. Figure 10 A schematic diagram of the overall z-domain analysis after the algorithm architecture is equivalently embedded with a loop is given; The designed loop parameters are substituted into the phase recursion model of the high dynamic scenario. The phase adjustment convergence speed and steady-state error of the position synchronization loop are verified by simulation to ensure that the parameters are adapted to the real-time and accuracy requirements of high dynamic two-way ranging.

[0041] Preferably, the evaluation of timestamp stability and ranging accuracy in step S5 includes: Normalized value based on the timestamp offset from the zero point of the symbol phase obtained from the solution Calculate under different signal-to-noise ratio conditions Standard deviation; Build The mapping curve between standard deviation and signal-to-noise ratio is used to complete the quantitative evaluation of the timestamp stability of the two-way ranging receiver in a high dynamic environment. Simultaneously based on The mapping relationship between standard deviation and ranging error is used to complete the quantitative analysis of the receiver ranging accuracy.

[0042] In this embodiment, OQPSK modulated signals are used to construct test frames. Both independent data channels are encoded using LDPC at a code rate of 7136 / 8160, and a 32-bit frame header is added to form a frame. The designed frame rate is 1536 frames per second, the theoretical symbol rate is 12,582,912 bits per second, and parallel demodulation is achieved using a 4x sampling rate.

[0043] Configure core carrier and Doppler parameters: carrier frequency The frequency is 2GHz, the initial Doppler frequency offset is 90kHz, and the Doppler frequency offset change rate is... The frequency is 9 kHz / s; a fixed-position timestamp is embedded in the baseband signal so that the timestamp appears stably at 1 / 4 of each symbol. Regardless of whether the Doppler effect exists, the normalized value of the timestamp deviating from the symbol end after demodulation should theoretically be 1 / 4.

[0044] The parallel NCO architecture of this invention is connected to the interpolation filtering module of high-speed parallel demodulation to complete bit synchronization processing and synchronously calculate timestamp information. The test results are as follows: The demodulated I / Q channel values ​​and constellation diagram conform to the OQPSK modulation characteristics (e.g. Figure 13 , Figure 14 As shown in the figure, the effectiveness of the bit synchronization algorithm is verified; After demodulation, the normalized value of the timestamp deviation from the symbol end stabilizes at 1 / 4 of the design value (e.g. Figure 15 As shown in the figure, the accuracy of the timestamp calculation mechanism is verified; By adjusting the signal-to-noise ratio (SNR) of the received signal, the standard deviation of the timestamp under different SNRs is obtained, and the curve of timestamp stability as a function of SNR is plotted (e.g., ...). Figure 16 As shown in the figure, the time stamp stability and ranging accuracy of the bidirectional ranging receiver under test in a high dynamic environment are quantitatively evaluated.

[0045] This embodiment verifies that the architecture described in this invention can accurately realize bit synchronization processing for high-speed parallel demodulation in high-dynamic scenarios, while simultaneously completing accurate calculation of bidirectional ranging timestamps, providing a high-precision and highly compatible bit synchronization and timestamp processing solution for high-dynamic bidirectional ranging receivers.

[0046] Second Embodiment Based on the same concept, this invention also provides a parallel NCO bit synchronization and timestamp calculation system for high dynamic bidirectional ranging, including: The temporal geometry modeling module constructs a temporal geometry model of the signal time stretching effect in high dynamic scenarios and establishes the mapping relationship between Doppler frequency offset, Doppler acceleration and sampling point phase increment. The optimal NCO processing module, based on the aforementioned temporal geometry model, constructs a parallel NCO optimal processing window architecture containing Doppler acceleration recursion, performs phase recursion calculation, state determination, and timing deviation estimation for several consecutive sampling points within the processing window, and outputs the timing deviation control parameters required for parallel interpolation. The suboptimal NCO processing module, based on the aforementioned temporal geometry model, constructs a parallel NCO suboptimal processing window architecture that ignores Doppler acceleration, performs phase calculation, scene branch determination, and timing deviation estimation within a fixed parallel processing window, and outputs timing deviation control parameters adapted to low-complexity scenarios. The timestamp calculation module establishes a mapping calculation mechanism between the bidirectional ranging timestamp and the parallel NCO phase. Based on the phase output of the optimal processing window architecture or the suboptimal processing window architecture of the parallel NCO, it calculates the normalized value and sequence mark of the timestamp deviation from the zero point of the symbol phase. The bit synchronization and performance evaluation module connects the time offset control parameters to the high-speed parallel demodulation interpolation filtering module to complete the bit synchronization process, synchronizes the timestamp information based on the calculated timestamp information, and evaluates the timestamp stability and ranging accuracy of the two-way ranging receiver.

[0047] Third Embodiment Based on the same concept, this embodiment also provides a computer device, including a memory and a processor. The memory stores computer-readable instructions, which, when executed by the processor, cause the processor to perform the steps of a parallel NCO bit synchronization and timestamp calculation method for high dynamic bidirectional ranging as described in the embodiment.

[0048] Based on the same concept, the present invention also provides a storage medium storing computer-readable instructions, which, when executed by one or more processors, cause the one or more processors to perform the steps of a parallel NCO bit synchronization and timestamp calculation method for high dynamic bidirectional ranging as described in any one embodiment.

[0049] It is understood that, for the aforementioned parallel NCO bit synchronization and timestamp calculation method for high-dynamic bidirectional ranging, if all of them are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer server or a network device, etc.) to execute all or part of the steps of the methods of the various embodiments of the present invention. The aforementioned storage medium includes: USB flash drive, mobile hard drive, read-only memory (ROM), random access memory (RAM), magnetic disk or optical disk, and other media capable of storing program code.

[0050] Computer-readable storage media may include data signals propagated in baseband or as part of a carrier wave, carrying readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A readable storage medium may also be any readable medium other than a readable storage medium that can transmit, propagate, or transfer a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the readable storage medium may be transmitted using any suitable medium, including but not limited to wireless, wired, optical fiber, RF, etc., or any suitable combination thereof.

[0051] The above description is merely a preferred embodiment of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principles of the present invention should also be considered within the scope of protection of the present invention.

Claims

1. A parallel NCO bit synchronization and timestamp calculation method for high-dynamic bidirectional ranging, characterized in that, Includes the following steps: S1: Construct a temporal geometric model of the signal time stretching effect in a high dynamic scene, and establish the mapping relationship between Doppler frequency offset, Doppler acceleration and sampling point phase increment; S2: Based on the aforementioned temporal geometry model, construct a parallel NCO optimal processing window architecture containing Doppler acceleration recursion, perform phase recursion calculation, state determination, and timing deviation estimation for several consecutive sampling points within the processing window, and output the timing deviation control parameters required for parallel interpolation; S3: Based on the aforementioned temporal geometry model, construct a parallel NCO suboptimal processing window architecture that ignores Doppler acceleration, perform phase calculation, scene branch determination, and timing deviation estimation with a fixed parallel processing window, and output timing deviation control parameters adapted to low-complexity scenarios. S4: Establish a mapping and solution mechanism between the bidirectional ranging timestamp and the parallel NCO phase. Based on the phase output of the optimal processing window architecture of the parallel NCO or the suboptimal processing window architecture of the parallel NCO, calculate the normalized value and sequence mark of the timestamp deviating from the zero point of the symbol phase. S5: Connect the time offset control parameters to the high-speed parallel demodulation interpolation filtering module to complete bit synchronization processing, synchronize the timestamp information based on the calculated timestamp information, and evaluate the timestamp stability and ranging accuracy of the two-way ranging receiver.

2. The parallel NCO bit synchronization and timestamp calculation method for high-dynamic bidirectional ranging according to claim 1, characterized in that, In step S1, a temporal geometric model is constructed, including: S11: with Using the normalized phase unit and the sampling interval as the normalized time unit, a two-dimensional geometric relationship between time and phase is established. S12: For scenarios with Doppler frequency offset, establish a mapping relationship between the normalized phase increment of sampling points and the Doppler frequency offset: ， in, The normalized phase increment of the sampling point. For Doppler frequency shift, For carrier frequency; S13: For high-dynamic scenarios with Doppler acceleration, establish a normalized phase increment recursive relationship between adjacent sampling points based on the mapping relationship: ， in, The normalized phase increment of the sampling point at time k+i. The rate of change of Doppler frequency deviation, is the sampling interval, and i is the offset of the sampling point number.

3. The parallel NCO bit synchronization and timestamp calculation method for high-dynamic bidirectional ranging according to claim 1, characterized in that, In step S2, the optimal parallel NCO processing window architecture is constructed, including: S21: Taking the k-th sampling point as the origin of the processing window, based on the phase increment recursive relationship, the phase value of m consecutive sampling points within the processing window is calculated using the phase accumulation formula. The phase recursive formula is as follows: ， in, The cumulative phase value of the sampling point at time k+m. To process the initial phase value of the window, The normalized phase increment of the sampling point at time k+i; S22: Calculate the phase difference between adjacent sampling points. Based on the phase difference, compare it with the preset ideal signal point phase characteristic threshold, and divide the sampling points within the processing window into three states: containing 2 ideal signal points, containing 1 ideal signal point, and having no ideal signal point. Obtain the state determination result. The formula for calculating the phase difference is: ； S23: Based on the state determination result, and combined with the phase value of the sampling point, calculate the estimated value of the timing deviation under the corresponding state. The timing deviation estimation formula is as follows: ， in, For the timing deviation estimate based on the (k+m)th sampling point, This is the timing deviation estimate based on the (k+m+1)th sampling point. This represents the normalized phase increment at the (k+m)th sampling point; S24: Based on pipelined timing logic design, phase calculation, state determination, and timing deviation estimation are decomposed into parallel processing branches. Each branch corresponds to the full-process calculation of a sampling point within the processing window. The results of each branch are summarized, and the timing deviation control parameters required for parallel interpolation filtering are output.

4. The parallel NCO bit synchronization and timestamp calculation method for high-dynamic bidirectional ranging according to claim 1, characterized in that, In step S3, a parallel NCO suboptimal processing window architecture that ignores Doppler acceleration is constructed, including: S31: Using 8 consecutive sampling points as a single processing window, based on the initial phase value of the processing window... With normalized phase increment Calculate the phase value at the end of the processing window: ， in, This is the modulo 8 remainder operation. The phase value of the (k+8)th sampling point. This represents the normalized phase increment of the sampling point; S32: Based on the initial phase value of the processing window The value range is divided into 4 basic scenarios, and each basic scenario is based on the phase value at the end of the processing window. Further divide into sub-scenes; S33: For the sub-scenario, based on the preset scenario-deviation mapping table, calculate the candidate timing deviation estimate for the scenario, and determine the interpolation position corresponding to the best sampling point in the 8 parallel branches by comparing the matching degree between the candidate timing deviation estimate and the ideal deviation threshold, and output the timing deviation control parameters. S34: Set the processing window to end phase value This serves as the initial phase value for the next processing window, completing the pipeline iteration of successive processing windows.

5. The parallel NCO bit synchronization and timestamp calculation method for high-dynamic bidirectional ranging according to claim 4, characterized in that, In step S32, the scenarios are divided into four basic categories, including: First scene segmentation: Initial phase value of the processing window satisfy ; Divide the second scene: process the initial phase value of the window satisfy ; Divide the third scene: process the initial phase value of the window satisfy ; Fourth scene segmentation: Initial phase value of the processing window satisfy or .

6. The parallel NCO bit synchronization and timestamp calculation method for high-dynamic bidirectional ranging according to claim 1, characterized in that, In step S4, a mapping mechanism for bidirectional ranging timestamps and parallel NCO phases is established, including: bidirectional ranging timestamp Normalized to the sampling duration dimension, its value range is: , where n is the number of parallel paths in the currently enabled parallel NCO processing window; Based on the integer part Determine the sampling segment containing the timestamp, and calculate the offset of the timestamp within the corresponding segment: ； Based on the initial phase value of the sampling segment With phase increment Calculate the mapped phase value corresponding to the timestamp: ； Calculate the normalized value of the timestamp offset from the zero point of the symbol phase. : ； Calculate the phase zero-point sequence number corresponding to the timestamp : ； According to the normalized value and the phase zero point number mark Obtain the bidirectional ranging timestamp calculation results.

7. The parallel NCO bit synchronization and timestamp calculation method for high-dynamic bidirectional ranging according to claim 1, characterized in that, Step S5 also includes discrete modeling and stability analysis after the parallel NCO embedding bit synchronization loop: Establish the recurrence relation of parallel NCO in the discrete domain: ， in, This represents the initial phase value of the k-th sampling point in the h-th processing. This represents the cumulative phase value of the (k+m)th sampling point in the (h+1)th processing iteration. is the average normalized phase increment of the h-th processing, and m is the number of parallel processing windows; The z-domain transfer function of the parallel NCO is derived based on the aforementioned recursive relationship: ， in, The z-transform result of the parallel NCO phase adjustment cumulant. This is the z-transform result of the loop filter output error filtering value. For discrete-domain delay operators; The z-domain transfer function is embedded into a second-order bit synchronization loop architecture. Combined with the transfer function of the loop filter, the loop characteristic equation is constructed based on the loop open-loop transfer function, and the loop stability detection polynomial is derived. The coefficients of the stability detection polynomial are determined according to the Routh criterion or the Julius criterion: if the polynomial satisfies that the modulus of all roots is less than 1, the loop is considered stable; otherwise, the loop filter parameters are adjusted until the stability condition is met. The designed loop parameters are substituted into the phase recursion model of the high dynamic scenario. The phase adjustment convergence speed and steady-state error of the position synchronization loop are verified by simulation to ensure that the parameters are adapted to the real-time and accuracy requirements of high dynamic two-way ranging.

8. The parallel NCO bit synchronization and timestamp calculation method for high-dynamic bidirectional ranging according to claim 1, characterized in that, In step S5, the evaluation of timestamp stability and ranging accuracy includes: Normalized value based on the timestamp offset from the zero point of the symbol phase obtained from the solution Calculate under different signal-to-noise ratio conditions Standard deviation; Build The mapping curve between standard deviation and signal-to-noise ratio is used to complete the quantitative evaluation of the timestamp stability of the two-way ranging receiver in a high dynamic environment. Simultaneously based on The mapping relationship between standard deviation and ranging error is used to complete the quantitative analysis of the receiver ranging accuracy.

9. A parallel NCO bit synchronization and timestamp calculation system for high-dynamic bidirectional ranging, characterized in that, include: The temporal geometry modeling module constructs a temporal geometry model of the signal time stretching effect in high dynamic scenarios and establishes the mapping relationship between Doppler frequency offset, Doppler acceleration and sampling point phase increment. The optimal NCO processing module, based on the aforementioned temporal geometry model, constructs a parallel NCO optimal processing window architecture containing Doppler acceleration recursion, performs phase recursion calculation, state determination, and timing deviation estimation for several consecutive sampling points within the processing window, and outputs the timing deviation control parameters required for parallel interpolation. The suboptimal NCO processing module, based on the aforementioned temporal geometry model, constructs a parallel NCO suboptimal processing window architecture that ignores Doppler acceleration, performs phase calculation, scene branch determination, and timing deviation estimation within a fixed parallel processing window, and outputs timing deviation control parameters adapted to low-complexity scenarios. The timestamp calculation module establishes a mapping calculation mechanism between the bidirectional ranging timestamp and the parallel NCO phase. Based on the phase output of the optimal processing window architecture or the suboptimal processing window architecture of the parallel NCO, it calculates the normalized value and sequence mark of the timestamp deviation from the zero point of the symbol phase. The bit synchronization and performance evaluation module connects the time offset control parameters to the high-speed parallel demodulation interpolation filtering module to complete the bit synchronization process, synchronizes the timestamp information based on the calculated timestamp information, and evaluates the timestamp stability and ranging accuracy of the two-way ranging receiver.

10. A computer device, characterized in that, The method includes a memory and a processor, wherein the memory stores computer-readable instructions that, when executed by the processor, cause the processor to perform the steps of the parallel NCO bit synchronization and timestamp calculation method for high dynamic bidirectional ranging as described in any one of claims 1 to 8.

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