Clock frequency synchronization method, network interconnection device and clock frequency synchronization apparatus

Abstract

The application discloses a clock frequency synchronization method, a network interconnection device and a clock frequency synchronization device. The clock frequency synchronization method comprises the following steps: if the clock frequency of a current network interconnection device changes, an Esmc indication packet is sent to a next-level network interconnection device, the Esmc indication packet comprises extended synchronization mode indication information, the next-level network interconnection device receives the Esmc indication packet, and clock frequency synchronization is performed based on the synchronization mode indication information. In the technical scheme, the clock frequency synchronization of the next-level network interconnection device is performed after the clock frequency of any level network interconnection device (a previous-level network interconnection device) changes, the situation that the synchronization starts before the clock frequency changes and the synchronization ends after the clock frequency changes is avoided, and the clock synchronization efficiency is improved.

Description

Technical Field

[0001] This invention relates to the field of clock frequency synchronization technology, specifically to a clock frequency synchronization method, a network interconnection device, and a clock frequency synchronization apparatus. Background Technology

[0002] The IEEE 1588 standard (IEEE 1588 Precision Time Protocol, or PTP for short) is a high-precision time synchronization standard developed by the Institute of Electrical and Electronics Engineers (IEEE). The core objective of this protocol is to provide sub-microsecond or even nanosecond-level time synchronization accuracy for devices in distributed networks, meeting the stringent time synchronization performance requirements of application scenarios. Currently, the PTP protocol is widely used in time-sensitive networks such as power automation systems, industrial control networks, data centers, and communication base stations, becoming one of the key technologies for achieving high-precision distributed clock synchronization.

[0003] In the PTP protocol calculation process, maintaining consistent clock frequencies among devices is crucial for achieving high-precision time synchronization. In existing technologies, when devices do not support hardware-based Synchronous Ethernet (SyncE) schemes (which rely on Esmc messages for exchanging clock quality information between devices) to maintain clock frequency synchronization, software-based clock frequency calibration is typically used. This involves calculating the cumulative deviation based on the timestamps carried in the PTP protocol messages to correct the frequency differences between interconnected network devices, thereby achieving high-precision clock synchronization. A common method in this software frequency synchronization scheme is as follows: Record the timestamps of the 1st and Nth messages when they are sent from the upstream interconnected device, and the timestamps of the 1st and Nth messages when they arrive at the downstream interconnected device. Clock frequency calibration is then performed using the ratio of the difference between the timestamps of the 1st and Nth messages sent from the upstream interconnected device and the difference between the timestamps of the 1st and Nth messages arriving at the downstream interconnected device. While this method can achieve clock frequency synchronization between network interconnection devices, it fails to detect changes in the clock frequency of the upstream network interconnection device. For example, when the upstream network interconnection device sends the 20th message (20 is less than N), the clock frequency changes. This means that the clock reference for messages 1 to 20 sent by the upstream network interconnection device is before the frequency change, while the clock reference for messages 21 to N is after the frequency change. Therefore, when the downstream network interconnection device performs clock frequency calibration based on these messages, the obtained clock frequency calibration value is incorrect. In other words, this clock frequency synchronization is invalid. It is only valid if the clock references for both the 1st and Nth messages are based on the changed clock frequency. Thus, the current clock frequency synchronization method may result in invalid calibration due to its inability to detect changes in the clock frequency of the upstream network interconnection device, leading to reduced clock synchronization efficiency. Summary of the Invention

[0004] The main technical problem solved by this invention is that current clock frequency synchronization methods may result in invalid calibration and reduced clock synchronization efficiency because they cannot detect changes in the clock frequency of the upstream network interconnection device.

[0005] According to a first aspect, one embodiment provides a clock frequency synchronization method applied to network interconnection devices, wherein multiple network interconnection devices can be cascaded, and the first-level network interconnection device in the cascaded configuration is connected to a clock source; the clock frequency synchronization method includes:

[0006] When the clock frequency of the first-level network interconnection device changes, a first Esmc message is sent to the second-level network interconnection device, so that the second-level network interconnection device starts frequency synchronization when it receives a PTP message that is K messages apart from the first Esmc message. The first Esmc message is used to indicate the synchronization mode indication information that frequency synchronization extension starts when a PTP message that is K messages apart from the first Esmc message is received.

[0007] When the clock frequency of a non-first-level network interconnection device changes, if the non-first-level network interconnection device has not synchronized its clock frequency with the next-level network interconnection device, the first Esmc message is sent to the next-level network interconnection device, so that the next-level network interconnection device can start frequency synchronization when it receives a PTP message that is K messages apart from the first Esmc message.

[0008] In one embodiment, when the clock frequency of a non-first-level network interconnection device changes, if the non-first-level network interconnection device has not synchronized its clock frequency with the next-level network interconnection device, the first Esmc message is sent to the next-level network interconnection device, so that the next-level network interconnection device starts frequency synchronization upon receiving a PTP message that is K messages apart from the first Esmc message. The process then includes:

[0009] Once the clock frequency synchronization of the third-level or subsequent network interconnection devices is completed, an Esmc feedback message is sent to the previous-level network interconnection device. This causes the previous-level network interconnection device to change the flag bit of the port that sends messages to the next-level network interconnection device from the first flag to the second flag. The first flag indicates that the next-level network interconnection device has not performed clock frequency synchronization with the previous-level network interconnection device, and the second flag indicates that the next-level network interconnection device has performed clock frequency synchronization with the previous-level network interconnection device. The Esmc feedback message indicates that frequency synchronization is complete.

[0010] In one embodiment, the clock frequency synchronization method further includes:

[0011] When the clock frequency of a non-first-level network interconnection device changes, if the non-first-level network interconnection device has synchronized its clock frequency with the next-level network interconnection device, a second Esmc message is sent to the next-level network interconnection device. The second Esmc message carries the clock frequency synchronization value of the non-first-level network interconnection device at the time of current frequency synchronization, so that the next-level network interconnection device can perform frequency synchronization based on the clock frequency synchronization value of the non-first-level network interconnection device at the time of current frequency synchronization.

[0012] The second Esmc message is used to characterize the synchronization method indication information for frequency synchronization based on the clock frequency synchronization value carried in the second Esmc message.

[0013] In one embodiment, when the clock frequency of a non-first-level network interconnection device changes, if the non-first-level network interconnection device has previously synchronized its clock frequency with a next-level network interconnection device, a second Esmc message is sent to the next-level network interconnection device. The second Esmc message carries the clock frequency synchronization value of the non-first-level network interconnection device at its current frequency synchronization, so that the next-level network interconnection device performs frequency synchronization based on the clock frequency synchronization value of the non-first-level network interconnection device at its current frequency synchronization. This then includes:

[0014] When the non-first-level network interconnection device sends the second Esmc message to the next-level network interconnection device, the port on which it sends the message to the next-level network interconnection device is changed from the second identifier to the first identifier. The first identifier is used to identify that the next-level network interconnection device and the previous-level network interconnection device have not performed clock frequency synchronization, and the second identifier is used to identify that the next-level network interconnection device and the previous-level network interconnection device have performed clock frequency synchronization.

[0015] Once the clock frequency synchronization of the next-level network interconnection device is completed, an Esmc feedback message is sent to the non-first-level network interconnection device, so that the non-first-level network interconnection device sets the flag bit of the port that sends messages to the next-level network interconnection device from the first flag to the second flag. The Esmc feedback message is used to indicate that the frequency synchronization is complete.

[0016] In one embodiment, the next-level network interconnection device performs frequency synchronization based on the clock frequency synchronization value of the non-first-level network interconnection device during current frequency synchronization by using the clock frequency synchronization value carried in the second Esmc message as the clock frequency synchronization value for this frequency synchronization.

[0017] In one embodiment, for the first-level network interconnection device, the clock frequency change is due to a switch in the clock source or a failure of the clock source.

[0018] In one embodiment, for the non-first-level network interconnection device, the clock frequency change is performed by clock frequency synchronization.

[0019] In one embodiment, the next-level network interconnection device starts frequency synchronization when it receives a PTP message that is K messages apart from the first Esmc message, and the next-level network interconnection device starts frequency synchronization when it receives a PTP message adjacent to the first Esmc message.

[0020] According to a second aspect, one embodiment provides a network interconnection device, comprising:

[0021] Memory, used to store programs;

[0022] A processor for implementing the clock frequency synchronization method as described above by executing the program.

[0023] According to a third aspect, one embodiment provides a clock frequency synchronization device, comprising: a plurality of network interconnected devices;

[0024] The plurality of network interconnection devices are cascaded, and the first-level network interconnection device is connected to the clock source. Each of the plurality of network interconnection devices is a network interconnection device as described above.

[0025] According to the clock frequency synchronization method, network interconnection device, and clock frequency synchronization apparatus of the above embodiments, when the clock frequency of the first-level network interconnection device changes, it can send a first Esmc message to cause the second-level network interconnection device to start clock frequency synchronization in response to the received first Esmc message. When the clock frequency of a non-first-level network interconnection device changes, if the non-first-level network interconnection device has not performed clock frequency synchronization with the next-level network interconnection device, it sends a first Esmc message to the next-level network interconnection device, causing the next-level network interconnection device to start clock frequency synchronization in response to the received first Esmc message. Therefore, at least in the case where the clock frequency of the first-level network interconnection device or a non-first-level network interconnection device has not performed clock frequency synchronization with the next-level network interconnection device, clock frequency synchronization of any next-level network interconnection device occurs after the clock frequency of the previous-level network interconnection device changes. This avoids situations where synchronization begins before the clock frequency change and ends after the clock frequency change, thus improving clock synchronization efficiency. Attached Figure Description

[0026] Figure 1 This is a flowchart of clock frequency synchronization in the prior art;

[0027] Figure 2 A PTP networking system with three-level network interconnection equipment;

[0028] Figure 3A flowchart illustrating clock frequency synchronization using existing technologies for a PTP networking system of three-level network interconnection devices;

[0029] Figure 4 This is a flowchart of a clock frequency synchronization method in one embodiment;

[0030] Figure 5 This is a flowchart illustrating the clock frequency synchronization process when a PTP networking system with three-level network interconnection devices in one embodiment uses a clock frequency synchronization method. Detailed Implementation

[0031] The present invention will now be described in further detail with reference to specific embodiments and accompanying drawings. Similar elements in different embodiments are referred to by associated similar element reference numerals. In the following embodiments, many details are described to facilitate a better understanding of the invention. However, those skilled in the art will readily recognize that some features may be omitted in different situations, or may be replaced by other elements, materials, or methods. In some cases, certain operations related to the present invention are not shown or described in the specification. This is to avoid obscuring the core parts of the invention with excessive description. For those skilled in the art, detailed description of these related operations is not necessary; they can fully understand the related operations based on the description in the specification and general technical knowledge in the art.

[0032] Furthermore, the features, operations, or characteristics described in the specification can be combined in any suitable manner to form various embodiments. At the same time, the steps or actions in the method description can be rearranged or adjusted in a manner obvious to those skilled in the art. Therefore, the various orders in the specification and drawings are only for the clear description of a particular embodiment and do not imply a necessary order, unless otherwise stated that a particular order must be followed.

[0033] The serial numbers assigned to components in this document, such as "first" and "second," are used only to distinguish the described objects and have no sequential or technical meaning. The terms "connection" and "linkage" used in this invention, unless otherwise specified, include both direct and indirect connections (linkages).

[0034] The IEEE 1588 standard (officially the IEEE 1588 Precision Time Protocol, or PTP for short) is a high-precision time synchronization standard developed by the Institute of Electrical and Electronics Engineers (IEEE). Its core objective is to provide sub-microsecond or even nanosecond-level time synchronization accuracy for devices in distributed networks, meeting the stringent time synchronization performance requirements of application scenarios. Currently, the PTP protocol is widely used in time-sensitive networks such as power automation systems, industrial control networks, data centers, and communication base stations, becoming one of the key technologies for achieving high-precision distributed clock synchronization.

[0035] Ethernet Synchronization Message Channel (ESMC) is the core message mechanism in synchronous Ethernet used to transmit Synchronization Status Messages (SSM). This mechanism is based on the ITU-T G.8264 standard and is carried out using the IEEE 802.3 organization's proprietary Slow Protocol (OSSP). The core function of EMC is to transmit the Clock Quality Level (QL), thereby enabling the selection and master determination of the synchronization source and effectively avoiding timing loops.

[0036] SyncE (Synchronous Ethernet) is a high-precision frequency synchronization technology implemented based on the Ethernet physical layer. Its core idea is to transmit a standard frequency reference through the Ethernet link, thereby achieving clock frequency synchronization among all devices in the network. This technology effectively solves the technical problem that traditional asynchronous Ethernet cannot provide a stable frequency reference.

[0037] The GM (Grandmaster Clock) is the time reference source for the entire PTP synchronization network and is located at the root node of the PTP hierarchical architecture. The time of all slave clocks and boundary clocks (BCs) in the network ultimately traces back to this Grandmaster Clock.

[0038] In PTP protocol calculations, consistent clock frequencies across all interconnected network devices are crucial for achieving high-precision time synchronization. Existing technologies, when interconnected network devices do not support hardware-based SyncE schemes (which require clock quality information exchange between devices based on the aforementioned Esmc messages) to maintain clock frequency synchronization, typically employ software-based solutions that calculate cumulative deviations based on the timestamps carried in the PTP protocol messages to correct frequency differences between devices, thus maintaining high-precision clock synchronization. Figure 1The illustrated process involves upstream and downstream network interconnection devices completing master-slave negotiation confirmation during clock frequency synchronization. After confirmation, the master device sends Sync messages to the slave device at a certain frequency (or, if using the two-step method for clock frequency synchronization, sending a Sync message + followup message). When the slave network interconnection device receives the first Sync message from the master network interconnection device, it parses the first Sync message (or parses the followup messages that arrive after the first Sync message) to obtain the timestamp of the first Sync message sent from the master network interconnection device (generated by the upstream network interconnection device) and the timestamp of the first Sync message arriving at the downstream network interconnection device (generated by the upstream network interconnection device). When the Nth Sync message is received from the network interconnection device, it is parsed (or a follow-up message that arrives after the Nth Sync message) to obtain the timestamp of the Nth Sync message sent from the main network interconnection device (generated by the upstream network interconnection device) and the timestamp of the Nth Sync message arriving at the downstream network interconnection device (generated by the downstream network interconnection device). Based on the four timestamps, the clock frequency difference is calculated using Formula 1. When the clock frequency interpolation is greater than the set threshold, clock frequency synchronization is performed on the downstream network interconnection device according to the calculated clock frequency difference, thus completing the clock frequency synchronization between the upstream and downstream network interconnection devices. Formula 1 is as follows:

[0039] ;

[0040] This represents the timestamp when the Nth Sync message arrives at the downstream network interconnect device; This indicates the timestamp when the first Sync message arrived at the downstream network interconnect device; This represents the timestamp when the Nth Sync message was sent from the upstream network interconnection device; This indicates the timestamp when the first Sync message was sent from the upstream network interconnect device.

[0041] In practical applications, maintaining consistent clock frequencies among interconnected network devices is crucial for achieving high-precision time synchronization during the PTP protocol calculation process. In existing technologies, when interconnected network devices do not support hardware-based Synchronous Ethernet (SyncE) schemes (which rely on Esmc messages for exchanging clock quality information between devices) to maintain clock frequency synchronization, software-based clock frequency calibration is typically used. This involves calculating the cumulative deviation based on the timestamps carried in the PTP protocol messages to correct the frequency difference between interconnected network devices, thereby achieving high-precision clock synchronization. In this software frequency synchronization scheme, to reduce the impact of quantization errors and message loss on the stability of frequency synchronization, a frequency deviation calculation is performed every N messages received (generally N is greater than 50) instead of every two messages. If the deviation exceeds a threshold, the downstream device performs a frequency synchronization, improving the accuracy and stability of frequency synchronization. For example, with a common packet transmission frequency of 8pps and N = 100, each clock frequency deviation calculation takes 100 / 8 = 12.5 seconds.

[0042] A real PTP network system is a strictly hierarchical network. To ensure time synchronization accuracy, it adopts a "neighborly interaction, layer-by-layer transmission" mechanism. Message interaction only occurs between the master and slave ports of adjacent layers, and the synchronization processes of upper and lower levels are independent of each other, without direct interaction across layers. When the master clock frequency of the entire network changes (such as a switch in the GM's clock source), all devices in the entire PTP network should recalculate frequency synchronization accordingly. In current technical solutions, the convergence time for frequency synchronization requires multiple software calculation cycles (because the lower layer can only correctly synchronize its frequency after each upper layer has completed frequency synchronization in the entire hierarchical structure). The main reasons affecting the completion time of the entire network clock frequency synchronization are as follows:

[0043] 1) PTP messages do not interact across levels; they can only be passed layer by layer. Specifically, after the M-1 level network interconnection device completes frequency synchronization, the M level network interconnection device can only correctly perform frequency synchronization if all PTP messages used for frequency updates by the M-1 level network interconnection device are PTP messages sent after the M-1 level frequency synchronization. Similarly, the M+1 level network interconnection device can only correctly perform frequency synchronization if all PTP messages used for frequency updates by the M+1 level network interconnection device are PTP messages sent after the M level frequency synchronization.

[0044] 2) When the M-level network interconnection device completes a clock frequency update by receiving a PTP message from the M-1 level, the M+1 level network interconnection device will not detect it in a timely manner. For example... Figure 1As shown, one frequency synchronization calculation requires receiving N PTP messages. If, within a certain frequency synchronization calculation cycle of the M+1 level network interconnection device, the M-level network interconnection device completes a frequency update (e.g., if N is 50, the clock frequency of the upper-level network interconnection device is updated when the 25th message is received), the M+1 level network interconnection device, unable to detect this in time, will continue to follow the same frequency calculation method. Figure 1 The process shown performs frequency synchronization. Clearly, since the two message timestamps recorded by the lower-level network interconnection device are from before and after the clock frequency update of the upper-level network interconnection device, respectively, at this time... Figure 1 The frequency difference calculated by the process shown is incorrect. A new complete cycle is needed to correctly calculate the frequency difference for synchronization (i.e., in the worst case, almost a complete calculation cycle is wasted).

[0045] In summary, the average time for a Level M network interconnection device to complete frequency synchronization to the level M+1 network interconnection device is approximately 1.5T, and the average time for a Level M-1 network interconnection device to complete frequency synchronization to the level M+1 network interconnection device is approximately 3T, where T is one software frequency synchronization calculation cycle.

[0046] Based on the above analysis, when the master clock source experiences a frequency change, the time required for the entire network to complete frequency synchronization can reach tens of seconds or even minutes. During this time, due to the inconsistent clock frequencies of the interconnected network devices, time synchronization cannot achieve the expected accuracy range, which is unacceptable in high-precision time-sensitive networks. Figure 2 The diagram shows a PTP networking system with three-level network interconnection devices. The specific process for clock frequency synchronization in this PTP networking system using existing methods is as follows: Figure 3 As shown, the first-level network interconnection device preferentially selects the first clock source among the clock sources. The second-level and third-level network interconnection devices receive PTP packets sent by the upper-level network interconnection device based on... Figure 1 The process begins with clock frequency offset calculation. While the first-level network interconnect device is synchronizing its frequency, the second-level network interconnect device cannot promptly notify the third-level network interconnect device that its local clock frequency has been updated. The third-level network interconnect device can only notify the third-level network interconnect device after a certain frequency offset calculation is completed. Figure 1Only when the clock frequency of the first-level network interconnect device changes can the second-level network interconnect device detect the clock frequency update and correctly update its own clock frequency in subsequent calculation cycles. Similarly, the second-level network interconnect device cannot detect when the clock frequency of the first-level network interconnect device changes. Therefore, when the clock frequency of the first-level network interconnect device changes, the second-level network interconnect device will not detect it in time. In a clock frequency synchronization, clock frequency synchronization may be based on the PTP packets sent by the first-level network interconnect device before the clock frequency change and the PTP packets sent by the first-level network interconnect device after the clock frequency change. Figure 1 The frequency difference calculated by the process shown is incorrect, and a new complete cycle is needed to correctly calculate the frequency difference for synchronization. Similarly, when the clock frequency of the second-level network interconnection device changes, the third-level network interconnection device will not detect it in time. Again, the frequency difference calculated in a certain calculation cycle is incorrect, and a new complete cycle is needed to correctly calculate the frequency difference for synchronization.

[0047] To address the aforementioned technical problems, this application provides a clock frequency synchronization method applied to network interconnection devices. When multiple network interconnection devices are cascaded, if the clock frequency of any level of network interconnection device changes, it will send an Esmc indication message to the next level of network interconnection device. Upon receiving the Esmc indication message, the next level network interconnection device will begin clock frequency synchronization based on the extended calibration method indication information included in the Esmc indication message. Thus, the clock frequency synchronization of the next level network interconnection device occurs after the clock frequency of the previous level network interconnection device changes, avoiding situations where synchronization begins before the clock frequency change and ends after the clock frequency change. This effectively changes the convergence time when frequency synchronization is completed when the clock frequency changes, improving clock synchronization efficiency.

[0048] In some embodiments, multiple network interconnection devices can be configured and cascaded. The first-level network interconnection device in the cascaded configuration is connected to a clock source, which may be referred to as the Grandmaster Clock (GM). The clock source may include a first clock source and a second clock source. The first-level network interconnection device connects to either the first or second clock source, preferentially selecting the first clock source; that is, if the first clock source is functioning normally, the first-level network interconnection device selects the first clock source. If the clock source connected to the first-level network interconnection device switches or fails, the clock frequency of the first-level network interconnection device is considered to have changed. A change in clock frequency is also considered to occur when non-first-level network interconnection devices are performing clock frequency synchronization.

[0049] When a network interconnection device experiences a clock frequency change, it can send a first Esmc message and a second Esmc message to the next-level network interconnection device. The first Esmc message is used to indicate an extended synchronization mode indication that frequency synchronization begins upon receiving a PTP message that is K messages apart from the first Esmc message. The second Esmc message is used to indicate an extended synchronization mode indication that frequency synchronization is performed based on the clock frequency synchronization value carried in the second Esmc message. The first-level network interconnection device, being the master clock, does not perform clock frequency synchronization; the first-level network interconnection device only sends the first Esmc message.

[0050] In some embodiments, when the clock frequency of the first-level network interconnect device changes, the first-level network interconnect device can send a first Esmc message to the second-level network interconnect device, so that after receiving the first Esmc message, the second-level network interconnect device can start frequency synchronization based on a PTP message that is K messages apart from the first Esmc message.

[0051] For non-first-level network interconnection devices: when any level of network interconnection device has performed clock frequency synchronization, and the next level of network interconnection device has not performed frequency synchronization with any level of network interconnection device, then any level of network interconnection device sends a first Esmc message to the next level of network interconnection device, so that the next level of network interconnection device, after receiving the first Esmc message, starts frequency synchronization based on an interval of K PTP messages from the first Esmc message.

[0052] For example, four cascaded network interconnection devices (no clock frequency synchronization has been performed between any two adjacent cascaded network interconnection devices). When the clock frequency of the first-level network interconnection device changes, it sends a first Esmc message to the second-level network interconnection device. The second-level network interconnection device starts clock frequency synchronization when it receives the first Esmc message after an interval of K PTP messages. After clock frequency synchronization is completed, the second-level network interconnection device sends a first Esmc message to the third-level network interconnection device. The third-level network interconnection device starts clock frequency synchronization when it receives the first Esmc message after an interval of K PTP messages. After clock frequency synchronization is completed, the third-level network interconnection device sends a first Esmc message to the fourth-level network interconnection device. The fourth-level network interconnection device starts clock frequency synchronization when it receives the first Esmc message after an interval of K PTP messages. After clock frequency synchronization is completed by the fourth-level network interconnection device, the clock frequency synchronization of this round is completed.

[0053] Therefore, it can be seen that, at least for the first-level network interconnection device or the non-first-level network interconnection device and the next-level network interconnection device, when the next-level network interconnection device of any level performs clock frequency synchronization, it is done after the clock frequency of the previous-level network interconnection device changes. This avoids the situation where synchronization starts before the clock frequency changes and ends after the clock frequency changes, thus improving clock synchronization efficiency.

[0054] In some embodiments, when frequency synchronization is started based on an interval of K PTP messages from the first Esmc message, K can be set to 0. That is, when the first Esmc message is received, frequency synchronization is started based on the PTP messages adjacent to the first Esmc message.

[0055] In some embodiments, after receiving an Esmc indication message (first Esmc message), a frequency synchronization value is calculated based on the first PTP message and a second PTP message that is N PTP messages apart from the first PTP message. N can be, but is not limited to, 50.

[0056] When calculating the frequency synchronization value, the next-level network interconnection device extracts the precise transmission time carried in the first PTP message it receives and records it as the first timestamp. Extract the precise transmission time carried in the received second PTP message and record it as the second timestamp. The next-level network interconnection devices each record their local clock time when they receive the first PTP packet, and record this as the third timestamp. The local clock time when the second PTP message is received is recorded as the fourth timestamp. Calculate the third timestamp and the fourth timestamp The time interval between the first and second time differences is called the second time difference. The frequency synchronization value is calculated using the first and second time differences. Specifically, the ratio R of the first and second time differences is calculated. When R > 1, it indicates that the local device is moving too slowly and needs to accelerate; when R < 1, it indicates that the local device is moving too fast and needs to decelerate. The local device can be understood as the next-level network interconnection device. The magnitude of R represents the correction direction. A value greater than 1 indicates that the current network interconnection device (the next-level network interconnection device) has a faster frequency, and a value less than 1 indicates that it is slower.

[0057] In one specific embodiment, ±1ns is compensated every N local cycles, where N = 1 / (8*|R-1|). The local cycle is set to 8ns, and the step size is 1ns. R is 1 and remains unchanged. If it is greater than 1, it is increased by 1ns, and if it is less than 1, it is decreased by 1ns.

[0058] In some embodiments, when the clock frequency synchronization of the third-level or subsequent network interconnection devices is completed, an Esmc feedback message is sent to the previous-level network interconnection device, so that the previous-level network interconnection device sets the flag bit of the port that sends messages to the next-level network interconnection device from the first flag to the second flag.

[0059] Specifically, for network interconnection devices at level 3 or later, after sending a first Esmc message to the next-level network interconnection device, the next-level network interconnection device responds to the first Esmc message by performing clock frequency synchronization and then sends an Esmc feedback message to the previous-level network interconnection device. The Esmc feedback message indicates that frequency synchronization is complete. That is, after receiving the Esmc feedback message, the previous-level network interconnection device considers that the next-level network interconnection device has completed clock frequency synchronization based on its first Esmc message. Therefore, the previous-level network interconnection device sets the flag bit of the port that sent the message to the next-level network interconnection device from the first flag to the second flag. The first flag indicates that the next-level network interconnection device and the previous-level network interconnection device have not performed clock frequency synchronization. The second flag indicates that the next-level network interconnection device and the previous-level network interconnection device have performed clock frequency synchronization. The Esmc feedback message indicates that frequency synchronization is complete.

[0060] In some embodiments, when the clock frequency of a non-first-level network interconnection device changes, if the non-first-level network interconnection device has synchronized its clock frequency with the next-level network interconnection device, a second Esmc message is sent to the next-level network interconnection device. The second Esmc message carries the clock frequency synchronization value of the non-first-level network interconnection device at the time of current frequency synchronization, so that the next-level network interconnection device can perform frequency synchronization based on the clock frequency synchronization value of the non-first-level network interconnection device at the time of current frequency synchronization.

[0061] Specifically, any network interconnection device at the second level or subsequent levels can determine whether clock frequency synchronization has been performed with the next-level network interconnection device by checking the flag bit of the port on which it sends messages to the next-level network interconnection device. That is, when the flag bit is the first flag, it means that clock frequency synchronization has not been performed; when the flag bit is the second flag, it means that clock frequency synchronization has been performed.

[0062] For second-level or subsequent network interconnection devices: After any level of network interconnection device performs clock frequency synchronization, if the flag bit of the port sending messages to the next-level network interconnection device is set to the second identifier, then the next-level network interconnection device sends a second Esmc message carrying the frequency synchronization value from this clock frequency synchronization. Upon receiving the second Esmc message, the next-level network interconnection device performs clock frequency synchronization based on the frequency synchronization value in the second Esmc message. Specifically, after any level of network interconnection device sends the second Esmc message to the next-level network interconnection device, it sets the flag bit of the port sending the message to the next-level network interconnection device from the second identifier to the first identifier. After the next-level network interconnection device completes clock frequency synchronization, it sends an Esmc feedback message to non-first-level network interconnection devices, causing the non-first-level network interconnection devices to set the flag bit of the port sending messages to the next-level network interconnection device from the first identifier to the second identifier. The Esmc feedback message indicates that frequency synchronization is complete.

[0063] Therefore, for second-level or subsequent network interconnection devices, when any level of network interconnection device has synchronized its clock frequency with the next level of network interconnection device, if the clock frequency changes again, a second Esmc message is sent to the next level of network interconnection device after the clock frequency synchronization is completed. This allows the next level of network interconnection device to synchronize its clock frequency based on the frequency synchronization value in the second Esmc message. This also avoids the situation where synchronization starts before the clock frequency changes and ends after the clock frequency changes, thus improving clock synchronization efficiency.

[0064] For example, four cascaded network interconnect devices (any two adjacent cascaded network interconnect devices have undergone clock frequency synchronization). For the second-level or subsequent network interconnect devices, after the clock frequency synchronization of the second-level network interconnect device is completed, the identifier bit of the port sending messages to the third-level network interconnect device is set from the second identifier to the first identifier, and a second Esmc message is sent to the third-level network interconnect device. Upon receiving the second Esmc message, the third-level network interconnect device performs clock frequency synchronization based on the frequency synchronization value in the second Esmc message, and after synchronization is completed, sends an Esmc feedback message to the second-level network interconnect device. The second-level network interconnect device responds to the Esmc message. The feedback message sets the identifier of the port that sends the message to the third-level network interconnection device to the second identifier; further, the third-level network interconnection device sets the identifier of the port that sends the message to the fourth-level network interconnection device from the second identifier to the first identifier, and sends a second Esmc message to the fourth-level network interconnection device. Upon receiving the second Esmc message, the fourth-level network interconnection device performs clock frequency synchronization based on the frequency synchronization value in the second Esmc message, and after synchronization is completed, sends an Esmc feedback message to the third-level network interconnection device. In response to the Esmc feedback message, the third-level network interconnection device sets the identifier of the port that sends the message to the fourth-level network interconnection device to the second identifier.

[0065] In some embodiments, the first identifier can be identified by 0 and the second identifier can be identified by 1. That is, when it is necessary to change from the first identifier to the second identifier, the flag is changed from 0 to 1. Similarly, when it is necessary to change from the second identifier to the first identifier, the flag is changed from 1 to 0.

[0066] In some embodiments, the next-level network interconnection device that receives the second Esmc message uses the frequency synchronization value carried in the second Esmc message as the frequency synchronization value for this clock frequency synchronization to perform clock frequency synchronization. That is, it uses the frequency synchronization value when the previous-level network interconnection device performs clock frequency synchronization as the frequency synchronization value for this clock frequency synchronization to perform clock frequency synchronization.

[0067] Based on the above discussion, this clock frequency synchronization method, when multiple network interconnection devices are cascaded, will send an Esmc indication message to the next lower-level network interconnection device when the clock frequency of any level of network interconnection device changes. Upon receiving the Esmc indication message, the next-level network interconnection device will begin clock frequency synchronization based on the extended calibration method indication information included in the Esmc indication message. This avoids situations where synchronization begins before the clock frequency change and ends after the clock frequency change, thus improving clock synchronization efficiency and effectively changing the convergence time when frequency synchronization is completed during clock frequency changes. Especially for third-level or later network interconnection devices, when a lower-level network interconnection device has previously performed frequency synchronization with a higher-level network interconnection device, the lower-level network interconnection device can directly use the frequency synchronization value from the previous level's clock frequency synchronization as the current clock frequency synchronization value, eliminating the need for calculation and greatly accelerating the convergence time.

[0068] The Esmc indication message includes a first Esmc message and a second Esmc message. When the clock frequency of a first-level network interconnection device changes, it sends a first Esmc message to a second-level network interconnection device. When the clock frequency of a second-level or subsequent network interconnection device changes, it sends a first Esmc message if it has not synchronized its clock frequency with the next-level network interconnection device, and sends a second Esmc message if it has synchronized its clock frequency. For details, please refer to the above discussion, which will not be elaborated on here.

[0069] like Figure 5 The diagram shows a flowchart illustrating clock frequency synchronization in a PTP networking system with three-level network interconnection devices, using a clock frequency synchronization method. Specifically, the three-level network interconnection devices perform PTP hierarchy election. When a first-level network interconnection device connects to a clock source, it prioritizes using the first clock source. If the second-level and third-level network interconnection devices have not previously synchronized their clock frequencies, the second-level network interconnection device, upon receiving a PTP message from a first-level network interconnection device, will begin synchronizing its clock frequency according to the specified clock frequency. Figure 1 The process involves calculating the clock frequency offset. When the calculated clock frequency offset exceeds a threshold, the second-level network interconnect device performs clock frequency synchronization. After synchronization, it sends a first Esmc message to the third-level network interconnect device, notifying it that the upstream network interconnect device's clock frequency has changed. Upon receiving the first Esmc message, the third-level network interconnect device restarts the process according to the specified procedure. Figure 1The process involves clock frequency synchronization, discarding previously received PTP messages, and after clock frequency synchronization is completed, sending an Esmc feedback message to the second-level network interconnection device. In response to the Esmc feedback message, the second-level network interconnection device will send a message to the third-level network interconnection device. The port identifier position of the message will be set to the second identifier, indicating that the third-level network interconnection device and the second-level network interconnection device have performed clock frequency synchronization. Subsequently, when an anomaly occurs in the clock signal input link between the first clock source and the first-level network interconnection device, the first-level network interconnection device detects the link anomaly and actively connects to the second clock source. The first-level network interconnection device then considers the clock frequency to have changed and sends a first Esmc message to the second-level network interconnection device. The second-level network interconnection device begins clock frequency synchronization. After clock frequency synchronization is completed, since clock frequency synchronization has already been performed with the third-level network interconnection device, it sends a second Esmc message to the third-level network interconnection device. The third-level network interconnection device performs frequency synchronization locally based on the frequency synchronization value carried in the second Esmc message, using the frequency synchronization value carried in the second Esmc message as the frequency synchronization value for this clock frequency synchronization.

[0070] In some embodiments, based on the scalable characteristics of Esmc messages specified in the ITU-T G.8264 standard, corresponding information is carried by supplementing the PDU (Protocol Data Unit) field of the Esmc message to realize information exchange about the frequency synchronization status when synchronizing the clock based on the PTP protocol message, thereby ensuring rapid frequency synchronization when the clock frequency changes.

[0071] Specifically, the extended TLV format is defined as shown in Table 1.

[0072] Table 1

[0073] 0x10 00-0C Sub_typeDirectionCorrretion_Value

[0074] In Table 1, Type indicates the extended TLV type, carrying a fixed value of 0x10 to indicate that this TLV is a SYNC_TLV used for clock frequency synchronization (distinguishing it from other TLVs, such as the standard QL_TLV, which has a value of 0x01 and carries clock quality information). Length indicates the length of the field occupied by the subsequent value, currently fixed at 00-0C (hexadecimal, 12 bytes): 2 bytes Sub_type, 2 bytes Direction, and 2 bytes Correction_Value; Value indicates the specific information carried by this TLV field, Sub_type indicates the subtype, Direction indicates the correction direction, and Correction_Value indicates the clock frequency synchronization value. Message encapsulation format: The message header encapsulation is completely consistent with the standard Esmc message. According to the ITU-T G.8264 standard, each Esmc message should carry a QL_TLV in the header. For devices that support SynCe, this TLV field is filled normally according to the standard (meaning the QL_TLV field is filled normally according to the Esmc standard without modifying the content of the field). For devices that do not support SynCe, this TLV is filled with 0x0f, indicating that it does not participate in the SynCe (election process). The above SYNC_TLV can be added after the QL_TLV to complete the encapsulation. The Value field contains three fields. The Sub_type field contains three message types used during software frequency synchronization, represented by 0x01, 0x02, and 0x03 respectively. Specifically, when a third-level or later network interconnect device completes clock frequency synchronization, it must actively notify the previous-level network interconnect device by sending an Esmc feedback message. This Esmc feedback message uses Sub_type0x01; parsing Sub_type0x01 indicates that the next-level network interconnect device has completed clock frequency synchronization. When the clock frequency of a network interconnect device changes, for the first-level network interconnect device, a first Esmc message is sent, using Sub_type0x02. For non-first-level network interconnect devices... If the next-level network interconnection device has not performed clock frequency synchronization, it sends a first Esmc message. The first Esmc feedback message uses Sub_type0x02. If the next-level network interconnection device has performed clock frequency synchronization, it sends a second Esmc message. The second Esmc feedback message uses Sub_type0x03, and the SYNC_TLV field in the second Esmc message is filled with Direction and Value fields. If the next-level network interconnection device needs clock frequency synchronization after receiving the second Esmc message, it can directly use the obtained Direction and Value to perform clock frequency synchronization without recalculation, which speeds up the convergence time. Then, it further sends an Esmc feedback message to the previous-level network interconnection device.

[0075] In some embodiments, the network interconnection device may be, but is not limited to, a switch.

[0076] In some embodiments, this application provides a network interconnection device, including a memory for storing a program and a processor for executing the program to implement the clock frequency synchronization method described above. Specific details are as described in the above embodiment of the clock frequency synchronization method, and will not be repeated here.

[0077] In some embodiments, this application provides a clock frequency synchronization device, including: a plurality of network interconnection devices; the plurality of network interconnection devices are cascaded, and the first-level network interconnection device is connected to a clock source, wherein each of the plurality of network interconnection devices is the network interconnection device described above. Specific details are as described in the specific embodiments of the clock frequency synchronization method above, and will not be elaborated further here.

[0078] In the above embodiments, implementation can be achieved, in whole or in part, by software, hardware, firmware, or any combination thereof. Furthermore, as those skilled in the art will understand, the principles herein can be reflected in a computer program product on a computer-readable storage medium pre-loaded with computer-readable program code. Any tangible, non-transitory computer-readable storage medium may be used, including magnetic storage devices (hard disks, floppy disks, etc.), optical storage devices (CDs, DVDs, Blu-ray discs, etc.), flash memory, and / or the like. These computer program instructions can be loaded onto a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to form a machine, such that instructions executing on the computer or other programmable data processing apparatus can generate means for performing a specified function. These computer program instructions can also be stored in a computer-readable storage medium that can instruct the computer or other programmable data processing apparatus to operate in a particular manner, such that instructions stored in the computer-readable storage medium can form an article of manufacture, including means for implementing the specified function. The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to perform a series of operational steps on the computer or other programmable apparatus to produce a computer-implemented process, such that instructions executing on the computer or other programmable apparatus can provide steps for implementing the specified function.

[0079] This document describes various exemplary embodiments with reference to them. However, those skilled in the art will recognize that changes and modifications can be made to the exemplary embodiments without departing from the scope of this document. For example, various operational steps and components for performing operational steps can be implemented in different ways depending on the specific application or considering any number of cost functions associated with the operation of the system (e.g., one or more steps can be deleted, modified, or combined with other steps).

[0080] While the principles herein have been illustrated in various embodiments, numerous modifications to the structures, arrangements, proportions, elements, materials, and components, particularly suited to specific environments and operational requirements, may be used without departing from the principles and scope of this disclosure. These modifications and other alterations or alterations will be included within the scope of this document. Those skilled in the art will recognize that many changes can be made to the details of the above embodiments without departing from the fundamental principles of the invention.

Claims

1. A clock frequency synchronization method, characterized in that, Applied to network interconnection devices, multiple such network interconnection devices can be cascaded, with the first-level network interconnection device in the cascaded configuration connected to a clock source; the clock frequency synchronization method includes: When the clock frequency of the first-level network interconnection device changes, a first Esmc message is sent to the second-level network interconnection device, so that the second-level network interconnection device starts frequency synchronization when it receives a PTP message that is K messages apart from the first Esmc message. The first Esmc message is used to indicate the synchronization mode indication information that frequency synchronization extension starts when a PTP message that is K messages apart from the first Esmc message is received. When the clock frequency of a non-first-level network interconnection device changes, if the non-first-level network interconnection device has not synchronized its clock frequency with the next-level network interconnection device, the first Esmc message is sent to the next-level network interconnection device, so that the next-level network interconnection device can start frequency synchronization when it receives a PTP message that is K messages apart from the first Esmc message.

2. The clock frequency synchronization method as described in claim 1, characterized in that, When the clock frequency of a non-first-level network interconnection device changes, if the non-first-level network interconnection device has not synchronized its clock frequency with the next-level network interconnection device, then the first Esmc message is sent to the next-level network interconnection device, so that the next-level network interconnection device starts frequency synchronization when it receives a PTP message that is K messages apart from the first Esmc message, and then includes: Once the clock frequency synchronization of the third-level or subsequent network interconnection devices is completed, an Esmc feedback message is sent to the previous-level network interconnection device. This causes the previous-level network interconnection device to change the flag bit of the port that sends messages to the next-level network interconnection device from the first flag to the second flag. The first flag indicates that the next-level network interconnection device has not performed clock frequency synchronization with the previous-level network interconnection device, and the second flag indicates that the next-level network interconnection device has performed clock frequency synchronization with the previous-level network interconnection device. The Esmc feedback message indicates that frequency synchronization is complete.

3. The clock frequency synchronization method as described in claim 1, characterized in that, The clock frequency synchronization method further includes: When the clock frequency of a non-first-level network interconnection device changes, if the non-first-level network interconnection device has synchronized its clock frequency with the next-level network interconnection device, a second Esmc message is sent to the next-level network interconnection device. The second Esmc message carries the clock frequency synchronization value of the non-first-level network interconnection device at the time of current frequency synchronization, so that the next-level network interconnection device can perform frequency synchronization based on the clock frequency synchronization value of the non-first-level network interconnection device at the time of current frequency synchronization. The second Esmc message is used to characterize the synchronization method indication information for frequency synchronization based on the clock frequency synchronization value carried in the second Esmc message.

4. The clock frequency synchronization method as described in claim 3, characterized in that, When the clock frequency of a non-first-level network interconnection device changes, if the non-first-level network interconnection device has previously synchronized its clock frequency with a next-level network interconnection device, a second Esmc message is sent to the next-level network interconnection device. This second Esmc message carries the clock frequency synchronization value of the non-first-level network interconnection device at its current frequency synchronization, enabling the next-level network interconnection device to perform frequency synchronization based on the clock frequency synchronization value of the non-first-level network interconnection device at its current frequency synchronization. The process then includes: When the non-first-level network interconnection device sends the second Esmc message to the next-level network interconnection device, the port on which it sends the message to the next-level network interconnection device is changed from the second identifier to the first identifier. The first identifier is used to identify that the next-level network interconnection device and the previous-level network interconnection device have not performed clock frequency synchronization, and the second identifier is used to identify that the next-level network interconnection device and the previous-level network interconnection device have performed clock frequency synchronization. Once the clock frequency synchronization of the next-level network interconnection device is completed, an Esmc feedback message is sent to the non-first-level network interconnection device, so that the non-first-level network interconnection device sets the flag bit of the port that sends messages to the next-level network interconnection device from the first flag to the second flag. The Esmc feedback message is used to indicate that the frequency synchronization is complete.

5. The clock frequency synchronization method as described in claim 3 or 4, characterized in that, The next-level network interconnection device performs frequency synchronization based on the clock frequency synchronization value of the non-first-level network interconnection device during current frequency synchronization by using the clock frequency synchronization value carried in the second Esmc message as the clock frequency synchronization value for this frequency synchronization.

6. The clock frequency synchronization method as described in claim 3 or 4, characterized in that, For the first-level network interconnection device, the change in clock frequency is due to a switch in the clock source or a failure of the clock source.

7. The clock frequency synchronization method as described in claim 6, characterized in that, For the non-first-level network interconnection devices, the clock frequency change is performed to synchronize the clock frequency.

8. The clock frequency synchronization method as described in claim 1, characterized in that, The next-level network interconnection device starts frequency synchronization when it receives a PTP message that is K messages apart from the first Esmc message, and the next-level network interconnection device starts frequency synchronization when it receives a PTP message that is adjacent to the first Esmc message.

9. A network interconnection device, characterized in that, include: Memory, used to store programs; A processor for implementing the clock frequency synchronization method as described in any one of claims 1 to 8 by executing the program.

10. A clock frequency synchronization device, characterized in that, include: Multiple interconnected network devices; The plurality of network interconnection devices are cascaded, and the first-level network interconnection device is connected to a clock source. Each of the plurality of network interconnection devices is the network interconnection device as described in claim 9.

Images