A data processing method and a data processing apparatus and system

Abstract

The application discloses a data processing method and a data processing device. The data processing method comprises multiple steps. Firstly, a first data stream at a first rate is received, and the first data stream is obtained by sequentially performing a first encoding processing and a second encoding processing. Then, at least one decoding processing is performed on the first data stream, one of the at least one decoding processing is a decoding processing corresponding to the second encoding processing, so as to obtain a second data stream. Then, the second data stream is sent to a receiving device, and the rate of the second data stream is the first rate. The receiving device performs two decoding processings on the received second data stream, and the two decoding processings correspond to the second encoding processing and the first encoding processing respectively, so as to obtain service data sent by a sending side device. At least three decoding processings are completed by cooperation of two receiving side devices, and the error correction performance of the system is improved.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to a data processing method, apparatus and system thereof. Background Technology

[0002] Driven by 5G, cloud computing, big data, and artificial intelligence, Ethernet networks are evolving towards greater capacity, higher speeds, and lower latency. Using forward error correction (FEC) to correct transmitted data can resolve transmission errors and recover the original data sent by the transmitter from the received data.

[0003] The currently proposed cascaded FEC transmission scheme connects the transmitting device and the transmitting processing module via an attachment unit interface (AUI). The transmitting device performs a first FEC encoding on the data to be transmitted and sends the first FEC-encoded data to the transmitting processing module. The transmitting processing module then performs a second FEC encoding on the first FEC-encoded data and transmits the second FEC-encoded data through optical fiber to the receiving processing module. The receiving processing module performs an FEC decoding on the second FEC-encoded data to reduce errors introduced by the optical fiber link, and transmits the first FEC-decoded data through the AUI to the receiving device. The receiving device performs a final FEC decoding to obtain the data sent by the transmitting device. The current cascaded FEC transmission scheme targets a single parallel transmission physical channel (also referred to as a physical lane) with a rate of 200Gbps, or simply 200G / Lane. Summary of the Invention

[0004] This application provides a data processing method, apparatus, and system that can correct more errors occurring during data transmission, provide more reliable decoded data, and meet the higher requirements for error correction performance in scenarios with speeds of 200G / Lane and above.

[0005] In a first aspect, embodiments of this application provide a data processing method, comprising: receiving a first data stream, wherein the rate of the first data stream is a first rate, and the first data stream is obtained by sequentially performing a first encoding process and a second encoding process; performing at least one decoding process on the first data stream, wherein at least one of the at least one decoding process corresponds to at least one of the second encoding processes, to obtain a second data stream; and sending the second data stream to a receiving device, wherein the rate of the second data stream is the first rate.

[0006] Optionally, at least one decoding process may include one decoding process, that is, only the first decoding process corresponding to the second encoding process is performed; it may also include two decoding processes, or even more; for example, the first data stream is decoded twice, the first decoding corresponds to the second encoding process, and the second decoding corresponds to the first encoding process; another example is to perform three decodings, where the first and third decodings correspond to the second encoding process, and the second decoding corresponds to the first encoding process; yet another example is that if there is a fourth decoding, the fourth decoding also corresponds to the first encoding process, and so on. This application does not limit the number of decodings.

[0007] Combining the first aspect and possible implementations, the rate of the output second data stream obtained after decoding the first data stream is consistent with the rate of the first data stream. That is, the output second data stream still retains the check bits added by the second encoding, allowing the receiving device to perform decoding for the second encoding on the second data stream, and then decode for the first encoding. It should be understood that in existing technical solutions, the data stream received by the receiving device does not contain the check bits added by the second encoding, and can only perform decoding for the first encoding. In this embodiment, by cooperating between the receiving processing module and the receiving device to perform at least three FEC decoding processes, the decoding performance can be improved, better matching the higher decoding performance requirements of the 400G / Lane scenario. It should be understood that this application embodiment is also applicable to other single-lane rates greater than 200G / Lane (e.g., 300G / Lane scenarios). Alternatively, this application embodiment is also applicable to scenarios with higher decoding performance requirements.

[0008] In conjunction with the first aspect, in a first possible implementation of the first aspect, the first encoding process employs RS encoding, for example, RS(544,514), RS(528,514), RS(560,514), or RS(576,514). The second encoding can employ Hamming encoding or BCH encoding.

[0009] In conjunction with the first aspect and its possible implementations, in a second possible implementation of the first aspect, the first decoding process is soft-decision decoding. Further, the soft-decision decoding is Hamming or BCH soft-decision decoding, which offers better performance. Alternatively, the first decoding process is hard-decision decoding, which consumes less power.

[0010] In conjunction with the first aspect and its possible implementations, in a third possible implementation of the first aspect, the first data stream includes a first codeword generated by the second encoding process, and the second data stream includes a second codeword, wherein the second codeword is obtained after the first codeword has undergone the at least one decoding process. Both the first codeword and the second codeword include a parity bit. This allows the receiving device to use this parity sequence to perform decoding on the second encoding process, thereby improving decoding performance.

[0011] In conjunction with the first aspect and its possible implementations, in a fourth possible implementation of the first aspect, the method further includes: the receiving device receiving the second data stream; performing at least one second decoding process and at least one third decoding process on the second data to obtain service data sent by the transmitting device, wherein the second decoding process corresponds to the second encoding process, and the third decoding process corresponds to the first encoding process. The receiving processing module and the receiving device cooperate to perform at least three FEC decoding processes, which can improve decoding performance.

[0012] In conjunction with the first aspect and possible implementations, in the fifth possible implementation of the first aspect, the second encoding process uses Hamming code encoding, and the second decoding process uses Hamming code decoding.

[0013] In conjunction with the first aspect and its possible implementations, in the sixth possible implementation of the first aspect, the second decoding process employs hard-decision decoding.

[0014] In conjunction with the first aspect and its possible implementations, in the seventh possible implementation of the first aspect, the first encoding process employs RS encoding, and the third decoding process employs RS decoding.

[0015] In conjunction with the first aspect and its possible implementations, in the eighth possible implementation of the first aspect, the first decoding process and the second decoding process are executed on different devices. Since the second decoding process and the third decoding process are executed on the same device, the first decoding process and the third decoding process are also executed on different devices.

[0016] Secondly, a data processing method is provided, comprising: receiving a second data stream, wherein the second data stream is a data stream obtained after a first data stream undergoes a first decoding process, the first data stream being obtained by sequentially undergoing a first encoding process and a second encoding process, and the first data stream and the second data stream having the same rate; performing a second decoding process and a third decoding process on the second data stream to obtain service data transmitted by a transmitting device, wherein the second decoding process corresponds to the second encoding process, and the third decoding process corresponds to the first encoding process. The receiving processing module and the receiving device cooperate to perform at least three FEC decoding processes, which can improve decoding performance.

[0017] In one possible implementation, the second encoding process uses Hamming code encoding, and the second decoding process uses Hamming code decoding. Further, the second decoding process can employ hard-decision decoding.

[0018] In one possible implementation, the first encoding process uses RS encoding, and the third decoding process uses RS decoding. For example, the RS encoding uses RS(544,514), RS(528,514), RS(560,514), or RS(576,514) encoding.

[0019] In one possible implementation, the second data stream includes a first check sequence, wherein the first check sequence is obtained after the check sequence generated by the second encoding process has undergone the at least one decoding.

[0020] Thirdly, a data processing apparatus is provided, the apparatus comprising a processing unit and a transceiver unit, wherein the transceiver unit is used to send a data stream sent by the processing unit, or to send a data stream to the processing unit; the processing unit is used to execute the method described in any one of the first aspects and their possible implementations, or to execute the method described in any one of the second aspects and their possible implementations. Furthermore, the processing unit may be divided into two sub-processing units, a first sub-processing unit used to implement the method described in any one of the first aspects and their first to third possible implementations, and a second sub-processing unit used to implement the method described in any one of the second aspects and their possible implementations; in this case, the two sub-processing units can be two different chips, or the first sub-processing unit can be a host-side device or a host-side chip, and the second processing unit can be an optical module or an electrical module, i.e., the two sub-processing units can be considered as two independent hardware components.

[0021] Fourthly, a chip is provided for performing the method as described in the first aspect and any one of the first to third possible implementations of the first aspect; or for performing the method as described in the second aspect and any one of its possible implementations.

[0022] Fifthly, an optical module is provided, the optical module including a processor and an interface, the processor being configured to perform the method as described in the first aspect and any of the first to third possible implementations of the first aspect, and to transmit and receive signals through the interface. For example, the interface is configured to transmit signals from the processor or transmit received signals to the processor.

[0023] In a sixth aspect, a communication device is provided, the communication device comprising a host-side device and an optical module as described in the fifth aspect, the optical module being connected to the host-side device; further, the host-side device is configured to perform the method as described in the second aspect and any of its possible implementations.

[0024] In a seventh aspect, a communication system is provided, comprising: a first communication device and a second communication device, wherein at least one of the first communication device and the second communication device is a communication device as described in the sixth aspect, and the first communication device and the second communication device are connected.

[0025] Eighthly, this application provides a computer-readable storage medium storing instructions that, when executed by a computer, cause the method described in the first aspect or any embodiment of the first aspect, or the second aspect or any embodiment of the second aspect, to be implemented.

[0026] Ninthly, this application provides a computer program product including program instructions that, when executed, implement the methods described in the first aspect or any embodiment of the first aspect, or the second aspect or any embodiment of the second aspect.

[0027] The beneficial effects of the above aspects can be referred to the beneficial effects of the first aspect, and will not be repeated here. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of a communication system used in an embodiment of this application;

[0029] Figure 2 A flowchart illustrating a data processing method provided in an embodiment of this application;

[0030] Figure 3 This is a schematic diagram of the decoding process of the receiving processing module provided in an embodiment of this application;

[0031] Figure 4 A flowchart illustrating another data processing method provided in an embodiment of this application;

[0032] Figure 5A flowchart illustrating another data processing method provided in an embodiment of this application;

[0033] Figure 6 This is a schematic diagram of the structure of a data processing device provided in an embodiment of this application;

[0034] Figure 7 This is a schematic diagram of the structure of an optical module provided in an embodiment of this application;

[0035] Figure 8 This is a schematic diagram of the structure of a communication device provided in an embodiment of this application. Detailed Implementation

[0036] First, some of the terms used in this application will be explained to facilitate understanding by those skilled in the art.

[0037] 1) Multiple refers to two or more. "And / or" describes the relationship between related objects, which can exist in three ways. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. In addition, in the description of this application, words such as "first" and "second" are used only for the purpose of distinguishing descriptions and should not be construed as indicating or implying relative importance or order.

[0038] 2) Service data refers to the service data carried by the data communication equipment. For example, it can be Ethernet service, packet service (PKT service), fixed rate service (CBR service), and / or wireless backhaul service, etc.

[0039] 3) Forward Error Correction (FEC) is a data encoding technique that increases the reliability of data communication. Specifically, it identifies a specified data stream through flow classification and adds redundant packets carrying verification information. If packet loss or corruption occurs in the network, the redundant packets are used to restore the packet. Unless otherwise specified, the encoding mentioned in this application refers to FEC encoding, and the decoding mentioned in this application refers to FEC decoding. It should be understood that the encoding and decoding described in this disclosure correspond to each other, meaning that both encoding and decoding use the same encoding code type, such as RS(544,514) or Hamming code. The correspondence between encoding and decoding can also be described as: decoding process A is for encoding process B.

[0040] 4) Unless otherwise specified, the specific description of certain technical features in one embodiment can also be used to explain the corresponding technical features mentioned in other embodiments. For example, an example of a data communication device in one embodiment can also be applied to data communication devices mentioned in other embodiments. Similarly, specific examples and descriptions of a certain type of encoding can be applied to the corresponding encoding descriptions mentioned in different specific embodiments. Furthermore, to more clearly illustrate the relationship between components in different embodiments, this application uses the same or similar drawing numbers to represent components or method steps with the same or similar functions in different embodiments.

[0041] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.

[0042] Figure 1 This is a schematic diagram of a communication system used in an embodiment of this disclosure. Figure 1 As shown, the communication system includes a transmitting device 01, a connection interface 02, a transmitting processing module 03, a channel transmission medium 04, a receiving processing module 05, a connection interface 06, and a receiving device 07.

[0043] Taking a data center network as an example, the transmitting device 01 and receiving device 07 can be data communication devices, such as switches or routers. Transmitting device 01 is also called a client-side device located on the transmitting side, and receiving device 07 is also called a client-side device located on the receiving end. The channel transmission medium 04 can be optical fiber or cable. Client-side devices are sometimes also called host devices, client chips, or host chips. The connection interface 02 between transmitting device 01 and transmitting processing module 03 can be connected via an AUI, and the connection interface 06 between receiving device 07 and receiving processing module 05 can also be connected via an AUI. Transmitting processing module 03 and receiving processing module 05 can be optical modules, electrical modules, connectors, or other modules that process data during transmission. It should be noted that the function of transmitting processing module 03 includes framing the received data using a digital signal processor (DSP).

[0044] For example, such processing modules can be long-range (LR) optical modules, such as 1.6T LR modules (a type of coherent optical module) or 3.2T LR optical modules. Alternatively, these processing modules can also be extended-range (ER) optical modules, or zebest-range (ZR) or ZR+longer-range optical modules. It should be noted that this communication system can support both bidirectional and unidirectional data transmission; this application does not specifically limit its capabilities in this regard.

[0045] It should be noted that, in some embodiments of this disclosure, the physical transmission channel rate for parallel transmission supported by connection interface 02 and / or connection interface 06 is 400Gbps. In other embodiments of this disclosure, the physical transmission channel rate for parallel transmission supported by connection interface 02 and / or connection interface 06 is 300Gbps.

[0046] It should also be noted that the technical solutions disclosed herein are applicable to other communication systems. As an example, the transmitting device and the transmitting processing module can be a single device, containing... Figure 1 The functions of the transmitting device 01, connection interface 02, and transmitting processing module 03 shown are the same as those of other components. Figure 1 Same. In another example, the lane rate of connection interface 02 is 200G, and the other components are the same. Figure 1 The description is the same.

[0047] Currently, the cascaded FEC transmission scheme is only applicable to 200G / lane data communication systems, and there is no FEC scheme for 400G / lane.

[0048] To address this problem, this disclosure provides a data processing method. This method is applied to a receiving processing module, which decodes the received data stream and then sends the decoded data stream to a receiving device. The data stream has the same rate before and after decoding. The receiving device then performs two more decoding processes on the decoded data obtained from the receiving processing module to obtain the service data sent by the transmitting device. The receiving processing module and the receiving device cooperate to complete at least three decoding operations, enabling the correction of more errors occurring during data transmission, providing more reliable decoded data, and meeting the higher error correction performance requirements of 400G / Lane scenarios.

[0049] It should be noted that the rate mentioned in this application refers to the nominal rate, which is acceptable within a certain range of error in practical applications. For example, the allowable variation is ±V parts per million (ppm), where V is an integer. Typically, V can be 10, 20, 40, 50, or 100, etc. The statement that "the data stream has the same rate before and after decoding" means that the nominal rate before and after decoding is the same; however, in practical applications, a certain range of error between the rates before and after decoding is permissible.

[0050] It should be noted that the channel transmission rate in this application refers to the nominal rate of service data transmission on the channel, while the actual data transmission rate is generally higher than this. For example, 200G / Lane means that the nominal rate of service data transmission on the channel is 200Gbps. Redundancy information is added by performing FEC encoding and other processing on the service data in the transmitting device and the transmitting end processing module, making the data transmission rate of the AUI interface channel greater than 200Gbps. For example, in one possible implementation of Ethernet services, after the first and second FEC encoding, the data transmission rate of the AUI interface channel is 226.875Gbps.

[0051] It should be understood that the receiving and processing module is also called a receiving and processing device or receiving and processing equipment.

[0052] Figure 2 This is a flowchart illustrating a data processing method provided in an embodiment of this application. Figure 2 The data processing method shown includes multiple steps, and multiple devices work together to complete the data processing. These steps are described in further detail below.

[0053] The steps performed by the transmitting device 20 include the following two steps.

[0054] Step 201: Perform first encoding and second encoding on the first data stream in sequence to obtain the second data stream.

[0055] Step 202: Send the second data stream.

[0056] In this embodiment, the above two steps are performed by a single device, namely, transmitting device 20. It should be understood that this is merely an example of a specific implementation. When implementing the solution described in this disclosure, references may also be made to, for example... Figure 4 The example shown illustrates how to achieve this.

[0057] Specifically, the transmitting device 20 encodes the acquired service data (hereinafter referred to as the first data stream) twice to obtain the encoded data stream (hereinafter referred to as the second data stream). The two encodings are the first encoding and the second encoding described in step 201. Generally, the first encoding can also be called the external encoding, and the second encoding can also be called the internal encoding.

[0058] This disclosure does not limit the specific encoding methods for "internal code encoding" and "external code encoding". For example, the transmitting device 20 may use Reed-Solomon (RS) code for external code encoding and Hamming code for internal code encoding. As another example, the transmitting device 20 may use RS code for external code encoding and BCH code for internal code encoding. BCH code for correcting a single error is equivalent to Hamming code. Yet another example, the transmitting device 20 may use RS code for external code encoding and Polar code for internal code encoding. Specifically, the RS code may be KP4 RS(544,514), KR4 RS(528,514), RS(560,514), RS(576,514), or other specific encoding formats.

[0059] The receiving and processing module 30 performs the following three steps.

[0060] Step 301: Receive the second data stream, the rate of the second data stream being the first rate.

[0061] Step 302: Perform a first decoding process on the second data stream to obtain a third data stream.

[0062] Step 303: Send the third data stream, the rate of the third data stream being the first rate.

[0063] Specifically, the receiving and processing module 30 receives the second data stream via optical fiber and performs decoding processing on the received second data stream for the second encoding to obtain the third data stream. The second and third data streams have the same rate. In some specific implementations, the rate of the second data stream is the data rate of the first data stream after the first and second encodings (i.e., the first rate). For example, considering a possible implementation of future 1.6T service transmission, if the first encoding is KP4 codewords and the second encoding is FEC(128,120), then the rate of the second data stream is 1.815Tbps, comprising four physical channels, each with a rate of 453.75Gbps. The rate of the second data stream is the data rate of the first data stream after the first and second encodings (i.e., the first rate). For example, considering a possible implementation of future 3.2T service transmission, if the first encoding is KP4 codewords and the second encoding is FEC(128,120), then the rate of the second data stream is 3.63Tbps, which includes 8 physical channels, each with a rate of 453.75Gbps.

[0064] It should be noted that the third data stream includes second-encoded information data (also called information bits) and check data (also called check bits). In some specific implementations, bit error correction may be performed on the check data during the first decoding of the codewords in the second data stream.

[0065] It should be noted that the decoding process for the second encoding refers to decoding based on the codeword constraints of the encoding process. For example, if the encoding process uses BCH encoding, then the decoding process uses BCH decoding. If the encoding process uses Hamming encoding, then the decoding process uses Hamming decoding.

[0066] Figure 3 This is a schematic diagram of the decoding process of the receiving processing module provided in an embodiment of this application. Figure 3 As shown, the second data stream obtained by the receiving and processing module includes multiple encoded blocks obtained after the second encoding, such as... Figure 3 The diagram shows coded blocks 1, ..., coded blocks N. Taking coded block 1 as an example with a length of N bits, these N bits contain K information bits and (NK) parity bits. After decoding multiple coded blocks of the second data stream, the receiving processing module outputs the third data stream. For example... Figure 3 As shown, the third data stream output by the receiving and processing module includes multiple encoded blocks, such as... Figure 3The code blocks shown are coded blocks 1', ..., coded blocks N'. Taking coded block 1' as an example with a length of N bits, these N bits contain K information bits and (NK) parity bits. Therefore, the receiving processing module 30 does not change the number of bits contained in the coded blocks within the data stream during the decoding process. The advantage of this is that the output data stream of the receiving processing module 30 retains the parity bits added by the second encoding, allowing the receiving device 40 to perform further decoding of the second encoding (described in detail in subsequent step 402) to cooperate with the receiving processing module in completing multiple decodings. This corrects errors introduced during transmission between the receiving processing module 30 and the receiving device 40, as well as bit errors introduced during other transmission processes of the service data (e.g., bit errors introduced in fiber optic transmission).

[0067] In one specific implementation, the first decoding process of the receiving processing module 30 can employ soft decision decoding. Soft decision decoding can also be called soft decoding. The decoding algorithm in soft decision decoding can include, but is not limited to, the Chase algorithm or ordered statistic decoding (OSD) algorithm, where Chase is a person's name. For example, if BCH(126,110) is used for the second encoding, the first decoding uses BCH soft decoding based on the Chase algorithm. Another example is FEC(128,120) used for the second encoding, and the first decoding uses FEC(128,120) soft decoding based on the Chase algorithm.

[0068] Continue to combine Figure 3 To explain, when the receiving and processing module 30 performs soft-decision decoding on the encoded block (e.g., encoded block 1) of the second data stream, it determines which bits are erroneous and flips the corresponding bits to correct errors, thus determining the decoded information bits and check bits. After the soft-decision decoding, the decoded encoded block (e.g., encoded block 1') is obtained.

[0069] For example, the first decoding process is a BCH(126, 110) soft-decision decoding process. The second encoding uses BCH(126, 110), indicating that the codeword size of the coded block is 126 bits, of which 110 bits are information bits and 16 bits are parity bits. After performing the first decoding process on each BCH(126, 110), the receiving processing module 40 outputs the 126 bits corresponding to the error correction (i.e., still containing information bits and parity bits).

[0070] For example, the first decoding process is FEC(128, 120) soft-decision decoding. The second encoding uses FEC(128, 120), which means that the FEC codeword length is 128 bits, of which 120 bits are information bits and 8 bits are parity bits. After FEC decoding of each FEC(128, 120), the corrected 126 bits are output (that is, it still contains information bits and parity bits).

[0071] In some specific applications, the above-mentioned coded block is obtained by interleaving multiple codewords. For example, the second encoding uses FEC(128, 120), and the coded block consists of 8 second FEC codewords, containing a total of 1024 bits, of which 960 bits are information bits and 64 bits are parity bits. After the receiving processing module 40 performs the first decoding process on the coded block, it outputs the 1024 bits corresponding to the correction (i.e., still containing information bits and parity bits).

[0072] In other specific applications, the above-mentioned coded block is obtained by interleaving multiple codewords. For example, the second encoding uses FEC(128, 120), and the coded block consists of 16 second FEC codewords, containing a total of 2048 bits, of which 1920 bits are information bits and 128 bits are parity bits. After the receiving processing module 40 performs the first decoding process on the coded block, it outputs the 2048 bits corresponding to the correction (i.e., still containing information bits and parity bits).

[0073] It should be noted that, due to the random distribution of errors, the number of erroneous bits in a coded block (also called a codeword) is uncertain. It is possible that at a certain moment, multiple coded blocks of the received second data stream may be error-free. If, during the first FEC decoding process performed by the receiving processing module 40, it is determined that there are no errors, error correction is not required for the processed bits, and the coded blocks of the output third data stream will be the multiple coded blocks of the received second data stream. Alternatively, it is possible that at a certain moment, the coded blocks of the received second data stream contain many errors, which may cause the receiving processing module 30 to perform miscorrection during the first decoding process, flipping the error-free bits. In this case, the coded blocks of the output third data stream will be the miscorrected coded blocks of the second data stream. Or, the receiving processing module 30 may fail to decode during the first decoding process; in this case, no error correction is performed, and the coded blocks of the output third data stream will still be the coded blocks of the received second data stream. Or, under normal circumstances, the receiving processing module 30 performs the first decoding process on the coded blocks of the second data stream correctly, correcting all erroneous bits, and the third data stream output by the receiving processing module 30 will be the multiple coded blocks after error correction. It should be understood that after the first decoding process, there may still be erroneous bits that have not been corrected. Therefore, the encoded blocks in the third data stream may still contain errors and be inconsistent with the bit information contained in the second data stream sent by the sender.

[0074] It should be noted that soft-decision decoding can be performed using the soft-decision information corresponding to the bits contained in the second data stream. That is, the receiving and processing module 30 can obtain the soft-decision information corresponding to the second data stream. Soft-decision information can also be called soft value. This soft-decision information is the soft-decision information corresponding to each bit of the received multiple codewords. Taking coded block 1 as an example, each bit it contains has soft-decision information including amplitude and sign, where the amplitude represents the reliability of the bit, and the sign indicates whether the bit is 0 or 1. In some specific applications, this soft-decision information is represented using log-likelihood ratio (LLR) information; in other specific applications, it is represented using probability information.

[0075] In another specific implementation, the first decoding process of the receiving processing module 30 can employ hard-decision decoding. For example, the first decoding process can be a hard-decision decoding process for the second code. The hard-decision decoding process outputs the corrected coded block (containing the information bits and parity bits of the second code). Specifically, if the second code uses Hamming or BCH, then the first decoding process uses Hamming or BCH for decoding.

[0076] The receiving device 40 performs the following two steps.

[0077] Step 401: Receive the third data stream;

[0078] Step 402: Perform a second decoding process and a third decoding process on the third data to obtain the first data stream.

[0079] Specifically, receiving device 40 receives the third data stream through the AUI interface and performs second and third decoding processes on the data stream to parse out the first data stream. The second and third decoding processes correspond to the second and first encoding processes performed by sending device 20, respectively. That is, if the sending side performs external encoding (first encoding) first and then performs second encoding (internal encoding), then the receiving side (i.e., receiving device 40) performs internal decoding first (e.g., second decoding process) and then performs external decoding (third decoding process). In some specific implementations, the rate of the third data stream is the data rate of the first data stream after first and second encoding (i.e., the first rate). For example, in a possible implementation considering future 1.6T service transmission, if the first encoding is KP4 codeword and the second encoding is FEC(128,120), then the rate of the third data stream is 1.815Tbps, which includes 4 physical channels, each physical channel being 453.75Gbps. The rate of the third data stream is the data rate of the first data stream after the first and second encodings (i.e., the first rate). For example, considering a possible implementation of future 3.2T service transmission, if the first encoding is KP4 codewords and the second encoding is FEC(128,120), then the rate of the third data stream is 3.63Tbps, which includes 8 physical channels, each with a rate of 453.75Gbps.

[0080] It should be noted that the second data stream received by the receiving processing module 30 and the third data stream received by the receiving device 40 contain the same number of physical channels and have the same data rate. For example, both data streams are 1.815Tbps and include 4 physical channels. The difference is that the second data stream may be obtained through an optical port, while the third data stream is obtained through an electrical port, such as an AUI interface.

[0081] For example, if the second encoding uses Hamming code, then the second decoding process uses Hamming code decoding to decode the third data stream to obtain the information bits of the second encoding contained in the third data stream. Then, if the first encoding uses RS(544,514) encoding, then the third decoding process uses RS(544,514) decoding to decode the information bits of the second encoding contained in the third data stream to obtain the first data stream. It should be noted that if the first encoding uses RS(528,514) encoding, then the third decoding process uses RS(528,514) decoding. If the first encoding uses RS(560,514) encoding, then the third decoding process uses RS(560,514) decoding. If the first encoding uses RS(576,514) encoding, then the third decoding process uses RS(576,514) decoding.

[0082] It should be understood that the first data stream undergoes FEC decoding processing by two devices at the fiber optic transmission and receiving ends. Therefore, the specific bit values ​​it contains may not be exactly the same as the bit values ​​generated by the transmitting device, i.e., bit errors occur. The two devices at the receiving end correct the bit errors that occurred in the first data stream during transmission. Alternatively, in some possible scenarios, because the first data stream contains too many erroneous bits, the receiving device 40 can only correct a portion of the transmission bit errors. In this case, some bit values ​​in the obtained first data stream will differ from the bit values ​​in the first data stream generated by the transmitting device.

[0083] In this embodiment, by cooperating with the receiving processing module and the receiving device to perform three FEC decoding processes, the decoding performance can be improved, better matching the higher decoding performance requirements of the 400G / Lane scenario. It should be understood that this embodiment is also applicable to other single-lane rates greater than 200G / Lane (e.g., 300G / Lane). Alternatively, this embodiment is also applicable to scenarios with higher decoding performance requirements. The receiving processing module maintains the input and output data stream rates unchanged, i.e., retains the parity bits in the data stream, allowing the receiving device to use this parity information for subsequent decoding processing, thereby improving decoding performance.

[0084] Figure 4 This is a flowchart illustrating another data processing method provided in an embodiment of this application. Figure 4 The data processing method shown includes multiple steps, and multiple devices work together to complete the data processing. These steps are described in further detail below.

[0085] The transmitting device 21 performs the following two steps.

[0086] Step 211: Perform first encoding and second encoding on the first data stream in sequence to obtain the second data stream.

[0087] Step 212: Send the second data stream.

[0088] The two steps performed by the transmitting device 21 are the same Figure 2 The steps performed by the transmitting device 20 are basically the same; see detailed description below. Figure 2 The relevant descriptions will not be repeated here. (And...) Figure 2 The difference is that the transmitting device 21 sends the generated second data stream to the transmitting processing module 22 instead of sending it directly to the receiving processing module.

[0089] The sending processing module 22 performs the following step.

[0090] Step 221: Forward the second data stream.

[0091] Specifically, after receiving the second data stream, the transmission processing module 22 performs some processing on the second data stream before transmitting it to the peer device via optical fiber. For example, in a coherent scenario, the second data stream is processed to obtain a DSP frame. This transmission processing includes adding at least one of the following sequences: frame alignment word sequence (FAW Sequence), training symbol sequence, reserved symbol sequence, and / or pilot symbol sequence. In a direct detection scenario, the transmission processing includes symbol mapping. Symbol mapping includes, for example, PAM4 mapping, PAM6 mapping, or PAM8 mapping.

[0092] It should be understood that the above-mentioned processing for the second data stream also applies. Figure 2 The transmitting device 20 in the middle.

[0093] The receiving and processing module 31 performs the following three steps.

[0094] Step 311: Receive the second data stream, the rate of the second data stream being the first rate.

[0095] Step 312: Perform a first decoding process and a second decoding process on the second data stream to obtain a third data stream.

[0096] Step 313: Send the third data stream, the rate of the third data stream being the first rate.

[0097] Except for the second decoding step, the other three steps performed by the receiving processing module 31 are the same. Figure 2 The steps performed by the receiving and processing module 30 are basically the same; see detailed description below. Figure 2 The relevant descriptions will not be repeated here. (And...) Figure 2 The difference is that the receiving processing module 31 performs decoding twice. Specifically, the receiving processing module 31 can perform a first decoding process for the second encoding on the received data stream, and then continue to perform a second decoding process for the first encoding. The advantage of doing this is that it can improve the decoding performance on the receiving side.

[0098] Optionally, the first decoding process can be either Hamming hard decision or soft decision. Optionally, when the first encoding uses RS(544,514) code, the second decoding process is based on RS(544,514) decoding. In other specific applications, when the first encoding uses RS(528,514) code, the second decoding process is based on RS(528,514) decoding. Alternatively, when the first encoding uses RS(560,514) code, the second decoding process is based on RS(560,514) decoding. Alternatively, when the first encoding uses RS(576,514) code, the second decoding process is based on RS(576,514) decoding.

[0099] The receiving device 41 performs the following two steps.

[0100] Step 411: Receive the third data stream;

[0101] Step 412: Perform third decoding and fourth decoding on the third data to obtain the first data stream.

[0102] Steps 411 and 412 performed by receiving device 41 are the same Figure 2 The steps 401-402 performed by the receiving and processing module 40 are basically the same; see detailed description below. Figure 2 The relevant descriptions will not be repeated here.

[0103] In one alternative approach, to enhance the burst resistance of the data transmission scheme, Figure 2 The transmitting device 20 shown or Figure 4 The transmitting processing module 22 shown performs interleaving before transmitting the second data stream to the peer device via the channel transmission medium. Correspondingly, the receiving device, such as the receiving processing module, first performs deinterleaving and then decoding.

[0104] In one alternative embodiment, the data processing method is applied in a coherent scenario. The receiving process includes one or more operations such as clock recovery, carrier phase recovery, equalization, symbol demodulation, DSP frame synchronization, and pilot sequence deletion. Deinterleaving is performed using one or more of BCH deinterleaving and inverse circular shift. Symbol demodulation includes double polarization 16-bit quadrature amplitude modulation (DP-16QAM) demodulation.

[0105] In one alternative approach, the data processing method in this embodiment is applied to a direct detection scenario. The receiving processing includes one or more of the following: clock recovery, BCJR equalization, symbol demodulation, internal code synchronization, and PMA4 deinterleaving. Symbol demodulation is PAM4 demodulation, and deinterleaving is PAM4 deinterleaving. The BCJR equalization algorithm is an algorithm defined on a trellis graph to maximize the posterior probability of error-correcting codes. This algorithm is named after its inventors: Bahl, Cocke, Jelinek, and Raviv.

[0106] In this embodiment, by cooperating with the receiving processing module and the receiving device to perform four FEC decoding processes, the decoding performance can be improved, better matching the higher decoding performance requirements of the 400G / Lane scenario. For example, the two devices on the transmitting side are connected via a 400G / Lane AUI, and the two devices on the receiving side are also connected via a 400G / Lane AUI. Alternatively, the two devices on the transmitting side can be connected via a 200G / Lane AUI, and the two devices on the receiving side can be connected via a 400G / Lane AUI. It should be understood that the embodiments of this application are also applicable to other scenarios with single-lane rates greater than 200G / Lane or higher requirements for decoding performance.

[0107] The receiving processing module maintains the input and output data stream rates unchanged, i.e., it retains the parity bits in the data stream. This allows the receiving device to use this parity information for subsequent decoding, thereby improving decoding performance. Furthermore, when the receiving processing module performs relatively high-power soft-decision decoding, while the receiving device performs relatively low-power hard-decision decoding, the decoding power consumption of the receiving device can be reduced, resulting in better heat dissipation.

[0108] Figure 5 This is a flowchart illustrating another data processing method provided in an embodiment of this application. Figure 5 The data processing method shown includes multiple steps, and multiple devices work together to complete the data processing. These steps are described in further detail below.

[0109] The transmitting device 50 performs the following two steps.

[0110] Step 501: Perform first encoding and second encoding on the first data stream in sequence to obtain the second data stream.

[0111] Step 502: Send the second data stream.

[0112] The two steps performed by the transmitting device 50 are the same Figure 4 The steps performed by the transmitting device 21 are basically the same; see detailed description below. Figure 4 The relevant descriptions will not be repeated here.

[0113] The sending processing module 60 performs the following step.

[0114] Step 601: Forward the second data stream.

[0115] The steps performed by the sending processing module 60 are the same as those in the previous step. Figure 4 The steps performed by the transmitting device 22 are basically the same; see detailed description below. Figure 4 The relevant descriptions will not be repeated here.

[0116] The receiving and processing module 70 performs the following three steps.

[0117] Step 701: Receive the second data stream, the rate of the second data stream being the first rate.

[0118] Step 702: Perform three decoding processes on the second data stream to obtain the third data stream.

[0119] Step 703: Send the third data stream, the rate of the third data stream being the first rate.

[0120] Apart from the three decoding steps, the other parts of the three steps executed by the receiving processing module 70 are the same. Figure 2 or Figure 4 The steps performed by the receiving and processing modules 30 or 31 are basically the same; see detailed description below. Figure 2 or Figure 4 The relevant descriptions will not be repeated here. (And...) Figure 2 or Figure 4 The difference is that the receiving and processing module 70 performs three decoding processes.

[0121] Specifically, the receiving processing module 70 can perform decoding processing for the second encoding on the received data stream, then continue to perform decoding processing for the first encoding, and finally perform decoding processing for the second encoding to output the third data stream. The advantage of doing this is that it can improve the decoding performance on the receiving side.

[0122] For example, the receiving processing module 70 can sequentially perform Hamming soft decoding, RS hard decision decoding, and Hamming soft decoding on the received data stream. As another example, the receiving processing module 70 can sequentially perform BCH soft decoding, RS hard decision decoding, and BCH soft decoding on the received data stream. The aforementioned RS hard decision decoding can be RS(544,514) hard decision decoding, RS(528,514) hard decision decoding, RS(560,514) hard decision decoding, or RS(575,514) hard decision decoding.

[0123] The receiving device 80 performs the following three steps.

[0124] Step 801: Receive the third data stream;

[0125] Step 802: Perform third decoding and fourth decoding on the third data to obtain the first data stream.

[0126] 80 receiving devices Figure 4 The steps performed by the receiving and processing module 41 are the same, and a detailed description can be found in [link to documentation]. Figure 4 The relevant descriptions will not be repeated here.

[0127] In this embodiment, by cooperating with the receiving processing module and the receiving device to perform five FEC decoding processes, the decoding performance can be improved, better matching the higher decoding performance requirements of the 400G / Lane scenario, or solving application scenarios with higher decoding performance requirements.

[0128] Apart from Figure 2 , Figure 4 or Figure 5 In addition to the provided embodiments, in some other embodiments, the receiving and processing module performs the following three steps.

[0129] Step 1: Receive the second data stream, which contains a plurality of first codewords, each of which contains an information bit and a check bit.

[0130] Step 2: Perform a first decoding process on the second data stream to obtain a third data stream.

[0131] Step 3: Send the third data stream, which contains a plurality of second codewords. The number of information bits in each of the plurality of second codewords is the same as the number of information bits in the first codeword, and the number of parity bits in each of the plurality of second codewords is the same as the number of parity bits in the first codeword.

[0132] Apart from the description of the data stream, the other parts of the three steps executed by the receiving and processing module are the same. Figure 2 The steps performed by the receiving and processing module 30 are basically the same; see detailed description below. Figure 2 The relevant descriptions will not be repeated here. (And...) Figure 2 The difference is that this embodiment describes the relationship between the number of information bits and the number of check bits in the codewords contained in different data streams, while... Figure 2 The example describes the rate relationship between different data streams.

[0133] The method steps in this embodiment can also be replaced with... Figure 4 or Figure 5 The provided processing steps, for example, step 2, can be replaced with... Figure 4Perform two decoding operations or, as in Figure 5 The code is decoded three times. Figure 4 or Figure 5 The difference is that this embodiment describes the relationship between the number of information bits and the number of check bits in the codewords contained in different data streams, while... Figure 4 or Figure 5 This describes the rate relationship between different data streams. The relevant beneficial effects have been described in the preceding embodiments; the execution steps and descriptions of the corresponding receiving device can be found in [reference needed]. Figure 2 , Figure 4 or Figure 5 The relevant descriptions will not be repeated here in this embodiment.

[0134] Figure 6 This is a schematic diagram of the structure of a data processing device provided in an embodiment of this application. Figure 6 As shown, the data processing apparatus 100 includes a processing unit 101 and a transceiver unit 102. The data processing apparatus 100 can be applied to a transmitting-side device. For example, the data processing apparatus 100 is a transmitting device 20, a transmitting device 21, or a transmitting device 50. The data processing apparatus 100 can also be applied to a receiving-side device. For example, the data processing apparatus 100 can be applied to a receiving device. For example, the data processing apparatus 100 is a receiving processing module 30, a receiving device 40, a receiving processing module 31, a receiving device 41, a receiving processing module 70, or a receiving device 80.

[0135] When applied to the transmitting-side device, the processing unit 101 is used to implement... Figure 2 , Figure 4 or Figure 5 The method executed by the transmitting device shown in the figure. In implementation, each step of the processing flow can be completed by the integrated logic circuit of the hardware in the processor 101 or by instructions in the form of software. The transceiver unit 102 is used to transmit the second data stream to the receiving device or to the transmitting processing module. The processing unit 101 can be divided into two sub-processing units, which perform the first encoding and the second encoding respectively. The first encoding and the second encoding can be executed by different hardware, for example, by two different chips, or the first encoding can be implemented on the host-side device or the host-side chip, and the second encoding can be implemented on the optical module or the electrical module; in this case, the two sub-units can be considered as two independent hardware.

[0136] When applied to a receiving device, the processing unit 101 is used to implement... Figure 2The receiving processing module 30, receiving device 40, receiving processing module 31, receiving device 41, receiving processing module 70, or receiving device 80 shown in the figure execute the methods. In implementation, each step of the processing flow can be accomplished by the integrated logic circuitry in the hardware of the processing unit 101 or by software instructions to perform the methods executed by the receiving device as described in the aforementioned figures. The transceiver unit 102 is used to receive the data stream sent by the transmitting device and send it to the processing unit 101 for subsequent processing; and / or, send the processed data stream received from the processing unit 101 to the receiving device. At this time, the processing unit 101 can also be divided into two sub-processing units, the first sub-processing unit being used to implement, as shown in the figure... Figure 2 and the receiving and processing module 30 shown in the above embodiments, or Figure 4 and the receiving and processing module 31 shown in the above embodiments, Figure 5 and the method executed by the receiving and processing module 70 shown in the above embodiments; the second sub-processing unit is used to implement as follows Figure 2 and the receiving device 40 shown in the above embodiments, or Figure 4 and the receiving device 41 shown in the above embodiments, Figure 5 The method executed by the receiving device 80 shown in the above embodiments; at this time, the two sub-processing units can be two different chips, or the first sub-processing unit is a host-side device or a host-side chip, and the second sub-processing unit is an optical module or an electrical module, that is, the two sub-processing units can be considered as two independent hardware.

[0137] Optionally, the data processing apparatus 100 further includes a storage unit 103. The storage unit 103 stores instructions so that the processing unit 101 can perform the steps mentioned in the figures above. Alternatively, the storage unit can also store other instructions to configure parameters of the processing unit 101 to achieve corresponding functions. The storage unit can also store data streams so that the processing unit can process the data streams.

[0138] It should be noted that, Figure 6 The device described above can also be used to perform the method steps mentioned in the aforementioned embodiments, variations or alternatives shown in the accompanying drawings, which will not be repeated here.

[0139] It should be understood that the data processing apparatus provided in this application can also be implemented in other ways. For example, the unit division in the above apparatus is only a logical functional division, and there may be other division methods in actual implementation. For example, multiple units or components may be combined or integrated into another system. In addition, the functional units in the various embodiments of this application may be integrated into one processing unit, or they may be independent physical units, or two or more functional units may be integrated into one processing unit. The integrated units described above can be implemented in hardware or as software functional units.

[0140] Figure 7 This is a schematic diagram of one structure of the optical module in an embodiment of this application. Figure 7 As shown, the optical module includes a processor 711 and an interface 712. The optical module can be applied to the transmitting end. For example, the optical module implements the functions of transmitting device 20, transmitting device 21, or transmitting device 50, or in other words, the optical module implements the function of the second encoding in transmitting device 20, transmitting device 21, or transmitting device 50. The function of the first encoding is implemented by the host-side device or chip, and the two together constitute the transmitting device. In addition, the optical module can also be applied to the receiving end. For example, the optical module implements the functions of receiving processing module 30, receiving processing module 31, or receiving processing module 70 in the above embodiments, and then sends the obtained third data stream to the receiving device through interface 202 for subsequent decoding. Optionally, the optical module may also include a memory 713, wherein the memory 713 is used to store program instructions and / or data.

[0141] Typically, an optical module consists of optoelectronic devices, a processor, and an interface. The optoelectronic devices include transmitting and receiving devices. The transmitting end of the optical module converts electrical signals into optical signals and transmits them through optical fibers. The receiving end of the optical module receives the optical signals and converts them back into electrical signals.

[0142] The types of optical modules in this application include, but are not limited to, ordinary optical modules, near-package optics (NPO) modules, and co-packaged optics (CPO) modules. Ordinary optical modules can perform functions including, but not limited to, digital signal processing and clock data recovery (CDR). For example, an ordinary optical module converts analog signals to digital signals, performs digital signal processing on the digital signals, and then converts them back to analog signals before sending them to the host device. Because digital signal processing requires retiming, ordinary optical modules can also be called retimed modules. Ordinary optical modules connect to the host device via an AUI. NPO and CPO modules do not have pluggable physical packaging and are closer to the host device. NPO and CPO modules can also be called optical engines. NPO or CPO technology is a technology that "packages" the host device (or host chip) and the optical engine. When NPO technology is used to package the host device and the optical engine, the optical engine can be called an NPO module. When CPO technology is used to encapsulate the host-side device and the optical engine, the optical engine can be called a CPO module.

[0143] Figure 8 This is a schematic diagram of the structure of a communication device according to an embodiment of this application. Figure 8 As shown, the communication device includes a host-side device 811 and an optical module 812. The host-side device 811 sends data to the optical module 812, and the optical module 812 generates an optical signal based on the data sent by the host-side device 811 and transmits the optical signal through the channel. For example, the host-side device may specifically be a router, switch, server, or optical transport network (OTN) equipment. This communication device can be a communication device including a host-side device 301 and an optical module 302.

[0144] OTN equipment includes line-side equipment and client-side equipment. In some scenarios, client-side equipment may also be referred to as tributary-side equipment. Both client-side and line-side equipment can include a processor and an interface. The processor is used to execute the data processing methods described in the above embodiments. The interface can be a transceiver or an input / output interface, used to receive signals from other devices outside the line-side equipment and transmit them to the processor, or to send signals from the processor to other devices outside the line-side equipment.

[0145] This application also provides a chip. This chip integrates circuitry for implementing the functions of the aforementioned processor, and may also include one or more interfaces. As an example, the chip integrates a memory. As another example, when the chip does not integrate a memory, it can be connected to an external memory via an interface. This chip can perform the method steps of any one or more of the foregoing embodiments. Alternatively, the chip can implement the actions performed by the data processing device in the foregoing embodiments based on program code stored in the memory.

[0146] As an example, the chip in the embodiments of this application can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. A general-purpose processor can be a microprocessor, any conventional processor, or a processing circuit that implements a specific function.

[0147] This application also provides a computer-readable storage medium, including a program or instructions that, when run on a computer, cause the data processing method as described in the above embodiments to be implemented.

[0148] It should be understood that the processor mentioned in the embodiments of this application can be implemented in hardware or software. When implemented in hardware, the processor can be a logic circuit, integrated circuit, etc. When implemented in software, the processor can be a general-purpose processor that reads software code stored in memory. The memory can exist independently and be connected to the processor, or the memory can be integrated with the processor.

[0149] As an example, the processor in the embodiments of this application can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. A general-purpose processor can be a microprocessor, any conventional processor, or a processing circuit that implements a specific function.

[0150] In embodiments of this application, the memory may be random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, portable hard disks, CD-ROMs, or any other form of storage medium known in the art. An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. Of course, the storage medium may also be a component of the processor. The processor and storage medium may reside in an ASIC. Additionally, the ASIC may reside in a network device or a terminal device. Alternatively, the processor and storage medium may exist as discrete components in the network device or terminal device.

[0151] In the above embodiments, it can be implemented entirely or partially by software, hardware, firmware, or any combination thereof.

[0152] When implemented in hardware, the data processing method provided in this application embodiment may be implemented without reading software code or instructions. For example, it may be implemented by CPU, DSP, ASIC, FPGA, other programmable logic devices, transistor logic devices, hardware components, or any combination thereof.

[0153] When implemented using software, it can be implemented entirely or partially in the form of a computer program product. A computer program product includes one or more computer programs or instructions. When the computer program or instructions are loaded and executed on a computer, all or part of the processes or functions of the embodiments of this application are performed. The computer can be a general-purpose computer, a special-purpose computer, a computer network, a network device, a terminal device, or other programmable device. The computer program or instructions can be stored in or transmitted through a computer-readable storage medium. The computer-readable storage medium can be any available medium that a computer can access, or a data storage device such as a server integrating one or more available media. The available medium can be a magnetic medium, such as a floppy disk, hard disk, or magnetic tape; it can also be an optical medium, such as a Digital Versatile Disc (DVD); or it can be a semiconductor medium, such as a solid-state disk (SSD).

[0154] Finally, it should be noted that the above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A data processing method, characterized in that, include: Receive a first data stream, the rate of the first data stream is a first rate, and the first data stream is obtained by sequentially undergoing a first encoding process and a second encoding process; The first data stream is subjected to at least one decoding process, wherein at least one first decoding process corresponds to the second encoding process, in order to obtain the second data stream; The second data stream is sent to the receiving device, and the rate of the second data stream is the first rate.

2. The data processing method as described in claim 1, characterized in that, The first encoding process uses RS encoding.

3. The data processing method as described in claim 1 or 2, characterized in that, The second encoding process uses either Hamming encoding or BCH encoding.

4. The data processing method according to any one of claims 1-3, characterized in that, The first decoding process is soft-decision decoding.

5. The data processing method as described in claim 4, characterized in that, The soft decision decoding is Hamming or BCH soft decision decoding.

6. The data processing method according to any one of claims 1-3, characterized in that, The first decoding process is hard-decision decoding.

7. The data processing method according to any one of claims 1-6, characterized in that, The first data stream includes a first codeword generated by the second encoding process, and the second data stream includes a second codeword, wherein the second codeword is obtained after the first codeword has undergone the at least one decoding process.

8. The data processing method according to any one of claims 1-7, characterized in that, The method further includes: The receiving device receives the second data stream; The second data is subjected to at least one second decoding process and at least one third decoding process to obtain the service data sent by the transmitting device. The second decoding process corresponds to the second encoding process, and the third decoding process corresponds to the first encoding process.

9. The data processing method as described in claim 8, characterized in that, The second encoding process uses Hamming code encoding, and the second decoding process uses Hamming code decoding.

10. The data processing method as described in claim 9, characterized in that, The second decoding process uses hard-decision decoding.

11. The data processing method according to any one of claims 8-10, characterized in that, The first encoding process uses RS encoding, and the third decoding process uses RS decoding.

12. The data processing method as described in claim 2 or 11, characterized in that, The RS encoding is RS(544,514), RS(528,514), RS(560,514), or RS(576,514).

13. The data processing method according to any one of claims 8-11, characterized in that, The first decoding process and the second decoding process are executed on different devices.

14. A data processing method, characterized in that, include: Receive a second data stream, wherein the second data stream is a data stream obtained after the first data stream has undergone at least one decoding process, and the first data stream is obtained by sequentially undergoing a first encoding process and a second encoding process, and the first data stream and the second data stream have the same rate; The second data is subjected to a second decoding process and a third decoding process to obtain the service data sent by the transmitting device. The second decoding process corresponds to the second encoding process, and the third decoding process corresponds to the first encoding process.

15. The data processing method as described in claim 14, characterized in that, The second encoding process uses Hamming code encoding, and the second decoding process uses Hamming code decoding.

16. The data processing method as described in claim 15, characterized in that, The second decoding process uses hard-decision decoding.

17. The data processing method according to any one of claims 14-16, characterized in that, The first encoding process uses RS encoding, and the third decoding process uses RS decoding.

18. The data processing method as described in claim 17, characterized in that, The RS encoding is RS(544,514), RS(528,514), RS(560,514), or RS(576,514).

19. The data processing method according to any one of claims 14-18, characterized in that, The second data stream includes a first check sequence, wherein the first check sequence is obtained after the check sequence generated by the second encoding process has been decoded at least once.

20. A data processing apparatus, characterized in that, The device includes a processing unit and a transceiver unit, wherein... The transceiver unit is used to send the data stream sent by the processing unit, or to send a data stream to the processing unit; the processing unit is used to perform the method as described in any one of claims 1-19.

21. A chip, characterized in that, The chip is used to perform the method as described in any one of claims 1 to 7 and 14 to 19.

22. An optical module, characterized in that, The optical module includes a processor and an interface, wherein the processor is used to perform the method as described in any one of claims 1 to 7 and to transmit and receive signals through the interface.

23. A communication device, characterized in that, The communication device includes a host-side device and an optical module as described in claim 22, the optical module being connected to the host-side device, and the host-side device being used to perform the method as described in any one of claims 14 to 19.

24. A communication system, characterized in that, include: A first communication device and a second communication device, wherein at least one of the first communication device and the second communication device is the communication device as described in claim 23, and the first communication device and the second communication device are connected.

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