Encoding method and apparatus

Abstract

This application provides an encoding method and apparatus. The method includes: performing LDPC encoding on information bits based on an exponential matrix to obtain encoded bits, {b1,b2,…,b...} j} represents the value corresponding to the non-zero element in a row of the above exponent matrix, {a1,a2,…,a…} i} represents the values ​​corresponding to non-zero elements in another row of the aforementioned exponent matrix, {a1,a2,…,a…} i} and {b1,b2,…,b j} satisfies: when i < j, {a1, a2, ..., a i} is a proper subset of; when i = j, {a1, a2, ..., a i} represents a non-identical permutation of , where represents floor function, mod represents modulo, c is an integer, d is a non-zero real number, Zc is the boost factor, and Zc is a positive integer; output the above encoded bits. In this way, the two rows in the exponent matrix have fixed structural characteristics, which helps ensure the stability of LDPC code performance. Furthermore, using the above method improves the flexibility of parity check matrix construction, thus adapting to more communication environments and needs.

Description

Technical Field

[0001] This application relates to the field of communications, and particularly to encoding methods and apparatus in the field of communications. Background Technology

[0002] Low-density parity-check (LDPC) codes are a forward error-correction coding technique that uses a parity-check matrix for encoding and decoding. The parity-check matrix is ​​typically constructed from a base matrix, which is a small, sparse matrix whose elements are generally 0 or 1. During the construction of the parity-check matrix, the positions of 0 elements in the base matrix can be expanded into an all-zero matrix, and the positions of 1 elements can be expanded into a cyclic shift matrix. This cyclic shift matrix is ​​obtained by cyclically shifting the identity matrix based on the shift value.

[0003] Currently, the shift values ​​corresponding to non-zero elements in the basis matrix are random, which makes the performance of LDPC codes unstable. For example, in some cases, the performance of LDPC codes may be poor. Summary of the Invention

[0004] This application provides an encoding method and apparatus to improve the stability of LDPC code performance.

[0005] In a first aspect, this application provides an encoding method that can be applied to the terminal side, such as a terminal device or a communication / computing module in a terminal device, or a circuit or chip in a terminal device responsible for communication functions (such as a modem chip, also known as a baseband chip, or a system-on-chip (SoC) chip containing a modem core or a system-in-package (SIP) chip), or a circuit or chip in a terminal device responsible for computing functions (such as a graphics processing unit (GPU), an artificial intelligence (AI) processor, or an application-specific integrated circuit (ASIC)), or a logic node, logic module, or software that can implement all or part of the functions of a terminal device.

[0006] In another possible design, the method can be applied to the network side, such as radio access network (RAN) equipment (hereinafter referred to as access network equipment), modules (e.g., circuits, chips or chip systems) in the access network equipment, or logical nodes, logical modules or software that can implement all or part of the functions of the access network equipment, or circuits or chips (such as GPUs, AI processors, or ASICs) in the access network equipment that are responsible for computing functions.

[0007] The following section uses the application of this method to terminal devices as an example.

[0008] For example, in this method, the terminal device performs LDPC encoding on the information bits based on the exponent matrix to obtain the encoded bits, {b1,b2,…,b...} j} represents the value corresponding to the non-zero element in a row of the above exponent matrix, {a1,a2,…,a…} i} represents the value corresponding to the non-zero element in another row of the aforementioned exponent matrix, {a1,a2,…,a…} i} and {b1,b2,…,b j} satisfies: when i < j, {a1, a2, ..., a i}yes A proper subset of; when i = j, {a1, a2, ..., a i}yes The non-identical permutations of, where, represents floor function, mod represents modulo, c is an integer, d is a non-zero real number, Zc is the boost factor, and Zc is a positive integer; output the above encoded bits.

[0009] In the above method, {a1,a2,…,a i} and {b1,b2,…,b j By satisfying the above characteristics, the two rows in the exponent matrix have fixed structural features, which helps ensure the stability of LDPC code performance. Furthermore, this method improves the flexibility of parity-check matrix construction, thus adapting to more communication environments and needs.

[0010] In one possible design, d = 1, {a1, a2, ..., a i} and {b1,b2,…,b j} satisfies: when i < j, {a1, a2, ..., a i} is {(-b1+c)modZc,(-b2+c)modZc,…,(-b j The proper subset of {a1, a2, ..., a} when i = j. i} is {(-b1+c)modZc,(-b2+c)modZc,…,(-b j Non-identical permutations of +c)modZc}.

[0011] In one possible design, when i = j, {a1, a2, ..., a i} and {b1,b2,…,b j}satisfy: Where π(k) = k + (e mod L), k ∈ {1, 2, ..., i}, e is a positive integer, L is greater than or equal to 2, and L is less than or equal to the number of columns of the above exponential matrix, and L is an integer.

[0012] In one possible design, d = 1, and when i = j, {a1, a2, ..., a i} and {b1,b2,…,b j} Satisfies: a k = (-b π(k) +c)modZc, where π(k)=k+(emodL), k∈{1,2,…,i}, e is a positive integer, L is greater than or equal to 2, and L is less than or equal to the number of columns of the above exponential matrix, and L is an integer.

[0013] In one possible design, {g1,g2,…,g v} represents the values ​​corresponding to non-zero elements in a column of the aforementioned exponent matrix, {h1,h2,…,h w} represents the values ​​corresponding to non-zero elements in another column of the aforementioned exponent matrix, {h1,h2,…,h w} and {g1,g2,…,g v} satisfies: when w < v, {h1,h2,…,h w}yes A proper subset of; when w = v, {h1, h2, ..., h w}yes Non-identical permutations; among which, q represents rounding down, mod represents modulo, q is an integer, and p is a non-zero real number.

[0014] In the above method, {h1,h2,…,h w} and {g1,g2,…,g v By satisfying the above characteristics, the two columns of the exponent matrix have fixed structural features, which helps ensure the stability of LDPC code performance. Furthermore, this method improves the flexibility of parity-check matrix construction, thus adapting to more communication environments and needs.

[0015] In one possible design, p = 1, {h1, h2, ..., h w} and {g1,g2,…,g v} satisfies: when w < v, {h1,h2,…,h w} is {(-g1+q)modZc,(-g2+q)modZc,…,(-g v The proper subset of {h1,h2,…,h} when w=v. w} is {(-g1+q)modZc,(-g2+q)modZc,…,(-g v Non-identical permutations of +q)modZc}.

[0016] In one possible design, when w = v, {h1,h2,…,h w} and {g1,g2,…,g v}satisfy: Where λ(t) = t + (umod K), t ∈ {1, 2, ..., w}, u is a positive integer, K is greater than or equal to 2, and K is less than or equal to the number of rows of the above exponential matrix, and K is an integer.

[0017] In one possible design, p = 1, and when w = v, {h1, h2, ..., h w} and {g1,g2,…,g v} satisfies: h t =(-g λ(t) +q)modZc, where λ(t)=t+(umod K), t∈{1,2,…,w}, u is a positive integer, K is greater than or equal to 2, and K is less than or equal to the number of rows of the above exponential matrix, and K is an integer.

[0018] Secondly, this application provides a decoding method that can be applied to the terminal side, such as a terminal device or a communication / computing module in the terminal device, or a circuit or chip in the terminal device responsible for communication functions (such as a modem chip, or a SoC chip or SIP chip containing a modem core), or a circuit or chip in the terminal device responsible for computing functions (such as a GPU, AI processor, or ASIC), or a logic node, logic module, or software that can implement all or part of the functions of the terminal device.

[0019] In another possible design, the method can be applied to the network side, such as access network devices, modules (e.g., circuits, chips, or chip systems) in access network devices, or logical nodes, logical modules, or software that can implement all or part of the functions of access network devices, or circuits or chips (such as GPUs, AI processors, or ASICs) in access network devices that are responsible for computing functions.

[0020] The following section uses the application of this method to access network equipment as an example.

[0021] For example, in this method, the access network device inputs the bit to be decoded; based on the exponent matrix, the bit to be decoded is LDPC decoded to obtain the information bit, {b1,b2,…,b...}. j} represents the value corresponding to the non-zero element in a row of the above exponent matrix, {a1,a2,…,a…} i} represents the value corresponding to the non-zero element in another row of the aforementioned exponent matrix, {a1,a2,…,a…} i} and {b1,b2,…,b j} satisfies: when i < j, {a1, a2, ..., a i}yes A proper subset of; when i = j, {a1, a2, ..., a i}yes The non-identical permutations of, where, represents rounding down, mod represents modulo, c is an integer, d is a non-zero real number, Zc is the promotion factor, and Zc is a positive integer.

[0022] In the above method, {a1,a2,…,a i} and {b1,b2,…,b j By satisfying the above characteristics, the two rows in the exponent matrix have fixed structural features, which helps ensure the stability of LDPC code performance. Furthermore, this method improves the flexibility of parity-check matrix construction, thus adapting to more communication environments and needs.

[0023] In one possible design, d = 1, {a1, a2, ..., a i} and {b1,b2,…,b j} satisfies: when i < j, {a1, a2, ..., a i} is {(-b1+c)modZc,(-b2+c)modZc,…,(-b j The proper subset of {a1, a2, ..., a} when i = j. i} is {(-b1+c)modZc,(-b2+c)modZc,…,(-b j Non-identical permutations of +c)modZc}.

[0024] In one possible design, when i = j, {a1, a2, ..., a i} and {b1,b2,…,b j}satisfy: Where π(k) = k + (e mod L), k ∈ {1, 2, ..., i}, e is a positive integer, L is greater than or equal to 2, and L is less than or equal to the number of columns of the above exponential matrix, and L is an integer.

[0025] In one possible design, d = 1, and when i = j, {a1, a2, ..., a i} and {b1,b2,…,b j} Satisfies: a k = (-b π(k) +c)modZc, where π(k)=k+(emodL), k∈{1,2,…,i}, e is a positive integer, L is greater than or equal to 2, and L is less than or equal to the number of columns of the above exponential matrix, and L is an integer.

[0026] In one possible design, {g1,g2,…,g v} represents the values ​​corresponding to non-zero elements in a column of the aforementioned exponent matrix, {h1,h2,…,h w} represents the values ​​corresponding to non-zero elements in another column of the aforementioned exponent matrix, {h1,h2,…,h w} and {g1,g2,…,g v} satisfies: when w < v, {h1,h2,…,h w}yes A proper subset of; when w = v, {h1, h2, ..., h w}yes Non-identical permutations; among which, q represents rounding down, mod represents modulo, q is an integer, and p is a non-zero real number.

[0027] In the above method, {h1,h2,…,h w} and {g1,g2,…,g v By satisfying the above characteristics, the two columns of the exponent matrix have fixed structural features, which helps ensure the stability of LDPC code performance. Furthermore, this method improves the flexibility of parity-check matrix construction, thus adapting to more communication environments and needs.

[0028] In one possible design, p = 1, {h1, h2, ..., h w} and {g1,g2,…,g v} satisfies: when w < v, {h1,h2,…,h w} is {(-g1+q)modZc,(-g2+q)modZc,…,(-g v The proper subset of {h1,h2,…,h} mod Zc} when w = v; w} is {(-g1+q)modZc,(-g2+q)modZc,…,(-g v Non-identical permutations of Zc} +q)mod Zc}.

[0029] In one possible design, when w = v, {h1,h2,…,h w} and {g1,g2,…,g v}satisfy: Where λ(t) = t + (umod K), t ∈ {1, 2, ..., w}, u is a positive integer, K is greater than or equal to 2, and K is less than or equal to the number of rows of the above exponential matrix, and K is an integer.

[0030] In one possible design, p = 1, and when w = v, {h1, h2, ..., h w} and {g1,g2,…,g v} satisfies: h t =(-g λ(t) +q)modZc, where λ(t)=t+(umod K), t∈{1,2,…,w}, u is a positive integer, K is greater than or equal to 2, and K is less than or equal to the number of rows of the above exponential matrix, and K is an integer.

[0031] Thirdly, this application provides an encoding method that can be applied to the terminal side, such as a terminal device or a communication module / computing module in the terminal device, or a circuit or chip in the terminal device that is responsible for communication functions (such as a modem chip, or a SoC chip or SIP chip containing a modem core), or a circuit or chip in the terminal device that is responsible for computing functions (such as a GPU, AI processor, or ASIC), or a logical node, logical module, or software that can implement all or part of the functions of the terminal device.

[0032] In another possible design, the method can be applied to the network side, such as access network devices, modules (e.g., circuits, chips, or chip systems) in access network devices, or logical nodes, logical modules, or software that can implement all or part of the functions of access network devices, or circuits or chips (such as GPUs, AI processors, or ASICs) in access network devices that are responsible for computing functions.

[0033] The following example uses the method applied to a terminal device, but this application does not limit it.

[0034] For example, in this method, the terminal device performs LDPC encoding on the information bits based on the exponent matrix to obtain the encoded bits, {h1,h2,…,h...}. w} represents the values ​​corresponding to non-zero elements in a column of the aforementioned exponent matrix, {g1,g2,…,g v} represents the values ​​corresponding to non-zero elements in another column of the aforementioned exponent matrix, {h1,h2,…,h w} and {g1,g2,…,g v} satisfies: when w < v, {h1,h2,…,h w}yes A proper subset of; when w = v, {h1, h2, ..., h w}yes Non-identical permutations; among which, This indicates rounding down, mod indicates modulo operation, q is an integer, p is a non-zero real number, Zc is the promotion factor, and Zc is a positive integer; output the above encoded bits.

[0035] In the above method, {h1,h2,…,h w} and {g1,g2,…,g v By satisfying the above characteristics, the two columns of the exponent matrix have fixed structural features, which helps ensure the stability of LDPC code performance. Furthermore, this method improves the flexibility of parity-check matrix construction, thus adapting to more communication environments and needs.

[0036] In one possible design, p = 1, {h1, h2, ..., h w} and {g1,g2,…,g v} satisfies: when w < v, {h1,h2,…,h w} is {(-g1+q)modZc,(-g2+q)modZc,…,(-g v The proper subset of {h1,h2,…,h} when w=v. w} is {(-g1+q)modZc,(-g2+q)modZc,…,(-g v Non-identical permutations of +q)modZc}.

[0037] In one possible design, when w = v, {h1,h2,…,h w} and {g1,g2,…,g v}satisfy: Where λ(t) = t + (umod K), t ∈ {1, 2, ..., w}, u is a positive integer, K is greater than or equal to 2, and K is less than or equal to the number of rows of the above exponential matrix, and K is an integer.

[0038] In one possible design, p = 1, and when w = v, {h1, h2, ..., h w} and {g1,g2,…,g v} satisfies: h t =(-g λ(t) +q)modZc, where λ(t)=t+(umod K), t∈{1,2,…,w}, u is a positive integer, K is greater than or equal to 2, and K is less than or equal to the number of rows of the above exponential matrix, and K is an integer.

[0039] Fourthly, this application provides another decoding method that can be applied to the terminal side, such as a terminal device or a communication / computing module in the terminal device, or a circuit or chip in the terminal device responsible for communication functions (such as a modem chip, or a SoC chip or SIP chip containing a modem core), or a circuit or chip in the terminal device responsible for computing functions (such as a GPU, AI processor, or ASIC), or a logical node, logical module, or software that can implement all or part of the functions of the terminal device.

[0040] In another possible design, the method can be applied to the network side, such as access network devices, modules (e.g., circuits, chips, or chip systems) in access network devices, or logical nodes, logical modules, or software that can implement all or part of the functions of access network devices, or circuits or chips (such as GPUs, AI processors, or ASICs) in access network devices that are responsible for computing functions.

[0041] The following example uses the method applied to access network equipment, but this application does not limit it.

[0042] For example, in this method, the access network device inputs the bits to be decoded; based on the exponent matrix, the bits to be decoded are LDPC decoded to obtain information bits, {h1,h2,…,h...}. w} represents the values ​​corresponding to non-zero elements in a column of the aforementioned exponent matrix, {g1,g2,…,g v} represents the values ​​corresponding to non-zero elements in another column of the aforementioned exponent matrix, {h1,h2,…,h w} and {g1,g2,…,g v} satisfies: when w < v, {h1,h2,…,h w}yes A proper subset of; when w = v, {h1, h2, ..., h w}yes Non-identical permutations; among which, q represents rounding down, mod represents modulo operation, q is an integer, p is a non-zero real number, Zc is the promotion factor, and Zc is a positive integer.

[0043] In the above method, {h1,h2,…,h w} and {g1,g2,…,g v By satisfying the above characteristics, the two columns of the exponent matrix have fixed structural features, which helps ensure the stability of LDPC code performance. Furthermore, this method improves the flexibility of parity-check matrix construction, thus adapting to more communication environments and needs.

[0044] In one possible design, p = 1, {h1, h2, ..., h w} and {g1,g2,…,g v} satisfies: when w < v, {h1,h2,…,h w} is {(-g1+q)modZc,(-g2+q)modZc,…,(-g v The proper subset of {h1,h2,…,h} mod Zc} when w = v; w} is {(-g1+q)modZc,(-g2+q)modZc,…,(-g v Non-identical permutations of Zc} +q)mod Zc}.

[0045] In one possible design, when w = v, {h1,h2,…,h w} and {g1,g2,…,g v}satisfy: Where λ(t) = t + (umod K), t ∈ {1, 2, ..., w}, u is a positive integer, K is greater than or equal to 2, and K is less than or equal to the number of rows of the above exponential matrix, and K is an integer.

[0046] In one possible design, p = 1, and when w = v, {h1, h2, ..., h w} and {g1,g2,…,g v} satisfies: h t =(-g λ(t) +q)modZc, where λ(t)=t+(umod K), t∈{1,2,…,w}, u is a positive integer, K is greater than or equal to 2, and K is less than or equal to the number of rows of the above exponential matrix, and K is an integer.

[0047] Fifthly, this application provides a communication device that has the functions of the first aspect described above. For example, the communication device includes modules, units, or means that perform the operations involved in the first aspect. These modules, units, or means can be implemented by software, hardware, or a combination of software and hardware.

[0048] Sixthly, this application provides a communication device that has the functions of the second aspect above. For example, the communication device includes a module, unit, or means for performing the operations involved in the second aspect above. The module, unit, or means can be implemented by software, hardware, or a combination of software and hardware.

[0049] Seventhly, this application provides a communication device that has the functions of the third aspect above. For example, the communication device includes a module, unit, or means for performing the operations involved in the third aspect above. The module, unit, or means can be implemented by software, hardware, or a combination of software and hardware.

[0050] Eighthly, this application provides a communication device that has the functions of the fourth aspect above. For example, the communication device includes a module, unit, or means for performing the operations involved in the fourth aspect above. The module, unit, or means can be implemented by software, hardware, or a combination of software and hardware.

[0051] Ninthly, this application provides a communication device including an interface circuit and one or more processors. The one or more processors are coupled to a memory. The memory stores part or all of the computer program or instructions necessary to implement the functions described in the first aspect above. The one or more processors are executable to carry out the computer program or instructions, causing the communication device to implement the methods in any possible design or implementation of the first aspect above. The interface circuit is used to implement the communication functions within the communication device and / or the communication functions between the communication device and other devices or components.

[0052] In one possible design, the processor is used to communicate with other devices or components through the interface circuit.

[0053] In one possible design, the communication device may also include the memory.

[0054] The aforementioned communication device may be a terminal device, a communication module in a terminal device, or a chip in a terminal device responsible for communication functions, such as a modem chip or a SoC chip or SIP chip containing a modem core.

[0055] The aforementioned communication device may also be an access network device, or a communication module in an access network device, or a chip in an access network device responsible for communication functions, such as a modem chip or a SoC chip or SIP chip containing a modem core.

[0056] Tenthly, this application provides a communication device including an interface circuit and one or more processors. The one or more processors are coupled to a memory. The memory stores part or all of the necessary computer program or instructions for implementing the functions described in the second aspect above. The one or more processors are executable to carry out the computer program or instructions, causing the communication device to implement the methods in any possible design or implementation of the second aspect above. The interface circuit is used to implement the communication functions within the communication device and / or the communication functions between the communication device and other devices or components.

[0057] In one possible design, the processor is used to communicate with other devices or components through the interface circuit.

[0058] In one possible design, the communication device may also include the memory.

[0059] The aforementioned communication device may be a terminal device, a communication module in a terminal device, or a chip in a terminal device responsible for communication functions, such as a modem chip or a SoC chip or SIP chip containing a modem core.

[0060] The aforementioned communication device may also be an access network device, or a communication module in an access network device, or a chip in an access network device responsible for communication functions, such as a modem chip or a SoC chip or SIP chip containing a modem core.

[0061] Eleventhly, this application provides a communication device including an interface circuit and one or more processors. The one or more processors are coupled to a memory. The memory stores part or all of the necessary computer program or instructions for implementing the functions described in the third aspect above. The one or more processors can execute the computer program or instructions, causing the communication device to implement the methods in any possible design or implementation of the third aspect above when executed. The interface circuit is used to implement the communication functions within the communication device and / or the communication functions between the communication device and other devices or components.

[0062] In one possible design, the processor is used to communicate with other devices or components through the interface circuit.

[0063] In one possible design, the communication device may also include the memory.

[0064] The aforementioned communication device may be a terminal device, a communication module in a terminal device, or a chip in a terminal device responsible for communication functions, such as a modem chip or a SoC chip or SIP chip containing a modem core.

[0065] The aforementioned communication device may also be an access network device, or a communication module in an access network device, or a chip in an access network device responsible for communication functions, such as a modem chip or a SoC chip or SIP chip containing a modem core.

[0066] In a twelfth aspect, this application provides a communication device including an interface circuit and one or more processors. The one or more processors are coupled to a memory. The memory stores part or all of the necessary computer program or instructions for implementing the functions described in the fourth aspect above. The one or more processors are executable to carry out the computer program or instructions, causing the communication device to implement the methods in any possible design or implementation of the fourth aspect above. The interface circuit is used to implement the communication functions within the communication device and / or the communication functions between the communication device and other devices or components.

[0067] In one possible design, the processor is used to communicate with other devices or components through the interface circuit.

[0068] In one possible design, the communication device may also include the memory.

[0069] The aforementioned communication device may be a terminal device, a communication module in a terminal device, or a chip in a terminal device responsible for communication functions, such as a modem chip or a SoC chip or SIP chip containing a modem core.

[0070] The aforementioned communication device may also be an access network device, or a communication module in an access network device, or a chip in an access network device responsible for communication functions, such as a modem chip or a SoC chip or SIP chip containing a modem core.

[0071] In a thirteenth aspect, this application provides a communication system that includes the communication devices of the ninth and tenth aspects; or, the communication system includes the communication devices of the eleventh and twelfth aspects.

[0072] In a fourteenth aspect, this application provides a computer-readable storage medium storing a computer program or instructions that, when executed, cause the method in any of the possible designs of the first to fourth aspects to be implemented.

[0073] In a fifteenth aspect, this application provides a computer program product containing instructions (or a program) that, when executed on a computer, cause the method in any of the possible designs of the first to fourth aspects to be implemented.

[0074] It should be understood that the fifth to fifteenth aspects of this application correspond to the technical solutions of the first to fourth aspects of this application, and the beneficial effects obtained by each aspect and the corresponding feasible implementation are similar, and will not be repeated here. Attached Figure Description

[0075] Figure 1 This is a schematic diagram of the architecture applicable to the methods provided in this application;

[0076] Figure 2 and Figure 3 This is a schematic diagram of a possible application framework in a communication system;

[0077] Figure 4 This is a schematic diagram of the information transmission process provided in an embodiment of this application;

[0078] Figure 5 This is a schematic flowchart of the encoding and decoding method provided in this application;

[0079] Figure 6 This is a possible exemplary block diagram of the communication device provided in the embodiments of this application;

[0080] Figure 7 This is a schematic diagram of the structure of a terminal provided in an embodiment of this application. Detailed Implementation

[0081] The technical solutions of this application can be applied to various communication systems, such as Long Term Evolution (LTE) systems, 5th generation (5G) systems, new radio (NR) systems, or future communication systems. This application does not limit the scope of these systems.

[0082] The following is a combination of... Figure 1 The architecture of the communication system applicable to the embodiments of this application will be described in detail. Figure 1 This is a schematic diagram illustrating one possible, non-limiting system. For example... Figure 1 As shown, the communication system 10 includes a RAN 100 and a core network (CN) 200. The RAN 100 includes at least one RAN node (e.g., Figure 1 110a and 110b (collectively referred to as 110) and at least one terminal (such as Figure 1 RAN 100, denoted as RAN 120a-120j, is collectively referred to as RAN 120. RAN 100 may also include other RAN nodes, such as wireless relay equipment and / or wireless backhaul equipment. Figure 1(Not shown in the image). Terminal 120 is connected to RAN node 110 wirelessly. RAN node 110 is connected to core network 200 wirelessly or via wired connection. The core network equipment in core network 200 and RAN node 110 in RAN 100 can be different physical devices, or they can be the same physical device integrating core network logical functions and radio access network logical functions.

[0083] RAN 100 can be a cellular system related to the 3rd Generation Partnership Project (3GPP), such as 4G, 5G mobile communication systems, or future-oriented evolution systems. RAN 100 can also be an open RAN (O-RAN or ORAN), a cloud RAN (CRAN), a virtualized RAN (vRAN), an artificial intelligence RAN (AI RAN), or a wireless fidelity (Wi-Fi) system. RAN 100 can also be a communication system that integrates two or more of the above systems.

[0084] RAN node 110, sometimes also referred to as access network equipment, RAN entity, or access node, constitutes part of the communication system and is used to help terminals achieve wireless access. The multiple RAN nodes 110 in this communication system 10 can be of the same type or different types. In some scenarios, the roles of RAN node 110 and terminal 120 are relative, for example... Figure 1 Network element 120i can be a helicopter or a drone, and it can be configured as a mobile base station. For terminals 120j that access RAN 100 through network element 120i, network element 120i is a base station; however, for base station 110a, network element 120i is a terminal. RAN node 110 and terminal 120 are sometimes referred to as communication devices, for example... Figure 1 Network elements 110a and 110b can be understood as communication devices with base station functions, while network elements 120a-120j can be understood as communication devices with terminal functions.

[0085] In one possible scenario, a RAN node can be a base station, an evolved NodeB (eNodeB), an access point (AP), a transmission reception point (TRP), a next-generation NodeB (gNB), a base station in a future mobile communication system, or an access node in a Wi-Fi system, etc. Figure 1 110a), micro base stations or indoor stations (such as Figure 1 The RAN node can be a relay node or donor node (as described in section 110b), or a wireless controller in a CRAN scenario. Optionally, the RAN node can also be a server, wearable device, vehicle, or in-vehicle equipment. For example, the access network equipment in vehicle-to-everything (V2X) technology can be a roadside unit (RSU). All or part of the functions of the RAN node in this application can also be implemented through software functions running on hardware, or through virtualization functions instantiated on a platform (e.g., a cloud platform). The RAN node can also be equipped with communication modules, circuits, or chips that perform corresponding communication functions. The RAN node can also be configured with program instructions for performing corresponding communication functions and corresponding program instructions. The RAN node in this application can also be a logical node, logical module, or software that can implement all or part of the access node functions, or a circuit or chip (such as a GPU, AI processor, or ASIC) responsible for computing functions in the access node.

[0086] In another possible scenario, multiple RAN nodes collaborate to assist terminals in achieving wireless access, with different RAN nodes each implementing some of the base station's functions. For example, RAN nodes can be central units (CUs), distributed units (DUs), CU-control plane (CPs), CU-user plane (UPs), or radio units (RUs), etc. CUs and DUs can be set up separately or included in the same network element, such as a baseband unit (BBU). RUs can be included in radio frequency equipment or radio frequency units, such as remote radio units (RRUs), active antenna units (AAUs), or remote radio heads (RRHs). Furthermore, RAN nodes can also be computing units, providing computing power for tasks (such as model inference and / or model training), and can also be used to implement one or more of the following: task partitioning, scheduling, and orchestration. The functionality of a computing unit can be implemented by a separate module independent of other units (e.g., CU, DU, RU), or by one or more other units (e.g., one or more of CU, DU, RU).

[0087] In different systems, CU (or CU-CP and CU-UP), DU, computing unit, or RU may have different names, but those skilled in the art will understand their meaning. For example, in an ORAN system, CU can also be called O-CU (open CU), DU can also be called O-DU, CU-CP can also be called O-CU-CP, CU-UP can also be called O-CU-UP, and RU can also be called O-RU. For ease of description, this application uses CU, CU-CP, CU-UP, DU, computing unit, and RU as examples. Any of the units among CU (or CU-CP, CU-UP), DU, computing unit, and RU in this application can be implemented through software modules, hardware modules, or a combination of software modules and hardware modules.

[0088] A terminal can be a device or module that accesses the aforementioned communication system and has corresponding communication functions. A terminal can also be called a terminal device, user equipment (UE), mobile station, mobile terminal, etc. Terminals can be widely used in various scenarios, such as device-to-device (D2D), vehicle-to-everything (V2X) communication, machine-type communication (MTC), Internet of Things (IoT), virtual reality, augmented reality, industrial control, autonomous driving, telemedicine, smart grids, smart furniture, smart offices, smart wearables, smart transportation, smart cities, etc. Terminals can be mobile phones, tablets, computers with wireless transceiver capabilities, wearable devices, vehicles, drones, helicopters, airplanes, ships, robots, robotic arms, smart home devices, transportation vehicles with wireless communication capabilities, communication modules, etc. The embodiments of this application do not limit the device form of the terminal. Terminals typically contain communication modules, circuits, or chips that perform corresponding communication functions, and may further contain modules, circuits, or chips that perform corresponding computing functions (such as GPUs, AI processors, or ASICs). The terminal can also be configured with program instructions for performing corresponding communication and / or computing functions.

[0089] To support AI technology in wireless networks, AI nodes can be introduced into the network. AI nodes can also be called AI network elements or AI modules, etc., and this application does not limit this. AI nodes can be deployed in one or more of the following locations in the communication system: RAN nodes, terminal devices, or core network devices, etc. Alternatively, AI nodes can be deployed independently, for example, in a location other than any of the above-mentioned devices, such as in the host or cloud server of an over-the-top (OTT) system. AI nodes can communicate with other devices in the communication system, which can be one or more of the following: access network devices, terminal devices, or core network devices, etc.

[0090] It is understood that this application does not limit the number of AI nodes. For example, when there are multiple AI nodes, these nodes can be divided based on function, such as different AI nodes being responsible for different functions.

[0091] It can also be understood that AI nodes can be independent devices, or they can be integrated into the same device to achieve different functions. Alternatively, they can be network elements in hardware devices, software functions running on dedicated hardware, or virtualization functions instantiated on a platform (e.g., a cloud platform). This application does not limit the specific form of the aforementioned AI nodes.

[0092] The following will combine Figure 2 and Figure 3 Provide a possible application framework for the communication system.

[0093] Figure 2 This is a schematic diagram of a possible application framework in a communication system. For example... Figure 2 As shown, network elements in this communication system are connected via interfaces (e.g., NG interfaces or Xn interfaces) or air interfaces. These network element nodes, such as core network equipment, access network equipment, terminals, or one or more devices in operations administration and maintenance (OAM), are equipped with one or more AI modules (for clarity, ...). Figure 2 (Only one is shown in the image). The access network device can be a single RAN node or can include multiple RAN nodes, such as CU and DU. The CU and / or DU can also be equipped with one or more AI modules. The CU can also be split into CU-CP and CU-UP, and one or more AI modules can be set in the CU-CP and / or CU-UP.

[0094] AI modules are used to implement corresponding AI functions. AI modules deployed in different network elements can be the same or different. The models of AI modules can achieve different functions depending on the parameter configurations. The models of AI modules can be configured based on one or more of the following parameters: structural parameters (e.g., at least one of the following: number of neural network layers, neural network width, inter-layer connections, neuron weights, neuron activation function, or biases in the activation function), input parameters (e.g., the type and / or dimension of the input parameters), or output parameters (e.g., the type and / or dimension of the output parameters). The biases in the activation function can also be referred to as the biases of the neural network.

[0095] In one example, the neural network mentioned above could be a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), or a generative adversarial network (GAN).

[0096] Deep Neural Networks (DNNs) are artificial neural network architectures with multiple layers of nonlinear transformation units stacked in a hierarchical structure to form deep computational models. Compared to shallow neural networks, deep neural networks have more hidden layers, allowing the network model to capture more complex data structures and higher-level abstract features.

[0097] A CNN is a deep neural network with a convolutional structure. A CNN contains a feature extractor consisting of convolutional layers and subsampling layers. This feature extractor can be viewed as a filter, and the convolution process can be seen as performing convolution between a trainable filter and an input image or a convolutional feature map.

[0098] RNN is a type of recursive neural network that takes sequence data as input, recursively moves along the direction of sequence evolution, and connects all nodes (recurrent units) in a chain-like manner.

[0099] GAN is a deep learning model. It consists of a generator and a discriminator, and is trained through adversarial learning. Its purpose is to estimate the potential distribution of data samples and generate new data samples.

[0100] An AI module can have one or more models. A model can infer an output, which includes one or more parameters. The learning, training, or inference processes of different models can be deployed on different nodes or devices, or they can be deployed on the same node or device.

[0101] Figure 3 This is a schematic diagram of another possible application framework in a communication system. For example... Figure 3 As shown, the communication system includes a RAN intelligent controller (RIC). For example, the RIC could be... Figure 2 The AI ​​module shown is used to implement AI-related functions. RICs include near-real-time RICs (near-RT RICs) and non-real-time RICs (non-RT RICs). Non-real-time RICs primarily process non-real-time information, such as data that is not sensitive to latency, with latency in the order of seconds. Real-time RICs primarily process near-real-time information, such as data that is relatively sensitive to latency, with latency in the order of tens of milliseconds.

[0102] Near real-time (NRT) RICs are used for model training and inference. For example, they are used to train AI models and then use those models for inference. NRT RICs can obtain network-side and / or terminal-side information from RAN nodes (e.g., CUs, CU-CPs, CU-UPs, DUs, compute nodes, and / or RUs) and / or terminals. This information can be used as training data or inference data. NRT RICs can deliver inference results to RAN nodes and / or terminals. Inference results can be exchanged between CUs and DUs, and / or between DUs and RUs. For example, a NRT RIC delivers an inference result to a DU, which then forwards it to an RU.

[0103] Non-real-time RICs are also used for model training and inference. For example, they are used to train AI models and then use those models for inference. Non-real-time RICs can obtain network-side and / or terminal-side information from RAN nodes (e.g., CUs, CU-CPs, CU-UPs, DUs, compute nodes, and / or RUs) and / or terminals. This information can be used as training data or inference data, and the inference results can be delivered to RAN nodes and / or terminals. Inference results can be exchanged between CUs and DUs, and / or between DUs and RUs; for example, a non-real-time RIC delivers inference results to a DU, which then forwards them to an RU.

[0104] Near real-time RICs and non-real-time RICs can also be configured as separate network elements. Near real-time RICs and non-real-time RICs can also be part of other devices. For example, near real-time RICs can be set in RAN nodes (e.g., CU, DU, or compute nodes), while non-real-time RICs can be set in OAM, cloud servers, core network devices, or other network devices.

[0105] The following will combine Figure 4 The process of sending and receiving information is described in detail.

[0106] Figure 4 This is a schematic diagram of the information transmission process provided in the embodiments of this application.

[0107] like Figure 4 As shown, the information source is the origin of information and information sequences. The information source outputs an information sequence, which is converted into a binary (or multi-level) information sequence through source coding. Then, channel coding is performed on this information sequence to obtain the encoded information sequence, thereby improving the reliability of message transmission. Further, the encoded information sequence can be modulated and then transmitted through the channel. Correspondingly, after receiving the modulated information sequence, the receiving end demodulates it and then performs channel decoding using decoding techniques corresponding to channel coding, followed by source decoding to obtain the original information sequence. Here, the information sink is the object (or destination) of information transmission. The method provided in this application mainly involves channel coding and channel decoding.

[0108] This application primarily relates to improvements in encoding information sequences at the transmitting end and decoding received information at the receiving end. For example, the methods described below may employ LDPC coding techniques. Therefore, before introducing the methods provided in this application, the relevant technical terms of LDPC will be explained in detail below.

[0109] LDPC codes are a forward error correction technique where the encoder uses a parity-check matrix (PCM) for encoding. The PCM is a sparse matrix used to define the parity-check equations for LDPC codes. Each row of the PCM represents a parity-check equation, and each column corresponds to a codeword bit. In other words, the number of rows in the PCM equals the number of parity-check equations, and the number of columns equals the length of the codeword.

[0110] The parity-check matrix can be constructed from the basis matrix. The elements in the basis matrix are generally 0 or 1. Based on the lifting factor, the basis matrix can be extended into a parity-check matrix, which can be used for encoding and / or decoding. The lifting factor can also be called the expansion factor, lifting value, expansion size, or expansion coefficient, etc., and this application does not specifically limit its name.

[0111] For example, the boost value is denoted as Zc. Each element in the base matrix can be boosted into a matrix with Zc rows and Zc columns. These matrices are combined to form the entire parity check matrix. For instance, the positions of elements 0 in the base matrix can be expanded into a matrix of all zeros with Zc rows and Zc columns, and the positions of elements 1 can be expanded into a cyclic shift matrix with Zc rows and Zc columns. This cyclic shift matrix can be a column-wise cyclic shift P of an identity matrix with Zc rows and Zc columns. i,j The matrix obtained after this step, where P i,j This is the shift value corresponding to the element in the i-th row and j-th column of the base matrix, where the element in the i-th row and j-th column has a value of 1. The shift value can also be called a translation value or a cyclic shift value, etc. It should be understood that the above method of expanding the base matrix into a parity check matrix is ​​merely an example and should not constitute any limitation on this application. The cyclic shift will be explained in detail below.

[0112] In this application, circular shift can be understood as follows: during the shift, the bits in the original range are not lost, but are instead used as fill bits at the other end. For example, circular right shift by x bits means: each bit is shifted right by x bits, and the original low x bits become high x bits; circular left shift by x bits means: each bit is shifted left by x bits, and the original high x bits become low x bits. Where x is a natural number.

[0113] In this application, cyclic shifting of columns or rows in a matrix can also be understood as performing column or row transformations on the matrix. For example, consider an identity matrix with 4 rows and 4 columns. The identity matrix is ​​obtained by cyclically shifting it one position to the right. After the identity matrix is ​​cyclically shifted to the right twice, the resulting matrix is: The identity matrix is ​​cyclically shifted three times to the right, resulting in the following matrix: It is understandable that the matrix obtained by cyclically shifting the identity matrix to the right 0 times is still the identity matrix.

[0114] The matrix formed by the values ​​of each element with a value of 1 (also called a non-zero element) in the base matrix (called shift values) and the values ​​of each element with a value of 0 (also called a zero element) (e.g., -1) can be called an exponential matrix. The positions with a value of -1 can be expanded into a matrix of Zc rows (Zc being the lift value) and Zc columns, all containing zeros. The positions with a value other than -1 can be expanded into a cyclic shift matrix of Zc rows and Zc columns. From the explanation of exponential and base matrices, it can be seen that the number of rows in the exponential matrix is ​​the same as the number of rows in the base matrix, and the number of columns in the exponential matrix is ​​the same as the number of columns in the base matrix.

[0115] Currently, the shift values ​​corresponding to non-zero elements (i.e., elements with a value of 1) in the basis matrix are random, which makes the performance of LDPC codes unstable. In some cases, the performance of LDPC codes is poor.

[0116] In view of this, in this application, the values ​​corresponding to non-zero elements in a row of the exponent matrix are {b1,b2,…,b...} j}, and the values ​​{a1, a2, ..., a} corresponding to the non-zero elements in another row. i}, satisfying: when i < j, {a1,a2,…,a i}yes A proper subset of; when i = j, {a1, a2, ..., a i}yes The non-identical arrangement of the exponent matrix results in a fixed structural characteristic, which helps ensure the stability of LDPC code performance. Furthermore, this method improves the flexibility of parity-check matrix construction, thus adapting to more communication environments and needs.

[0117] In another possible implementation, the values ​​{g1, g2, ..., g...} corresponding to the non-zero elements in a column of the aforementioned exponent matrix... v} and the values ​​{h1,h2,…,h} corresponding to the non-zero elements in another column. w}, satisfying: when w < v, {h1,h2,…,h w}yes A proper subset of; when w = v, {h1, h2, ..., h w}yes The non-identical arrangement of the exponent matrix results in a fixed structural characteristic, which helps ensure the stability of LDPC code performance. Furthermore, this method improves the flexibility of parity-check matrix construction, thus adapting to more communication environments and needs.

[0118] The encoding method, decoding method, and communication device provided in this application will be described in detail below with reference to the accompanying drawings. It is understood that this application uses a terminal device and an access network device as examples to illustrate the interaction, but this application does not limit the entities that can perform the interaction. The terminal device can be considered as the information sender, and can encode information bits based on the encoding method provided in this application. The access network device can be considered as the information receiver, and can decode the bits to be decoded based on the decoding method provided in this application.

[0119] Optionally, the encoding method provided in this application may also be executed by a communication module / computing module in a terminal device, or a circuit or chip in a terminal device responsible for communication functions (such as a modem chip, or a SoC chip or SIP chip containing a modem core), or a circuit or chip in a terminal device responsible for computing functions (such as a GPU, AI processor, or ASIC), or a logic node, logic module, or software that can implement all or part of the functions of the terminal device.

[0120] In another design, the encoding method provided in this application may also be executed by an access network device, a module (e.g., a circuit, a chip, or a chip system) in the access network device, or a logical node, logical module, or software that can implement all or part of the functions of the access network device, or a circuit or chip (such as a GPU, AI processor, or ASIC) in the access network device that is responsible for computing functions.

[0121] Similarly, the decoding method provided in this application can also be executed by a terminal device, or a communication module / computing module in a terminal device, or a circuit or chip in a terminal device responsible for communication functions (such as a modem chip, or a SoC chip or SIP chip containing a modem core), or a circuit or chip in a terminal device responsible for computing functions (such as a GPU, AI processor, or ASIC), or a logic node, logic module, or software that can implement all or part of the functions of the terminal device.

[0122] In another design, the decoding method provided in this application may also be executed by a module (e.g., circuit, chip or chip system, etc.) in the access network device, or a logical node, logical module or software that can implement all or part of the functions of the access network device, or a circuit or chip (such as GPU, AI processor or ASIC) in the access network device that is responsible for computing functions.

[0123] The methods described below can be applied, for example, to... Figure 1 The communication system shown, the encoding method provided in this application, can be, for example, by... Figure 1 The decoding method provided in this application can be executed by terminal 120 in the system shown. Figure 1 The access network device 110 in the communication system shown is used to perform the operation, or the encoding method provided in this application can be performed by, for example, the access network device 110 in the communication system shown. Figure 1 The decoding method provided in this application can be performed by the access network device 110 in the communication system shown. Figure 1 The method is executed by terminal 120 in the communication system shown. Alternatively, the method provided in this application can also be applied to communication between terminals, that is, the encoding method can be executed by one terminal and the decoding method can be executed by another terminal. Or, the method provided in this application can also be applied to communication between access network devices, that is, the encoding method can be executed by one access network device and the decoding method can be executed by another access network device. This application does not limit this.

[0124] Figure 5 This is a schematic flowchart of the encoding / decoding method 500 provided in this application. The method 500 includes the following steps:

[0125] In step 510, the terminal device encodes the information bits based on the exponential matrix to obtain the encoded bits.

[0126] In step 520, the terminal device outputs the aforementioned encoded bits.

[0127] The encoded bits can also undergo one or more of the following processes: rate matching, interleaving, or modulation, to obtain the bit sequence to be transmitted, which the terminal device then transmits. Correspondingly, the access network device receives the bit sequence from the terminal device.

[0128] In step 530, the access network device decodes the bits to be decoded based on the exponential matrix to obtain the information bits.

[0129] Access network devices can obtain the bits to be decoded by performing one or more of the following operations on the received bit sequence: demodulation, deinterleaving, or rate matching, etc. Then, the access network devices can decode the bits to be decoded based on the exponential matrix to obtain the information bits.

[0130] Terminal devices can encode information bits based on an exponential matrix, and access network devices can decode bits to be decoded based on an exponential matrix. The following will use a terminal device as an example to detail the improvements to the exponential matrix in this application. The two rows of elements in this exponential matrix satisfy characteristic one, assuming {b1, b2, ..., b...} j} represents the value corresponding to the non-zero element in a row of the above exponent matrix, {a1,a2,…,a…} i} represents the value corresponding to the non-zero element in another row of the aforementioned exponent matrix, {a1,a2,…,a…} i} and {b1,b2,…,b j} satisfies (for ease of description, the following can be referred to as characteristic one): when i < j, {a1,a2,…,a...} i}yes A proper subset of; when i = j, {a1, a2, ..., a i}yes The non-identical permutations of, where, represents rounding down, mod represents modulo, c is an integer, d is a non-zero real number, Zc is the promotion factor, and Zc is a positive integer.

[0131] Here, the values ​​corresponding to the non-zero elements can refer to the values ​​corresponding to the non-zero elements in the base matrix (or base graph, BG), or shift values ​​corresponding to the non-zero elements in the base matrix. For example, the value corresponding to the zero element in the exponent matrix is ​​-1, and the value corresponding to the non-zero element in the base matrix is ​​the value in the exponent matrix that is not equal to -1. In this scenario, {b1,b2,…,b j} represents the value corresponding to the non-zero element in a row of the above exponent matrix, which can be replaced with {b1,b2,…,b j} represents the values ​​in a row of the above exponent matrix that are not equal to -1; {a1,a2,…,a i} represents the value corresponding to the non-zero element in another row of the aforementioned exponent matrix, which can be replaced with {a1,a2,…,a...} i} represents the value in the other row of the above exponential matrix that is not equal to -1.

[0132] It should be noted that i represents {a1, a2, ..., a...} i The number of elements in {b1, b2, ..., b} does not represent the position / column index of each element in the exponent matrix. Similarly, j represents {b1, b2, ..., b}. jThe number of elements in the exponent matrix does not represent the position / column index of each element in the exponent matrix. For example, all elements in a row of the above exponent matrix are represented as {x1,x2,x3,x4,x5}, where x2 and x4 take values ​​of -1, that is, the values ​​corresponding to the zero element are x2 and x4, and {a1,a2,…,a5}. i} is the set of elements after removing the values ​​corresponding to zero elements (such as -1) from {x1,x2,x3,x4,x5}. Therefore, i = 3, for example, a1 = x1, a2 = x3, a3 = x5.

[0133] In one possible implementation, {b1,b2,…,b j} represents the values ​​corresponding to non-zero elements in all elements (or columns) of a row of the aforementioned exponent matrix, {a1, a2, ..., a...} i} represents the values ​​corresponding to non-zero elements in all elements (or columns) of the other row of the aforementioned exponential matrix, {a1, a2, ..., a i} and {b1,b2,…,b j The above two rows in the exponent matrix satisfy feature one. In this way, they have fixed structural features, which helps ensure the stability of LDPC code performance. Furthermore, the above method improves the flexibility of parity-check matrix construction, thus adapting to more communication environments and needs.

[0134] In another possible implementation, {b1,b2,…,b j} represents the values ​​corresponding to non-zero elements in a subset of elements (or columns) of a row of the aforementioned exponential matrix, {a1, a2, ..., a i} represents the values ​​corresponding to non-zero elements in a subset of elements (or columns) of the other row of the aforementioned exponential matrix. For example, suppose the number of columns in the exponential matrix is ​​denoted as n, {b1, b2, ..., b...} j} represents the values ​​corresponding to the non-zero elements in column L of a row of the aforementioned exponent matrix, {a1,a2,…,a…} i} represents the value corresponding to the non-zero element in column L of the other row of the aforementioned exponent matrix, where L is greater than or equal to 2, L is less than n, and L is an integer. In this implementation, the two rows and L columns of the exponent matrix have fixed structural characteristics, which helps to ensure the stability of LDPC code performance.

[0135] It should be understood that the position / column index of column L in one of the above rows in the above index matrix is ​​the same as the position / column index of column L in the above index matrix in the other row. That is, if one row selects certain columns, the other row must also select the same columns.

[0136] Alternatively, the above L columns can be adjacent, for example, {b1,b2,…,b j} represents the values ​​corresponding to the non-zero elements in the first, second, third, and fourth columns of the above index matrix, {a1,a2,…,a…} i} represents the values ​​corresponding to the non-zero elements in the first, second, third, and fourth columns of the other row of the aforementioned exponential matrix.

[0137] Alternatively, the L columns mentioned above can also be partially adjacent or completely non-adjacent, for example, {b1,b2,…,b j} represents the values ​​corresponding to the non-zero elements in the first, third, and fourth columns of the above index matrix, where {a1, a2, ..., a i} represents the values ​​corresponding to the non-zero elements in the first, third, and fourth columns of the other row of the aforementioned exponent matrix. For example, {b1,b2,…,b j} represents the values ​​corresponding to the non-zero elements in the first, third, and fifth columns of the above index matrix, {a1,a2,…,a…} i} represents the values ​​corresponding to the non-zero elements in the first, third, and fifth columns of the other row of the aforementioned exponential matrix, which will not be listed here individually.

[0138] The term "mod" above represents modulo, for example, X mod Y represents the remainder when X is divided by Y, where X and Y are integers. Specifically, when X = Y, X mod Y is 0. The range of values ​​for X mod Y depends on the sign of Y. When Y is a positive integer, the range of values ​​for X mod Y is an integer between 0 and Y-1; when Y is a negative integer, the range of values ​​for X mod Y is an integer between Y+1 and 0. In this application, Zc is the promotion factor, and Zc is a positive integer; therefore, The values ​​of {a1, a2, ..., a} are all integers between 0 and (Zc-1), thus ensuring that {a1, a2, ..., a} are all integers. i} is an integer between 0 and (Zc-1).

[0139] The above {a1,a2,…,a i}yes A proper subset of a is defined as {a1, a2, ..., a...} i} contained in But {a1,a2,…,a i} does not equal For example, if the values ​​corresponding to the non-zero elements in one row of the above exponent matrix are x1 = 1, x3 = 30, x4 = 25, and the values ​​corresponding to the non-zero elements in the other row of the above exponent matrix are y1 and y2, then y1 and y2 can be y1 = 1, y2 = 30, or y1 = 1, y2 = 25, or y1 = 30, y2 = 25. It should be understood that the values ​​corresponding to the non-zero elements in the other row are merely examples and should not constitute any limitation on this application. In one possible implementation, the order of the values ​​corresponding to the non-zero elements in the other row is not limited; for example, y1 = 30, y2 = 1, or y1 = 25, y2 = 1, or y1 = 25, y2 = 30.

[0140] The above {a1,a2,…,a i}yes A non-identical permutation refers to {a1, a2, ..., a...} i}and It contains the same elements, but at least two elements differ in order / position. The above {a1, a2, ..., a...} i}yes The non-identical permutations of can be represented as Where k∈{1,2,…,i}, there exists at least one k such that π(k)≠k, such as π(1)≠1. For example, the values ​​corresponding to the non-zero elements in one row of the above exponential matrix are: x1=1, x3=30, x4=25. The values ​​corresponding to the non-zero elements in the other row of the above exponential matrix are y1, y3, and y5 (that is, the number of values ​​corresponding to the non-zero elements in these two rows is equal). Then the values ​​corresponding to the non-zero elements in this other row can be y1=1, y3=25, y5=30, or y1=25, y3=30, y5=1, or y1=30, y3=1, y5=25, etc., which will not be listed here.

[0141] Optionally, when i > j, {b1, b2, ..., b j}yes A proper subset of , for a detailed explanation, please refer to the description when i < j. , which will not be elaborated here.

[0142] In one possible design, d = 1, {a1, a2, ..., a i} and {b1,b2,…,b j} satisfies: when i < j, {a1, a2, ..., a i} is {(-b1+c)modZc,(-b2+c)modZc,…,(-b j The proper subset of {a1, a2, ..., a} when i = j. i} is {(-b1+c)modZc,(-b2+c)modZc,…,(-b j Non-identical permutations of +c)modZc}.

[0143] For example, d = 1, c = 3, {a1, a2, ..., a i} and {b1,b2,…,b j} satisfies: when i < j, {a1, a2, ..., a i} is {(-b1+3)mod Zc,(-b2+3)mod Zc,…,(-b j +3)mod Zc} is a proper subset of {a1,a2,…,a}; when i=j, {a1,a2,…,a} i} is {(-b1+3)mod Zc,(-b2+3)mod Zc,…,(-b j The non-identical permutation of +3)mod Zc}.

[0144] Another example, d = 1, c = 0, {a1, a2, ..., a i} and {b1,b2,…,b j} satisfies: when i < j, {a1, a2, ..., a i} is {(-b1)mod Zc,(-b2)mod Zc,…,(-b j The proper subset of {a1, a2, ..., a} mod Zc}; when i = j, {a1, a2, ..., a} i} is {(-b1)mod Zc,(-b2)mod Zc,…,(-b j Non-identical permutations of )modZc}.

[0145] In one possible design, when i = j, {a1, a2, ..., a i} and {b1,b2,…,b j}satisfy: Where π(k) = k + (e mod L), k ∈ {1, 2, ..., i}, e is a positive integer, L is greater than or equal to 2, and L is less than or equal to the number of columns of the above exponential matrix, and L is an integer.

[0146] For example, when i = j, For example, when e = 3 and L = 5, and i = j, In other words, Shifting to the right cyclically 3 times, we get {a1, a2, ..., a i}

[0147] It should be understood that the above non-identical permutation π(k) = k + (emodL) is merely an example and should not constitute any limitation on this application.

[0148] In one possible design, d = 1, and when i = j, {a1, a2, ..., a i} and {b1,b2,…,b j} Satisfies: a k = (-b π(k) +c)modZc, where π(k)=k+(emodL), k∈{1,2,…,i}, e is a positive integer, L is greater than or equal to 2, and L is less than or equal to the number of columns of the above exponential matrix, and L is an integer.

[0149] One example is d=1, c=3, when i=j, {a1,a2,…,a i} and {b1,b2,…,b j} Satisfies: a k = (-b π(k) +3)mod Zc, where π(k)=k+(emodL). Another example is d=1, c=0, when i=j, {a1,a2,…,a i} and {b1,b2,…,b j} Satisfies: a k = (-b π(k) )mod Zc, where π(k)=k+(emodL).

[0150] The following uses an exponential matrix Taking this as an example, we will explain in detail the improvement of the exponent matrix.

[0151] One possible implementation is that the values ​​corresponding to the non-zero elements in all columns of a row of the aforementioned exponential matrix A satisfy characteristic one, as do the values ​​corresponding to the non-zero elements in all columns of another row of the aforementioned exponential matrix A. An example is that the values ​​corresponding to the non-zero elements in the first row of the aforementioned exponential matrix A satisfy characteristic one, as do the values ​​corresponding to the non-zero elements in the second row of the aforementioned exponential matrix A. For example, the values ​​corresponding to the non-zero elements in the first row are {x}. 1,1 ,x 1,2 ,x 1,4 ,x 1,6 In the second row, the value corresponding to the non-zero element is {x}. 2,1 ,x 2,3 ,x 2,4}, then {x 2,1 ,x 2,3 ,x 2,4} and {x 1,1 ,x 1,2 ,x 1,4 ,x1,6} satisfies: {x 2,1 ,x 2,3 ,x 2,4}yes A proper subset of . When d = 1, {x 2,1 ,x 2,3 ,x 2,4} and {x 1,1 ,x 1,2 ,x 1,4 ,x 1,6} satisfies: {x 2,1 ,x 2,3 ,x 2,4} is {(-x 1,1 +c)mod Zc,(-x 1,2 +c)modZc,(-x 1,4 +c)mod Zc,(-x 1,6 The proper subset of {x} is {x + c) mod Zc}. For example, the set of all elements in the first row whose non-zero elements correspond to the value {x}. 1,1 ,x 1,2 ,x 1,4 ,x 1,6 In the second row, the value corresponding to the non-zero element is {x}. 2,1 ,x 2,3 ,x 2,4 ,x 2,7}, then {x 2,1 ,x 2,3 ,x 2,4 ,x 2,7} and {x 1,1 ,x 1,2 ,x 1,4 ,x 1,6} satisfies: {x 2,1 ,x 2,3 ,x 2,4 ,x 2,4}yes Non-identical permutations. When d = 1, {x 2,1 ,x 2,3 ,x 2,4 ,x 2,7} and {x 1,1 ,x 1,2 ,x 1,4 ,x 1,6} satisfies: {x 2,1 ,x 2,3 ,x 2,4 ,x 2,4} is {(-x 1,1 +c)mod Zc,(-x 1,2 +c)modZc,(-x 1,4+c)mod Zc,(-x 1,6 The non-identical permutation of {x +c)mod Zc}. A more general rule is that, assuming all elements in the first row are values ​​corresponding to non-zero elements, and all elements in the second row are values ​​corresponding to non-zero elements, then {x} 1,1 ,x 1,2 ,…,x 1,n}yes Non-identical permutations. When d = 1, {x 1,1 ,x 1,2 ,…,x 1,n} is {(-x 1,1 +c)modZc,(-x 1,2 +c)mod Zc,…,(-x 1,n Non-identical permutations of Zc} +c)mod Zc}.

[0152] Another example is that the values ​​corresponding to the non-zero elements in a subset of elements in the first row of the aforementioned exponential matrix A satisfy characteristic one, as do the values ​​corresponding to the non-zero elements in a subset of elements in the second row of the aforementioned exponential matrix A. For example, if the first, second, third, and fourth columns of the aforementioned first and second rows are selected respectively, {x 1,1 ,x 1,2 ,x 1,3 ,x 1,4 The value corresponding to the non-zero element in} is {x} 1,1 ,x 1,2 ,x 1,3}, {x 2,1 ,x 2,2 ,x 2,3 ,x 2,4 The value corresponding to the non-zero element in} is {x} 2,1 ,x 2,3}, then {x 1,1 ,x 1,2 ,x 1,3} and {x 2,1 ,x 2,3} satisfies: {x 2,1 ,x 2,3}yes A proper subset of . When d = 1, {x 2,1 ,x 2,3} is {(-x 1,1 +c)mod Zc,(-x 1,2 +c)modZc,(-x 1,3 +c)mod Zc} is a proper subset. For example, if the first and second rows above select the first, second, third, and fourth columns respectively, {x 1,1 ,x 1,2 ,x 1,3 ,x 1,4The value corresponding to the non-zero element in} is {x} 1,1 ,x 1,2 ,x 1,3}, {x 2,1 ,x 2,2 ,x 2,3 ,x 2,4 The value corresponding to the non-zero element in} is {x} 2,1 ,x 2,3 ,x 2,4}, then {x 1,1 ,x 1,2 ,x 1,3} and {x 2,1 ,x 2,3 ,x 2,4} satisfies: {x 2,1 ,x 2,3 ,x 2,4}yes Non-identical permutations. When d = 1, {x 2,1 ,x 2,3 ,x 2,4} is {(-x 1,1 +c)mod Zc,(-x 1,2 +c)modZc,(-x 1,3 Non-identical permutations of Zc} +c)mod Zc}.

[0153] The above example uses the first and second rows of the aforementioned exponential matrix A as examples, but this should not constitute any limitation on this application. Any two rows in the exponential matrix can satisfy feature one. For example, when m is even, such as m = 2s, the aforementioned exponential matrix A can be divided into at most s groups, each group including two rows, and the elements of the two rows in each group satisfy feature one; when m is odd, such as m = 2s + 1, the aforementioned exponential matrix A can be divided into at most s groups, each group including two rows, and the elements of the two rows in each group satisfy feature one.

[0154] One possible design is that, when m is even, the above exponent matrix can be divided into at most s groups, and these s groups can be: The c corresponding to the s groups are denoted as c1, c2, ..., c. s In this context, the corresponding values ​​of c in the s groups can be the same, completely different, or partially the same; this application does not impose any restrictions on this. Furthermore, the non-identical permutations corresponding to the s groups are denoted as π1, π2, ..., π s , where π r (k)=k+(e rGiven a matrix A (mod L), r∈{1,2,...,s}, k∈{1,2,…,i}, the non-identical permutations corresponding to each group can be the same, completely different, or partially the same; this application does not impose any limitations on this. For example, assuming that all elements in the above exponent matrix A are values ​​corresponding to non-zero elements, then...

[0155] {x 1,1 ,x 1,2 ,…,x 1,n} and {x s+1,1 ,x s+1,2 ,…,x s+1,n}satisfy: or, Where 1≤i≤n;

[0156] {x 2,1 ,x 2,2 ,…,x 2,n} and {x s+2,1 ,x s+2,2 ,…,x s+2,n}satisfy: or, Where 1≤i≤n;

[0157] …;

[0158] {x s,1 ,x s,2 ,…,x s,n} and {x 2s,1 ,x 2s,2 ,…,x 2s,n}satisfy: or, Where 1≤i≤n.

[0159] It should be understood that when m is even, the above division of s groups is merely an example and should not constitute any limitation on this application. For example, the above s groups can be: For example, the above group s can also be: They will not be listed one by one here.

[0160] An example of the above exponential matrix A is as follows. This exponential matrix A has 4 rows, 17 columns, and a promotion factor of 289. The elements in the first row of exponential matrix A are {221,223,122,199,33,183,182,178,74,7,108,150,188,61,248,127,81}, and the elements in the second row are {243,2,126,103,84,140,91,94,263,270,11,254,199,173,171,181,81}. c1 = 0, c2 = 3, d = 1. The elements in the first and third rows are grouped together, and the elements in the second and fourth rows are grouped together. Therefore, the elements in the third row {x 3,1 ,x 3,2 ,…,x 3,17} is {(-x 1,1 mod289,(-x 1,2 mod289,…,(-x 1,17 The non-identical permutation of )mod289}, the fourth row element {x 4,1 ,x 4,2 ,…,x 4,17} is {(-x 2,1 +3)mod289,(-x 2,2 +3)mod289,…,(-x 2,17 The non-identical permutations of +3)mod289}, for example, the third row of elements is {162,208,68,66,167,90,256,106,107,111,215,282,181,139,101,228,41}, and the fourth row of elements is {111,211,49,290,166,189,208,152,201,198,29,22,281,38,93,119,121}.

[0161] It should be noted that, in this application, the above-mentioned index matrix A satisfies feature one, that at least two rows, at least two columns, or at least two rows and at least two columns in the above-mentioned index matrix A can be interchanged, such as the first row and the second row can be interchanged. Multiple index matrices can be obtained by interchanged at least two rows and / or at least two columns in the index matrix A. The terminal device can encode information bits based on one of the multiple index matrices to obtain encoded bits. For example, if the third row contains elements {162,208,68,66,167,90,256,106,107,111,215,282,181,139,101,228,41} and the fourth row contains elements {111,211,49,290,166,189,208,152,201,198,29,22,281,38,93,119,121}, the terminal device can swap the positions of the first and second rows, and the third and fourth rows. Based on the resulting exponent matrix, the information bits are encoded to obtain the encoded bits.

[0162] When m is odd, the above exponent matrix can be divided into at most s groups, and these s groups can be: That is, the elements from the 2nd row to the 2s+1th row of the exponent matrix are divided into s groups, and the c corresponding to these s groups are denoted as c1, c2, ..., c. s In this context, the corresponding values ​​of c in the s groups can be the same, completely different, or partially the same; this application does not impose any restrictions on this. Furthermore, the non-identical permutations corresponding to the s groups are denoted as π1, π2, ..., π s , where, where, π r (k)=k+(e r Given a matrix A (mod L), r∈{1,2,...,s}, k∈{1,2,…,i}, the non-identical permutations corresponding to each group can be the same, completely different, or partially the same; this application does not impose any limitations on this. For example, assuming that all elements in the above exponent matrix A are values ​​corresponding to non-zero elements, then...

[0163] {x 2,1 ,x 2,2 ,…,x 2,n} and {x s+2,1 ,x s+2,2 ,…,x s+2,n}satisfy:

[0164] or,

[0165] Where 1≤i≤n;

[0166] {x 3,1 ,x 3,2,…,x 3,n} and {x s+3,1 ,x s+3,2 ,…,x s+3,n}satisfy:

[0167] or,

[0168] Where 1≤i≤n;

[0169] …;

[0170] {x s+1,1 ,x s+1,2 ,…,x s+1,n} and {x 2s+1,1 ,x 2s+1,2 ,…,x 2s+1,n}satisfy:

[0171] or,

[0172] Where 1≤i≤n.

[0173] It should be understood that when m is odd, the above division of s groups is merely an example and should not constitute any limitation on this application. For example, the above s groups can be: That is, divide the elements from the first row to the second row of the exponent matrix into s groups. For example, the above s groups can also be: They will not be listed one by one here.

[0174] An example of the above exponential matrix A is as follows. This exponential matrix A has 4 rows, 17 columns, and a promotion factor of 289. The elements in the first row are {221,223,122,199,33,183,182,178,74,7,108,150,188,61,248,127,81}, and the elements in the second row are {243,2,126,103,84,140,91,94,263,270,11,254,199,173,171,181,81}. c1 = 3, d = 1. The elements in the second and third rows are grouped together, so the elements in the third row {x 3,1 ,x 3,2 ,…,x 3,17} is {(-x 2,1 +3)mod289,(-x 2,2 +3)mod289,…,(-x 2,17The non-identical permutation of +3)mod289}, for example, the third row of elements is {111,211,49,290,166,189,208,152,201,198,29,22,281,38,93,119,121}.

[0175] In one possible implementation, {g1,g2,…,g v} represents the values ​​corresponding to non-zero elements in a column of the aforementioned exponent matrix, {h1,h2,…,h w} represents the values ​​corresponding to non-zero elements in another column of the aforementioned exponent matrix, {h1,h2,…,h w} and {g1,g2,…,g v} satisfies (for ease of description, the following content is only characteristic two): when w < v, {h1,h2,…,h w}yes A proper subset of; when w = v, {h1, h2, ..., h w}yes Non-identical permutations; among which, q represents rounding down, mod represents modulo, q is an integer, p is a non-zero real number, Zc is the promotion factor, and Zc is a positive integer.

[0176] It should be understood that in this application, one possible implementation is that two rows in the exponent matrix have characteristic one; another possible implementation is that two columns in the exponent matrix have characteristic two; yet another possible implementation is that two rows in the exponent matrix have characteristic one, and two columns in the exponent matrix have characteristic two. The above-mentioned characteristic two will be explained in detail below.

[0177] Where w represents {h1,h2,…,h w The number of elements in {g1, g2, ..., g} does not represent the position / row index of each element in the exponent matrix. Similarly, v represents {g1, g2, ..., g}. v The number of elements in the exponent matrix does not represent the position / row index of each element in the exponent matrix. For example, if all the elements in a column of the above exponent matrix are represented as {y1,y2,y3,y4,y5}, where the value corresponding to the non-zero element is {y1,y3,y5}, then h1 = y1, h2 = y3, h3 = y5, that is, w = 3.

[0178] In one possible implementation, {h1,h2,…,h w} represents the values ​​corresponding to non-zero elements in all elements (or rows) of a column of the aforementioned exponent matrix, {g1, g2, ..., g v} represents the values ​​corresponding to non-zero elements in all elements (or rows) of the other column of the aforementioned exponent matrix, {h1,h2,…,h…} w} and {g1,g2,…,g v This satisfies feature two. In this way, the two columns in the exponent matrix have fixed structural characteristics, which helps ensure the stability of LDPC code performance. Furthermore, using this method improves the flexibility of parity-check matrix construction, thus adapting to more communication environments and needs.

[0179] In another possible implementation, {h1,h2,…,h w} represents the values ​​corresponding to non-zero elements in a partial column (or row) of the aforementioned exponential matrix, {g1, g2, ..., g v} represents the values ​​corresponding to non-zero elements in a subset of elements (or rows) of the other column of the aforementioned exponent matrix. For example, suppose the number of rows in the exponent matrix is ​​denoted as m, and {h1, h2, ..., h...} w} represents the values ​​corresponding to the non-zero elements in the K rows of a column of the aforementioned exponent matrix, {g1,g2,…,g v} represents the value corresponding to the non-zero element in the Kth row of the other column of the aforementioned exponent matrix, where K is greater than or equal to 2, K is less than m, and K is an integer. In this implementation, the aforementioned two columns and K rows of the exponent matrix have fixed structural characteristics, which helps to ensure the stability of LDPC code performance.

[0180] It should be understood that the position / row index of row K in one of the above columns in the above index matrix is ​​the same as the position / row index of row K in the above index matrix of the other column. That is, if one column selects certain rows, the other column must also select the same rows.

[0181] Optionally, the above K rows can be adjacent, for example, {h1,h2,…,h...} w} represents the values ​​corresponding to the non-zero elements in the first, second, third, and fourth rows of the above exponent matrix, {g1,g2,…,g v} represents the values ​​corresponding to the non-zero elements in the first, second, third, and fourth rows of the other column of the aforementioned exponential matrix.

[0182] Alternatively, the above K rows can also be partially adjacent or completely non-adjacent, for example, {h1,h2,…,h...} w} represents the values ​​corresponding to the non-zero elements in the first, third, and fourth rows of the above exponent matrix, {g1,g2,…,g v} represents the values ​​corresponding to the non-zero elements in the first, third, and fourth rows of the other column of the aforementioned exponent matrix. For example, {h1,h2,…,h...} w} represents the values ​​corresponding to the non-zero elements in the first, third, and fifth rows of the above exponent matrix, {g1,g2,…,g v} represents the values ​​corresponding to non-zero elements in the first, third, and fifth rows of the other column of the aforementioned exponential matrix, which will not be listed here.

[0183] The above "mod" refers to modulo operation; a detailed explanation can be found above and will not be elaborated upon here. In this application, Zc is the promotion factor, and Zc is a positive integer; therefore, The values ​​of are all integers between 0 and (Zc-1), thus ensuring that {h1, h2, ..., h w} is an integer between 0 and (Zc-1).

[0184] The above {h1,h2,…,h w}yes A proper subset of is {h1, h2, ..., h...} w} contained in But {h1,h2,…,h w} does not equal For example, in the above exponent matrix, the values ​​corresponding to the non-zero elements in one column are l1 = 1, l3 = 30, l4 = 25, and the values ​​corresponding to the non-zero elements in the other column are m1 and m2. Then m1 and m2 can be m1 = 1, m2 = 30, or m1 = 1, m2 = 25, or m1 = 30, m2 = 25. It should be understood that the values ​​corresponding to the non-zero elements in the other column are merely examples and should not constitute any limitation on this application.

[0185] The above {h1,h2,…,h w}yes A non-identical permutation is defined as {h1, h2, ..., h...} w}and It contains the same elements, but at least two elements differ in order / position. The above {h1,h2,…,h... w}yes A non-identical permutation of can be represented as h t =(-g λ(t) +q)mod Zc, where there exists at least one t∈{1,2,…,w} such that λ(t)≠t, such as λ(1)≠1. For example, the values ​​corresponding to the non-zero elements in one column of the above exponential matrix are: l1=1, l3=30, l4=25, and the values ​​corresponding to the non-zero elements in another column of the above exponential matrix are m1, m2, and m3 (that is, the number of values ​​corresponding to the non-zero elements in these two columns is equal). Then the values ​​corresponding to the non-zero elements in this other column can be m1=1, m2=25, m3=30, or m1=25, m2=30, m3=1, or m1=30, m2=1, m3=25, etc., which will not be listed here.

[0186] Optionally, when w > v, {g1,g2,…,g v}yes The proper subset of .

[0187] In one possible design, p = 1, {h1, h2, ..., h w} and {g1,g2,…,g v} satisfies: when w < v, {h1,h2,…,h w} is {(-g1+q)modZc,(-g2+q)modZc,…,(-g v The proper subset of {h1,h2,…,h} mod Zc} when w = v; w} is {(-g1+q)modZc,(-g2+q)modZc,…,(-g v Non-identical permutations of Zc} +q)mod Zc}.

[0188] For example, p = 1, q = 3, {h1, h2, ..., h w} and {g1,g2,…,g v} satisfies: when w < v, {h1,h2,…,h w} is {(-g1+3)mod Zc,(-g2+3)mod Zc,…,(-g v +3)mod Zc} is a proper subset of {h1,h2,…,h}; when w=v, {h1,h2,…,h} w} is {(-g1+3)mod Zc,(-g2+3)mod Zc,…,(-g v The non-identical permutation of +3)mod Zc}.

[0189] Another example, d = 1, c = 0, {h1, h2, ..., h w} and {g1,g2,…,g v} satisfies: when w < v, {h1,h2,…,h w} is {(-g1)mod Zc,(-g2)mod Zc,…,(-g v The proper subset of {h1,h2,…,h} mod Zc}; when w = v, {h1,h2,…,h} w} is {(-g1)mod Zc,(-g2)mod Zc,…,(-g v Non-identical permutations of )mod Zc}.

[0190] In one possible design, when w = v, {h1,h2,…,h w} and {g1,g2,…,g v}satisfy: Where λ(t) = t + (umod K), t ∈ {1, 2, ..., w}, u is a positive integer, K is greater than or equal to 2 and less than or equal to the number of rows of the exponential matrix, and K is an integer.

[0191] For example, when w = v, For example, when u = 3 and K = 5, and w = v, In other words, {(-g1)modZc,(-g2)modZc,…,(-g w )modZc} is shifted to the right cyclically 3 times to obtain {h1,h2,…,h w}

[0192] It should be understood that the above non-identical permutation λ(t) = t + (umod K) is merely an example and should not constitute any limitation on this application.

[0193] In one possible design, p = 1, and when w = v, {h1, h2, ..., h w} and {g1,g2,…,g v} satisfies: h t =(-g λ(t) +q)mod Zc, where λ(t)=t+(umod K), t∈{1,2,…,w}, u is a positive integer, K is greater than or equal to 2, and K is less than or equal to the number of rows of the above exponential matrix, and K is an integer.

[0194] One example is p = 1, q = 3, when w = v, {h1, h2, ..., h w} and {g1,g2,…,g v} satisfies: h t =(-g λ(t) +3)modZc, where λ(t)=t+(umod K). Another example is, p=1, q=0, when w=v, {h1,h2,…,h w} and {g1,g2,…,g v} satisfies: h t =(-g λ(t) )mod Zc, where λ(t)=t+(umod K).

[0195] The following uses the above index matrix Taking the above feature two as an example, we will explain it in detail.

[0196] One possible implementation is that the values ​​corresponding to the non-zero elements in all rows of one column of the aforementioned exponential matrix A satisfy characteristic two with the values ​​corresponding to the non-zero elements in all rows of another column of the aforementioned exponential matrix A. An example is that the values ​​corresponding to the non-zero elements in all elements of the first column of the aforementioned exponential matrix A satisfy characteristic two with the values ​​corresponding to the non-zero elements in all elements of the second column of the aforementioned exponential matrix A. For example, the values ​​corresponding to the non-zero elements in all elements of the first column are {x}. 1,1 ,x 2,1 ,x 4,1 ,x 6,1}, the value corresponding to the non-zero element in the second column is {x}. 2,2 ,x 3,2 ,x 4,2}, then {x 2,2 ,x 3,2 ,x 4,2} and {x 1,1 ,x 2,1 ,x 4,1 ,x 6,1} satisfies: {x 2,2 ,x 3,2 ,x 4,2}yes A proper subset of . When p = 1, {x 2,2 ,x 3,2 ,x 4,2} is {(-x 1,1 +q)modZc,(-x 2,1 +q)modZc,(-x 4,1 +q)modZc,(-x 6,1 A proper subset of {x}. For example, in the first column, the value corresponding to the non-zero element is {x}. 1,1 ,x 2,1 ,x 4,1 ,x 6,1}, the value corresponding to the non-zero element in the second column is {x}. 2,2 ,x 3,2 ,x 4,2 ,x 7,2}, then {x 2,2 ,x 3,2 ,x 4,2 ,x 7,2} and {x 1,1 ,x 2,1 ,x 4,1 ,x 6,1} satisfies: {x 2,2 ,x 3,2 ,x 4,2 ,x 7,2}yes Non-identical permutations. When p = 1, {x2,2 ,x 3,2 ,x 4,2 ,x 7,2} is {(-x 1,1 +q)modZc,(-x 2,1 +q)modZc,(-x 4,1 +q)modZc,(-x 6,1 The proper subset of {x +q)modZc}. A more general rule is that, assuming all elements in the first column are values ​​corresponding to non-zero elements, and all elements in the second column are values ​​corresponding to non-zero elements, then {x} is a proper subset of {x}. 1,1 ,x 2,1 ,…,x m,1}yes Non-identical permutations. When p = 1, {x 1,1 ,x 2,1 ,…,x m,1} is {(-x 1,2 +q)modZc,(-x 2,2 +q)modZc,…,(-x m,2 Non-identical permutations of +q)modZc}.

[0197] Another example is that the values ​​corresponding to the non-zero elements in a subset of elements in the first column of the aforementioned exponential matrix A satisfy characteristic two with the values ​​corresponding to the non-zero elements in a subset of elements in the second column of the aforementioned exponential matrix A. For example, if the first and second columns are selected from the first, second, third, and fourth rows respectively, {x 1,1 ,x 2,1 ,x 3,1 ,x 4,1 The value corresponding to the non-zero element in} is {x} 1,1 ,x 2,1 ,x 3,1}, {x 1,2 ,x 2,2 ,x 3,2 ,x 4,2 The value corresponding to the non-zero element in} is {x} 1,2 ,x 3,2}, then {x 1,1 ,x 2,1 ,x 3,1} and {x 1,2 ,x 3,2} satisfies: {x 1,2 ,x 3,2}yes A proper subset of . When p = 1, {x 1,2 ,x 3,2} is {(-x 1,1 +q)mod Zc,(-x 2,1 +q)modZc,(-x3,1 The proper subset of {x}. For example, if the first and second columns above are selected from the first, second, third, and fourth rows respectively, then {x} 1,1 ,x 2,1 ,x 3,1 ,x 4,1 The value corresponding to the non-zero element in} is {x} 1,1 ,x 2,1 ,x 3,1}, {x 1,2 ,x 2,2 ,x 3,2 ,x 4,2 The value corresponding to the non-zero element in} is {x} 1,2 ,x 3,2 ,x 4,2}, then {x 1,1 ,x 2,1 ,x 3,1} and {x 1,2 ,x 3,2 ,x 4,2} satisfies: {x 1,2 ,x 3,2 ,x 4,2}yes Non-identical permutations. When p = 1, {x 1,2 ,x 3,2 ,x 4,2} is {(-x 1,1 +q)modZc,(-x 2,1 +q)modZc,(-x 3,1 Non-identical permutations of +q)modZc}.

[0198] The above example uses the first and second columns of the aforementioned exponential matrix A as examples, but this should not constitute any limitation on this application. Any two columns in the exponential matrix can satisfy feature two. For example, when n is even, such as n = 2s, the aforementioned exponential matrix A can be divided into at most s groups, each group including two columns, and the elements of the two columns in each group satisfy feature two; when n is odd, such as n = 2s + 1, the aforementioned exponential matrix A can be divided into at most s groups, each group including two columns, and the elements of the two columns in each group satisfy feature two.

[0199] One possible design is that when n is even, the above exponent matrix can be divided into at most s groups, and these s groups can be: The q corresponding to the s groups are denoted as q1, q2, ..., q. s In this context, the q corresponding to the s groups can be the same, completely different, or partially the same; this application does not impose any restrictions on this. Furthermore, the non-identical permutations corresponding to the s groups are denoted as λ1, λ2, ..., λ s , where λf (t)=t+(u f Given a matrix A (mod K), f∈{1,2,...,s}, t∈{1,2,...,i}, the non-identical permutations corresponding to each group can be the same, completely different, or partially the same; this application does not impose any limitations on this. For example, assuming that all elements in the above exponent matrix A are values ​​corresponding to non-zero elements, then...

[0200] {x 1,1 ,x 2,1 ,…,x m,1} and {x 1,s+1 ,x 2,s+1 ,…,x m,s+1}satisfy:

[0201] or,

[0202] Where 1≤i≤n;

[0203] {x 1,2 ,x 2,2 ,…,x m,2} and {x 1,s+2 ,x 2,s+2 ,…,x m,s+2}satisfy:

[0204] or,

[0205] Where 1≤i≤n;

[0206] …;

[0207] {x 1,s ,x 2,s ,…,x m,s} and {x 1,2s ,x 2,2s ,…,x m,2s}satisfy:

[0208] or,

[0209] Where 1≤i≤n.

[0210] It should be understood that when n is even, the above division of s groups is merely an example and should not constitute any limitation on this application. For example, the above s groups can be: For example, the above group s can also be: They will not be listed one by one here.

[0211] It should be noted that, in this application, the aforementioned exponent matrix A satisfies feature two: at least two rows, at least two columns, or at least two rows and at least two columns in exponent matrix A can be interchanged. For example, the first and second columns can be interchanged. By interchanged, multiple exponent matrices can be obtained. The terminal device can encode information bits based on one of these multiple exponent matrices to obtain encoded bits. For example, the terminal device can interchange the positions of the first and second columns and encode information bits based on the resulting exponent matrix to obtain encoded bits.

[0212] When n is odd, the above exponent matrix can be divided into at most s groups, and these s groups can be: That is, the elements from the 2nd column to the 2s+1th column in the exponent matrix are divided into s groups, and the q corresponding to these s groups are denoted as q1, q2, ..., q. s In this context, the q corresponding to the s groups can be the same, completely different, or partially the same; this application does not impose any restrictions on this. Furthermore, the non-identical permutations corresponding to the s groups are denoted as λ1, λ2, ..., λ s , where λ f (t)=t+(u f Given a matrix A (mod K), f∈{1,2,...,s}, t∈{1,2,…,i}, the non-identical permutations corresponding to each group can be the same, completely different, or partially the same; this application does not impose any restrictions on this. Assuming that all elements in the above exponent matrix A are non-zero values, then...

[0213] {x 1,2 ,x 2,2 ,…,x m,2} and {x 1,s+2 ,x 2,s+2 ,…,x m,s+2}satisfy:

[0214] or,

[0215] Where 1≤i≤n;

[0216] {x 1,3 ,x 2,3 ,…,x m,3} and {x 1,s+3 ,x 2,s+3 ,…,x m,s+3}satisfy:

[0217] or,

[0218] Where 1≤i≤n;

[0219] …;

[0220] {x 1,s+1 ,x 2,s+1 ,…,x m,s+1} and {x 1,2s+1 ,x 2,2s+1 ,…,x m,2s+1}satisfy:

[0221] or,

[0222] Where 1≤i≤n.

[0223] It should be understood that when n is odd, the above division of s groups is merely an example and should not constitute any limitation on this application. For example, the above s groups could also be: That is, divide the elements in the first to second-to-last columns of the exponent matrix into s groups. For example, the above s groups can also be: They will not be listed one by one here.

[0224] Figure 6 This is a possible exemplary block diagram of the communication device provided in the embodiments of this application. For example... Figure 6 As shown, the communication device 600 may include modules or units for implementing the methods described in the embodiments above. In one possible design, the communication device 600 includes a processing unit 602 and a communication unit 603. Optionally, the communication device 600 may further include a storage unit 601 for storing device program code and / or data.

[0225] The communication device 600 can be a terminal as described in the above embodiments, or a communication module in a terminal, or a circuit or chip in a terminal that is responsible for communication functions. For example, it can be an access network device or a communication module in an access network device, or a circuit or chip in an access network device that is responsible for communication functions.

[0226] For example, in one embodiment, the processing unit 602 is used to: perform LDPC encoding on the information bits based on the exponent matrix to obtain the encoded bits, {b1,b2,…,b j} represents the values ​​corresponding to non-zero elements in a row of the exponent matrix, {a1, a2, ..., a...} i} represents the values ​​corresponding to non-zero elements in another row of the exponent matrix, {a1,a2,…,a…} i} and {b1,b2,…,b j} satisfies: when i < j, {a1, a2, ..., a i}yes A proper subset of; when i = j, {a1, a2, ..., a i}yes The non-identical permutations of, where, The expression indicates rounding down, mod indicates modulo, c is an integer, d is a non-zero real number, Zc is a boost factor, and Zc is a positive integer; the communication unit 603 is used to output the encoded bits.

[0227] In one possible design, d = 1, {a1, a2, ..., a i} and {b1,b2,…,b j} satisfies: when i < j, {a1, a2, ..., a i} is {(-b1+c)mod Zc,(-b2+c)mod Zc,…,(-b j +c)mod Zc} is a proper subset of {a1,a2,…,a}; when i=j, {a1,a2,…,a} i} is {(-b1+c)mod Zc,(-b2+c)mod Zc,…,(-b j Non-identical permutations of Zc} +c)mod Zc}.

[0228] In one possible design, when i = j, {a1, a2, ..., a i} and {b1,b2,…,b j}satisfy: Where π(k) = k + (e mod L), k ∈ {1, 2, ..., i}, e is a positive integer, L is greater than or equal to 2, and L is less than or equal to the number of columns of the exponential matrix, and L is an integer.

[0229] In one possible design, {g1,g2,…,g v} represents the values ​​corresponding to non-zero elements in a column of the exponent matrix, {h1,h2,…,h... w} represents the values ​​corresponding to non-zero elements in another column of the exponent matrix, {h1,h2,…,h w} and {g1,g2,…,g v} satisfies: when w < v, {h1,h2,…,h w}yes A proper subset of; when w = v, {h1, h2, ..., h w}yes Non-identical permutations; among which, q represents rounding down, mod represents modulo, q is an integer, and p is a non-zero real number.

[0230] In one possible design, p = 1, {h1, h2, ..., h w} and {g1,g2,…,g v} satisfies: when w < v, {h1,h2,…,h w} is {(-g1+q)modZc,(-g2+q)modZc,…,(-g v The proper subset of {h1,h2,…,h} mod Zc} when w = v; w} is {(-g1+q)modZc,(-g2+q)modZc,…,(-g v Non-identical permutations of Zc} +q)mod Zc}.

[0231] In one possible design, when w = v, {h1,h2,…,h w} and {g1,g2,…,g v}satisfy: Where λ(t) = t + (umod K), t ∈ {1, 2, ..., w}, u is a positive integer, K is greater than or equal to 2 and less than or equal to the number of rows of the exponential matrix, and K is an integer.

[0232] In one possible design, when the communication device 600 is a terminal or a communication module within a terminal, the function of the processing unit 602 can be implemented by one or more processors. Specifically, the processor may include a modem chip, or a system-on-a-chip (SoC) chip or a SIP chip containing a modem core. The function of the communication unit 603 can be implemented by transceiver circuitry.

[0233] In one possible design, when the communication device 600 is a circuit or chip in a terminal responsible for communication functions, such as a modem chip or a system-on-a-chip (SoC) or SIP chip containing a modem core, the function of the processing unit 602 can be implemented by a circuit system in the aforementioned chip that includes one or more processors or processor cores. The function of the communication unit 603 can be implemented by an interface circuit or data transceiver circuit on the aforementioned chip.

[0234] In one possible design, when the communication device 600 is a terminal or a computing module within a terminal, the functionality of the processing unit 602 can be implemented by one or more processors. Specifically, the processor may include a GPU, or a system-on-a-chip (SoC) or SIP chip containing a GPU. Alternatively, the processor may include an AI processor, or a SoC or SIP chip containing an AI processor. Or, the processor may include an ASIC, or a SoC or SIP chip containing an ASIC. The functionality of the communication unit 603 can be implemented by transceiver circuitry.

[0235] In one possible design, when the communication device 600 is a circuit or chip in a terminal responsible for computing functions, such as a GPU or a system-on-a-chip (SoC) or SIP chip containing a GPU, an AI processor or a SoC or SIP chip containing an AI processor, or an ASIC or a SoC or SIP chip containing an ASIC, the function of the processing unit 602 can be implemented by a circuit system in the aforementioned chip that includes one or more processors or processor cores. The function of the communication unit 603 can be implemented by interface circuitry or data transceiver circuitry on the aforementioned chip.

[0236] The communication device 600 can also be the access network device in the above embodiments, or the communication module in the access network device, or the circuit or chip in the access network device responsible for communication functions.

[0237] For example, in one embodiment, the communication unit 603 is used to: input the bit to be decoded; the processing unit 602 is used to: perform LDPC decoding on the bit to be decoded based on the exponent matrix to obtain the information bit, {b1,b2,…,b j} represents the value corresponding to the non-zero element in a row of the above exponent matrix, {a1,a2,…,a…} i} represents the value corresponding to the non-zero element in another row of the aforementioned exponent matrix, {a1,a2,…,a…} i} and {b1,b2,…,b j} satisfies: when i < j, {a1, a2, ..., a i}yes A proper subset of; when i = j, {a1, a2, ..., a i}yes The non-identical permutations of, where, represents floor function, mod represents modulo, c is an integer, d is a non-zero real number, Zc is the boost factor, and Zc is a positive integer; output the above encoded bits.

[0238] In one possible design, d = 1, {a1, a2, ..., a i} and {b1,b2,…,b j} satisfies: when i < j, {a1, a2, ..., a i} is {(-b1+c)mod Zc,(-b2+c)mod Zc,…,(-b j +c)mod Zc} is a proper subset of {a1,a2,…,a}; when i=j, {a1,a2,…,a} i} is {(-b1+c)mod Zc,(-b2+c)mod Zc,…,(-b j Non-identical permutations of Zc} +c)mod Zc}.

[0239] In one possible design, when i = j, {a1, a2, ..., a i} and {b1,b2,…,b j}satisfy: Where π(k) = k + (e mod L), k ∈ {1, 2, ..., i}, e is a positive integer, L is greater than or equal to 2, and L is less than or equal to the number of columns of the exponential matrix, and L is an integer.

[0240] In one possible design, {g1,g2,…,g v} represents the values ​​corresponding to non-zero elements in a column of the exponent matrix, {h1,h2,…,h... w} represents the values ​​corresponding to non-zero elements in another column of the exponent matrix, {h1,h2,…,h w} and {g1,g2,…,g v} satisfies: when w < v, {h1,h2,…,h w}yes A proper subset of; when w = v, {h1, h2, ..., h w}yes Non-identical permutations; among which, q represents rounding down, mod represents modulo, q is an integer, and p is a non-zero real number.

[0241] In one possible design, p = 1, {h1, h2, ..., h w} and {g1,g2,…,g v} satisfies: when w < v, {h1,h2,…,h w} is {(-g1+q)modZc,(-g2+q)modZc,…,(-g v The proper subset of {h1,h2,…,h} mod Zc} when w = v; w} is {(-g1+q)modZc,(-g2+q)modZc,…,(-g v Non-identical permutations of Zc} +q)mod Zc}.

[0242] In one possible design, when w = v, {h1,h2,…,h w} and {g1,g2,…,g v}satisfy: Where λ(t) = t + (umod K), t ∈ {1, 2, ..., w}, u is a positive integer, K is greater than or equal to 2 and less than or equal to the number of rows of the exponential matrix, and K is an integer.

[0243] The communication device 600 can be a terminal as described in the above embodiments, or a communication module in a terminal, or a circuit or chip in a terminal that is responsible for communication functions. For example, it can be an access network device or a communication module in an access network device, or a circuit or chip in an access network device that is responsible for communication functions.

[0244] For example, in another embodiment, the processing unit 602 is configured to: perform LDPC encoding on the information bits based on the exponent matrix to obtain the encoded bits, {h1,h2,…,h...} w} represents the values ​​corresponding to non-zero elements in a column of the aforementioned exponent matrix, {g1,g2,…,g v} represents the values ​​corresponding to non-zero elements in another column of the aforementioned exponent matrix, {h1,h2,…,h w} and {g1,g2,…,g v} satisfies: when w < v, {h1,h2,…,h w}yes A proper subset of; when w = v, {h1, h2, ..., h w}yes Non-identical permutations; among which, q represents rounding down, mod represents modulo operation, q is an integer, p is a non-zero real number, Zc is the boost factor, and Zc is a positive integer; the communication unit 603 is used to output the above encoded bits.

[0245] In one possible design, p = 1, {h1, h2, ..., h w} and {g1,g2,…,g v} satisfies: when w < v, {h1,h2,…,h w} is {(-g1+q)modZc,(-g2+q)modZc,…,(-g v The proper subset of {h1,h2,…,h} mod Zc} when w = v; w} is {(-g1+q)modZc,(-g2+q)modZc,…,(-g v Non-identical permutations of Zc} +q)mod Zc}.

[0246] In one possible design, when w = v, {h1,h2,…,h w} and {g1,g2,…,g v}satisfy: Where λ(t) = t + (umod K), t ∈ {1, 2, ..., w}, u is a positive integer, K is greater than or equal to 2, and K is less than or equal to the number of rows of the above exponential matrix, and K is an integer.

[0247] In one possible design, p = 1, and when w = v, {h1, h2, ..., hw} and {g1,g2,…,g v} satisfies: h t =(-g λ(t) +q)mod Zc, where λ(t)=t+(umod K), t∈{1,2,…,w}, u is a positive integer, K is greater than or equal to 2, and K is less than or equal to the number of rows of the above exponential matrix, and K is an integer.

[0248] The communication device 600 can also be the access network device in the above embodiments, or the communication module in the access network device, or the circuit or chip in the access network device responsible for communication functions.

[0249] For example, in another embodiment, the communication unit 603 is used to: input the bits to be decoded; the processing unit 602 is used to: perform LDPC decoding on the bits to be decoded based on the exponent matrix to obtain information bits, {h1,h2,…,h... w} represents the values ​​corresponding to non-zero elements in a column of the aforementioned exponent matrix, {g1,g2,…,g v} represents the values ​​corresponding to non-zero elements in another column of the aforementioned exponent matrix, {h1,h2,…,h w} and {g1,g2,…,g v} satisfies: when w < v, {h1,h2,…,h w}yes A proper subset of; when w = v, {h1, h2, ..., h w}yes Non-identical permutations; among which, q represents rounding down, mod represents modulo operation, q is an integer, p is a non-zero real number, Zc is the promotion factor, and Zc is a positive integer.

[0250] In one possible design, p = 1, {h1, h2, ..., h w} and {g1,g2,…,g v} satisfies: when w < v, {h1,h2,…,h w} is {(-g1+q)modZc,(-g2+q)modZc,…,(-g v The proper subset of {h1,h2,…,h} mod Zc} when w = v; w} is {(-g1+q)modZc,(-g2+q)modZc,…,(-g v Non-identical permutations of Zc} +q)mod Zc}.

[0251] In one possible design, when w = v, {h1,h2,…,h w} and {g1,g2,…,g v}satisfy: Where λ(t) = t + (umod K), t ∈ {1, 2, ..., w}, u is a positive integer, K is greater than or equal to 2, and K is less than or equal to the number of rows of the above exponential matrix, and K is an integer.

[0252] In one possible design, p = 1, and when w = v, {h1, h2, ..., h w} and {g1,g2,…,g v} satisfies: h t =(-g λ(t) +q)mod Zc, where λ(t)=t+(umod K), t∈{1,2,…,w}, u is a positive integer, K is greater than or equal to 2, and K is less than or equal to the number of rows of the above exponential matrix, and K is an integer.

[0253] It is understood that the division of units in the above-described device is merely a logical functional division. One function can correspond to one functional unit, or two or more functions can be integrated into one functional unit. In actual implementation, all or some units can be integrated onto a single physical entity, or distributed across different physical entities. Furthermore, the aforementioned functional units can be implemented in hardware, software, or a combination of both. Whether a function is executed in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for specific applications, but such implementations should not be considered beyond the scope of this application.

[0254] In one example, the functional unit in any of the above devices may be one or more integrated circuits configured to implement the above methods, such as: one or more ASICs, or one or more central processing units (CPUs), one or more microcontroller units (MCUs), one or more digital signal processors (DSPs), or one or more field-programmable gate arrays (FPGAs), or a combination of at least two of these integrated circuit forms.

[0255] In one example, storage unit 601 may include random access memory, flash memory, read-only memory, programmable read-only memory or electrically erasable programmable memory and / or registers, etc.

[0256] Figure 7 This is a schematic diagram of the structure of a terminal 700 provided in an embodiment of this application. The terminal 700 can correspond to... Figure 1 The terminal shown is used to implement the operations of the terminal in the above embodiments. Figure 7 As shown, the terminal includes: one or more antennas 710, a radio frequency processing system 720, and a processor system 730.

[0257] In the downlink or sidelink direction, the RF processing system 720 receives RF signals through the antenna 710 and sends the RF-processed signals to the processor system 730 for further processing. In the uplink or sidelink direction, the processor system 730 processes the terminal-side information and sends it to the RF processing system 720, which then processes the signal and transmits it through the antenna 710.

[0258] In one example, the radio frequency (RF) processing system 720 serves as the communication interface for external communication of the terminal and may include an RF front end (RFFE) 721 and an RF transceiver 722. The RFFE 721 is primarily used for one or more processing operations, such as shaping, passband selection, or gain adjustment, on the RF signals received by the antenna or those to be transmitted through the antenna. It may include one or more components such as RF switches, duplexers, filters, power amplifiers, antenna tuners, and low-noise amplifiers. The RFFE 721 can be a circuit system composed of multiple discrete components or integrated into one or more chips. The RF transceiver 722 processes the RF signals received by the RFFE into baseband / IF signals for further processing by the processor system 730, and processes the baseband / IF signals provided by the processor system 730 into RF signals for transmission to the RFFE 721. The baseband / IF signals transmitted between the RF transceiver 722 and the processor system 730 can be digital or analog signals. The RF transceiver 722 can be implemented by one or more chips, which are commonly referred to as RF ICs.

[0259] In one example, the processor system 730 may include one or more processors for processing signals and executing one or more communication protocols. Optionally, the processor system 730 may also include a memory 736. In one example, the one or more processors include at least one baseband processor 731 (also known as a modem processor). The memory 736 is used to store data and / or computer program instructions. Optionally, the processor system 730 may also include one or more application processors 732 for implementing processing of the terminal operating system and application layer. Optionally, the processor system 730 may also include one or more of a voice subsystem 733, a multimedia subsystem 734, or an interface circuit 735. The voice subsystem 733 is used to process voice signals, the multimedia subsystem 734 is used to handle multimedia-related operations, such as video encoding / decoding, image processing, etc., and the interface circuit 735 is used to enable communication with other terminal components, such as a display 740, an input device 750, a memory 760, etc. The above-mentioned components in the processor system 730 can communicate with each other via a bus or communication interface circuit.

[0260] In one example, the processor system 730 can be packaged as a single processor chip, such as a SoC chip or a SIP chip. In another example, the processor system 730 can be a system composed of multiple chips; for example, the baseband processor 731 can be packaged as a single chip, or packaged with part or all of the circuitry of the radio frequency processing system into a single chip.

[0261] In one example, memory 736 can be on-chip memory, i.e., located on the processor system 730 chip. In another example, memory 760 can be off-chip memory, i.e. located outside the processor system 730 chip.

[0262] In one example, the baseband processor 731 may include one or more processor cores 7311 and interface circuitry 7314. The one or more processor cores 7311 are used to process signals and execute one or more communication protocols. Optionally, the baseband processor 731 may also include a memory 7312 for storing at least a portion of the corresponding computer program instructions and / or data. In one example, the one or more processor cores 7311 implement the relevant operations (such as executing...) in the above method embodiments by executing the computer program instructions stored in the memory 7312. Figure 5 The operations of steps 510 and 520 in the embodiment, or the execution of... Figure 5(The operations of steps 520 and 530 in the embodiments). In this disclosure, the memory 7312 is used to store corresponding computer program instructions and / or data. This can mean that the memory 7312 is used to store all corresponding computer program instructions and / or data for execution by the processor core 7311; or it can mean that the memory 7312 is used to store a portion of the corresponding computer program instructions and / or data, which includes the computer program instructions and / or data that currently need to be executed by the processor core 7311. The memory 7312 can store different portions of computer program instructions and / or data multiple times for execution by the processor core 7311 to implement the relevant operations in the above method embodiments. The interface circuit 7314 serves as a communication interface for communication with other components, such as transmitting signals with the radio frequency processing system 720, communicating with other subsystems and related components of the processor system 730 via a bus, such as transmitting data control signals with the application processor 732, and transmitting data or computer program instructions with the memory 736 or memory 760. Optionally, in order to reduce the load on the processor core, a baseband signal processing circuit 7313 can be set to perform at least some baseband signal processing, including one or more of signal demodulation, modulation, encoding or decoding.

[0263] In one example, the communication device provided in this application may be a terminal 700, a communication module including a processor system 730 and a radio frequency system 720, or a baseband processor 731.

[0264] The processor, processor system, application processor, baseband processor, processor circuit, or processor core mentioned above can be collectively referred to as a processor. The processor may include one or more of the following: CPU, digital signal processor (DSP), microprocessor unit (MPU), microcontroller unit (MCU), graphics processing unit (GPU), field programmable gate array (FPGA), artificial intelligence processor (AI processor), or neural processing unit (NPU).

[0265] The aforementioned memory may include one or more of the following storage media: random access memory (RAM), static random access memory (SRAM), dynamic random access memory (DRAM), phase-change memory (PCM), resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), cache, register, read-only memory (ROM), flash memory, erasable programmable read-only memory (EPROM), hard disk, etc. In one example, computer program instructions for executing the above embodiments may be stored on non-volatile memory, such as at least a portion of the aforementioned memory 760 (e.g., one or more of ROM, flash memory, EPROM, or hard disk). When the terminal is running, the corresponding computer program instructions may be partially or wholly loaded onto a memory with a faster transfer speed than the processor, such as at least a portion of memory 736 and / or memory 7312 (e.g., one or more of RAM, SRAM, DRAM, PCM, RERAM, MRAM, FRAM, cache, or register), for the processor to execute in order to implement the steps in the above method embodiments.

[0266] In one example, the RF transceiver 722 and the RF front-end 721 can also be packaged in a single chip. In another example, the RF transceiver 722, the RF front-end 721, and the baseband processor 731 can also be packaged in a single chip.

[0267] The terms "system" and "network" in this application embodiment are used interchangeably. "At least one" refers to one or more, and "multiple" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, "at least one of A, B, or C" includes A, B, C, AB, AC, BC, or ABC; "at least one of A, B, and C" can also be understood as including A, B, C, AB, AC, BC, or ABC. Furthermore, unless otherwise specified, the ordinal numbers such as "first" and "second" mentioned in this application embodiment are used to distinguish multiple objects and are not used to limit the order, sequence, priority, or importance of multiple objects.

[0268] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, optical storage, etc.) containing computer-usable program code.

[0269] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0270] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0271] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

Claims

1. An encoding method, characterized in that, include: Based on the exponent matrix, low-density parity-check (LDPC) encoding is performed on the information bits to obtain the encoded bits, {b1,b2,…,b...}. j } represents the value corresponding to the non-zero element in a row of the exponent matrix, {a1,a2,…,a…} i } represents the value corresponding to the non-zero element in another row of the exponent matrix, {a1,a2,…,a…} i } and {b1,b2,…,b j }satisfy: When i < j, {a1,a2,…,a i }yes A proper subset of; when i = j, {a1, a2, ..., a i }yes The non-identical permutations of, where, represents floor function, mod represents modulo, c is an integer, d is a non-zero real number, Zc is the promotion factor, and Zc is a positive integer; Output the encoded bits.

2. The method as described in claim 1, characterized in that, d = 1, {a1, a2, ..., a i } and {b1,b2,…,b j }satisfy: When i < j, {a1,a2,…,a i } is {(-b1+c)modZc,(-b2+c)modZc,…,(-b j A proper subset of {+c)modZc}; When i = j, {a1, a2, ..., a i } is {(-b1+c)modZc,(-b2+c)modZc,…,(-b j Non-identical permutations of +c)modZc}.

3. The method as described in claim 1 or 2, characterized in that, When i = j, {a1, a2, ..., a i } and {b1,b2,…,b j }satisfy: Where π(k) = k + (e mod L), k ∈ {1, 2, ..., i}, e is a positive integer, L is greater than or equal to 2, and L is less than or equal to the number of columns of the exponential matrix, and L is an integer.

4. The method according to any one of claims 1 to 3, characterized in that, {g1,g2,…,g v } represents the values ​​corresponding to non-zero elements in a column of the exponent matrix, {h1,h2,…,h... w } represents the values ​​corresponding to non-zero elements in another column of the exponent matrix, {h1,h2,…,h w } and {g1,g2,…,g v }satisfy: When w < v, {h1,h2,…,h w }yes A proper subset of; when w = v, {h1, h2, ..., h w }yes Non-identical permutations; among which, q represents rounding down, mod represents modulo, q is an integer, and p is a non-zero real number.

5. The method as described in claim 4, characterized in that, p = 1, {h1,h2,…,h} w } and {g1,g2,…,g v }satisfy: When w < v, {h1,h2,…,h w } is {(-g1+q)modZc,(-g2+q)modZc,…,(-g v A proper subset of} +q)modZc}; When w = v, {h1,h2,…,h w } is {(-g1+q)modZc,(-g2+q)modZc,…,(-g v Non-identical permutations of +q)modZc}.

6. The method as described in claim 4 or 5, characterized in that, When w = v, {h1,h2,…,h w } and {g1,g2,…,g v }satisfy: Where λ(t) = t + (umod K), t ∈ {1, 2, ..., w}, u is a positive integer, K is greater than or equal to 2, and K is less than or equal to the number of rows of the exponential matrix, and K is an integer.

7. An encoding method, characterized in that, include: Based on the exponential matrix, low-density parity-check (LDPC) encoding is performed on the information bits to obtain the encoded bits, {h1,h2,…,h...}. w } represents the values ​​corresponding to non-zero elements in a column of the exponent matrix, {g1, g2, ..., g v } represents the values ​​corresponding to non-zero elements in another column of the exponent matrix, {h1,h2,…,h w } and {g1,g2,…,g v }satisfy: When w < v, {h1,h2,…,h w }yes A proper subset of; when w = v, {h1, h2, ..., h w }yes Non-identical permutations; among which, q represents rounding down, p represents modulo operation, q is an integer, p is a non-zero real number, Zc is the promotion factor, and Zc is a positive integer. Output the encoded bits.

8. The method as described in claim 7, characterized in that, p = 1, {h1,h2,…,h} w } and {g1,g2,…,g v }satisfy: When w < v, {h1,h2,…,h w } is {(-g1+q)modZc,(-g2+q)modZc,…,(-g v A proper subset of Zc}; When w = v, {h1,h2,…,h w } is {(-g1+q)modZc,(-g2+q)modZc,…,(-g v Non-identical permutations of Zc} +q)mod Zc}.

9. The method as described in claim 7 or 8, characterized in that, When w = v, {h1,h2,…,h w } and {g1,g2,…,g v }satisfy: Where λ(t) = t + (umod K), t ∈ {1, 2, ..., w}, u is a positive integer, K is greater than or equal to 2, and K is less than or equal to the number of rows of the exponential matrix, and K is an integer.

10. A communication device, characterized in that, It includes a unit for performing the method as described in any one of claims 1 to 6, or includes a unit for performing the method as described in any one of claims 7 to 9.

11. A computer-readable storage medium, characterized in that, Used to store computer programs or instructions, which, when run, cause the method as described in any one of claims 1 to 6 to be implemented, or cause the method as described in any one of claims 7 to 9 to be implemented.

12. A computer program product, the computer program product comprising instructions, characterized in that, When the instructions are executed on a computer, they cause the method as described in any one of claims 1 to 6, or the method as described in any one of claims 7 to 9, to be implemented.

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