A coding method, device and system

Abstract

The application relates to the communication technical field, and discloses a coding and decoding method, device and system. The method comprises the following steps: determining a first shift value matrix according to a base matrix of a first low density parity check (LDPC) code and a first lifting factor, the first shift value matrix comprising a first block matrix and a second block matrix, the first block matrix comprising at least one row vector of the first shift value matrix, and the second block matrix comprising row vectors of the first shift value matrix except the at least one row vector; obtaining a second shift value matrix according to the first block matrix and the second block matrix; and performing LDPC encoding on first information according to the second shift value matrix to obtain second information, and outputting the second information. In this way, the decoding performance of the LDPC code can be improved while being compatible with the first LDPC code.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to a coding / decoding method, apparatus, and system. Background Technology

[0002] In the field of channel coding, low-density parity check (LDPC) codes are one of the most mature and widely used coding schemes. LDPC codes are a channel coding scheme that is very close to the Shannon limit, and have the characteristics of good performance and low complexity. LDPC codes were selected as the data channel coding method in the 5th generation (5G) standard protocol.

[0003] However, for future mobile communication networks, commercial applications such as extended reality (XR), mixed reality (MR), and immersive services are emerging, offering real-time high data rates. These emerging services place higher demands on the peak throughput and area efficiency of encoding and decoding, with peak rates even requiring terabits per second (Tbps), while simultaneously requiring further reductions in decoder power consumption. Although 5G LDPC codes have played a crucial role in 5G communication, they have limitations in meeting the high demands of these emerging services. Summary of the Invention

[0004] This application provides a coding and decoding method, apparatus, and system for expanding a new shift value matrix / check matrix based on the base matrix and a first lifting factor of a first LDPC code, and for coding and decoding based on the new shift value matrix / check matrix, thereby improving the performance of the LDPC code while maintaining compatibility with the first LDPC code.

[0005] In a first aspect, embodiments of this application provide an encoding method, which can be executed by a first communication device (or encoding device). Unless otherwise specified, the "first communication device" in this application can refer to a communication device (e.g., a network device, a terminal device, an encoding device, etc.), a component within that communication device (e.g., a processor, a chip, or a chip system, etc.), or a logic module or software capable of implementing all or part of the functions of the communication device. For example, in the method provided in the first aspect, the first communication device determines a first shift value matrix based on the base matrix of a first low-density parity-check (LDPC) code and a first boosting factor. The first shift value matrix includes a first block matrix and a second block matrix. The first block matrix includes at least one row vector of the first shift value matrix, and the second block matrix includes row vectors in the first shift value matrix other than the at least one row vector. A second shift value matrix is ​​obtained based on the first block matrix and the second block matrix. First information is LDPC encoded using the second shift value matrix to obtain second information, and the second information is output. The second shift value matrix satisfies:

[0006]

[0007] Where S represents the second shift value matrix, S local,i Let S be the first block matrix. global,i Based on the second block matrix, S is determined to contain S excluding S local,i and S global,i The remaining positions have no corresponding shift value, i = 0, 1, 2...t-1, where t is an integer greater than 1.

[0008] Using the above method, a first shift value matrix is ​​determined based on the base matrix and the first boosting factor of the first LDPC code. Then, a second shift value matrix is ​​determined based on the first block matrix and the second block matrix within the first shift value matrix. Encoding is then performed based on the second shift value matrix. For example, if the first LDPC code is a QC-LDPC code, such as a 5G LDPC code, since the 5G standard protocol already specifies the base matrix and boosting factor of the 5G LDPC code, this embodiment designs a new shift value matrix based on the existing base matrix and boosting factor of the 5G LDPC code. This improves the performance of the LDPC code while maintaining compatibility with the 5G LDPC code.

[0009] In one possible design, S global,i Determined based on the second block matrix, including: S global,i Determined based on t sub-block matrices in the second block matrix, and S global,0 To S global,t-1The i×K+1 to (i+1)×K rows include the t sub-block matrices; the sub-block matrix j in the t sub-block matrices includes the j×V+1 to (j+1)×V column vectors in the second block matrix, j=0,1,2……t-1, V=n / t, where n is the number of columns in the second block matrix.

[0010] In one possible design, S excluding S local,i and S global,i The remaining position takes a value of -1.

[0011] In one possible design, the second information is obtained by LDPC encoding the first information according to the second shift value matrix, including: determining the parity check matrix of the second LDPC code according to the second shift value matrix and the first boosting factor; and performing LDPC encoding on the first information to obtain the second information according to the parity check matrix of the second LDPC code; wherein the parity check matrix of the second LDPC code satisfies:

[0012]

[0013] Where H represents the parity check matrix of the second LDPC code, H local,i It is based on S loca,l i H obtained from the first enhancement factor global,i It is based on S global,i And the first enhancement factor obtained, H excluding H local,i and H global,i The remaining positions are all 0.

[0014] In one possible design, the method further includes: determining the base matrix and the first boosting factor of the first LDPC code based on the code length and / or target code rate of the first LDPC code, wherein the code length of the second LDPC code is t times the code length of the first LDPC code, and t is an integer greater than 1.

[0015] Secondly, embodiments of this application provide a decoding method, which can be executed by a second communication device (or decoding device). Unless otherwise specified, the "second communication device" in this application can refer to a communication device (e.g., a terminal device, network device, decoding device, etc.), a component within that communication device (e.g., a processor, chip, or chip system, etc.), or a logic module or software capable of implementing all or part of the functions of the communication device. For example, in the method provided in the second aspect, the second communication device determines a first shift value matrix based on the base matrix of a first low-density parity-check (LDPC) code and a first boosting factor. The first shift value matrix includes a first block matrix and a second block matrix. The first block matrix includes at least one row vector of the first shift value matrix, and the second block matrix includes row vectors in the first shift value matrix other than the at least one row vector. A second shift value matrix is ​​determined based on the first block matrix and the second block matrix. Third information is then LDPC decoded using the second shift value matrix to obtain first information. The second shift value matrix satisfies the following:

[0016]

[0017] Where S represents the second shift value matrix, S local,i Let S be the first block matrix. global,i Based on the second block matrix, S is determined to contain S excluding S local,i and S global,i The remaining positions have no corresponding shift value, i = 0, 1, 2...t-1, where t is an integer greater than 1.

[0018] Using the above method, a first shift value matrix is ​​determined based on the base matrix and the first boosting factor of the first LDPC code. Then, a second shift value matrix is ​​determined based on the first block matrix and the second block matrix within the first shift value matrix. Decoding is then performed based on the second shift value matrix. For example, if the first LDPC code is a QC-LDPC code, such as a 5G LDPC code, since the 5G standard protocol already specifies the base matrix and boosting factor of the 5G LDPC code, this embodiment designs a new shift value matrix based on the existing base matrix and boosting factor of the 5G LDPC code. This improves the performance of the LDPC code while maintaining compatibility with the 5G LDPC code.

[0019] In one possible design, S global,i Determined based on the second block matrix, including: S global,i Determined based on t sub-block matrices in the second block matrix, and S global,0 To S global,t-1The i×K+1 to (i+1)×K rows include the t sub-block matrices; the sub-block matrix j in the t sub-block matrices includes the j×V+1 to (j+1)×V column vectors in the second block matrix, j=0,1,2……t-1, V=n / t, where n is the number of columns in the second block matrix.

[0020] In one possible design, S excluding S local,i and S global,i The remaining position takes a value of -1.

[0021] In one possible design, the second information is obtained by LDPC encoding the first information according to the second shift value matrix, including: determining the parity check matrix of the second LDPC code according to the second shift value matrix and the first boosting factor; and performing LDPC encoding on the first information to obtain the second information according to the parity check matrix of the second LDPC code; wherein the parity check matrix of the second LDPC code satisfies:

[0022]

[0023] Where H represents the parity check matrix of the second LDPC code, H local,i It is based on S loca,l i H obtained from the first enhancement factor global,i It is based on S global,i And the first enhancement factor obtained, H excluding H local,i and H global,i The remaining positions are all 0.

[0024] In one possible design, the method further includes: determining the base matrix and the first boosting factor of the first LDPC code based on the code length and / or target code rate of the first LDPC code, wherein the code length of the second LDPC code is t times the code length of the first LDPC code, and t is an integer greater than 1.

[0025] Thirdly, embodiments of this application provide an encoding method, which can be executed by a first communication device (or encoding device). Unless otherwise specified, the "first communication device" in this application can refer to a communication device (e.g., a network device, a terminal device, an encoding device, etc.), a component within that communication device (e.g., a processor, a chip, or a chip system, etc.), or a logic module or software capable of implementing all or part of the functions of the communication device. For example, in the method provided in the first aspect, the first communication device determines a first shift value matrix based on the base matrix of a first low-density parity-check (LDPC) code and a first boosting factor. The first shift value matrix includes a first block matrix and a second block matrix. The first block matrix includes at least one row vector of the first shift value matrix, and the second block matrix includes row vectors in the first shift value matrix other than the at least one row vector. Based on the first block matrix and the second block matrix, a check matrix for a second LDPC code is determined. Based on the check matrix of the second LDPC code, first information is LDPC encoded to obtain second information, and the second information is output. The check matrix of the second LDPC code satisfies:

[0026]

[0027] Where H represents the parity check matrix of the second LDPC code, H local,i Based on the first block matrix and the first lifting factor, where i = 0, 1, 2, ..., t-1, H is determined. global Based on the second block matrix and the second lifting factor, where the second lifting factor is t times the first lifting factor, and t is an integer greater than 1, H is divided by H local,i and H global The remaining positions are all 0.

[0028] Using the above method, a first shift value matrix is ​​determined based on the base matrix and the first boosting factor of the first LDPC code. Then, a parity check matrix for the second LDPC code is determined based on the first block matrix and the second block matrix in the first shift value matrix. Encoding is then performed based on the parity check matrix of the second LDPC code. For example, if the first LDPC code is a QC-LDPC code, such as a 5G LDPC code, since the 5G standard protocol already specifies the base matrix and boosting factor for 5G LDPC codes, this embodiment designs a new parity check matrix based on the existing base matrix and boosting factor of 5G LDPC codes. This improves the performance of LDPC codes while maintaining compatibility with 5G LDPC codes.

[0029] In one possible design, H global Determined based on the second block matrix and the second lifting factor, including: H globalIt is obtained by performing column permutations on the first matrix, which is derived from the second block matrix and the second lifting factor.

[0030] In one possible design, H global It is obtained by performing column permutations on the first matrix, including: H global It is obtained by permuting the c-th column and the σ(c)-th column in the first matrix; where σ(c) and c satisfy:

[0031]

[0032] Where Z represents the first lifting factor, n represents the number of columns in the second block matrix, and c = 1, 2, 3, ..., t*n*Z, This indicates rounding down to the nearest integer.

[0033] In one possible design, the second boosting factor and the first boosting factor belong to the same set of boosting factors.

[0034] In one possible design, the method further includes: determining the base matrix and the first boosting factor of the first LDPC code based on the code length and / or target code rate of the first LDPC code, wherein the code length of the second LDPC code is t times the code length of the first LDPC code, and t is an integer greater than 1.

[0035] Fourthly, embodiments of this application provide a decoding method, which can be executed by a second communication device (or decoding device). Unless otherwise specified, the "second communication device" in this application can refer to a communication device (e.g., a terminal device, network device, decoding device, etc.), a component within that communication device (e.g., a processor, chip, or chip system, etc.), or a logic module or software capable of implementing all or part of the functions of the communication device. For example, in the method provided in the second aspect, the second communication device determines a first shift value matrix based on the base matrix of a first low-density parity-check (LDPC) code and a first boosting factor. The first shift value matrix includes a first block matrix and a second block matrix. The first block matrix includes at least one row vector of the first shift value matrix, and the second block matrix includes row vectors in the first shift value matrix other than the at least one row vector. Based on the first block matrix and the second block matrix, a parity-check matrix of a second LDPC code is determined. Based on the parity-check matrix of the second LDPC code, third information is LDPC decoded to obtain first information. The parity-check matrix of the second LDPC code satisfies:

[0036]

[0037] Where H represents the parity check matrix of the second LDPC code, Hlocal,i Based on the first block matrix and the first lifting factor, where i = 0, 1, 2, ..., t-1, H is determined. global Based on the second block matrix and the second lifting factor, where the second lifting factor is t times the first lifting factor, and t is an integer greater than 1, H is divided by H local,i and H global The remaining positions are all 0.

[0038] Using the above method, a first shift value matrix is ​​determined based on the base matrix and the first boosting factor of the first LDPC code. Then, a parity check matrix for the second LDPC code is determined based on the first block matrix and the second block matrix in the first shift value matrix. Decoding is then performed based on the parity check matrix of the second LDPC code. For example, if the first LDPC code is a QC-LDPC code, such as a 5G LDPC code, since the 5G standard protocol already specifies the base matrix and boosting factor of the 5G LDPC code, this embodiment designs a new parity check matrix based on the existing base matrix and boosting factor of the 5G LDPC code. This improves the performance of the LDPC code while maintaining compatibility with the 5G LDPC code.

[0039] In one possible design, H global Determined based on the second block matrix and the second lifting factor, including: H global It is obtained by performing column permutations on the first matrix, which is derived from the second block matrix and the second lifting factor.

[0040] In one possible design, H global It is obtained by performing column permutations on the first matrix, including: H global It is obtained by permuting the c-th column and the σ(c)-th column in the first matrix; where σ(c) and c satisfy:

[0041]

[0042] Where Z represents the first lifting factor, n represents the number of columns in the second block matrix, and c = 1, 2, 3, ..., t*n*Z, This indicates rounding down to the nearest integer.

[0043] In one possible design, the second boosting factor and the first boosting factor belong to the same set of boosting factors.

[0044] In one possible design, the method further includes: determining the base matrix and the first boosting factor of the first LDPC code based on the code length and / or target code rate of the first LDPC code, wherein the code length of the second LDPC code is t times the code length of the first LDPC code, and t is an integer greater than 1.

[0045] Fifthly, this application provides a communication device that enables the functions described in any one of the first to fourth aspects. For example, the communication device includes modules, units, or means corresponding to the operations described in any one of the first to fourth aspects. The functions, units, or means can be implemented by software, hardware, or hardware executing corresponding software.

[0046] In one possible design, the communication device includes a processing unit and a communication unit, wherein the communication unit can be used to transmit and receive signals to enable communication between the communication device and other devices; the processing unit can be used to perform some internal operations of the communication device. The functions performed by the processing unit and the communication unit can correspond to the operations involved in any of the first to fourth aspects described above.

[0047] In one possible design, the communication device includes a processor that can be coupled to a memory. The memory can store necessary computer programs or instructions for implementing the functions involved in any of the first to fourth aspects described above. The processor can execute the computer programs or instructions stored in the memory, such that, when executed, the communication device implements the methods in any of the possible designs or implementations of the first to fourth aspects described above.

[0048] In one possible design, the communication device includes a processor and a memory, the memory of which may store necessary computer programs or instructions for implementing the functions involved in any of the first to fourth aspects described above. The processor may execute the computer programs or instructions stored in the memory, and when the computer programs or instructions are executed, cause the communication device to implement the methods in any possible design or implementation of the first to fourth aspects described above.

[0049] In one possible design, the communication device includes a processor and an interface circuit, wherein the processor is configured to communicate with other devices via the interface circuit and to execute the methods in any of the possible designs or implementations of the first to fourth aspects described above.

[0050] Understandably, in the fifth aspect above, the processor can be implemented in hardware or software. When implemented in hardware, the processor can be a logic circuit, integrated circuit, etc.; when implemented in software, the processor can be a general-purpose processor that reads software code stored in memory. Furthermore, there can be one or more processors, and one or more memories. The memory can be integrated with the processor, or the memory and processor can be separate. In specific implementations, the memory can be integrated with the processor on the same chip, or it can be set on different chips. This application does not limit the type of memory or the arrangement of the memory and processor.

[0051] In a sixth aspect, this application provides a communication system, which may include a first communication device and a second communication device; wherein the first communication device is used to perform the method described in the first aspect, and the second communication device is used to perform the method described in the second aspect.

[0052] In a seventh aspect, this application provides a computer-readable storage medium storing a computer program (or computer-readable instructions) in which, when a computer reads and executes some or all of the computer-readable instructions, the method in any of the possible designs in the first to fourth aspects described above is executed.

[0053] For example, a computer-readable storage medium can be any available medium that a computer can access. This includes, but is not limited to, non-transient computer-readable media, random-access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), CD-ROM or other optical disc storage, magnetic disk storage media, or other magnetic storage devices, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer.

[0054] Eighthly, this application provides a computer program product that, when read and executed by a computer, causes any of the possible designs in the first to fourth aspects described above to be performed.

[0055] Ninthly, this application provides a chip (or chip system) including a processor coupled to a memory storing a computer program; the processor is configured to invoke part or all of the computer program in the memory, such that any of the possible designs in the first to fourth aspects described above are executed. Attached Figure Description

[0056] Figure 1 This is a schematic diagram of the architecture of a communication system applicable to the embodiments of this application;

[0057] Figure 2 This is a schematic diagram illustrating the information transmission process applicable to embodiments of this application;

[0058] Figure 3 This is the Tanner plot of the verification matrix H;

[0059] Figure 4 This is a schematic diagram of the matrix structure of the base map of 5G LDPC codes;

[0060] Figure 5 This is a schematic diagram of a 5G LDPC code;

[0061] Figure 6 Tanner plot for GC-LDPC;

[0062] Figure 7 This is a flowchart illustrating the method provided in Embodiment 1 of this application;

[0063] Figure 8A A schematic diagram of the first shift value matrix, the first block matrix, and the second block matrix provided in the embodiments of this application;

[0064] Figure 8B This is a schematic diagram of the third shift value matrix provided in an embodiment of this application;

[0065] Figure 8C This is a schematic diagram of the fourth shift value matrix provided in an embodiment of this application;

[0066] Figure 8D This is a schematic diagram of the second shift value matrix provided in an embodiment of this application;

[0067] Figure 9 This is a flowchart illustrating the method provided in Embodiment 2 of this application;

[0068] Figure 10 A schematic diagram illustrating the process of determining the second sub-verification matrix provided in an embodiment of this application;

[0069] Figure 11 A schematic diagram of simulation results provided for an embodiment of this application;

[0070] Figure 12 This is an exemplary block diagram of the apparatus involved in the embodiments of this application;

[0071] Figure 13 This is a schematic diagram of the structure of a communication device provided in an embodiment of this application. Detailed Implementation

[0072] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings. This application will focus on various aspects, embodiments, or features of a system that may include multiple devices, components, modules, etc. It should be understood and appreciated that each system may include additional devices, components, modules, etc., and / or may not include all the devices, components, modules, etc. discussed in conjunction with the accompanying drawings. Furthermore, combinations of these solutions may also be used.

[0073] In the embodiments of this application, words such as "exemplarily" and "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design scheme described as an "example" in this application should not be construed as being more preferred or advantageous than other embodiments or design schemes. Specifically, the use of the term "example" is intended to present concepts in a concrete manner. In the embodiments of this application, "of," "corresponding, relevant," and "corresponding" may sometimes be used interchangeably, and it should be noted that their intended meanings are consistent unless their distinction is emphasized.

[0074] The technical solutions of this application can be applied to various wireless communication systems, such as Universal Mobile Telecommunications System (UMTS), Wireless Local Area Network (WLAN), short-range wireless communication systems (such as sidelink, Wireless Fidelity (Wi-Fi), Bluetooth, etc.), wired networks, vehicle-to-everything (V2X) communication systems, device-to-device (D2D) communication systems, vehicle-to-everything (V2X) communication systems, 4th generation (4G) mobile communication systems (such as Long Term Evolution (LTE) systems), LTE Frequency Division Duplex (FDD) systems, LTE Time Division Duplex (TDD) systems, Worldwide Interoperability for Microwave Access (WiMAX) communication systems, 5G mobile communication systems (such as New Radio (NR) systems), Future Communications systems, or other similar communication systems, and are not limited thereto. The embodiments of this application use... Figure 1The communication system shown is used as an example for description. When the technical solutions of the embodiments of this application are applied to other communication systems, the devices, components, modules, etc. in the embodiments can be replaced with corresponding devices, components, modules in other communication systems without limitation.

[0075] Figure 1 This is a schematic diagram of the architecture of the communication system used in the embodiments of this application. Figure 1 As shown, the communication system includes an access network 100. Optionally, the communication system may also include a core network 200 and an Internet 300. The access network 100 may include at least one network device, such as... Figure 1 110a and 110b may also include at least one terminal device, such as Figure 1 The series consists of 120a-120j. Specifically, 110a is a base station, 110b is a micro-station, 120a, 120e, 120f, and 120j are mobile phones, 120b is a car, 120c is a fuel dispenser, 120d is a home access point (HAP) deployed indoors or outdoors, 120g is a laptop, 120h is a printer, and 120i is a drone. The same terminal device or network device can provide different functions in different application scenarios. For example... Figure 1 The mobile phones included are 120a, 120e, 120f, and 120j. Mobile phone 120a can access base station 110a, connect to car 120b, communicate directly with mobile phone 120e, and access HAP. Car 120b can access HAP and communicate directly with mobile phone 120a. Mobile phone 120f can connect to micro-station 110b, connect to laptop 120g, and connect to printer 120h. Mobile phone 120j can control drone 120i.

[0076] (1) Network equipment

[0077] A network device is a network-side device with wireless transceiver capabilities. A network device can be a device in a radio access network (RAN) that provides wireless communication capabilities to terminal devices; this is called RAN equipment. The RAN can be an access network within the 3rd Generation Partnership Project (3GPP), such as 4G, 5G, or future networks. The RAN can also be an open RAN (O-RAN or ORAN), a cloud radio access network (CRAN), or a communication network combining two or more of these.

[0078] RAN equipment can also be a base station, an evolved NodeB (eNodeB), a transmission reception point (TRP), a next-generation NodeB (gNB) in a 5G mobile communication system, a base station in a future mobile communication system, or an access node in a WiFi system, etc.

[0079] RAN equipment can also be modules or units that perform some of the functions of a base station. For example, it can be a central unit (CU), a distributed unit (DU), or a radio unit (RU). The CU performs the functions of the radio resource control (RRC) and PDCP protocols of the base station, and can also perform the functions of the service data adaptation protocol (SDAP). The CU can be further divided into a CU control plane (CP) (i.e., CU-CP) and a CU user plane (UP) (i.e., CU-UP). The DU performs the functions of the RLC and MA layers of the base station, and can also perform some or all of the physical layer functions. For specific descriptions of the above protocol layers, please refer to the relevant 3GPP technical specifications. CU and DU can be set up separately, or they can be included in the same network element, such as in a baseband unit (BBU). The RU can be included in radio frequency equipment or radio frequency units, such as in a remote radio unit (RRU), an active antenna unit (AAU), or a remote radiohead (RRH). In different systems, CU, DU, or RU may have different names, but those skilled in the art will understand their meaning. For example, in an ORAN system, CU can also be called O-CU (open CU), DU can also be called O-DU, and RU can also be called O-RU. Any of the CU (or CU-CP, CU-UP), DU, and RU units in this application can be implemented through software modules, hardware modules, or a combination of software and hardware modules. RA equipment can be a macro base station (such as...) Figure 1 110a in the text), can also be a micro base station or an indoor station (such as... Figure 1 In 110b), it can also be a relay node or a donor node, etc. The embodiments of this application do not limit the specific technology or device form used in the network equipment.

[0080] In the embodiments of this application, the functions of the network device can be executed by modules (such as chips) within the network device, or by a control subsystem that includes the functions of the network device. This control subsystem, which includes the functions of the network device, can be a control center in the aforementioned application scenarios such as smart grids, industrial control, intelligent transportation, and smart cities.

[0081] (2) Terminal equipment

[0082] A terminal device is a user-side device with wireless transceiver capabilities. Terminal devices can also be called terminals, user equipment (UE), mobile stations, mobile terminals, etc. Terminal devices can be widely used in various scenarios, such as device-to-device (D2D), vehicle-to-everything (V2X) communication, machine-type communication (MTC), the Internet of Things (IoT), virtual reality, augmented reality, industrial control, autonomous driving, telemedicine, smart grids, smart furniture, smart offices, smart wearables, intelligent transportation, and smart cities. Terminal devices can be mobile phones, tablets, computers with wireless transceiver capabilities, wearable devices, vehicles, drones, helicopters, airplanes, ships, robots, robotic arms, smart home devices, etc. In the embodiments of this application, the device used to implement the functions of the terminal device can be the terminal device itself, or it can be a device that supports the terminal device in implementing that function, such as a chip system or a combination of devices or components that can implement the functions of the terminal device. This device can be installed in the terminal device. The embodiments of this application do not limit the specific technology or specific device form used in the terminal device.

[0083] In this embodiment of the application, the functions of the terminal device can also be performed by modules (such as chips or modems) in the terminal device, or by a device containing the functions of the terminal device.

[0084] Network devices and terminal devices can be fixed in location or mobile. They can be deployed on land, including indoors or outdoors, handheld or vehicle-mounted; they can also be deployed on water; and they can also be deployed in the air on airplanes, balloons, and artificial satellites. The embodiments of this application do not limit the application scenarios of the network devices and terminal devices.

[0085] The roles of network devices and terminal devices can be relative, for example, Figure 1The helicopter or drone 120i can be configured as a mobile network device. For terminal devices 120j that access the wireless access network 100 via 120i, terminal device 120i is a network device; however, for network device 110a, 120i is a terminal device, meaning that 110a and 120i communicate via a wireless air interface protocol. Of course, 110a and 120i can also communicate via a network device-to-network device interface protocol; in this case, 120i is also a network device relative to 110a. Therefore, both network devices and terminal devices can be collectively referred to as communication devices. Figure 1 110a and 110b can be referred to as communication devices with network equipment functions. Figure 1 The 120a-120j in the text can be referred to as communication devices with terminal equipment functions.

[0086] Network devices and terminal devices, network devices and network devices, and terminal devices can communicate through licensed spectrum, unlicensed spectrum, or both simultaneously, without limitation.

[0087] The network architecture and business scenarios described in this application are intended to more clearly illustrate the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of network architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0088] The following is an explanation of the relevant terms used in the embodiments of this application. Unless otherwise specified, these explanations are provided to support the meaning of the relevant terms and to make the embodiments of this application easier to understand, and should not be regarded as a strict limitation of the relevant terms within the scope of protection claimed by this application.

[0089] (1) Channel coding and channel decoding

[0090] Figure 2 This is a schematic diagram of an information transmission process. For example... Figure 2 As shown, the transmitting end (i.e., the source) obtains the bit sequence to be encoded (i.e., the information bit sequence) through source coding, and then performs channel coding on the information bit sequence to obtain the encoded bit sequence. Correspondingly, after the receiving end (i.e., the sink) obtains the symbol sequence to be decoded, it performs channel decoding on the symbol sequence to be decoded to obtain the information bit sequence, and then performs source recovery on the information bit sequence to obtain useful information.

[0091] Since source coding does not consider interference resistance, if the bit sequence output from source coding is directly transmitted through the channel, noise interference in the channel will cause bit errors, reducing communication reliability. Therefore, channel coding, which encodes the bit sequence output from source coding again, can improve communication reliability. Channel decoding is the inverse process of channel coding.

[0092] There are various channel coding methods, such as LDPC codes. LDPC codes have been selected as the data channel coding method in the 5G standard protocol. LDPC codes are linear block codes with sparse parity-check matrices. They not only have good performance that approaches the Shannon limit, but also have low decoding complexity and flexible structure.

[0093] (2) LDPC code

[0094] In LDPC codes, the proportion of non-zero elements in the parity-check matrix is ​​extremely small; in other words, the row weight and column weight of the parity-check matrix are very small compared to the code length of the LDPC. For an LDPC code with k information bits and a code length of N, the dimension of its parity-check matrix H is (Nk)×N, and the corresponding codeword C can be defined by the parity-check matrix H as follows:

[0095] C={C|HC T =0, C∈{0,1} N}

[0096] In the parity-check matrix H, each row corresponds to a parity-check equation of the LDPC code, and Nk parity-check equations correspond to Nk parity-check nodes of the LDPC code; each column corresponds to a symbol of the LDPC code, and N symbols correspond to N variable nodes of the LDPC code. The non-zero elements h in the parity-check matrix H... i,j This indicates that the i-th check node and the j-th variable node are connected. The number of non-zero elements in each row of the check matrix represents the degree of the check node, and the number of non-zero elements in each column represents the degree of the variable node. The degree distribution of the check matrix refers to the distribution of the degrees of the variable nodes and check nodes throughout the code. The degree distribution has a crucial impact on the decoding performance of LDPC codes; a suitable degree distribution allows decoding algorithms (such as the belief propagation algorithm) to transmit messages more efficiently. If all check nodes have the same degree, and all variable nodes also have the same degree, the LDPC code corresponding to this matrix is ​​a regular code; otherwise, it is an irregular code. For example, the check matrix H of a regular LDPC code with a code length of 10 and a code rate of 1 / 2 can be as follows:

[0097]

[0098] Where v0, v1, ..., v9 represent 10 variable nodes, and c0, c1, ..., c4 represent 5 check nodes. The 5 check equations corresponding to the 5 check nodes are as follows:

[0099] c0: v0 + v1 + v2 + v6 = 0

[0100] c1: v0+v4+v5+v6=0

[0101] c2: v1+v4+v7+v8=0

[0102] c3: v2+v3+v6+v9=0

[0103] c4: v3+v7+v8+v9=0

[0104] LDPC codes can be represented using graphical models. Commonly used graphical models include Tanner graphs, factor graphs, and tree graphs, among which Tanner graphs offer the most concise and intuitive representation. The Tanner graph of the parity-check matrix H mentioned above can be represented as follows: Figure 3 As shown, Figure 3 The degree in the above-mentioned check matrix H corresponds to the definition of degree. The degree of a node can be defined as the number of edges connected to it.

[0105] (3) QC-LDPC code

[0106] Quasi-cyclic low-density parity check (QC-LDPC) codes are a type of structured LDPC codes. Due to the unique structure of their parity check matrix, encoding can be achieved using a simple feedback shift register, reducing the encoding complexity of LDPC codes.

[0107] QC-LDPC codes are represented using a base graph (BG). Taking a binary field as an example, the elements in the BG are either 0 or 1, and a 1 in the BG can be expanded to Z. C ×Z C The cyclic permutation matrix BG, where 0 can be extended to Z C ×Z C The zero matrix is ​​expanded to obtain the parity-check matrix. Where Z... C To increase the factor, Z C It can also be referred to as lifting size, lifting factor, expansion factor, expansion value, expansion coefficient, or lifting dimension, etc. Z C It can also be denoted as Z. The BG model of the QC-LDPC code is BG = (X, Y, F), where X corresponds to the variables, Y corresponds to the check equation, and F represents the edge relationships. The lifting factor is Z. C After QC expansion, we obtain the Tanner graph, which is a bipartite graph G = (V, C, E), where V are variable nodes, C are check nodes, and E are the edges between variable nodes and check nodes, corresponding to the number of columns in the check matrix N = |V| = Z. c|X|, the number of rows in the parity check matrix M = |C| = Z c The number of non-zero elements in the parity check matrix is ​​|E| = Z. c |F|.

[0108] BG can also be expressed in matrix form, denoted as the basis matrix H. BG Based on the basis matrix H BG The parity check matrix can be obtained by lifting and shifting, specifically: based on the basis matrix H BG And the enhancement factor Z c The shift value matrix S = [P] can be obtained. i,j The dimension of the shifted value matrix S is the same as that of the basis matrix H. BG Similarly, the element P in the shift value matrix i,j The basis matrix H BG The shifting value (SV) corresponding to the element in the i-th row and j-th column; then, based on the basis matrix and the lifting factor Z... c The shifted matrix S yields the parity check matrix. Specifically, this involves replacing each element in the basis matrix S with a Z. C ×Z C A square matrix, in which elements with a value of 0 are replaced with Z. C ×Z C A zero matrix, replacing each element with a Z-value that is 1. C ×Z C The identity matrix (to the right) is cyclically shifted by P i,j The matrix. With Z C The result of shifting to 4 with values ​​of -1, 0, 1, 2, and 3 is shown below:

[0109]

[0110] (4) Base map of 5G LDPC code

[0111] Currently, the 3GPP TS 38.212 protocol defines the base map of 5G LDPC codes as BG1 and BG2, both of which have a common matrix structure. Figure 4 This is a schematic diagram of the matrix structure of the 5G LDPC code basemap. The 5G LDPC code basemap can be divided into five regions: A, B, C, D, and E. Region A is the high-rate region, corresponding to the high-rate information columns. Region B is the core check region, also corresponding to the high-rate. Region C is an all-zero region, a zero matrix. Region D is the incremental redundancy region, corresponding to the low-rate. Region E is a diagonal region (like a raptor-like region), possessing an identity matrix structure.

[0112] In 5G LDPC codes, the protocol specifies a maximum-sized base map for storage. In practical applications, different matrix regions are selected based on the code rate. Specifically, rows 1 to M0 and columns 1 to N0 are selected. As the code rate decreases, M0 and N0 gradually increase, and the area of ​​the matrix used also gradually expands. For example... Figure 5 The dashed boxes containing high-bit-rate regions correspond to different bit-rates. The base map of 5G LDPC codes has a nested characteristic, meaning that low-bit-rate regions contain high-bit-rate regions.

[0113] The 3GPP TS 38.212 protocol further defines shift values ​​as follows: 1. a list of boosting factors; 2. a list of shift values ​​that corresponds one-to-one with each row of the boosting factor list. Table 1 is an example of a boosting factor list.

[0114] Table 1: List of Enhancement Factors

[0115]

[0116] The main characteristic of a list of promoted values ​​is that the j-th row of the list... Where a j ∈{2,3,5,7,9,11,13,15}, max(k j )∈{7,7,6,5,5,5,4,4}.

[0117] Table 2 is a list of the edges and shift values ​​for a portion of BG1, where the first two columns correspond to the basis matrix of that portion, and the last eight columns correspond to the shift values ​​for that portion.

[0118] Table 2: List of edges and shift values ​​for a portion of BG1

[0119]

[0120]

[0121] The row indices of the lifting factor list correspond one-to-one with the column indices of the shift values. That is, each row of the lifting factor list corresponds to a set of shift values ​​for each lifting factor. Multiple lifting factors share the same set of shift values. For example, in Table 2, the set index i... LS The lifting factors {2, 4, 8, 16, 32, 64, 128, 256} for = 0 correspond to shift values ​​{250, 69, 226, 159, 100, 10, 59, 229, 110, 191, 9, 195, 23, 190, 35, 239, 31, 1, 0}. Assuming Zc = 4, then the basis matrix H... BGThe shift values ​​corresponding to the elements with a value of 1 in row 0 are 250 mod 4, 69 mod 4, 226 mod 4, 159 mod 4, 100 mod 4, 10 mod 4, 59 mod 4, 229 mod 4, 110 mod 4, 191 mod 4, 9 mod 4, 195 mod 4, 23 mod 4, 190 mod 4, 35 mod 4, 239 mod 4, 31 mod 4, 1 mod 4, 0 mod 4, which are 2, 1, 2, 3, 0, 2, 3, 1, 2, 3, 1, 3, 3, 2, 3, 3, 3, 1, 0. For the base matrix H... BG For each element in row 0 that has a value of 0, the corresponding shift value is -1. In 5G LDPC codes, the boost factor is determined first, and then the shift value corresponding to the boost factor is selected to construct the parity check matrix.

[0122] (6) GC-LDPC

[0123] Globally coupled LDPC (GC-LDPC) codes are a special type of LDPC code with a coupled structure, proposed in 2016 by J. Li, S. Lin, and others. Based on the Tanner graph, GC-LDPC codes are constructed by connecting the Tanner graphs of multiple independent LDPC codes together using a set of global check nodes or variable nodes. For example... Figure 6 As shown, there is a Tanner graph {G0, G1, ..., Ga-1} of a independent LDPC codes. G0 to Ga-1 are called local sections / parts. The check nodes in G0 correspond to the variable nodes within the range of G0, the check nodes in G1 correspond to the variable nodes within the range of G1, and so on. That is, the check nodes in the local section correspond to the variable nodes within the local range. If there are s additional global check nodes (GCNs) connected to the variable nodes of these a independent Tanner graphs, that is, the s global check nodes correspond to the variable nodes within the global range, then the whole consisting of these a independent Tanner graphs and these s additional global check nodes is a Tanner graph of a GC-LDPC code.

[0124] GC-LDPC codes have good decoding performance, which is reflected in the following three aspects:

[0125] ① The decoding of GC-LDPC codes can be divided into local decoding and global decoding. Local decoding is highly parallel, which results in low decoding latency.

[0126] ② GC-LDPC codes connect the variable nodes of multiple independent LDPC codes through highly connected check nodes, thus exhibiting excellent error correction performance. When errors occur during data transmission, because multiple independent LDPC codes are interconnected through highly connected check nodes, information can be checked and corrected over a wider range. Compared to a single independent LDPC code, GC-LDPC codes can utilize more check relationships to detect and correct errors. For example, if a variable node in an independent LDPC code is faulty, relevant information from other independent LDPC codes can be used to assist in error correction through highly connected check nodes, thereby improving the overall error correction capability and reducing the bit error rate.

[0127] ③ Because the high-connectivity check nodes provide constraints on multiple independent LDPC codes, GC-LDPC codes also possess a certain degree of resistance to burst errors. For example, if a segment of continuous variable nodes in an independent LDPC code is affected by a burst error, the correct information from the other codes can be used to help recover this part of the error through the interaction between the high-connectivity check nodes and other independent LDPC codes. This enhances the resistance to burst errors and makes the system more stable and reliable when facing complex channel interference.

[0128] As mentioned above, LDPC codes have been selected as the data channel coding method in 5G standard protocols. For future mobile communication networks, commercial applications such as XR, MR, and immersive services are emerging, offering real-time high data rates. These emerging services place higher demands on the peak throughput and area efficiency of encoding and decoding, with peak rates even requiring Tbps, while simultaneously requiring further reductions in decoder power consumption. Although 5G LDPC codes have played a crucial role in 5G communication, they have limitations in meeting the high demands of these emerging services. For example, current 5G standard protocols (such as 3GPP TS 38.212) specify a maximum length of 8448 bits for the information bit sequence of 5G LDPC codes. When the length of the information bit sequence exceeds 8448 bits, it is necessary to divide the information bit sequence into multiple segments, each with a length less than or equal to 8448 bits, and then encode these segments separately based on 5G LDPC codes.

[0129] When the length of the information bit sequence is greater than 8448, another possible approach is to encode it based on GC-LDPC codes. Since GC-LDPC codes utilize the independent relationships between multiple independent LDPC code blocks, they can reduce error propagation during decoding. Furthermore, the constraints of global check nodes improve their decoding performance, effectively resisting burst errors. Therefore, theoretically, when the length of the information bit sequence is greater than 8448, the decoding performance based on GC-LDPC codes is higher than that based on 5GLDPC codes.

[0130] However, existing research on GC-LDPC codes involves designing GC-LDPC codewords from scratch. The codewords designed using this method differ significantly from the excellent codewords already present in current standard protocols and are often incompatible.

[0131] Based on this, embodiments of this application provide a coding and decoding method and apparatus for expanding a new shift value matrix / check matrix according to the base matrix and the first lifting factor of the first LDPC code, and performing coding and decoding according to the new shift value matrix / check matrix, thereby improving the decoding performance of the LDPC code while maintaining compatibility with the first LDPC code.

[0132] For example, the first LDPC code is a QC-LDPC code, such as a 5G LDPC code. Since the 5G standard protocol has already specified the base matrix and boosting factor of the 5G LDPC code (see Tables 1 and 2 above), this application proposes to design the shift value matrix / check matrix of the GC-LDPC code based on the existing base matrix and boosting factor of the 5G LDPC code, thereby improving the decoding performance of the LDPC code while maintaining compatibility with the 5G LDPC code.

[0133] The method provided in this application embodiment will be described in detail below with reference to specific embodiments. The method provided in this application embodiment involves a first communication device and / or a second communication device. The first communication device is a signal transmitting end, and the second communication device is a signal receiving end. Unless otherwise specified, the "first communication device" in this application can refer to a communication device (e.g., a network device, a terminal device, an encoding device, etc.), a component within that communication device (e.g., a processor, a chip, or a chip system, etc.), or a logic module or software capable of implementing all or part of the functions of the communication device; similarly, the "second communication device" in this application can refer to a communication device (e.g., a terminal device, a network device, a decoding device, etc.), a component within that communication device (e.g., a processor, a chip, or a chip system, etc.), or a logic module or software capable of implementing all or part of the functions of the communication device. For example, the first communication device may be a network device, and the second communication device may be a terminal device; or, the first communication device may be a terminal device, and the second communication device may be a network device.

[0134] This application involves code length, information bit sequence length, and code rate, and these terms are explained below. The length of the information bit sequence is the number of information bits to be transmitted. These information bits may or may not include cyclic redundancy check (CRC) bits; there is no restriction. Code length refers to the length of the (to be) transmitted bits, which can be the number of transmitted bits corresponding to the modulated symbol. Code rate is the ratio of the number of information bits to the number of transmitted bits. Code length, information bit length, and code rate can be pre-configured by higher-layer signaling, medium access control (MAC) layer, or downlink physical layer signals, and they can also be directly obtained and calculated by the transceiver. More specifically, the code length can be determined by the frame structure, number of layers, and modulation scheme of the encoded and transmitted information bits; the code rate can be indicated in the above ways or given in the modulation and coding scheme (MCS) table.

[0135] Example 1

[0136] Figure 7 This is a flowchart illustrating the method provided in Embodiment 1 of this application. Figure 7 As shown, the process may include:

[0137] S701, the first communication device determines the first shift value matrix based on the base matrix of the first LDPC code and the first boosting factor.

[0138] For example, the first communication device can determine the base matrix of the first LDPC code based on the code length and / or target code rate, and then determine the first boosting factor based on the code length and base matrix of the first LDPC code. Specific details can be found in the description of LDPC in the 5G standard protocol. The code length of the first LDPC code is obtained based on the code length of the second LDPC code, which is the target code length. For example, the code length of the second LDPC code is t times the code length of the first LDPC code, where t is an integer greater than 1. The specific value of t depends on the internal implementation of the first communication device and is not limited.

[0139] After determining the base matrix and the first boosting factor of the first LDPC code, the first communication device can obtain the first shift value matrix by referring to the methods described above (such as Tables 1 and 2). The dimension of the first shift value matrix is ​​the same as the dimension of the base matrix of the first LDPC code. The first shift value matrix includes a first block matrix and a second block matrix. The first block matrix includes at least one row vector of the first shift value matrix, and the second block matrix includes all row vectors of the first shift value matrix except for the at least one row vector. Optionally, the number of columns in the first block matrix, the number of columns in the second block matrix, and the number of columns in the first shift value matrix are the same. Optionally, the number of rows in the first block matrix and the number of rows in the second block matrix can be the same or different, without specific limitation.

[0140] For example, the first shift value matrix includes m row vectors, and the first block matrix includes the first to m rows from the m row vectors. l m row vectors, i.e., the first block matrix includes m l The second block matrix includes the m-th row vector among the m row vectors; l +1 to m row vectors, that is, the second block matrix includes m g There are m row vectors. l +m g =m. In this case, assuming the number of columns in the first shift value matrix is ​​n, the first shift value matrix can be denoted as S1 = [P i,j ] m×n The first block matrix can be denoted as The second block matrix can be denoted as:

[0141] For example, see Figure 8A As shown, the first shift value matrix comprises 3 row vectors, the first block matrix comprises the first 2 row vectors, and the second block matrix comprises the last row vector. It should be understood that... Figure 8A This is merely a simple example to illustrate the implementation of the embodiments of this application. The dimension and size of the first shift value matrix obtained in a specific implementation may differ from this example.

[0142] S702, the first communication device determines the second shift value matrix based on the first block matrix and the second block matrix.

[0143] For example, the second shift value matrix satisfies:

[0144]

[0145] Where S represents the second shift value matrix, S local,i Let S be the first block matrix. global,i Based on the second block matrix, S is divided by S local,i and S global,iThe remaining positions have no corresponding shift value, for example, S. local,i and S global,i The remaining position can be -1 or other possible values. In this embodiment, "-1" will be used as an example, i = 0, 1, 2...t-1, where t is an integer greater than 1.

[0146] When the first shift value matrix is ​​denoted as S1 = [P] i,j ] m×n When the second shift value matrix is ​​reached, it can be denoted as S2 = [P i,j '] tm×tn Continue to use Figure 8A In the example, assuming t=2, the second shift value matrix can be found in [reference needed]. Figure 8D As shown, Figure 8D The element at the middle space position takes a value of -1 (indicating that there is no corresponding shift value).

[0147] As one possible implementation, the second shift value matrix comprises two parts: a third shift value matrix and a fourth shift value matrix. The first communication device can obtain the third shift value matrix based on the first block matrix and the fourth shift value matrix based on the second block matrix, without being limited in the specific execution order; then, the third and fourth shift value matrices are concatenated to obtain the second shift value matrix.

[0148] (1) Describe the specific implementation of “obtaining the third shift value matrix based on the first block matrix”.

[0149] For example, the first communication device performs a unified hash on the first block matrix to obtain a third shift value matrix. For instance, performing a unified hash on the first block matrix means replacing the elements with values ​​of 1 in a diagonal matrix with both rows and columns of t with the first block matrix, and replacing the elements with values ​​of 0 in the diagonal matrix with matrix a, where all elements in matrix a have values ​​of -1 (indicating no corresponding shift value), and matrix a has the same dimensions as the first block matrix.

[0150] The third shift matrix satisfies:

[0151]

[0152] Among them, S local S represents the third shift value matrix. local,0 To S local,t-1 Each item in the matrix represents the first block matrix. The first block matrix is ​​denoted as... When the third shift value matrix is, it can be denoted as: Continue Figure 8A In the example, assuming t = 2, the diagonal matrix is: The third shift value matrix is ​​as follows: Figure 8B As shown, where Figure 8B The element at the middle space position has a value of -1.

[0153] (2) Describe the specific implementation of “obtaining the fourth shift value matrix based on the second block matrix”.

[0154] For example, the second block matrix includes t sub-block matrices, the number of rows in the t sub-block matrices being the same as the number of rows in the second block matrix. Sub-block matrix j in the t sub-block matrices includes the j×V+1 to (j+1)×V column vectors in the second block matrix, where j = 0, 1, 2, ..., t-1, V is the number of columns in the sub-block matrix, V = n / t, and n is the number of columns in the second block matrix. For a t×t binary square matrix T, where each row and each column has exactly one element of 1 and the rest are 0, this matrix is ​​called a permutation matrix, and there are t! permutation matrices in total. The first communication device can independently hash the t sub-block matrices based on the t! permutation matrices to obtain the fourth shift value matrix.

[0155] Taking permutation matrix T1 out of t permutation matrices as an example, independently hashing the t sub-block matrices based on permutation matrix T1 means: replacing the elements with a value of 1 in the first row of permutation matrix T1 with sub-block matrix 0 from the t sub-block matrices; replacing the elements with a value of 1 in the second row of permutation matrix T1 with sub-block matrix 1 from the t sub-block matrices, and so on, replacing the elements with a value of 1 in the t-th row of permutation matrix T1 with sub-block matrix t-1 from the t sub-block matrices; and replacing the elements with a value of 0 in permutation matrix T1 with matrix b, where all elements have a value of -1 (indicating no corresponding shift value), and matrix b has the same dimension as the sub-block matrices.

[0156] Among them, the t permutation matrices satisfy the following condition: the positions of the elements with a value of 1 in each row of the t permutation matrices are different. For example, if t = 2, the t permutation matrices include permutation matrix T1 and permutation matrix T2, then the permutation matrix... Permutation matrix

[0157] The fourth shift matrix satisfies:

[0158] S global =[S global,0 S global,1 … S global,t-1 ]

[0159] Among them, S global S represents the fourth shift value matrix. global,0 To S global,t-1 Each item in the matrix is ​​obtained by hashing t sub-block matrices. Specifically, S global,0It is obtained by independently hashing t sub-block matrices based on the permutation matrix T1, S global,1 This is obtained by independently hashing t sub-block matrices based on permutation matrix T2, and so on. Since the positions of the elements with a value of 1 are different in each row of the t permutation matrices, therefore, S global The i×K+1 to (i+1)×K rows in the matrix contain t sub-block matrices, where i = 0, 1, 2, ..., t-1, and K is the number of rows in the sub-block matrices; for example, if K = 1, then S global Each row in the matrix contains t sub-block matrices. Furthermore, when the second block matrix is ​​denoted as... When the fourth shift value matrix is, it can be denoted as:

[0160] Continue Figure 8A In the example, assuming t = 2, refer to... Figure 8C As shown, there are t sub-block matrices, including sub-block matrix 1 and sub-block matrix 2, with each sub-block matrix having n / t = 2 columns; and t permutation matrices, including permutation matrix T1 and permutation matrix T2. Assume that the permutation matrix... Permutation matrix Then, hashing the t sub-block matrices independently based on the permutation matrix T1 yields matrix 1, hashing the t sub-block matrices independently based on the permutation matrix T2 yields matrix 2, and concatenating matrix 1 and matrix 2 yields the fourth shift value matrix. Figure 8C The element at the middle space position takes a value of -1 (indicating that there is no corresponding shift value).

[0161] It is understood that the embodiments of this application do not limit the specific implementation of "determining the second shift value matrix according to the first block matrix and the second block matrix". The above is only one possible implementation. In other examples, the first communication device may also obtain the second shift value matrix directly according to the first shift value matrix based on predefined rules.

[0162] S703, the first communication device performs LDPC encoding on the first information according to the second shift value matrix to obtain the second information.

[0163] For example, the first communication device determines the parity check matrix of the second LDPC code based on the second shift value matrix and the first boosting factor, such as the second LDPC code being a GC-LDPC code. Then, the first communication device performs LDPC encoding on the first information to obtain the second information based on the parity check matrix of the second LDPC code; the specific encoding process can be referred to the preceding description of LDPC codes.

[0164] Specifically, regarding "determining the parity check matrix of the second LDPC code based on the second shift value matrix and the first lifting factor," one possible implementation is as follows: Assuming the first lifting factor is denoted as Z, the first communication device replaces the elements in the second shift value matrix with a Z×Z cyclic permutation matrix to obtain the parity check matrix of the second LDPC code, where -1 is replaced with a Z×Z 0 matrix, and P... i,j Replace with a Z×Z identity matrix (circularly shifted to the right) P i,j ' matrix.

[0165] Alternatively, it can be described as follows: The first communication device obtains the basis matrix of the second LDPC code based on the basis matrix of the first LDPC code. The specific implementation process can be found in the description of "Determining the second shift value matrix based on the first and second block matrices," where the element P in the second shift value matrix... i,j ' is the shift value corresponding to the element in the i-th row and j-th column of the base matrix of the second LDPC code. The first communication device improves the base matrix of the second LDPC code according to the cyclic permutation matrix corresponding to the first improvement factor. The specific improvement process is as follows: the elements with a value of 0 in the base matrix of the second LDPC code are replaced with a Z×Z 0 matrix, and the elements with a value of 1 are replaced with a Z×Z identity matrix (circularly shifted to the right by P). i,j ' matrix.

[0166] For example, the parity-check matrix of the second LDPC code satisfies:

[0167]

[0168] Where H represents the parity check matrix of the second LDPC code, H local,i It is based on S local,i H, obtained from the first enhancement factor global,i It is based on S global,i The first enhancement factor is used to obtain H, excluding H. local,i and H global,i The remaining positions are all 0. It can be seen that H local,0 The check node in H corresponds to local,0 Variable nodes within the range, H local,1 The check node in H corresponds to local,1 The variable nodes within the range, and so on, i.e., H loca The check nodes in S correspond to variable nodes within a local scope. global The i×K+1 to (i+1)×K rows in H contain t sub-block matrices, therefore, H global The verification node in the code corresponds to the variable node in the global scope.

[0169] S704, the first communication device outputs the second information; correspondingly, the second communication device obtains the third information.

[0170] For example, the first communication device can modulate the encoded second information to obtain multiple modulation symbols, and send the multiple modulation symbols to the second communication device; correspondingly, the second communication device can receive the multiple modulation symbols and obtain the third information by demodulation. Since errors may occur during transmission, the third information may differ from the second information; for example, if the second information includes 011101, and assuming the first bit "0" is lost during transmission, the third information obtained by the second communication device through demodulation includes 111101.

[0171] Optionally, the above method further includes:

[0172] S705, the second communication device obtains the first shift value matrix based on the base matrix of the first LDPC code and the first boosting factor.

[0173] S706, the second communication device determines the second shift value matrix based on the first block matrix and the second block matrix.

[0174] For example, the implementation of S705 to S706 can be referred to the description on the first communication device side, and will not be repeated here.

[0175] S707, the second communication device performs LDPC decoding on the third information according to the second shift value matrix to obtain the first information.

[0176] For example, the specific decoding process can be referred to the previous description of LDPC codes.

[0177] Using the above method, a first shift value matrix is ​​determined based on the base matrix and the first boosting factor of the first LDPC code. Then, a second shift value matrix is ​​determined based on the first position matrix, and encoding / decoding is performed based on the second shift value matrix. The first LDPC code is a QC-LDPC code, such as a 5G LDPC code. Since the 5G standard protocol already specifies the base matrix and boosting factor of the 5G LDPC code, this embodiment designs a new LDPC code shift value matrix based on the existing 5G LDPC code base matrix and boosting factor. This allows for effective expansion of the information bit sequence length supported by the LDPC code while maintaining compatibility with the 5G LDPC code. Furthermore, the GC-LDPC code constructed using the method in this embodiment has the same degree distribution as the original QC-LDPC code, facilitating the construction of GC-LDPC codes using existing excellent codewords in the standard protocol, thereby improving the decoding performance of the LDPC code.

[0178] Example 2

[0179] Figure 9 This is a flowchart illustrating the method provided in Embodiment 2 of this application. Figure 9 As shown, the process may include:

[0180] S901, the first communication device determines the first shift value matrix based on the base matrix of the first LDPC code and the first boosting factor.

[0181] For example, the specific implementation of S901 can be referred to the description of S801.

[0182] S902, the first communication device determines the check matrix of the second LDPC code based on the first block matrix and the second block matrix.

[0183] For example, the parity check matrix of the second LDPC code satisfies:

[0184]

[0185] Where H represents the parity check matrix of the second LDPC code, H local,i Based on the first block matrix and the first lifting factor, where i = 0, 1, 2, ..., t-1, H is determined. global The second lifting factor is determined based on the second block matrix and the second lifting factor, where the second lifting factor is t times the first lifting factor, and t is an integer greater than 1. For example, the second lifting factor and the first lifting factor belong to the same set of lifting sizes.

[0186] As one possible implementation, the parity check matrix of the second LDPC code comprises two parts: a first sub-parity check matrix and a second sub-parity check matrix. The first communication device can determine the first sub-parity check matrix based on the first block matrix and the first lifting factor, and determine the second sub-parity check matrix based on the second block matrix and the second lifting factor, without limiting the specific execution order; then, the first sub-parity check matrix and the second sub-parity check matrix are concatenated to obtain the parity check matrix of the second LDPC code.

[0187] Among them, the first sub-verification matrix H local for:

[0188]

[0189] The check nodes in the first sub-check matrix correspond to variable nodes within a local scope. For example, in a Tanner graph, the check nodes in the first sub-check matrix connect to variable nodes within that local scope. Alternatively, the first sub-check matrix can be understood as a local section / part of the second LDPC code (such as a GC-LDPC code). The check nodes in the second sub-check matrix correspond to variable nodes within a global scope. For example, in a Tanner graph, the check nodes in the second sub-check matrix connect to variable nodes within that global scope. Alternatively, the second sub-check matrix can be understood as a global section / part of the second LDPC code (such as a GC-LDPC code).

[0190] For example, the specific implementation of "determining the first sub-check matrix based on the first block matrix and the first lifting factor" can be referred to the description of Embodiment 1.

[0191] Regarding the task of "determining the second sub-parity check matrix based on the second block matrix and the second lifting factor," one implementation is as follows: Assuming the first lifting factor is Z and the second lifting factor is tZ, the first communication device will use the second block matrix... The elements in the matrix are replaced with a tZ×tZ cyclic permutation matrix to obtain the first matrix; where -1 is replaced with a tZ×tZ matrix of 0s, and g is... i,j Replace with a unit matrix (rightward) cyclically shifted by g i,j The first communication device then performs column permutations on the first matrix to obtain a second sub-parity check matrix. For example, the first communication device permutes the c-th column and the σ(c)-th column in the first matrix to obtain the second sub-parity check matrix; where σ(c) and c satisfy:

[0192]

[0193] Where Z represents the first lifting factor, n represents the number of columns in the second block matrix, c = 1, 2, 3, ..., t*n*Z, and t*n*Z (or denoted as tnZ) is the number of columns in the first matrix. This indicates rounding down. By permuting the c-th column with the σ(c)-th column in the first matrix, the check nodes in the second check matrix correspond to variable nodes in the global scope.

[0194] The following is combined with Figure 10 To further describe: As mentioned above, the first sub-parity check matrix is ​​determined based on the first block matrix and the first lifting factor. Therefore, the number of rows in the first sub-parity check matrix is ​​t*n*Z, while the number of rows in the second block matrix is ​​n, as shown in (1) of 10. Figure 10The example is based on t=2. The second block matrix follows the same principle. Figure 8A (Example in [reference]). Based on the second block matrix and the second lifting factor, the first matrix has t*n*Z rows. See [reference] Figure 10 As shown in (2) above. Further, by permuting the c-th column and the σ(c)-th column in the first matrix based on the above formula, the second sub-verification matrix can be obtained, see [reference]. Figure 10 As shown in (3) of the text.

[0195] It is understood that the embodiments of this application do not limit the specific implementation of "determining the parity check matrix of the second LDPC code based on the first block matrix and the second block matrix". The above is only one possible implementation. In other examples, the first communication device may also obtain the parity check matrix of the second LDPC code directly based on the first shift value matrix according to predefined rules (such as...). Figure 10 (as shown in (3)).

[0196] S903, the first communication device performs LDPC encoding on the first information to obtain the second information based on the check matrix of the second LDPC code.

[0197] For example, the specific encoding process can be referred to the previous description of LDPC codes.

[0198] S904, the first communication device outputs the second information; correspondingly, the second communication device obtains the third information.

[0199] For example, the first communication device can modulate the encoded second information to obtain multiple modulation symbols and send the multiple modulation symbols to the second communication device; correspondingly, the second communication device can receive the multiple modulation symbols and obtain the third information by demodulation.

[0200] Optionally, the above method further includes:

[0201] S905, the second communication device determines the first shift value matrix based on the base matrix of the first LDPC code and the first boosting factor.

[0202] S906, the second communication device determines the check matrix of the second LDPC code based on the first block matrix and the second block matrix.

[0203] For example, the implementation of S905 and S906 can be referred to the description on the first communication device side, and will not be repeated here.

[0204] S907, the second communication device decodes the third information to obtain the first information based on the check matrix of the second LDPC code.

[0205] For example, the specific decoding process can be referred to the previous description of LDPC codes.

[0206] Using the above method, a first shift value matrix is ​​determined based on the base matrix and first boosting factor of the first LDPC code. Then, the parity check matrix of the second LDPC code is determined based on the first position matrix, and encoding and decoding are performed based on the parity check matrix of the second LDPC code. The first LDPC code is a QC-LDPC code, such as a 5G LDPC code. Since the 5G standard protocol already specifies the base matrix and boosting factor of the 5G LDPC code, this embodiment designs a new parity check matrix for the LDPC code based on the existing base matrix and boosting factor of the 5G LDPC code. This allows for effective expansion of the length of the information bit sequence supported by the LDPC code while maintaining compatibility with the 5G LDPC code. Furthermore, the GC-LDPC code constructed using the method in this embodiment has the same degree distribution as the original QC-LDPC code, facilitating the construction of GC-LDPC codes using existing excellent codewords in the standard protocol, thereby improving the decoding performance of the LDPC code.

[0207] It is understood that the method provided in Embodiment 1 or Embodiment 2 of this application can be applied to design QC-LDPC codes of arbitrary structure into GC-LDPC codes.

[0208] The performance of the encoding / decoding method in the embodiments of this application is illustrated below through simulation results.

[0209] The simulation example is as follows: The first LDPC code is a 5G LDPC code with a code rate of 2 / 3. The base matrix of the first LDPC code includes 13 rows and 35 columns, and the corresponding first shift value matrix also includes 13 rows and 35 columns. The first 9 rows of the first shift value matrix are used as the first block matrix, and the last 4 rows are used as the second block matrix. The modulation method is quadrature phase shift keying (QPSK).

[0210] Figure 11 The horizontal axis represents the signal-to-noise ratio (e.g., the ratio of bit energy to noise power spectral density, Eb / N0), and the vertical axis represents the bit error rate (BER) / block error rate (BLER). Figure 11 The following data are shown: the BER and BLER of the 5G-LDPC code when the length of the information bit sequence is 4224; the BER and BLER of the 5G-LDPC code, the BER and BLER of GC-LDPC V1 (i.e., the GC-LDPC code designed in Embodiment 1 of this application), and the BER and BLER of GC-LDPC V2 (i.e., the GC-LDPC code designed in Embodiment 2 of this application) when the length of the information bit sequence is 5632.

[0211] according to Figure 11It can be seen that the performance of GC-LDPC codes (GC-LDPC V1 or GC-LDPC V2) with an information bit sequence length of 5632 is between that of 5G LDPC codes with an information bit sequence length of 5632 and 5G LDPC codes with an information bit sequence length of 4224. Although GC-LDPC codes with an information bit sequence length of 5632 are inferior to 5G LDPC codes of the same length, GC-LDPC codes support parallel local decoding, have low decoding latency, and the local part of GC-LDPC codes can be 5G LDPC codes, i.e., they are compatible with 5G LDPC codes. The global part supports coupling multiple 5G LDPC codes into a long code.

[0212] Regarding the above embodiments, it is understood that:

[0213] (1) In the embodiments of this application, unless otherwise specified or logically conflicting, the terms and / or descriptions between different examples are consistent and can be referenced by each other. The technical features of different examples can be combined to form new embodiments according to their inherent logical relationships. In addition, different implementations or different examples can also be referenced or referenced by each other.

[0214] (2) The various numerical designations used in this application are merely for descriptive convenience and are not intended to limit the scope of this application. The step numbers in the above flowcharts are only examples of the execution process and do not constitute a restriction on the order of execution of the steps. That is, the size of each step number does not imply the order of execution; the execution order of each step should be determined by its function and internal logic. Furthermore, not all steps shown in the flowcharts are mandatory steps; some steps may be added or deleted based on actual needs.

[0215] The above mainly describes the solution provided by the embodiments of this application from the perspective of the interaction between the first communication device and the second communication device. It is understood that, in order to achieve the above functions, the first communication device and the second communication device may include hardware structures and / or software modules corresponding to the execution of each function. Those skilled in the art should readily recognize that, in conjunction with the units and algorithm steps of the various examples described in the embodiments disclosed herein, the embodiments of this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed in hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0216] In this application embodiment, the first communication device and the second communication device can be divided into functional units according to the above method example. For example, each function can be divided into a separate functional unit, or two or more functions can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0217] When using integrated units, Figure 12 A possible exemplary block diagram of the apparatus involved in an embodiment of this application is shown. For example... Figure 12 As shown, device 1200 may include a processing unit 1202 and a communication unit 1203. The processing unit 1202 is used to control and manage the operation of device 1200. The communication unit 1203 is used to support communication between device 1200 and other devices. Optionally, the communication unit 1203, also called a transceiver unit, may include a receiving unit and / or a transmitting unit, respectively used to perform receiving and transmitting operations. Device 1200 may also include a storage unit 1201 for storing program code and / or data of device 1200.

[0218] (1) The device 1200 can be the first communication device in the above embodiments. The processing unit 1202 can support the device 1200 in performing the actions of the first communication device in the above method embodiments. Alternatively, the processing unit 1202 mainly performs the internal actions of the first communication device in the method embodiments, and the communication unit 1203 can support communication between the device 1200 and other devices.

[0219] For example, in one embodiment, the processing unit 1202 is configured to: determine a first shift value matrix based on the basis matrix of a first low-density parity-check LDPC code and a first boosting factor, wherein the first shift value matrix includes a first block matrix and a second block matrix, the first block matrix includes at least one row vector of the first shift value matrix, and the second block matrix includes row vectors in the first shift value matrix other than the at least one row vector; obtain a second shift value matrix based on the first block matrix and the second block matrix; perform LDPC encoding on the first information based on the second shift value matrix to obtain second information, and output the second information; wherein the second shift value matrix satisfies:

[0220]

[0221] Where S represents the second shift value matrix, S local,i Let S be the first block matrix. global,i Based on the second block matrix, S is determined to contain S excluding S local,i and S global,iThe remaining positions have no corresponding shift value, i = 0, 1, 2...t-1, where t is an integer greater than 1.

[0222] In one possible design, S global,i Determined based on the second block matrix, including: S global,i Determined based on t sub-block matrices in the second block matrix, and S global,0 To S global,t-1 The i×K+1 to (i+1)×K rows include the t sub-block matrices; the sub-block matrix j in the t sub-block matrices includes the j×V+1 to (j+1)×V column vectors in the second block matrix, j=0,1,2……t-1, V=n / t, where n is the number of columns in the second block matrix.

[0223] In one possible design, S excluding S local,i and S global,i The remaining position takes a value of -1.

[0224] In one possible design, the processing unit 1202 is specifically configured to: determine the parity check matrix of the second LDPC code based on the second shift value matrix and the first boosting factor; and perform LDPC encoding on the first information to obtain the second information based on the parity check matrix of the second LDPC code; wherein the parity check matrix of the second LDPC code satisfies:

[0225]

[0226] Where H represents the parity check matrix of the second LDPC code, H local,i It is based on S loca,l i H obtained from the first enhancement factor global,i It is based on S global,i And the first enhancement factor obtained, H excluding H local,i and H global,i The remaining positions are all 0.

[0227] In one possible design, the method further includes: determining the base matrix and the first boosting factor of the first LDPC code based on the code length and / or target code rate of the first LDPC code, wherein the code length of the second LDPC code is t times the code length of the first LDPC code, and t is an integer greater than 1.

[0228] (2) The device 1200 can be the second communication device in the above embodiments. The processing unit 1202 can support the device 1200 in performing the actions of the second communication device in the above method embodiments. Alternatively, the processing unit 1202 mainly performs the internal actions of the second communication device in the method embodiments, and the communication unit 1203 can support communication between the device 1200 and other devices.

[0229] For example, in one embodiment, the processing unit 1202 is configured to: determine a first shift value matrix based on the basis matrix of a first low-density parity-check LDPC code and a first boosting factor, wherein the first shift value matrix includes a first block matrix and a second block matrix, the first block matrix includes at least one row vector of the first shift value matrix, and the second block matrix includes row vectors in the first shift value matrix other than the at least one row vector; determine a second shift value matrix based on the first block matrix and the second block matrix; and perform LDPC decoding on the third information based on the second shift value matrix to obtain the first information; wherein the second shift value matrix satisfies:

[0230]

[0231] Where S represents the second shift value matrix, S local,i Let S be the first block matrix. global,i Based on the second block matrix, S is determined to contain S excluding S local,i and S global,i The remaining positions have no corresponding shift value, i = 0, 1, 2...t-1, where t is an integer greater than 1.

[0232] In one possible design, S global,i Determined based on the second block matrix, including: S global,i Determined based on t sub-block matrices in the second block matrix, and S global,0 To S global,t-1 The i×K+1 to (i+1)×K rows include the t sub-block matrices; the sub-block matrix j in the t sub-block matrices includes the j×V+1 to (j+1)×V column vectors in the second block matrix, j=0,1,2……t-1, V=n / t, where n is the number of columns in the second block matrix.

[0233] In one possible design, S excluding S local,i and S global,i The remaining position takes a value of -1.

[0234] In one possible design, the processing unit 1202 is specifically configured to: determine the parity check matrix of the second LDPC code based on the second shift value matrix and the first boosting factor; and perform LDPC encoding on the first information to obtain the second information based on the parity check matrix of the second LDPC code; wherein the parity check matrix of the second LDPC code satisfies:

[0235]

[0236] Where H represents the parity check matrix of the second LDPC code, H local,i It is based on S loca,l i H obtained from the first enhancement factor global,i It is based on S global,i And the first enhancement factor obtained, H excluding H local,i and H global,i The remaining positions are all 0.

[0237] In one possible design, the method further includes: determining the base matrix and the first boosting factor of the first LDPC code based on the code length and / or target code rate of the first LDPC code, wherein the code length of the second LDPC code is t times the code length of the first LDPC code, and t is an integer greater than 1.

[0238] It should be understood that the division of units in the above device is merely a logical functional division. In actual implementation, they can be fully or partially integrated into a single physical entity, or they can be physically separated. Furthermore, all units in the device can be implemented entirely through software calls from processing elements; all units can be implemented entirely in hardware; or some units can be implemented through software calls from processing elements, and some units can be implemented in hardware. For example, each unit can be a separate processing element, or it can be integrated into a chip within the device. Alternatively, it can be stored as a program in memory, called and executed by a processing element of the device. Moreover, these units can be fully or partially integrated together, or implemented independently. The processing element mentioned here can also be called a processor, which can be an integrated circuit with signal processing capabilities. In the implementation process, the operations of the above methods or the various units mentioned above can be implemented through integrated logic circuits in the processor element or through software calls from processing elements.

[0239] In one example, a unit in any of the above devices can be one or more integrated circuits configured to implement the methods described above, such as: one or more application-specific integrated circuits (ASICs), or one or more digital signal processors (DSPs), or one or more field-programmable gate arrays (FPGAs), or a combination of at least two of these forms of integrated circuits. As another example, when a unit in the device can be implemented in the form of a processing element scheduler, the processing element can be a processor, such as a general-purpose central processing unit (CPU), or other processor capable of calling programs. Furthermore, these units can be integrated together and implemented as a System-on-a-Chip (SoC).

[0240] The receiving unit described above is an interface circuit of the device, used to receive signals from other devices. For example, when the device is implemented as a chip, the receiving unit is an interface circuit for the chip to receive signals from other chips or devices. The transmitting unit described above is an interface circuit of the device, used to transmit signals to other devices. For example, when the device is implemented as a chip, the transmitting unit is an interface circuit for the chip to transmit signals to other chips or devices.

[0241] Based on the same technical concept, embodiments of this application also provide a communication device, which is used to implement the functions of the first or second communication device in the above embodiments. For example... Figure 13 As shown, the device can be a communication device or a component within a communication device (e.g., a processor, chip, or chip system). The device includes a processor 1301 and a communication interface 1302, and optionally, a memory 1303. The memory 1303 can be independent of the processor 1301 or integrated into the processor 1301; no specific limitation is made. It is understood that... Figure 13 Only the main components of the communication device are shown. Furthermore, the communication device may further include input / output devices (not shown in the figure).

[0242] The processor 1301 is used to execute the program code stored in the memory 1303, specifically to perform the actions of the processing unit 1202, which will not be described in detail here. The communication interface 1302 is specifically used to perform the actions of the communication unit 1203, which will not be described in detail here.

[0243] Processor 1301 can be a CPU, a digital processing unit, etc. Processor 1301 can be used to process communication protocols and communication data, control the entire communication device, execute software programs, and process software program data, such as, but not limited to, baseband-related processing. Communication interface 1302 can be used for transmitting and receiving signals, such as, but not limited to, radio frequency transceiver. The above-mentioned devices can be disposed on separate chips, or at least partially or entirely on the same chip. For example, processor 1301 can be further divided into an analog baseband processor and a digital baseband processor. The analog baseband processor can be integrated with the transceiver on the same chip, while the digital baseband processor can be disposed on a separate chip. With the continuous development of integrated circuit technology, more and more devices can be integrated on the same chip. For example, a digital baseband processor can be integrated with multiple application processors (such as, but not limited to, graphics processors, multimedia processors, etc.) on the same chip. Such a chip can be called a system-on-a-chip (SoC). Whether to dispose of individual devices independently on different chips or integrate them on one or more chips often depends on the specific needs of the product design. The embodiments of the present invention do not limit the specific implementation of the above-mentioned devices.

[0244] The communication interface 1302 can be a transceiver, an interface circuit such as a transceiver circuit, or a transceiver chip, etc. Optionally, the communication interface 1302 may include radio frequency (RF) circuitry and an antenna. The RF circuitry is mainly used for converting baseband signals to RF signals and processing RF signals. The antenna is mainly used for transmitting and receiving RF signals in the form of electromagnetic waves. Input / output devices, such as touch screens, displays, and keyboards, are mainly used for receiving user input data and outputting data to the user.

[0245] Memory 1303 is used to store programs executed by processor 1301. Memory 1303 can be non-volatile memory, such as a hard disk drive (HDD) or solid-state drive (SSD), or it can be volatile memory, such as random-access memory (RAM). Memory 1303 can be any other medium capable of carrying or storing desired program code in the form of instructions or data structures that can be accessed by a computer, but is not limited to this.

[0246] When the communication device is powered on, the processor 1301 can read the software program in the memory 1303, interpret and execute the instructions of the software program, and process the data of the software program. When data needs to be transmitted wirelessly, the processor 1301 performs baseband processing on the data to be transmitted and outputs the baseband signal to the radio frequency (RF) circuit. The RF circuit then performs RF processing on the baseband signal and transmits the RF signal outward in the form of electromagnetic waves through the antenna. When data is sent to the communication device, the RF circuit receives the RF signal through the antenna, converts the RF signal into a baseband signal, and outputs the baseband signal to the processor 1301. The processor 1301 converts the baseband signal into data and processes the data.

[0247] In another implementation, the radio frequency circuitry and antenna can be set up independently of the processor performing baseband processing. For example, in a distributed scenario, the radio frequency circuitry and antenna can be arranged remotely, independent of the communication device.

[0248] This application embodiment does not limit the specific connection medium between the communication interface 1302, processor 1301, and memory 1303. This application embodiment... Figure 13 The memory 1303, processor 1301, and communication interface 1302 are connected via a bus 1304. Figure 13 The connections between other components are shown in bold lines only and are not intended to be limiting. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, Figure 13 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0249] Optionally, the communication device described above can be a standalone device or part of a larger device. For example, the communication device can be:

[0250] (1) An independent integrated circuit (IC), or chip, or chip system or subsystem;

[0251] (2) A collection of one or more ICs, optionally including a storage component for storing data and instructions;

[0252] (3) Application-specific integrated circuit (ASIC), such as modem;

[0253] (4) Modules that can be embedded in other devices;

[0254] (5) Receivers, smart terminals, wireless devices, handheld devices, mobile units, vehicle-mounted devices, cloud devices, artificial intelligence devices, etc.;

[0255] (6) Others, etc.

[0256] In this application embodiment, "multiple" can refer to two or more. Therefore, in this application embodiment, "multiple" can also be understood as "at least two". "At least one" can be understood as one or more, such as one, two, or more. For example, "including at least one" means including one, two, or more. For example, including at least one of A, B, and C, then it could include A, B, C, A and B, A and C, B and C, or A, B, and C. "And / or" describes the association relationship between related objects. Specifically, there can be three relationships. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / ", unless otherwise specified, generally indicates that the preceding and following related objects have an "or" relationship.

[0257] Furthermore, the terms "system" and "network" in the embodiments of this application can be used interchangeably, as can "according to" and "based on". The ordinal numbers such as "first" and "second" mentioned in the embodiments of this application are generally used to distinguish different objects and are not used to limit the order, sequence, priority, or importance of multiple objects. For example, the first communication device and the second communication device in the embodiments of this application are used to distinguish between two communication devices, and do not limit the priority or importance of these two communication devices.

[0258] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0259] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0260] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0261] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

Claims

1. An encoding method, characterized in that, The method includes: Based on the basis matrix of the first low-density parity-check LDPC code and the first boosting factor, a first shift value matrix is ​​determined. The first shift value matrix includes a first block matrix and a second block matrix. The first block matrix includes at least one row vector of the first shift value matrix, and the second block matrix includes row vectors in the first shift value matrix other than the at least one row vector. The second shift value matrix is ​​determined based on the first block matrix and the second block matrix; Based on the second shift value matrix, the first information is LDPC encoded to obtain the second information, and the second information is output. The second shift matrix satisfies: Where S represents the second shift value matrix, S local,i Let S be the first block matrix. global,i Based on the second block matrix, S is determined to contain S excluding S local,i and S global,i The remaining positions have no corresponding shift value, i = 0, 1, 2...t-1, where t is an integer greater than 1.

2. The method according to claim 1, characterized in that, S global,i Determined based on the second block matrix, including: S global,i Determined based on t sub-block matrices in the second block matrix, and S global,0 To S global,t-1 The i×K+1 to (i+1)×K rows include the t sub-block matrices; the sub-block matrix j in the t sub-block matrices includes the j×V+1 to (j+1)×V column vectors in the second block matrix, j=0,1,2……t-1, V=n / t, where n is the number of columns in the second block matrix.

3. The method according to claim 1 or 2, characterized in that, S excluding S local,i and S global,i The remaining position takes a value of -1.

4. The method according to any one of claims 1 to 3, characterized in that, Based on the second shift value matrix, the first information is LDPC encoded to obtain the second information, including: The parity check matrix of the second LDPC code is determined based on the second shift value matrix and the first boosting factor. The first information is obtained by performing LDPC encoding on the second LDPC code according to the parity check matrix of the second LDPC code; The parity-check matrix of the second LDPC code satisfies: Where H represents the parity check matrix of the second LDPC code, H local,i It is based on S loca,li H obtained from the first enhancement factor global,i It is based on S global,i And the first enhancement factor obtained, H excluding H local,i and H global,i The remaining positions are all 0.

5. The method according to any one of claims 1 to 4, characterized in that, The method further includes: Based on the code length and / or target code rate of the first LDPC code, the base matrix and the first boosting factor of the first LDPC code are determined, and the code length of the second LDPC code is t times the code length of the first LDPC code, where t is an integer greater than 1.

6. A decoding method, characterized in that, The method includes: Based on the basis matrix of the first low-density parity-check LDPC code and the first boosting factor, a first shift value matrix is ​​determined. The first shift value matrix includes a first block matrix and a second block matrix. The first block matrix includes at least one row vector of the first shift value matrix, and the second block matrix includes row vectors in the first shift value matrix other than the at least one row vector. The second shift value matrix is ​​determined based on the first block matrix and the second block matrix; Based on the second shift value matrix, the third information is decoded by LDPC to obtain the first information; The second shift matrix satisfies: Where S represents the second shift value matrix, S local,i Let S be the first block matrix. global,i Based on the second block matrix, S is determined to contain S excluding S local,i and S global,i The remaining positions have no corresponding shift value, i = 0, 1, 2...t-1, where t is an integer greater than 1.

7. The method according to claim 6, characterized in that, S global,i Determined based on the second block matrix, including: S global,i Determined based on t sub-block matrices in the second block matrix, and S global,0 To S global,t-1 The i×K+1 to (i+1)×K rows include the t sub-block matrices; the sub-block matrix j in the t sub-block matrices includes the j×V+1 to (j+1)×V column vectors in the second block matrix, j=0,1,2……t-1, V=n / t, where n is the number of columns in the second block matrix.

8. The method according to claim 6 or 7, characterized in that, S excluding S local,i and S global,i The remaining position takes a value of -1.

9. The method according to any one of claims 6 to 8, characterized in that, Based on the second shift value matrix, the first information is LDPC encoded to obtain the second information, including: The parity check matrix of the second LDPC code is determined based on the second shift value matrix and the first boosting factor. The first information is obtained by performing LDPC encoding on the second LDPC code according to the parity check matrix of the second LDPC code; The parity-check matrix of the second LDPC code satisfies: Where H represents the parity check matrix of the second LDPC code, H local,i It is based on S loca,li H obtained from the first enhancement factor global,i It is based on S global,i And the first enhancement factor obtained, H excluding H local,i and H global,i The remaining positions are all 0.

10. The method according to any one of claims 6 to 9, characterized in that, The method further includes: Based on the code length and / or target code rate of the first LDPC code, the base matrix and the first boosting factor of the first LDPC code are determined, and the code length of the second LDPC code is t times the code length of the first LDPC code, where t is an integer greater than 1.

11. An encoding method, characterized in that, The method includes: Based on the basis matrix of the first low-density parity-check LDPC code and the first boosting factor, a first shift value matrix is ​​determined. The first shift value matrix includes a first block matrix and a second block matrix. The first block matrix includes at least one row vector of the first shift value matrix, and the second block matrix includes row vectors in the first shift value matrix other than the at least one row vector. Based on the first block matrix and the second block matrix, determine the parity check matrix of the second LDPC code; Based on the parity check matrix of the second LDPC code, the first information is LDPC encoded to obtain the second information, and the second information is output. The parity-check matrix of the second LDPC code satisfies: Where H represents the parity check matrix of the second LDPC code, H local,i Based on the first block matrix and the first lifting factor, where i = 0, 1, 2, ..., t-1, H is determined. global Based on the second block matrix and the second lifting factor, where the second lifting factor is t times the first lifting factor, and t is an integer greater than 1, H is divided by H local,i and H global The remaining positions are all 0.

12. The method according to claim 11, characterized in that, H global Determined based on the second block matrix and the second lifting factor, including: H global It is obtained by performing column permutations on the first matrix, which is derived from the second block matrix and the second lifting factor.

13. The method according to claim 12, characterized in that, H global It is obtained by performing column permutations on the first matrix, including: H global It is obtained by permuting the c-th column and the σ(c)-th column in the first matrix; where σ(c) and c satisfy: Where Z represents the first lifting factor, n represents the number of columns in the second block matrix, and c = 1, 2, 3, ..., t*n*Z, This indicates rounding down to the nearest integer.

14. The method according to any one of claims 11 to 13, characterized in that, The second boosting factor and the first boosting factor belong to the same set of boosting factors.

15. The method according to any one of claims 11 to 14, characterized in that, The method further includes: Based on the code length and / or target code rate of the first LDPC code, the base matrix and the first boosting factor of the first LDPC code are determined, and the code length of the second LDPC code is t times the code length of the first LDPC code, where t is an integer greater than 1.

16. A decoding method, characterized in that, The method includes: Based on the basis matrix of the first low-density parity-check LDPC code and the first boosting factor, a first shift value matrix is ​​determined. The first shift value matrix includes a first block matrix and a second block matrix. The first block matrix includes at least one row vector of the first shift value matrix, and the second block matrix includes row vectors in the first shift value matrix other than the at least one row vector. Based on the first block matrix and the second block matrix, determine the parity check matrix of the second LDPC code; Based on the parity check matrix of the second LDPC code, the third information is LDPC decoded to obtain the first information; The parity-check matrix of the second LDPC code satisfies: Where H represents the parity check matrix of the second LDPC code, H local,i Based on the first block matrix and the first lifting factor, where i = 0, 1, 2, ..., t-1, H is determined. global Based on the second block matrix and the second lifting factor, where the second lifting factor is t times the first lifting factor, and t is an integer greater than 1, H is divided by H local,i and H global The remaining positions are all 0.

17. The method according to claim 16, characterized in that, H global Determined based on the second block matrix and the second lifting factor, including: H global It is obtained by performing column permutations on the first matrix, which is derived from the second block matrix and the second lifting factor.

18. The method according to claim 17, characterized in that, H global It is obtained by performing column permutations on the first matrix, including: H global It is obtained by permuting the c-th column and the σ(c)-th column in the first matrix; where σ(c) and c satisfy: Where Z represents the first lifting factor, n represents the number of columns in the second block matrix, and c = 1, 2, 3, ..., t*n*Z, This indicates rounding down to the nearest integer.

19. The method according to any one of claims 16 to 18, characterized in that, The second boosting factor and the first boosting factor belong to the same set of boosting factors.

20. The method according to any one of claims 16 to 19, characterized in that, The method further includes: Based on the code length and / or target code rate of the first LDPC code, the base matrix and the first boosting factor of the first LDPC code are determined, and the code length of the second LDPC code is t times the code length of the first LDPC code, where t is an integer greater than 1.

21. A communication device, characterized in that, The device includes a processor coupled to a memory in which a computer program is stored; the processor is configured to invoke part or all of the computer program in the memory such that the method as described in any one of claims 1 to 20 is executed.

22. A communication system, characterized in that, The communication system includes a first communication device and a second communication device; wherein the first communication device is used to perform the method as described in any one of claims 1 to 5, and the second communication device is used to perform the method as described in any one of claims 6 to 10; or, the first communication device is used to perform the method as described in any one of claims 11 to 15, and the second communication device is used to perform the method as described in any one of claims 16 to 20.

23. A computer-readable storage medium, characterized in that, The storage medium stores a computer program that, when some or all of the computer program is executed by a computer, causes the method as described in any one of claims 1 to 20 to be performed.

24. A computer program product, characterized in that, When the computer reads and executes the computer program product, the method as described in any one of claims 1 to 20 is performed.

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