A high speed peripheral component interconnect bus optical transmission system and method

Abstract

The application provides a high-speed peripheral component interconnect bus optical transmission system and method, belonging to the technical field of optical communication, comprising: a first communication end and a second communication end which are physically separated, wherein the first communication end and the second communication end are both configured with clock synchronization subsystems and high-speed peripheral component interconnect communication modules which have the same structure; and a data fibre channel connected between the first communication end and the second communication end, wherein the data fibre channel is a channel without a dedicated clock signal transmission channel, and the high-speed peripheral component interconnect bus optical transmission system determines a local target clock signal by processing a target frequency precision threshold value obtained, provides a local control clock for the local high-speed peripheral component interconnect communication module through the local target clock signal, and realizes high-precision and low-delay synchronous transmission of data of the first communication end and the second communication end.

Description

Technical Field

[0001] This invention relates to the field of optical communication technology, and in particular to a high-speed peripheral component interconnection bus optical transmission system and method. Background Technology

[0002] In high-performance computing (HPC) and data center interconnect scenarios spanning racks or regions, the high-speed peripheral component interconnect (PCIe) bus, as an internal interconnect standard, faces physical transmission distance limitations due to signal loss and timing constraints. To overcome this limitation, the industry commonly uses fiber optic media to extend PCIe links, enabling long-distance, low-loss data transmission. However, when the PCIe bus is physically extended via fiber optics, the synchronization of its reference clock becomes a critical bottleneck restricting system performance. Existing technologies mainly develop in two directions: one is a physical pass-through scheme, which directly transmits the master clock signal from one end to the remote end via fiber optics, hoping to recover the same clock at the receiving end; the other is a conventional independent clock scheme, which configures local crystal oscillators at both the transmitting and receiving ends, relying on the elastic buffer and idle character insertion mechanism built into the PCIe protocol layer to absorb the frequency deviation between the two clocks.

[0003] Both of the aforementioned existing technologies suffer from insurmountable drawbacks in practical applications. For physical pass-through schemes, due to the bandwidth limitations of photoelectric conversion devices and the dispersion effect during fiber transmission, the transmitted clock signal is superimposed with significant high-frequency phase noise during remote recovery. Its jitter performance often fails to meet the stringent jitter requirements of PCIe 5.0 (32GT / s) and PCIe 6.0 (64GT / s PAM4 modulation) for the reference clock (RefClk). Even with high-performance clock recovery circuits, the nonlinear distortion and temperature drift introduced by the optical transmission channel still degrade clock quality, making it difficult to guarantee the reliability of this scheme at high-order modulation rates. For conventional independent clock schemes, both the transmitting and receiving ends use ordinary crystal oscillators (typically with a frequency deviation on the order of ±300ppm). Due to the lack of any frequency synchronization mechanism, there is a large relative frequency offset between the clocks at both ends. To address this frequency offset, the PCIe link layer must maintain a deep elastic buffer depth and frequently send skipped ordered sets (SKPs) for clock compensation. While this compensation mechanism maintains link connectivity, it introduces additional transmission latency and reduces the effective bandwidth of the link due to frequent interruptions in effective data transmission, failing to meet the demands of high-performance computing scenarios requiring low latency and high throughput. Therefore, existing technologies lack a system solution capable of achieving high-precision relative synchronization of reference clocks at both transmitting and receiving ends through purely hardware means, while ensuring that the clock electrical characteristics conform to high-end clock specifications such as CK440, even when the physical clock transmission channel is severed. Summary of the Invention

[0004] This invention provides a high-speed peripheral component interconnection bus optical transmission system and method, which solves the problems of low synchronization accuracy and large delay in high-speed peripheral component interconnection optical transmission.

[0005] To solve the above-mentioned technical problems, the technical solution of the present invention is as follows: This invention provides a high-speed peripheral component interconnect bus optical transmission system, comprising: a physically separated first communication terminal and a second communication terminal; The first communication terminal includes: a first clock synchronization subsystem and a first high-speed peripheral component interconnection communication module that communicates with the first clock synchronization subsystem; The second communication terminal includes: a second clock synchronization subsystem and a second high-speed peripheral component interconnection communication module that communicates with the second clock synchronization subsystem; The first high-speed peripheral component interconnection communication module and the second high-speed peripheral component interconnection communication module are connected via a data fiber optic channel. The first clock synchronization subsystem performs symmetry calibration on the electrical characteristics of the first reference clock signal of the first communication terminal according to the target frequency accuracy threshold to obtain the first target clock signal; The second clock synchronization subsystem performs symmetry calibration on the electrical characteristics of the second reference clock signal of the second communication terminal according to the target frequency accuracy threshold to obtain the second target clock signal; the deviation between the second target clock signal and the first target clock signal is less than a preset threshold. The first high-speed peripheral component interconnection communication module sends first service data to the second high-speed peripheral component interconnection communication module through the data fiber optic channel according to the first target clock signal, and receives second service data sent by the second high-speed peripheral component interconnection communication module through the data fiber optic channel according to the second target clock signal.

[0006] Optionally, the first clock synchronization subsystem includes: The first oscillation module is used to determine the configuration parameters of the first oscillation module according to the first target frequency accuracy threshold, perform homologous configuration of the first oscillation module according to the configuration parameters of the first oscillation module, and output the first reference clock signal. The first de-jitter phase-locked loop module connected to the first oscillation module is used to determine the first local loop configuration parameters according to the first reference clock signal, and to perform filtering and frequency standardization processing on the first reference clock signal according to the first local loop configuration parameters, and output the first reference clock signal. A first level matching output module connected to the first dejittering phase-locked loop module, the output terminal of the first level matching output module being connected to the reference clock input terminal of the first high-speed peripheral component interconnection communication module, is used to determine the calibration parameters of the matching circuit of the first local level matching output module according to the first local reference clock signal, perform symmetry calibration processing on the electrical characteristics of the first local reference clock signal according to the calibration parameters of the local matching circuit of the first level matching output module, and output a first target clock signal to the first high-speed peripheral component interconnection communication module.

[0007] Optionally, the first debouncing phase-locked loop module includes: The first jitter attenuator, the input of which is used to receive the first reference clock signal; The first loop filter has its input connected to the output of the first jitter attenuator. The first loop filter is used to filter out near-end spurious signals and power domain broadband noise from the first reference clock signal to obtain a filtered clock signal. The first fractional frequency divider has its input connected to the output of the first loop filter. The first fractional frequency divider is used to perform low-noise frequency conversion on the filtered clock signal and output a first reference clock signal.

[0008] Optionally, the first de-jittering phase-locked loop module configures its parameters according to a preset phase noise template, so that the loop bandwidth of the first loop filter is set within a preset frequency band.

[0009] Optionally, the first level matching output module includes: A first low-voltage differential signal matching network is used to calibrate the voltage swing, common-mode voltage, and slew rate of the first reference clock signal.

[0010] This invention also provides a high-speed peripheral component interconnect bus optical transmission method, applied to the first communication end of the aforementioned high-speed peripheral component interconnect bus optical transmission system, the method comprising: Obtain the target frequency accuracy threshold; The configuration parameters of the first oscillation module are determined based on the target frequency accuracy threshold. Based on the configuration parameters of the first oscillation module, the first oscillation module is configured in the same source to obtain the first reference clock signal; The first loop configuration parameters are determined based on the first reference clock signal; Based on the first loop configuration parameters, the first reference clock signal is filtered and frequency standardized to obtain the first reference clock signal. The calibration parameters of the first level matching output module are determined based on the first reference clock signal; Based on the calibration parameters of the first level matching output module, the electrical characteristics of the first reference clock signal are symmetrically calibrated to obtain the first target clock signal; Based on the first target clock signal, control the first high-speed peripheral component interconnection communication module and the second high-speed peripheral component interconnection communication module to perform service data transmission.

[0011] Optionally, the configuration parameters of the first oscillation module are determined based on the first target frequency accuracy threshold, including: Obtain the full operating temperature range and device aging compensation index of the first communication terminal; Based on the target frequency accuracy threshold and the full operating temperature range, the temperature stability parameters of the first communication terminal are determined; Based on the preset maximum relative frequency offset threshold and the device aging compensation index, the frequency calibration parameters and stability compensation parameters of the first oscillation module are determined. The temperature stability parameters, frequency calibration parameters, and stability compensation parameters are integrated to obtain the configuration parameters of the first oscillation module.

[0012] Optionally, based on the configuration parameters of the first oscillation module, the first oscillation module is configured to be source-compatible to obtain a first reference clock signal, including: Based on the configuration parameters of the first oscillation module, the first oscillation module is subjected to constant temperature control to obtain a temperature-stable original oscillation signal; The original oscillation signal is calibrated at the center frequency and compensated for aging drift to obtain a pre-reference signal; The pre-reference signal is subjected to frequency consistency verification to obtain a first reference clock signal, and the relative frequency deviation of the first reference clock signal meets the preset constraint conditions.

[0013] Optionally, based on the first reference clock signal, the first loop configuration parameters are determined, including: Obtain the preset phase noise template, the transfer function of the clock data recovery circuit, the link equalization capability parameters, and the standard reference clock frequency; Based on the center frequency and phase noise template of the first reference clock signal, the loop bandwidth range and phase margin interval of the dejitter phase-locked loop are determined. Based on the transfer function and link equalization capability parameters of the clock data recovery circuit, the optimal loop parameters are determined within the loop bandwidth range and phase margin interval. The fractional frequency division coefficient of the dejitter phase-locked loop is determined based on the center frequency of the first reference clock signal and the standard reference clock frequency. The optimal loop parameters and fractional frequency division coefficients are integrated to obtain the first loop configuration parameters.

[0014] Optionally, based on the first loop configuration parameters, the first reference clock signal is filtered and frequency normalized to obtain a first reference clock signal, including: Based on the configuration parameters of the first loop, the first de-jitter phase-locked loop module is initialized and calibrated to obtain the first de-jitter phase-locked loop module after initialization and calibration. Based on the first dejitter phase-locked loop module after initialization and calibration, the first reference clock signal is filtered to obtain a filtered clock signal. The filtered clock signal is divided by frequency to obtain a frequency-divided clock signal; The frequency-divided clock signal is subjected to verification processing to obtain the first reference clock signal.

[0015] The technical solution of the present invention has at least the following effects: The high-speed peripheral component interconnect bus optical transmission system of the present invention includes a physically separated first communication terminal and a second communication terminal; the first communication terminal includes: a first clock synchronization subsystem and a first high-speed peripheral component interconnect communication module communicating with the first clock synchronization subsystem; the second communication terminal includes: a second clock synchronization subsystem and a second high-speed peripheral component interconnect communication module communicating with the second clock synchronization subsystem; the first high-speed peripheral component interconnect communication module and the second high-speed peripheral component interconnect communication module are connected via a data fiber optic channel; the first clock synchronization subsystem performs symmetry calibration processing on the electrical characteristics of a first reference clock signal of the first communication terminal according to a target frequency accuracy threshold to obtain a first target clock. The second clock synchronization subsystem performs symmetry calibration on the electrical characteristics of the second reference clock signal of the second communication terminal according to the target frequency accuracy threshold to obtain the second target clock signal; the deviation between the second target clock signal and the first target clock signal is less than a preset threshold; the first high-speed peripheral component interconnection communication module sends first service data to the second high-speed peripheral component interconnection communication module through the data fiber optic channel according to the first target clock signal, and receives second service data sent by the second high-speed peripheral component interconnection communication module through the data fiber optic channel according to the second target clock signal, thereby realizing high-precision, low-latency synchronous transmission of data between the first communication terminal and the second communication terminal. Attached Figure Description

[0016] Figure 1 This is a structural diagram of the high-speed peripheral component interconnect bus optical transmission system provided in an embodiment of the present invention; Figure 2This is a circuit diagram of the level matching output module of the high-speed peripheral component interconnect bus optical transmission system provided in this embodiment of the invention; Figure 3 This is a flowchart of a high-speed peripheral component interconnection bus optical transmission method provided in an embodiment of the present invention. Detailed Implementation

[0017] Exemplary embodiments of the invention will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this invention will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0018] like Figure 1 As shown, an embodiment of the present invention proposes a high-speed peripheral component interconnect bus optical transmission system, comprising: a physically separated first communication terminal and a second communication terminal; The first communication terminal includes: a first clock synchronization subsystem and a first high-speed peripheral component interconnection communication module that communicates with the first clock synchronization subsystem; The second communication terminal includes: a second clock synchronization subsystem and a second high-speed peripheral component interconnection communication module that communicates with the second clock synchronization subsystem; The first high-speed peripheral component interconnection communication module and the second high-speed peripheral component interconnection communication module are connected via a data fiber optic channel. The first clock synchronization subsystem performs symmetry calibration on the electrical characteristics of the first reference clock signal of the first communication terminal according to the target frequency accuracy threshold to obtain the first target clock signal; The second clock synchronization subsystem performs symmetry calibration on the electrical characteristics of the second reference clock signal of the second communication terminal according to the target frequency accuracy threshold to obtain the second target clock signal; the deviation between the second target clock signal and the first target clock signal is less than a preset threshold. The first high-speed peripheral component interconnection communication module sends first service data to the second high-speed peripheral component interconnection communication module through the data fiber optic channel according to the first target clock signal, and receives second service data sent by the second high-speed peripheral component interconnection communication module through the data fiber optic channel according to the second target clock signal.

[0019] In this embodiment, the high-speed peripheral component interconnect bus optical transmission system can be applied to high-performance computing interconnection scenarios across racks and regions. It is compatible with high-speed serial bus specifications of PCIe 5.0, PCIe 6.0, and subsequent iterations, solving the technical problems of insufficient clock synchronization accuracy, high transmission latency, and strong coupling between clock quality and transmission distance in existing PCIe optical transmission solutions. The system includes a first communication end and a second communication end physically separated from each other. The first and second communication ends are two peer communication nodes of the system, without a master-slave architecture distinction. Both ends are equipped with a clock synchronization subsystem and a high-speed peripheral component interconnect communication module with identical structure and symmetrical hardware parameters. The clock synchronization subsystem provides a local reference clock conforming to the PCIe CK440 high-standard clock specification for both nodes, serving as the hardware carrier for achieving relative synchronization without a clock. Its output is directly connected to the reference clock input of the high-speed peripheral component interconnect communication module, providing a stable and compliant operating clock reference for the communication module. The high-speed peripheral component interconnect communication module is used to complete the link layer processing, physical layer transmission and reception, and photoelectric signal conversion of PCIe service data, serving as the execution carrier for cross-end data interaction.

[0020] After the system is powered on, the first clock synchronization subsystem and the second clock synchronization subsystem synchronously execute signal processing procedures, specifically including: obtaining a target frequency accuracy threshold; determining the configuration parameters of the oscillation modules of the first and second communication terminals based on the target frequency accuracy threshold; configuring the oscillation modules of the first and second communication terminals in a common source configuration according to the configuration parameters to obtain a reference clock signal; determining local loop configuration parameters based on the reference clock signal; filtering and frequency standardizing the local reference clock signal according to the local loop configuration parameters to obtain a local reference clock signal; determining local matching circuit calibration parameters based on the local reference clock signal; performing symmetry calibration on the electrical characteristics of the local reference clock signal according to the local matching circuit calibration parameters to obtain a local target clock signal; wherein, the local target clock signal includes a first target clock signal and a second target clock signal, and the deviation between the first target clock signal and the second target clock signal is less than ≤1ppm; and controlling the two high-speed peripheral component interconnection communication modules to perform synchronous data transmission based on the local target clock signal.

[0021] Since the first and second communication ends are connected only through a data fiber optic channel, which is a non-dedicated clock signal transmission channel, only PCIe service data streams are transmitted within the channel. No clock signals, frequency correction signals, or clock discipline feedback signals used for synchronization between the two ends are transmitted, eliminating the impact of dispersion and crosstalk in the optical transmission link on clock signal quality and achieving decoupling of clock synchronization performance from transmission distance. During system operation, both ends independently generate their local reference clocks through symmetrically configured clock synchronization subsystems. This allows bilateral synchronization misalignment to be controlled within ≤1ppm without cross-end clock interaction, supporting the rapid completion of link training by the high-speed peripheral component interconnection communication modules at both ends, enabling them to enter a low-latency synchronous data transmission state.

[0022] This invention proposes the above-mentioned technical solution, which involves configuring identical clock synchronization subsystems at physically separated first and second communication ends. Based on a target frequency accuracy threshold, the oscillation modules at both ends are configured in a homogeneous manner to obtain a reference clock signal. Then, local loop parameters are determined based on the reference clock signal, and filtering and frequency standardization are performed on the signal to obtain a reference clock signal. Subsequently, matching circuit calibration parameters are determined based on the reference clock signal, and the electrical characteristics of the reference clock signal are symmetrically calibrated to obtain a local target clock signal. This provides a control clock for the local high-speed peripheral component interconnection communication module, and the two ends transmit service data only through a data fiber optic channel, without setting up a dedicated clock signal transmission channel. This achieves the goal of controlling the relative frequency offset between the two ends within a small range under the condition of cross-end transmission without a clock signal, ensuring that the output clock meets the requirements of the high-speed peripheral component interconnection bus specification, reducing the difficulty of link equalization processing, reducing data transmission latency, improving the effective bandwidth utilization of the link, and maintaining compatibility with standard high-speed peripheral component interconnection devices, enabling stable data synchronization transmission between the two ends.

[0023] In an optional embodiment of the present invention, the first clock synchronization subsystem includes: The first oscillation module is used to determine the configuration parameters of the first oscillation module according to the first target frequency accuracy threshold, perform homologous configuration of the first oscillation module according to the configuration parameters of the first oscillation module, and output the first reference clock signal. The first de-jitter phase-locked loop module connected to the first oscillation module is used to determine the first local loop configuration parameters according to the first reference clock signal, and to perform filtering and frequency standardization processing on the first reference clock signal according to the first local loop configuration parameters, and output the first reference clock signal. A first level matching output module connected to the first dejittering phase-locked loop module, the output terminal of the first level matching output module being connected to the reference clock input terminal of the first high-speed peripheral component interconnection communication module, is used to determine the calibration parameters of the matching circuit of the first local level matching output module according to the first local reference clock signal, perform symmetry calibration processing on the electrical characteristics of the first local reference clock signal according to the calibration parameters of the local matching circuit of the first level matching output module, and output a first target clock signal to the first high-speed peripheral component interconnection communication module.

[0024] The first debouncing phase-locked loop module includes: The first jitter attenuator, the input of which is used to receive the first reference clock signal; The first loop filter has its input connected to the output of the first jitter attenuator. The first loop filter is used to filter out near-end spurious signals and power domain broadband noise from the first reference clock signal to obtain a filtered clock signal. The first fractional frequency divider has its input connected to the output of the first loop filter. The first fractional frequency divider is used to perform low-noise frequency conversion on the filtered clock signal and output a first reference clock signal.

[0025] The first de-jitter phase-locked loop module configures its parameters according to a preset phase noise template, so that the loop bandwidth of the first loop filter is set within a preset frequency band.

[0026] The first level matching output module includes: A first low-voltage differential signal matching network is used to calibrate the voltage swing, common-mode voltage, and slew rate of the first reference clock signal.

[0027] In this embodiment, the clock synchronization subsystem is deployed within the physically separated first and second communication terminals. The clock synchronization subsystems of the two communication terminals adopt a completely symmetrical hardware architecture and parameter configuration, serving as the hardware carrier for achieving relative synchronization between the two communication terminals under conditions where there is no dedicated clock signal transmission channel. Specifically, taking the first clock synchronization subsystem as an example, the first clock synchronization subsystem consists of a first oscillation module, a first dejittering phase-locked loop module, and a first level matching output module connected in sequence. The three modules form a cascaded signal processing link, with the output signal of the previous module serving as the input signal of the next module, forming a local clock generation and calibration link, without any cross-fiber clock signal interaction or frequency feedback throughout the entire process.

[0028] The first oscillation module provides a frequency reference for the first clock synchronization subsystem. Its function is to output a reference clock signal with a frequency accuracy meeting preset requirements, forming the physical basis for achieving transmission-free relative synchronization. The main hardware component of the first oscillation module is a dual-crystal controlled crystal oscillator, specifically preferably a Connor-Winfield DOC10 series 10MHz dual-crystal controlled crystal oscillator. The initial frequency error of the dual-crystal controlled crystal oscillator is less than 0.5ppm. This model of dual-crystal controlled crystal oscillator exhibits a center frequency temperature stability better than ±0.2ppm within its full operating temperature range of -40℃ to 85℃, fully meeting the initial frequency accuracy requirements. Its nominal 10MHz output frequency is a common reference frequency for high-precision clock systems and can be well-matched with the subsequent de-jittering phase-locked loop module. The dual-temperature-controlled crystal oscillator, through a dual-closed-loop temperature control structure, suppresses crystal resonant frequency drift caused by ambient temperature changes within the full operating temperature range of -40℃ to 85℃. This ensures that the temperature stability of the center frequency remains within a preset range, guaranteeing that the output reference clock signals of the two independently operating oscillator modules are naturally in quasi-synchronous frequency state without any cross-terminal communication interaction. The first reference clock signal output by the first oscillator module is directly transmitted to the input of the subsequent first de-jittering PLL module, serving as its input reference signal.

[0029] The first jitter-reducing phase-locked loop (PLL) module is used for signal reconstruction of the first clock synchronization subsystem. It receives the reference clock signal output from the front-end oscillation module and outputs a low-jitter local reference clock signal conforming to the high-speed peripheral component interconnect bus clock specification. The first jitter-reducing PLL module includes a first jitter attenuator, a first loop filter, and a first fractional divider connected in sequence. The input of the first jitter attenuator receives the reference clock signal output from the first oscillation module, completing preliminary phase locking and jitter attenuation of the clock signal, providing a phase-stable input signal for subsequent filtering. Specifically, the first jitter attenuator includes a digital frequency and phase detector, a charge pump, and a phase-lock detection unit. The first input of the digital frequency and phase detector receives the reference clock signal output from the first oscillation module, and the second input receives the divided clock signal fed back from the first fractional divider. The output of the digital frequency and phase detector is connected to the input of the charge pump, used to detect the frequency difference and phase difference between the input reference clock signal and the feedback clock signal, and outputs a pulse signal corresponding to the difference. The output of the charge pump is connected to the input of the loop filter to convert the pulse signal output by the phase-frequency discriminator into an analog voltage signal of corresponding amplitude. The input of the phase-locked loop detection unit is connected to the output of the digital phase-frequency discriminator to detect the phase-locked loop's phase-locked state in real time. When the lock state meets preset requirements, a lock indication signal is output to the subsequent circuit. The input of the first loop filter is connected to the output of the jitter attenuator, and its function is to filter out near-end spurious signals and broadband noise in the power supply domain from the reference clock signal. The loop bandwidth and phase margin parameters of the first loop filter are not universally configured, but are specifically optimized based on the CK440 or CK441 phase noise template. The loop bandwidth is set in the range of 200kHz to 400kHz. This setting matches the transfer function of the clock data recovery circuit at the high-speed peripheral component interconnect bus receiver, effectively attenuating low-frequency drift of the reference clock signal and filtering out high-frequency thermal noise, ensuring that the phase noise characteristics of the output signal fully comply with the bus specification requirements. The loop filter specifically adopts a third-order passive RC loop filter. The input of the first loop filter is connected to the output of the charge pump, and the output of the first loop filter is connected to the control terminal of the voltage-controlled oscillator of the first fractional divider. The resistor and capacitor parameters of the third-order passive RC loop filter are matched according to the preset 200kHz to 400kHz loop bandwidth and 45° to 60° phase margin. Through the frequency response characteristics of the RC network, high-frequency ripple, near-end spurious components, and broadband noise coupled to the power supply domain in the charge pump output voltage are filtered out, and a smooth DC control voltage is output to the voltage-controlled oscillator. The input of the first fractional frequency divider is connected to the output of the first loop filter. Its function is to perform low-noise frequency conversion on the filtered clock signal and output the first reference clock signal.The first fractional frequency divider adopts a fractional frequency division working mode, which can multiply the low-frequency reference clock signal input from the front end to the 100MHz standard reference clock frequency required by the high-speed peripheral component interconnect bus while maintaining an extremely low phase noise floor. This solves the problem of mismatch between the output frequency of the high-precision oscillator and the standard clock frequency of the bus, and ensures that the frequency of the output clock is fully adapted to the operating requirements of the standard commercial high-speed peripheral component interconnect controller and physical layer chip. The first fractional frequency divider specifically includes: The system comprises a modulator, a multi-mode frequency divider, and a low-noise voltage-controlled oscillator (VCO). The control terminal of the VCO is connected to the output of the loop filter, used to generate an oscillation clock signal of the corresponding frequency based on the DC control voltage output from the first loop filter. The input terminal of the multi-mode frequency divider is connected to the output of the VCO, and the division ratio control terminal of the multi-mode frequency divider is connected to... The output of the modulator is connected to, for use with respect to... The frequency division ratio control word output by the modulator dynamically divides the clock signal output by the voltage-controlled oscillator. The modulator receives a preset fractional division ratio command and uses high-order noise shaping technology to push the quantization noise of the division ratio to a higher frequency band. This, combined with the first loop filter, removes noise and achieves low-phase-noise fractional division. The output of the multi-mode divider is fed back to the second input of the digital frequency and phase detector in the jitter attenuator, forming a closed-loop feedback loop for the phase-locked loop. The output of the low-noise voltage-controlled oscillator serves as the output of the fractional divider, outputting a first reference clock signal with the required frequency. The first reference clock signal output by the first de-jittering phase-locked loop module is directly transmitted to the input of the subsequent first level matching output module, serving as its input signal.

[0030] like Figure 2As shown, the first level matching output module is used for output calibration of the clock synchronization subsystem. Its output terminal is connected to the reference clock input terminal of the first high-speed peripheral component interconnection communication module. Its function is to output the first target clock signal after electrical characteristic symmetry calibration. The hardware of the first level matching output module is a low-voltage differential signal matching network. The function of the low-voltage differential signal matching network is to calibrate the voltage swing, common-mode voltage, and slew rate of the local reference clock signal. The low-voltage differential signal matching network performs closed-loop calibration of the electrical parameters of the output clock signal through hardware resistor fine-tuning or digital-to-analog converter circuit current control, forcing the first target clock signal output from both communication terminals to maintain a high degree of consistency in the three parameters of voltage swing, common-mode voltage, and slew rate, achieving a 1:1 mirror match. The low-voltage differential signal matching network specifically includes an HCSL differential drive circuit, a programmable impedance calibration unit, a multi-channel digital-to-analog converter current control unit, and a terminating matching resistor network. The HCSL differential drive circuit receives the first reference clock signal from the first de-jittering PLL module at its input. The power supply of the HCSL differential drive circuit is connected to the output of the multi-channel digital-to-analog converter current control unit. The control unit adjusts the bias current of the drive circuit to calibrate the conversion rate of the output clock signal. A programmable impedance calibration unit is connected to the output of the HCSL differential drive circuit. Through hardware resistor fine-tuning or on-chip one-time programmable adjustment, it adjusts the on-resistance of the output differential pair and the resistance value of the terminating matching resistor to calibrate the differential voltage swing and common-mode voltage of the output clock signal. The terminating matching resistor network adopts... The single-ended characteristic impedance design matches the on-chip terminating resistor at the reference clock input of the high-speed peripheral component interconnect (PBI) physical layer chip, reducing signal reflection and ensuring clock signal integrity. The nominal value of the differential voltage swing is set to 750mV with a deviation controlled within 1%, and the nominal value of the slew rate is set to 3.5V / ns with a deviation controlled within 5%. This mirror-level electrical parameter matching allows the PBI analog front-ends of the two high-speed PBI communication modules to operate in a highly symmetrical electrical environment, significantly reducing the complexity of link equalization and shortening the convergence time of link training. The local target clock signal output by the level matching output module is directly input to the reference clock input of the high-speed PBI communication module, providing a stable and compliant operating reference clock for the PBI communication module's physical layer chip and controller. This enables the two communication ends to complete link training and synchronous data transmission even without a dedicated clock signal transmission channel.

[0031] All signal processing in the entire clock synchronization subsystem is completed locally at a single communication end, without any cross-end clock signal transmission or frequency feedback. By using only the symmetrical hardware architecture and parameter configuration at both ends, the synchronization misalignment at both ends can be controlled within 1ppm, achieving relative synchronization under conditions without clock transmission. At the same time, it ensures that the output clock fully complies with the specifications of the high-speed peripheral component interconnect bus, achieving full compatibility with standard commercial equipment.

[0032] like Figure 3 As shown, an embodiment of the present invention proposes a high-speed peripheral component interconnect bus optical transmission method, applied to the first communication end of the aforementioned high-speed peripheral component interconnect bus optical transmission system. The method includes: Step 31: Obtain the first target frequency accuracy threshold; Step 32: Determine the configuration parameters of the first oscillation module based on the first target frequency accuracy threshold; Step 33: According to the configuration parameters of the first oscillation module, perform homogeneous configuration on the first oscillation module to obtain the first reference clock signal; Step 34: Determine the first loop configuration parameters based on the first reference clock signal; Step 35: Based on the first loop configuration parameters, filter and frequency standardize the first reference clock signal to obtain the first reference clock signal; Step 36: Determine the calibration parameters of the first level matching output module based on the first reference clock signal; Step 37: Based on the calibration parameters of the first level matching output module, perform symmetry calibration on the electrical characteristics of the first reference clock signal to obtain the first target clock signal; Step 38: Based on the first target clock signal, control the first high-speed peripheral component interconnection communication module and the second high-speed peripheral component interconnection communication module to transmit data.

[0033] In step 31 of this embodiment, after the system is powered on, the first clock synchronization subsystem and the second clock synchronization subsystem synchronously execute the signal processing process; therefore, the methods executed by the first clock synchronization subsystem and the second clock synchronization subsystem are completely identical. Taking the first clock synchronization subsystem as an example, the target frequency accuracy threshold of the first clock synchronization subsystem is determined comprehensively based on the maximum allowable relative frequency deviation required by the corresponding version specification of the high-speed peripheral component interconnect bus, the system's full operating temperature range, the long-term aging drift margin, and the link transmission distance requirements, providing a unified benchmark for the subsequent parameter configuration, loop parameter design, and electrical calibration of the oscillation module. The typical value of the target frequency accuracy threshold corresponds to a maximum allowable relative frequency deviation of no more than 1ppm at both ends, which can adapt to the synchronization requirements of high-speed serial buses such as PCIe 5.0 and PCIe 6.0. The threshold parameter can be pre-stored in the system's non-volatile storage unit, or customized parameters adapted to different application scenarios can be issued through the host computer configuration interface.

[0034] In step 32, the configuration parameters include the nominal center frequency of the oscillation module, the full-temperature range temperature stability parameters, the upper limit of the initial frequency error, the dual closed-loop isothermal control parameters, and the temperature drift compensation coefficient. All parameters are designed and matched with the target frequency accuracy threshold as a constraint. The typical value of the nominal center frequency is 10MHz, which is the common reference frequency for high-precision clock systems. The full-temperature range temperature stability parameters must be better than ±0.5ppm, and the upper limit of the initial frequency error must be less than 0.5ppm to meet the quasi-synchronous frequency requirement under conditions without cross-end clock feedback. The configuration parameters of the oscillation modules at the first and second communication ends are completely identical. After the parameters are determined, they are written into the storage unit of the matching control circuit of the oscillation modules at both ends to ensure that they can be directly called and executed after the system is powered on.

[0035] In step 33, the same-source configuration refers to the consistent offline frequency calibration and parameter configuration performed on the identical dual-temperature-controlled crystal oscillators at both ends under a unified constant-temperature environment and a unified traceability test benchmark before shipment. During the same-source configuration process, the initial frequency error of the crystals at both ends is corrected synchronously, and identical dual closed-loop constant-temperature control parameters and temperature drift compensation coefficients are configured. This ensures that the single-end frequency temperature stability of the oscillation modules at both ends is better than ±0.2ppm within the full operating temperature range of -40℃ to 85℃, and the initial relative frequency deviation at both ends is controlled within 0.3ppm. After the same-source configuration is completed, the oscillation modules at both ends start synchronously when the system is powered on, and independently output a stable reference clock signal, which is directly used as the input reference signal of the subsequent de-jittering phase-locked loop module, without any cross-end signal interaction throughout the process.

[0036] In step 34, the local loop configuration parameters are the operating parameters of the jitter-reducing PLL module, specifically including loop bandwidth, phase margin, and fractional divider coefficient. The loop bandwidth ranges from 200kHz to 400kHz, and the phase margin ranges from 45° to 60°. These parameters are determined comprehensively based on the center frequency of the reference clock signal, the CK440 or CK441 phase noise template of the high-speed peripheral component interconnect bus, and the transfer function of the receiver clock data recovery circuit. The fractional divider coefficient is calculated based on the center frequency of the reference clock signal and the standard reference clock frequency required by the bus specification to ensure low-noise frequency conversion. The local loop configuration parameters of the first and second communication ends are completely symmetrical, ensuring that the processing of the clock signals at both ends is completely consistent and avoiding the introduction of additional relative frequency offset.

[0037] In step 35, filtering is achieved using a third-order passive RC loop filter. Based on the determined loop bandwidth and phase margin, the corresponding resistor and capacitor parameters are matched to filter out near-end spurious signals, broadband noise coupled from the power domain, and crystal thermal noise, thus suppressing low-frequency drift. Frequency normalization is achieved using a fractional divider. Employing fractional divider operation, the reference clock signal is frequency-multiplied to the 100MHz standard reference clock frequency required by the high-speed peripheral component interconnect bus while maintaining an extremely low phase noise floor. This resolves the mismatch between the high-precision oscillator output frequency and the bus standard clock frequency. The jitter integration range is set to 12kHz to 20MHz, and the typical root mean square jitter of the output signal is controlled within 70fs, fully complying with bus specifications. The processed local reference clock signal is directly transmitted to the subsequent level matching output module.

[0038] In step 36, the calibration parameters include the nominal values ​​and permissible deviation ranges of the differential voltage swing, common-mode voltage, and slew rate of the clock signal. These parameters are determined comprehensively based on the electrical specifications of the HCSL interface physical layer of the high-speed peripheral component interconnect bus and the symmetrical matching requirements at both ends. The nominal value of the differential voltage swing is set to 750mV with a permissible deviation of no more than ±1%; the nominal value of the common-mode voltage is set to 0V with a permissible deviation of no more than ±50mV; and the nominal value of the slew rate is set to 3.5V / ns with a permissible deviation of no more than ±5%. The calibration parameters correspond to the control words of the programmable impedance calibration unit and the multi-channel digital-to-analog converter current control unit. The calibration parameters of the first communication terminal and the second communication terminal are completely consistent to ensure that the electrical characteristics of the output clocks at both ends achieve mirror matching.

[0039] In steps 37 and 38, the local target clock signal is used to provide a local control clock for the local high-speed peripheral component interconnect communication module, enabling synchronous data transmission between the first and second communication ends. The symmetry calibration process finely adjusts the on-resistance of the output differential pair and the value of the terminal matching resistor through hardware resistors, adjusts the bias current of the driver stage through the digital-to-analog converter circuit, and performs closed-loop calibration on the three parameters of differential voltage swing, common-mode voltage, and slew rate, ensuring that the output signal fully meets the preset parameter requirements. The calibrated local target clock signal is directly input to the reference clock input terminal of the physical layer chip of the local high-speed peripheral component interconnect communication module, providing a stable and compliant operating reference for the physical layer and controller. The relative frequency offset of the target clock signals at both ends is stably controlled within 1ppm, which is entirely within the phase tracking capability range of the clock data recovery circuit at the bus receiver. The link can complete phase locking and link training solely through the service data stream, without the need for frequent insertion of idle correction characters or deep elastic buffering, achieving low-latency, high-stability synchronous data transmission. The system transmits business data only through the data fiber optic channel throughout the entire process, without transmitting any clock signal or frequency correction signal, thus achieving cross-end synchronization without a dedicated clock signal transmission channel.

[0040] The technical solution described in this embodiment first obtains the target frequency accuracy threshold, matches and determines the configuration parameters of the oscillation modules of the first and second communication ends and completes the same-source configuration to obtain a reference clock signal that meets the accuracy requirements; then, based on the reference clock signal, it determines the local loop configuration parameters, performs filtering and frequency standardization processing on the reference clock signal, and obtains a local reference clock signal that conforms to the high-speed peripheral component interconnect bus specification; finally, it determines the matching circuit calibration parameters, performs symmetrical calibration on the electrical characteristics of the reference clock signal, and generates a local target clock signal. This technical means of eliminating cross-end clock signal transmission throughout the process achieves precise control of the relative frequency offset of the two communication ends, the output clock meets the requirements of the high-speed bus clock specification, reduces the difficulty of link equalization, reduces data transmission latency, improves the effective bandwidth utilization of the link, decouples the correlation between synchronization performance and transmission distance, and maintains compatibility with standard commercial bus equipment.

[0041] In an optional embodiment of the present invention, step 32, determining the configuration parameters of the first oscillation module based on the first target frequency accuracy threshold, may include: Step 321: Obtain the full operating temperature range and device aging compensation index of the first communication terminal; Step 322: Determine the temperature stability parameters of the first communication terminal based on the target frequency accuracy threshold and the full operating temperature range; Step 323: Determine the frequency calibration parameters and stability compensation parameters of the first oscillation module based on the preset maximum relative frequency offset threshold and the device aging compensation index; Step 324: Integrate the temperature stability parameters, frequency calibration parameters, and stability compensation parameters to obtain the configuration parameters of the first oscillation module.

[0042] In step 321 of this embodiment, the full operating temperature range is determined based on the application scenario and environmental adaptability requirements of the system, with a typical value of -40℃ to 85℃. The device aging compensation index is determined based on the system's design service life and long-term operational stability requirements. These two parameters provide complete boundary constraints for the parameter design of the oscillation module.

[0043] In step 322, the temperature stability parameter is the maximum allowable frequency drift of the oscillation module within the entire operating temperature range. The parameter value is allocated based on the target frequency accuracy threshold and the accuracy budget. A typical value is a frequency drift better than ±0.5ppm within the entire temperature range, which is adapted to the hardware characteristics of the dual constant temperature bath controlled crystal oscillator to ensure that the frequency fluctuation of the oscillation module within the entire operating temperature range does not exceed the allocated accuracy budget.

[0044] In step 323, the frequency calibration parameter is the center frequency correction amount when the oscillation module leaves the factory, and the stability compensation parameter is the aging drift compensation coefficient during the long-term operation of the oscillation module. The two parameters together constrain the frequency deviation of the oscillation module throughout its entire life cycle, ensuring that the relative frequency deviation at both ends never exceeds the preset maximum relative frequency deviation threshold.

[0045] In step 324, the integrated configuration parameters are completely consistent in the first communication terminal and the second communication terminal. The parameters are pre-stored in the non-volatile storage units of the oscillation modules at both ends, providing a unified execution basis for the same configuration of the oscillation modules at both ends.

[0046] In an optional embodiment of the present invention, step 33, configuring the first oscillation module according to its configuration parameters to obtain a first reference clock signal, may include: Step 331: According to the configuration parameters of the first oscillation module, perform constant temperature control on the first oscillation module to obtain a temperature-stable original oscillation signal; Step 332: Perform center frequency calibration and aging drift compensation on the original oscillation signal to obtain a pre-reference signal; Step 333: Perform frequency consistency verification on the pre-reference signal to obtain a first reference clock signal. The relative frequency offset of the first reference clock signal meets the preset constraint conditions.

[0047] In step 331 of this embodiment, the oscillation module adopts a dual closed-loop constant temperature control structure. Based on the temperature stability parameters in the configuration parameters, the working temperature of the crystal resonator unit is stabilized at a preset constant value, and the temperature fluctuation is controlled within ±0.1℃. Within the full working temperature range of -40℃ to 85℃, the drift of the crystal resonator frequency caused by changes in ambient temperature is suppressed. The constant temperature control parameters of the first communication terminal and the second communication terminal are completely consistent, ensuring that the working environment of the two oscillation modules is highly symmetrical and outputting a stable original oscillation signal.

[0048] In step 332, based on the frequency calibration parameters in the configuration parameters, the center frequency of the original oscillation signal is calibrated in a closed loop under a traceable unified frequency reference to correct the initial frequency error of the crystal; based on the stability compensation parameters in the configuration parameters, the frequency aging drift during the entire life cycle of the crystal is pre-compensated by the preset aging drift compensation coefficient, and the initial single-ended frequency error after calibration is less than 0.5ppm, thus obtaining a pre-reference signal with the required frequency accuracy.

[0049] In step 333, under a uniform constant temperature and uniform test standard environment, the frequency of the pre-reference signal output by the first communication terminal is compared and verified. The relative frequency deviation of the pre-reference signal satisfies the following constraints: ; in, The relative frequency offset between the first communication terminal and the output reference clock signal. The actual frequency of the reference clock signal output by the local oscillator source at the first communication terminal. The nominal value of the center frequency of the reference clock signal. The preset target relative frequency offset threshold is used; after the verification is passed, a reference clock signal with a relative frequency offset that meets the requirements is obtained, providing a stable frequency reference for subsequent clock processing.

[0050] In an optional embodiment of the present invention, step 34, determining the first loop configuration parameters based on the first reference clock signal, may include: Step 341: Obtain the preset phase noise template, the transfer function of the clock data recovery circuit, the link equalization capability parameters, and the standard reference clock frequency; Step 342: Determine the loop bandwidth range and phase margin range of the dejitter phase-locked loop based on the center frequency and phase noise template of the first reference clock signal. Step 343: Determine the optimal loop parameters within the loop bandwidth range and phase margin interval based on the transfer function and link equalization capability parameters of the clock data recovery circuit. Step 344: Determine the fractional frequency division coefficient of the dejitter phase-locked loop based on the center frequency of the first reference clock signal and the standard reference clock frequency; Step 345: Integrate the optimal loop parameters and fractional frequency division coefficients to obtain the first loop configuration parameters.

[0051] In step 341 of this embodiment, the phase noise template adopts the CK440 or CK441 phase noise template defined by the high-speed peripheral component interconnect bus specification. The transfer function of the clock data recovery circuit is the inherent transfer characteristic of the clock recovery circuit built into the commercial standard physical layer chip. The link equalization capability parameter is the insertion loss, dispersion and crosstalk characteristic parameter of the optical transmission link. The standard reference clock frequency is the 100MHz nominal frequency required by the bus specification. All parameters are pre-stored in the system storage unit, providing complete design input for loop parameter design.

[0052] In step 342, the typical value of the loop bandwidth range is 200kHz to 400kHz, and the typical value of the phase margin range is 45° to 60°. The parameter range is determined comprehensively based on the center frequency of the reference clock signal and the in-band and out-of-band noise requirements of the phase noise template to ensure that the phase-locked loop can effectively suppress in-band low-frequency drift and out-of-band high-frequency noise and meet the constraint requirements of the phase noise template.

[0053] In step 343, the optimal loop parameters are the combination of loop bandwidth and phase margin that match the noise transmission characteristics of the clock data recovery circuit and the link equalization capability. This allows the jitter characteristics of the phase-locked loop output clock to be matched with the tracking capability of the receiver recovery circuit, reducing the convergence difficulty of link equalization and improving the stability of link operation.

[0054] In step 344, the fractional frequency division coefficients satisfy the following constraints: ; in, The fractional frequency division coefficient, For standard reference clock frequency, The center frequency of the reference clock signal is used; by setting the fractional divider coefficient, the low-frequency reference frequency of the reference clock signal can be converted into the standard reference clock frequency required by the bus specification, thus solving the problem of mismatch between the reference source output frequency and the bus clock frequency.

[0055] In step 345, the integrated local loop configuration parameters are completely symmetrical in the first and second communication terminals. The parameters are pre-set in the configuration register of the dejitter phase-locked loop module, providing a unified execution basis for subsequent clock signal processing.

[0056] In an optional embodiment of the present invention, step 35, which involves filtering and frequency normalizing the first reference clock signal according to the first loop configuration parameters to obtain a first reference clock signal, may include: Step 351: According to the configuration parameters of the first loop, perform initialization calibration on the first de-jittering phase-locked loop module to obtain the first de-jittering phase-locked loop module after initialization calibration; Step 352: Based on the first dejittering phase-locked loop module after initialization and calibration, the first reference clock signal is filtered to obtain a filtered clock signal; Step 353: Perform frequency division processing on the filtered clock signal to obtain a frequency-divided clock signal; Step 354: Perform verification processing on the frequency-divided clock signal to obtain the first reference clock signal.

[0057] In step 351 of this embodiment, the initialization calibration process includes writing the optimal loop parameters and fractional frequency division coefficients into the configuration register of the phase-locked loop module, completing the power-on reset of the phase-locked loop, charge pump leakage calibration and voltage-controlled oscillator linearity calibration, eliminating parameter errors caused by device manufacturing deviations, and ensuring that the actual operating parameters of the phase-locked loop are completely consistent with the preset configuration parameters.

[0058] In step 352, the filtering process is achieved through a third-order passive RC loop filter. Based on the preset loop bandwidth and phase margin parameters, the filter removes near-end spurious noise, broadband noise coupled to the power domain, and crystal thermal noise from the reference clock signal, suppresses low-frequency drift of the signal, and outputs a filtered clock signal with smooth phase and noise level that meets the preset phase noise template requirements.

[0059] In step 353, the frequency division process is performed through... The modulator-controlled multimode fractional divider performs low-noise fractional division and multiplication on the filtered clock signal according to the preset fractional division coefficient, converting the center frequency of the reference clock signal to the 100MHz standard reference clock frequency required by the high-speed peripheral component interconnect bus specification, thus obtaining a divided clock signal with the required frequency accuracy.

[0060] In step 354, the verification process includes closed-loop detection of the frequency accuracy, phase noise, and root mean square jitter of the frequency-divided clock signal. The root mean square jitter of the output signal satisfies the following constraints: ; in, This represents the root mean square jitter value of the clock signal after frequency division. The frequency is the lower limit of the dither integral. The maximum frequency for jitter integration. The single-sideband phase noise power spectral density of the signal. This is the maximum permissible jitter threshold specified in the bus specification; after verification, a local reference clock signal is obtained that meets the requirements of the bus specification in terms of both jitter and frequency.

[0061] In an optional embodiment of the present invention, step 36, determining the calibration parameters of the first level matching output module based on the first reference clock signal, may include: Step 361: Obtain the electrical specifications of the physical layer interface of the high-speed peripheral component interconnect bus, the symmetry matching requirements of the two communication ends, and the signal integrity constraints. Step 362: Based on the electrical specifications and symmetry matching requirements, determine the nominal values ​​and allowable deviation ranges of the differential voltage swing, common-mode voltage, and slew rate of the local reference clock signal; Step 363: Based on the nominal value and allowable deviation range, determine the control word of the programmable impedance calibration unit and the multi-channel digital-to-analog conversion current control unit to obtain the calibration parameters of the first level matching output module.

[0062] In step 361 of this embodiment, the electrical specification of the physical layer interface of the high-speed peripheral component interconnect bus is the low-voltage differential signal interface electrical standard defined in the corresponding version of the bus. The symmetrical matching requirement of the two communication ends is the design requirement of 1:1 mirror matching of the electrical characteristics of the output clock signals at both ends in the scenario without a dedicated clock transmission channel. The signal integrity constraint index is the characteristic impedance matching of the clock transmission link, the signal reflection suppression and anti-interference capability requirements. The three parameters together provide complete design constraints for the determination of calibration parameters.

[0063] In step 362, the nominal value of the differential voltage swing is set to 750mV, with an allowable deviation of no more than ±1%; the nominal value of the common-mode voltage is set to 0V, with an allowable deviation of no more than ±50mV; and the nominal value of the slew rate is set to 3.5V / ns, with an allowable deviation of no more than ±5%. The nominal values ​​of all parameters simultaneously comply with the bus electrical specifications and symmetrical matching requirements. The allowable deviation range meets the preset constraints of the comprehensive matching degree of the electrical characteristics of the clock signals at both ends. The constraint formula is as follows: ; In the formula, The overall electrical characteristic matching degree of the final reference clock signals at both ends; , These are the differential voltage swings of the final reference clock signals for the first and second communication terminals, respectively. , These are the conversion rates of the final reference clock signals for the first and second communication terminals, respectively. , These are the common-mode voltages of the final reference clock signals for the first and second communication terminals, respectively. , , These are the nominal values ​​for differential voltage swing, slew rate, and common-mode voltage, respectively. The preset minimum matching threshold ensures that the electrical characteristics of the output clocks at both ends are highly consistent.

[0064] In step 363, the control word of the programmable impedance calibration unit corresponds to the adjustment range of the output differential pair conduction impedance and the terminal matching resistor, which is used to calibrate the differential voltage swing and common mode voltage. The control word of the multi-channel digital-to-analog conversion current control unit corresponds to the output range of the drive stage bias current, which is used to calibrate the conversion rate. The control words of the first communication terminal and the second communication terminal are completely identical. The calibration parameters of the first level matching output module obtained after integration are preset in the system non-volatile storage unit.

[0065] In an optional embodiment of the present invention, step 37 involves performing symmetry calibration on the electrical characteristics of the first reference clock signal according to the calibration parameters of the first level matching output module to obtain the first target clock signal, including: Step 371: Based on the calibration parameters of the first level matching output module, the on-resistance of the output differential pair and the resistance value of the termination matching resistor are finely adjusted by hardware resistors to calibrate the differential voltage swing and common-mode voltage of the local reference clock signal. Step 372: Adjust the bias current of the driver stage through the digital-to-analog converter circuit to calibrate the conversion rate of the local reference clock signal; Step 373: Perform electrical characteristic consistency verification on the calibrated clock signal to ensure that the overall electrical characteristic matching degree of the clock signals output at both ends meets the preset requirements, and obtain the first target clock signal.

[0066] In step 371 of this embodiment, based on the impedance adjustment control word in the calibration parameters, the on-resistance of the low-voltage differential signal drive output differential pair and the resistance value of the output terminal matching resistor are adjusted through the on-chip one-time programmable hardware resistor fine-tuning process. This precisely controls the impedance characteristics of the output circuit, so that the differential voltage swing and common-mode voltage of the output clock signal converge to the preset nominal value range. At the same time, it ensures that the output impedance matches the 50-ohm characteristic impedance of the transmission line, reduces signal reflection, and ensures the integrity of clock signal transmission.

[0067] In step 372, based on the current control word in the calibration parameters, the static bias current of the low-voltage differential signal driver stage is adjusted through the multi-channel digital-to-analog converter circuit to change the conduction speed and output current capability of the driver transistor, thereby accurately calibrating the edge switching rate of the clock signal, stabilizing the switching rate within the preset nominal value range, avoiding electromagnetic interference problems caused by excessively fast switching rates, and insufficient timing margin problems caused by excessively slow switching rates, ensuring that the output characteristics of the driver circuits at both ends are highly consistent.

[0068] In step 373, the electrical characteristic consistency verification is performed on the calibrated clock signal to ensure that the comprehensive electrical characteristic matching degree of the clock signals output from both ends meets the preset requirements, thereby obtaining the local target clock signal. Under a unified test benchmark and constant temperature environment, the electrical parameter comparison test is performed on the calibrated clock signals of the first communication end and the second communication end to calculate the comprehensive electrical characteristic matching degree. After the verification is passed, a local target clock signal with symmetrical electrical characteristics and conforming to the bus specification is obtained, providing a stable reference clock benchmark for the local high-speed peripheral component interconnection communication module.

[0069] like Figures 1 to 3 As shown, a specific embodiment of the high-speed peripheral component interconnect bus optical transmission method provided by this invention is as follows: Step 1: Obtain the target frequency accuracy threshold, the full operating temperature range of the first and second communication terminals, and the device aging compensation parameters. Simultaneously, obtain the CK440 phase noise template defined by the high-speed peripheral component interconnect bus specification, the transfer function of the physical layer clock data recovery circuit, link equalization capability parameters, the 100MHz standard reference clock frequency, the HCSL low-voltage differential signal physical layer interface electrical specifications, and the symmetry matching requirements, signal integrity constraints, and differential transmission line impedance parameters of the two communication terminals. The parameters obtained in this step provide unified design constraints for subsequent configuration and calibration throughout the entire process. The target frequency accuracy threshold corresponds to a maximum allowable relative frequency deviation of no more than 1ppm at both ends; the full operating temperature range is -40℃ to 85℃, adapting to the requirements of industrial and commercial applications; the differential transmission line impedance parameter is a 100Ω differential characteristic impedance; and the transmission link design requirements for the matched level matching output module are also specified.

[0070] Step 2: Based on the target frequency accuracy threshold and the full operating temperature range, determine the temperature stability parameters of the oscillation modules at the first and second communication ends. Based on the preset maximum relative frequency deviation threshold and device aging compensation index, determine the frequency calibration parameters and stability compensation parameters of the oscillation modules. Integrate the temperature stability parameters, frequency calibration parameters, and stability compensation parameters to obtain unified configuration parameters for the oscillation modules at both ends. In this step, the temperature stability parameters are set to a frequency drift better than ±0.2ppm across the entire temperature range, and the frequency calibration parameters correspond to an initial frequency error of less than 0.5ppm at one end. The configuration parameters at both ends are completely identical, adapting to the hardware characteristics of the dual-temperature-controlled crystal oscillator and providing an execution basis for subsequent homogeneous configuration.

[0071] Step 3: performing dual closed-loop constant temperature control on the oscillation modules at both ends according to the configuration parameters, controlling the operating temperature fluctuation of the crystal resonance unit within ±0.1°C, suppressing frequency drift caused by ambient temperature changes, obtaining a temperature-stable original oscillation signal, performing center frequency calibration and aging drift compensation on the original oscillation signal to obtain a pre-reference signal, and performing frequency consistency check on the pre-reference signal to obtain a reference clock signal. The relative frequency offset of the reference clock signals at both ends satisfies the following constraint: ; The reference clock signal that passes the check is directly used as the input reference of the post-stage de-jittering phase-locked loop module.

[0072] Step 4: determining the loop bandwidth range of the de-jittering phase-locked loop is 200kHz to 400kHz and the phase margin range is 45° to 60° according to the center frequency and phase noise template of the reference clock signal, determining the optimal loop parameters within the above range according to the transfer function of the clock data recovery circuit and the link equalization capability parameter, determining the fractional frequency division coefficient of the de-jittering phase-locked loop according to the center frequency of the reference clock signal and the 100MHz standard reference clock frequency, and integrating the optimal loop parameters and the fractional frequency division coefficient to obtain local loop configuration parameters. In this step, the local loop configuration parameters of the first communication end and the second communication end are completely symmetrical, and are pre-stored in the non-volatile storage units matched with the phase-locked loops at both ends, so as to ensure that the processing processes of the clock signals at both ends are completely consistent and avoid introducing additional relative frequency offset.

[0073] Step 5: filtering the reference clock signal through a third-order passive RC loop filter according to the local loop configuration parameters, filtering out near-end spurs and power domain broadband noise of the signal, then performing low-noise frequency conversion on the filtered signal through a fractional frequency divider, frequency-multiplying and converting the reference clock signal into a 100MHz standard reference clock frequency to obtain a local reference clock signal, which is the input disciplined clock of the level matching output module. The root-mean-square jitter of the output local reference clock signal satisfies the following constraint: ; The root-mean-square jitter of the output signal is controlled within 70fs, which meets the requirements of the high-speed peripheral component interconnect bus specification.

[0074] Step 6: Based on the electrical specifications of the HCSL low-voltage differential signal interface of the high-speed peripheral component interconnect bus, the symmetrical matching requirements at both ends, the signal integrity constraints, and the impedance parameters of the 100Ω differential transmission line, determine the nominal values ​​and allowable deviation ranges of the differential voltage swing, common-mode voltage, and slew rate of the local reference clock signal. At the same time, determine the 1.25V reference voltage accuracy requirements of the level matching output module, the cutoff frequency parameters of the differential low-pass filter network, the differential transmission line impedance parameters, and the resistance values ​​of the terminating matching resistor. Based on the above nominal values ​​and parameter requirements, determine the control words of the programmable impedance calibration unit and the multi-channel digital-to-analog converter current control unit to obtain the calibration parameters of the local matching circuit. In this step, the nominal value of the differential voltage swing is set to 750mV with an allowable deviation of no more than ±1%, the nominal value of the common-mode voltage is set to 0V with an allowable deviation of no more than ±50mV, the nominal value of the slew rate is set to 3.5V / ns with an allowable deviation of no more than ±5%, the cutoff frequency of the differential low-pass filter network is set to 150MHz, and the differential impedance of the terminating matching resistor network is set to 100Ω. The calibration parameters at both ends are completely consistent to ensure that the electrical characteristics of the output clock achieve mirror matching.

[0075] Step 7: Based on the calibration parameters of the local matching circuit, configure a fully symmetrical dual-path hardware link for the level matching output module of the first communication terminal and the second communication terminal. The first communication terminal corresponds to channel A link, and the second communication terminal corresponds to channel B link. Both links generate the bias voltage of the corresponding channel through a 1.25V high-precision low-temperature drift voltage reference source to provide a stable common-mode bias for the differential driver of the corresponding channel. The local reference clock signal obtained in step 5 is used as the discipline clock input to the differential driver of the corresponding channel to complete the conversion from single-ended clock to differential clock. In this step, the on-impedance of the differential driver output pair and the resistance value of the terminating matching resistor network are finely adjusted using hardware resistors to calibrate the differential voltage swing and common-mode voltage of the differential clock signal. The bias current of the differential driver stage is adjusted using a multi-channel digital-to-analog converter circuit to calibrate the conversion rate of the differential clock signal. The calibrated differential clock signal is then input to a differential low-pass filter network with a cutoff frequency of 150MHz for the corresponding channel to filter out high-frequency harmonics and noise. The signal is then transmitted via a 100Ω differential transmission line. After impedance matching is achieved through the terminating matching resistor network, the electrical characteristic consistency of the clock signals output from the two links is checked. The overall electrical characteristic matching degree of the clock signals output from both ends meets the following constraints: ; The verified local target clock signal is directly input to the reference clock input terminal of the local high-speed peripheral component interconnection communication module of the corresponding channel.

[0076] Step 8, the high-speed peripheral component interconnection communication module between the first communication end and the second communication end ( Figure 2PCIe devices A and B in the system receive the local target clock signal output from the corresponding channel level matching output module, completing the initialization configuration of the physical layer and link layer. Both ends transmit service data streams only through a data fiber optic channel without a dedicated clock signal transmission channel, completing link training and phase locking to achieve low-latency synchronous data transmission at both ends. In this step, the relative frequency offset of the clock signals at both ends is stably controlled within 1ppm, which is completely within the phase tracking capability range of the clock data recovery circuit at the bus receiver. This eliminates the need for frequent insertion of idle correction characters and deep elastic buffering, effectively improving the effective bandwidth utilization of the link. Furthermore, the absence of cross-end clock signal interaction decouples the correlation between synchronization performance and transmission distance.

[0077] This invention proposes the above-mentioned technical solution, which achieves precise control of the relative frequency offset of the clocks at both communication ends by using the same source constant temperature configuration and frequency calibration of the oscillation modules at both ends, the symmetrical phase-locked loop circuit parameter design, and the level drive and electrical characteristic closed-loop calibration of dual-path mirror matching. Combined with the fiber optic link architecture without a dedicated clock signal transmission channel, it achieves the same as the high degree of mirror matching of the electrical characteristics of the clocks at both ends. This reduces the difficulty of implementing PCIe link equalization and link training, reduces transmission delay, improves the effective bandwidth utilization of the link, decouples the correlation between clock synchronization performance and fiber optic transmission distance, and ensures the stability of bus synchronization in long-distance optical transmission scenarios.

[0078] The above are preferred embodiments of the present invention. It should be noted that, for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A high-speed peripheral component interconnection bus optical transmission system, characterized in that, include: The first and second communication terminals are physically separated. The first and second communication terminals are two peer communication nodes of the system, both of which are equipped with a clock synchronization subsystem and a high-speed peripheral component interconnection communication module with identical structure and identical and symmetrical hardware parameters; The first communication terminal includes: a first clock synchronization subsystem and a first high-speed peripheral component interconnection communication module that communicates with the first clock synchronization subsystem; The second communication terminal includes: a second clock synchronization subsystem and a second high-speed peripheral component interconnection communication module that communicates with the second clock synchronization subsystem; The first high-speed peripheral component interconnection communication module and the second high-speed peripheral component interconnection communication module are connected via a data fiber optic channel. The first clock synchronization subsystem performs symmetry calibration on the electrical characteristics of the first reference clock signal of the first communication terminal according to the target frequency accuracy threshold to obtain the first target clock signal; The second clock synchronization subsystem performs symmetry calibration on the electrical characteristics of the second reference clock signal of the second communication terminal according to the target frequency accuracy threshold to obtain the second target clock signal; the deviation between the second target clock signal and the first target clock signal is less than a preset threshold. The first high-speed peripheral component interconnection communication module sends first service data to the second high-speed peripheral component interconnection communication module through the data fiber optic channel according to the first target clock signal, and receives second service data sent by the second high-speed peripheral component interconnection communication module through the data fiber optic channel according to the second target clock signal.

2. The high-speed peripheral component interconnection bus optical transmission system according to claim 1, characterized in that, The first clock synchronization subsystem includes: The first oscillation module is used to determine the configuration parameters of the first oscillation module according to the target frequency accuracy threshold, perform homologous configuration of the first oscillation module according to the configuration parameters of the first oscillation module, and output the first reference clock signal. The first de-jitter phase-locked loop module connected to the first oscillation module is used to determine the first loop configuration parameters according to the first reference clock signal, and to perform filtering and frequency normalization processing on the first reference clock signal according to the first loop configuration parameters, and output the first reference clock signal. A first level matching output module connected to the first dejittering phase-locked loop module, the output terminal of the first level matching output module being connected to the reference clock input terminal of the first high-speed peripheral component interconnection communication module, is used to determine the calibration parameters of the matching circuit of the first level matching output module according to the first reference clock signal, perform symmetry calibration processing on the electrical characteristics of the first reference clock signal according to the calibration parameters of the matching circuit of the first level matching output module, and output a first target clock signal to the first high-speed peripheral component interconnection communication module.

3. The high-speed peripheral component interconnection bus optical transmission system according to claim 2, characterized in that, The first debouncing phase-locked loop module includes: The first jitter attenuator, the input of which is used to receive the first reference clock signal; The first loop filter has its input connected to the output of the first jitter attenuator. The first loop filter is used to filter out near-end spurious signals and power domain broadband noise from the first reference clock signal to obtain a filtered clock signal. The first fractional frequency divider has its input connected to the output of the first loop filter. The first fractional frequency divider is used to perform low-noise frequency conversion on the filtered clock signal and output a first reference clock signal.

4. The high-speed peripheral component interconnect bus optical transmission system according to claim 3, characterized in that, The first de-jitter phase-locked loop module configures its parameters according to a preset phase noise template, so that the loop bandwidth of the first loop filter is set within a preset frequency band.

5. The high-speed peripheral component interconnect bus optical transmission system according to claim 2, characterized in that, The first level matching output module includes: A first low-voltage differential signal matching network is used to calibrate the voltage swing, common-mode voltage, and slew rate of the first reference clock signal.

6. A high-speed peripheral component interconnection bus optical transmission method, characterized in that, The method, applied to a first communication terminal of the high-speed peripheral component interconnect bus optical transmission system according to any one of claims 1 to 5, comprises: Obtain the target frequency accuracy threshold; Based on the target frequency accuracy threshold, the configuration parameters of the first oscillation module are determined; Based on the configuration parameters of the first oscillation module, the first oscillation module is configured in the same source to obtain the first reference clock signal; The first loop configuration parameters are determined based on the first reference clock signal; Based on the first loop configuration parameters, the first reference clock signal is filtered and frequency standardized to obtain the first reference clock signal. The calibration parameters of the first level matching output module are determined based on the first reference clock signal; Based on the calibration parameters of the first level matching output module, the electrical characteristics of the first reference clock signal are symmetrically calibrated to obtain the first target clock signal; Based on the first target clock signal, control the first high-speed peripheral component interconnection communication module and the second high-speed peripheral component interconnection communication module to perform service data transmission.

7. The high-speed peripheral component interconnection bus optical transmission method according to claim 6, characterized in that, Based on the target frequency accuracy threshold, the configuration parameters of the first oscillation module are determined, including: Obtain the full operating temperature range and device aging compensation index of the first communication terminal; Based on the target frequency accuracy threshold and the full operating temperature range, the temperature stability parameters of the first communication terminal are determined; Based on the preset maximum relative frequency offset threshold and the device aging compensation index, the frequency calibration parameters and stability compensation parameters of the first oscillation module are determined. The temperature stability parameters, frequency calibration parameters, and stability compensation parameters are integrated to obtain the configuration parameters of the first oscillation module.

8. The high-speed peripheral component interconnection bus optical transmission method according to claim 6, characterized in that, Based on the configuration parameters of the first oscillation module, the first oscillation module is configured in a common-source manner to obtain a first reference clock signal, including: Based on the configuration parameters of the first oscillation module, the first oscillation module is subjected to constant temperature control to obtain a temperature-stable original oscillation signal; The original oscillation signal is calibrated at the center frequency and compensated for aging drift to obtain a pre-reference signal; The pre-reference signal is subjected to frequency consistency verification to obtain a first reference clock signal, and the relative frequency deviation of the first reference clock signal meets the preset constraint conditions.

9. The high-speed peripheral component interconnection bus optical transmission method according to claim 6, characterized in that, Based on the first reference clock signal, the first loop configuration parameters are determined, including: Obtain the preset phase noise template, the transfer function of the clock data recovery circuit, the link equalization capability parameters, and the standard reference clock frequency; Based on the center frequency and phase noise template of the first reference clock signal, the loop bandwidth range and phase margin interval of the dejitter phase-locked loop are determined. Based on the transfer function and link equalization capability parameters of the clock data recovery circuit, the optimal loop parameters are determined within the loop bandwidth range and phase margin interval. The fractional frequency division coefficient of the dejitter phase-locked loop is determined based on the center frequency of the first reference clock signal and the standard reference clock frequency. The optimal loop parameters and fractional frequency division coefficients are integrated to obtain the first loop configuration parameters.

10. The high-speed peripheral component interconnect bus optical transmission method according to claim 6, wherein the first reference clock signal is filtered and frequency normalized according to the first loop configuration parameters to obtain a first reference clock signal, comprising: Based on the configuration parameters of the first loop, the first de-jitter phase-locked loop module is initialized and calibrated to obtain the first de-jitter phase-locked loop module after initialization and calibration. Based on the first dejitter phase-locked loop module after initialization and calibration, the first reference clock signal is filtered to obtain a filtered clock signal. The filtered clock signal is divided by frequency to obtain a frequency-divided clock signal; The frequency-divided clock signal is subjected to verification processing to obtain the first reference clock signal.

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