Based on 2 k High-speed processing acceleration method and system for NTT-free lattice-based cryptography

By using a modular NTT-free lattice cryptography acceleration method, the modular space of the lattice polynomial is designed as a bitwise AND operation, which solves the problems of high resource consumption, long computation path and high power consumption in the hardware implementation of existing NTT algorithms. This achieves hardware resource saving and security improvement, and is suitable for resource-constrained embedded systems and autonomous intelligent agents.

CN122394787APending Publication Date: 2026-07-14BEIJING LANGKONG QUANTUM TECHNOLOGY CO LTD
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
BEIJING LANGKONG QUANTUM TECHNOLOGY CO LTD
Filing Date
2026-05-09
Publication Date
2026-07-14

AI Technical Summary

Technical Problem

Existing NTT-based post-quantum cryptography algorithms suffer from high resource consumption, long computational paths, high power consumption, and difficulties in security hardening in resource-constrained hardware implementations with high real-time requirements, making them difficult to adapt to next-generation autonomous intelligent systems.

Method used

A modular NTT-free lattice cryptography acceleration method is adopted. By designing the modular space of the lattice polynomial as a bitwise AND operation, polynomial multiplication is performed directly in the time domain. Hardware masks and gate circuits are used for modular reduction to avoid complex mathematical modulo operations.

Benefits of technology

It achieves extreme hardware resource conservation and zero cycle latency, improves security, and is suitable for resource-constrained embedded systems and autonomous intelligent agents, meeting the requirements of high concurrency and ultra-low latency.

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Abstract

The application discloses a kind of based on the high-speed processing acceleration method and system of no NTT lattice cryptosystem based on modulus, the method comprises: configuration polynomial ring, modulus q is set as, define modulo mask variable as;Obtain polynomial matrix A and private key vector;Without the aid of number theory transform, directly in time domain through hardware shift register array and parallel multiplication and addition unit executes polynomial multiplication;Intermediate result and mask variable are carried out hardware level bitwise and logic operation, complete modulus q reduction.The application also provides corresponding acceleration system and self-defined extension instruction set.The application reduces the dimension of traditional complex modulus reduction to bitwise and operation, completely gives up NTT module, significantly reduces chip area and dynamic power consumption, shortens calculation delay, and naturally has anti side channel attack ability, and is suitable for resource limited embedded device and autonomous intelligent agent system.
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