Signal transmission method and system based on spi and rs485

Abstract

The application discloses a signal transmission method and system based on SPI and RS485, which comprises an SPI chip and an RS485 transceiver; the SPI chip is connected with a first device; a host output slave input end of the SPI chip is connected with a driver input end of the RS485 transceiver; a host input slave output end of the SPI chip is connected with a receiver output end of the RS485 transceiver; and a driver output end of the RS485 transceiver is connected with a second device. When data is transmitted, the first device controls the host output slave input end of the SPI chip to directly transmit data to the driver input end of the RS485 transceiver, and the data is output to the second device by the RS485 transceiver. The application directly connects the SPI chip with the RS485 transceiver port, omits an intermediate protocol conversion link, realizes direct fusion of the SPI high-speed characteristics and the RS485 long-distance characteristics, and has high transmission rate, no conversion delay and low cost.

Description

Technical Field

[0001] This invention belongs to the field of data transmission technology, specifically relating to a signal transmission method and system based on SPI and RS485. Background Technology

[0002] In the field of industrial communication, especially in the SMT (Surface Mount Technology) industry, communication between master equipment (such as pick-and-place machines) and slave equipment (such as feeders) often requires rapid multi-station response. This application scenario not only demands extremely high data transmission speeds but also needs to support long transmission distances.

[0003] Currently, original master-slave devices typically rely on proprietary chips and private protocols for communication, resulting in high costs and limited compatibility. In domestic substitution or general-purpose device integration, common serial ports are often used to connect to the host. However, ordinary serial ports have low communication speeds, which cannot meet the communication requirements of high-speed devices, leading to the inability to establish effective communication connections in many situations.

[0004] To address the challenge of long-distance transmission of high-speed signals, one existing approach is to first receive data from a high-speed bus (such as SPI) and then transmit it via a long-distance bus (such as RS485). This approach typically requires middleware such as a microcontroller to participate in protocol conversion; that is, after receiving the SPI signal, it is asynchronously forwarded via RS485. Due to the middleware's reception, protocol conversion, and forwarding processes, this transmission method cannot maintain the synchronous high-speed characteristics of the original high-speed bus. It is an asynchronous byte-by-byte transmission, which is not only slow but also introduces significant conversion delays, making it difficult to meet the stringent requirement of a single master responding quickly to multiple slave devices simultaneously.

[0005] Therefore, how to achieve long-distance transmission while ensuring high-speed signal characteristics, and avoid delay and rate loss caused by relay processing, is a technical problem that urgently needs to be solved. Summary of the Invention

[0006] The technical problem to be solved by this invention is to overcome the shortcomings of the SMT industry in that it is difficult to achieve simultaneous, efficient and long-distance data transmission between devices, thereby providing a signal transmission method and system based on SPI and RS485.

[0007] A signal transmission system based on SPI and RS485 includes an SPI chip and an RS485 transceiver; The SPI chip is connected to the first device via SPI communication. The master output / slave input terminal MOSI of the SPI chip is connected to the driver input terminal DI of the RS485 transceiver; the master input / slave output terminal MISO of the SPI chip is connected to the receiver output terminal RO of the RS485 transceiver. The driver output of the RS485 transceiver is connected to the RS485 communication port of the second device.

[0008] Furthermore, the first device is a feeder; the second device is a chip mounter.

[0009] Furthermore, the RS485 transceiver is model number MAX13443EASA+.

[0010] Furthermore, the master output slave input terminal MOSI and the master input slave output terminal MISO of the SPI chip are directly connected to the driver input terminal DI and the receiver output terminal RO of the RS485 transceiver, respectively.

[0011] Furthermore, the clock signal terminal SCK of the SPI chip is connected to the first device to generate the data level change of the master output slave input terminal MOSI; the RS485 transceiver receives the data level signal.

[0012] A signal transmission method based on SPI and RS485, wherein when a first device sends data to a second device, the first device controls the master output slave input terminal MOSI of the SPI chip to send data to the driver input terminal DI of the RS485 transceiver, and the driver output terminal of the RS485 transceiver outputs corresponding data to the second device.

[0013] Furthermore, when the second device sends data to the first device, the receiver input of the RS485 transceiver receives the data from the second device, and the receiver output RO of the RS485 transceiver sends corresponding data to the master input / slave output MISO of the SPI chip, and the first device receives the corresponding data from the SPI chip.

[0014] Furthermore, the first device controls the SPI chip to operate in half-duplex mode; when the first device sends data, the SPI chip sends data through the master output slave input terminal MOSI; when the first device receives data, the SPI chip receives data through the master input slave output terminal MISO.

[0015] Furthermore, the first device controls the SPI chip to generate a synchronization clock signal, which is used to trigger a change in the data level of the master output slave input terminal MOSI; the RS485 transceiver and the second device receive the data level signal.

[0016] Furthermore, when the first device sends data, the SPI chip generates a start transmission signal, then sends all the data to be transmitted in the form of level signals at once, and sends an end signal level when the last data level is sent; the data level signals are transmitted by the SPI chip to the RS485 transceiver.

[0017] Beneficial Effects: This invention provides a signal transmission system based on SPI and RS485. By connecting the master output / slave input terminal MOSI of the SPI chip to the driver input terminal DI of the RS485 transceiver, and the master input / slave output terminal MISO to the receiver output terminal RO of the RS485 transceiver, direct hardware-level fusion transmission of SPI and RS485 signals is achieved. This system eliminates the intermediate microcontroller (MCU) receiving, protocol conversion, and forwarding process, eliminating the time delay caused by chip conversion. Data sent from SPI can be directly transmitted to peripheral devices via the RS485 transceiver, perfectly maintaining the high-speed synchronous transmission characteristics of SPI while utilizing the long-distance, strong anti-interference transmission characteristics of RS485.

[0018] This invention provides a signal transmission method based on SPI and RS485. When a first device sends data to a second device, the first device directly controls the MOSI pin of the SPI chip to send data to the DI pin of the RS485 transceiver, allowing the high-speed level signal of the SPI to be directly transmitted to the RS485 bus. This direct control signal transmission method breaks through the bottleneck of asynchronous byte-by-byte transmission in traditional schemes, which requires receiving first and then forwarding, and realizes synchronous and continuous high-speed data stream transmission, significantly improving the transmission rate and reducing system cost and dependence on dedicated chips. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of the main system structure of the present invention; Figure 2 This is a schematic diagram of the circuit structure of the present invention. Detailed Implementation

[0021] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, the specific embodiments of this application are described in detail below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a thorough understanding of this application. However, this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0022] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0023] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0024] Example 1: Reference Figure 1 As shown, this embodiment provides a signal transmission system based on SPI and RS485, which includes an SPI chip and an RS485 transceiver. The SPI chip is SPI-connected to a first device; the master output / slave input terminal MOSI of the SPI chip is connected to the driver input terminal DI of the RS485 transceiver; the master input / slave output terminal MISO of the SPI chip is connected to the receiver output terminal RO of the RS485 transceiver; and the driver output terminal of the RS485 transceiver is connected to the RS485 communication terminal of a second device.

[0025] Through the above system architecture, this invention directly fuses the high-speed characteristics of SPI and the long-distance characteristics of RS485. The data transmit / receive pins of the SPI chip are directly connected to the data transmit / receive pins of the RS485 transceiver, eliminating the intermediate microcontroller (MCU) steps of protocol parsing, packetizing, and forwarding. This eliminates the time delay caused by MCU processing and achieves synchronous direct transmission. Thus, while maintaining the high speed of SPI, long-distance, interference-resistant transmission is achieved using RS485, effectively complementing the advantages and disadvantages of the two communication methods.

[0026] In this embodiment, the first device is a feeder; the second device is a pick-and-place machine. In the SMT industry, the pick-and-place machine host needs to respond to information from multiple feeders simultaneously, requiring high speed and long distance. This system solves the problem of communication failure between domestic feeders and pick-and-place machines due to the low speed of ordinary serial ports.

[0027] As a preferred embodiment, refer to Figure 2 As shown, the RS485 transceiver is model MAX13443EASA+. Existing ordinary RS485 chips have a switching speed of only a few hundred Kbps, which cannot keep up with the high-speed signals of SPI. According to the chip specifications of MAX13443EASA+, it guarantees a data rate of up to 10Mbps, perfectly matching and keeping up with the high-speed transmission pace of SPI up to 10Mbps, ensuring the distortion-free transmission of high-speed signals. Simultaneously, the chip's driver and receiver propagation delays are low. This extremely low chip-level latency further ensures that from the SPI signal transmission to the signal transmission to the peripheral device, only the signal transmission time on the line is delayed, without the time delay required for chip conversion. Furthermore, MAX13443EASA+ features ±60V fault protection and ±15kV ESD protection. In long-distance industrial communication, the bus is susceptible to external high voltage or electrostatic interference. This chip can withstand overvoltage faults on the signal bus without damage, providing the system with extremely strong anti-interference and surge protection capabilities. Its true fail-safe receiver input characteristics ensure that the receiver output remains at a logic high level when the receiver input is open-circuited, short-circuited, or connected to an idle data line, preventing false triggering when long-distance lines are idle.

[0028] In this embodiment, the master-to-slave input (MOSI) and master-to-slave output (MISO) terminals of the SPI chip are directly connected to the driver input (DI) and receiver output (RO) of the RS485 transceiver, respectively. This direct hardware-level connection without an MCU intermediary is the physical basis for achieving zero conversion delay.

[0029] The clock signal terminal SCK of the SPI chip is connected to the first device and is used to generate the data level change of the master output slave input terminal MOSI; the RS485 transceiver receives the data level signal. During communication, the SPI clock signal is only used to trigger and generate the high and low data level changes of the MOSI terminal on the first device side. This clock signal does not need to be transmitted to the RS485 transceiver and the second device. The RS485 transceiver only needs to receive the normal level signal generated according to the clock change to complete the data transmission, which further simplifies the line requirements for long-distance transmission and ensures the smooth transmission of high-speed signals.

[0030] Example 2: Based on the signal transmission system of Embodiment 1 above, this embodiment provides a signal transmission method based on SPI and RS485. The specific implementation steps of this method are as follows: After the equipment is installed, it is powered on, and the system begins initialization, including self-tests of timers and communication lines. Because the selected MAX13443EASA+ chip has a hot-swappable input circuit, during the feeder circuit board's power-on initialization phase, the internal circuitry pulls the driver enable pin (DE) low for at least 10μs. This prevents leakage current or coupling noise caused by the processor's high impedance output during power-on from causing incorrect data transmission on the bus, ensuring that bus communication is not affected at the moment of power-on. After normal power-on, the feeder (first device) is recognized by the pick-and-place machine (second device) through a handshake signal, and communication is ready.

[0031] Read the data that needs to be transferred from the array.

[0032] The SPI generates a synchronous clock signal. Before actual data transmission, the SPI generates a start transmission signal, and the RS485 transmission is ready. At this time, since the MAX13443EASA+ is operating in half-duplex mode, the transmit and receive directions need to be switched by controlling its DE (driver output enable) and RE# (receiver output enable) pins.

[0033] In this embodiment, the DE and RE# pins of the RS485 transceiver are connected to and controlled by the IO pins of the feeder's control chip, and are connected to the same IO pin, thereby controlling the receive and transmit states of the RS485 transceiver.

[0034] The process of the first device sending data to the second device: The first device controls the SPI chip to operate in half-duplex mode; when the first device sends data, the SPI chip sends data through the master output slave input terminal MOSI, and does not receive data at this time. At the same time, it controls the RS485 transceiver to enter the transmit state (DE high, RE low).

[0035] The first device controls the SPI chip to generate a synchronization clock signal, which triggers a change in the data level of the master output slave input terminal MOSI. The RS485 transceiver and the second device receive the data level signal. Specifically, after the start signal is received, the first device controls the SPI chip to send data from the master output slave input terminal MOSI to the driver input terminal DI of the RS485 transceiver, and the driver output terminal of the RS485 transceiver outputs corresponding data to the second device. SPI transmission officially begins, sending the data to be transmitted to the RS485 chip as a level signal. When the first device sends data, the SPI chip generates a start transmission signal, and then sends the data to be transmitted in one go as a level signal, without needing to divide it into multiple bytes; it can transmit any length of bytes at once for high-speed transmission. An end signal level is issued after the last data level is sent, ending one frame of SPI data transmission; the data level signal is transmitted by the SPI chip to the RS485 transceiver.

[0036] During this transmission process, due to the direct connection of MOSI to DI and the high speed of 10Mbps and low latency of 60ns of MAX13443EASA+, RS485 directly transmits each received level to the peripheral device (second device), realizing high-speed synchronous direct transmission without relay, with a speed of up to 10,000,000 bits / s and a distance of up to 1,000 meters.

[0037] The process of the second device sending data to the first device: When the second device sends data to the first device, it controls the RS485 transceiver to enter the receive state (DE low, RE low). The receiver input terminals (A, B) of the RS485 transceiver receive the data from the second device, and the receiver output terminal RO of the RS485 transceiver sends the corresponding data to the master input / slave output terminal MISO of the SPI chip. The first device receives the corresponding data from the SPI chip.

[0038] When the first device receives data, the SPI chip receives the data through the master input / slave output (MISO) terminal, but does not send data at this time. Because RS485 operates in half-duplex mode, SPI also operates in half-duplex mode to adapt to this. That is, after SPI finishes sending data, it starts receiving. Sending and receiving are performed separately, avoiding the need for simultaneous sending and receiving, thus avoiding bus conflicts and ensuring the stability and reliability of high-speed, long-distance data transmission.

[0039] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0040] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A signal transmission system based on SPI and RS485, characterized in that, The device includes an SPI chip and an RS485 transceiver; the SPI chip is SPI-connected to a first device; the master output / slave input terminal MOSI of the SPI chip is connected to the driver input terminal DI of the RS485 transceiver; the master input / slave output terminal MISO of the SPI chip is connected to the receiver output terminal RO of the RS485 transceiver; and the driver output terminal of the RS485 transceiver is connected to the RS485 communication terminal of a second device. When the first device sends data to the second device, the first device controls the master output of the SPI chip (MOSI) to send data to the driver input (DI) of the RS485 transceiver. The driver output of the RS485 transceiver outputs the corresponding data to the second device. The SPI chip generates a start transmission signal, and then sends the data to be transmitted as a data level signal all at once. When the last data level signal is sent, an end signal level is issued. The data level signal is transmitted from the SPI chip to the RS485 transceiver. When the second device sends data to the first device, the receiver input of the RS485 transceiver receives the data from the second device, and the receiver output RO of the RS485 transceiver sends the corresponding data to the master input / slave output MISO of the SPI chip. The first device receives the corresponding data from the SPI chip. The clock signal terminal SCK of the SPI chip is connected to the first device and is used to generate a data level change at the master output slave input terminal MOSI on the first device side. The RS485 transceiver receives the data level signal generated according to the change of the clock signal terminal SCK to complete data transmission. The first device controls the SPI chip to work in half-duplex mode. When the first device sends data, the SPI chip sends data through the master output slave input terminal MOSI. When the first device receives data, the SPI chip receives data through the master input slave output terminal MISO. The SPI chip starts receiving after sending data, and sending and receiving are performed separately. The first device controls the SPI chip to generate a synchronization clock signal, which is used to trigger a data level change at the master output slave input terminal MOSI, and the synchronization clock signal is not transmitted to the RS485 transceiver and the second device. The RS485 transceiver and the second device receive the data level signal. The first device is a feeder; the second device is a chip mounter.

2. The signal transmission system based on SPI and RS485 according to claim 1, characterized in that, The RS485 transceiver is model MAX13443EASA+.

3. The signal transmission system based on SPI and RS485 according to claim 1, characterized in that, The master output / slave input terminal MOSI and the master input / slave output terminal MISO of the SPI chip are directly connected to the driver input terminal DI and the receiver output terminal RO of the RS485 transceiver, respectively.

4. A signal transmission method based on SPI and RS485, applied to the signal transmission system based on SPI and RS485 as described in any one of claims 1-3, characterized in that, The first device controls the SPI chip to operate in half-duplex mode; when the first device sends data, the SPI chip sends data through the master output slave input terminal MOSI; the first device controls the SPI chip to generate a synchronization clock signal, which is used to trigger a change in the data level of the master output slave input terminal MOSI on the first device side; the RS485 transceiver and the second device only receive the data level signal generated according to the change of the synchronization clock signal; the SPI chip generates a start transmission signal, then sends all the data to be transmitted as data level signals at once, and sends an end signal level when the last data level signal is sent; when the first device receives data, the SPI chip receives data through the master input slave output terminal MISO.

5. The signal transmission method based on SPI and RS485 according to claim 4, characterized in that, The first device controls the SPI chip to generate a synchronous clock signal, which is used to trigger the master to output a change in the data level of the slave input terminal MOSI; the RS485 transceiver and the second device receive the data level signal.

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