A method and system for testing a relay protection device implicit communication fault
By setting unconventional internal communication bus parameters, reverse tracing, forward verification, and extreme stress testing were conducted, resolving the hidden problem of internal communication faults in relay protection devices and improving the reliability of the devices and the safety of the power grid.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- CHINA ELECTRIC POWER RESEARCH INSTITUTE CO LTD
- Filing Date
- 2026-03-19
- Publication Date
- 2026-07-14
Smart Images
Figure CN122395033A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of power system relay protection technology, and more specifically, to a test method and system for latent communication faults in relay protection devices. Background Technology
[0002] In the process of localization of power system relay protection devices, ensuring the long-term stability and reliability of core chips and internal communication links is crucial. Existing testing and verification of protection devices mainly focus on external, macroscopic protection logic functions. There is a lack of systematic and specialized testing methods for the reliability of the underlying communication bus (such as SPI) between the device's internal processor (CPU) and core components such as the field-programmable gate array (FPGA). Traditional aging tests and functional tests are unable to reproduce the implicit and intermittent communication failures caused by performance differences between chip production batches and the critical state of driver clock parameter settings.
[0003] For example, when the CPU's SPI controller clock source is set outside the range recommended in the chip manual, it may lead to insufficient signal setup and hold time margin, causing data transmission errors. According to the datasheet of a certain chip model, the recommended SPI clock source is ≤200MHz; exceeding this enters the out-of-range zone. Actual testing showed that 600MHz is a high-risk value. This type of fault is insidious: it may not be reproducible in routine laboratory tests or on certain batches of chips, but it may be triggered in specific batches of chips or after prolonged high-temperature operation. Symptoms include device restarts, input / output delays, LCD malfunctions, or even more serious differential protection sampling synchronization failures, seriously threatening power grid safety.
[0004] Current technology lacks a testing scheme that can proactively and systematically stimulate and verify such latent communication defects. Therefore, a testing method for latent communication faults in relay protection devices is needed. Summary of the Invention
[0005] This invention proposes a testing method and system for latent communication faults in relay protection devices, in order to solve the problem of how to test latent communication faults in relay protection devices.
[0006] To address the aforementioned problems, according to one aspect of the present invention, a method for testing latent communication faults in relay protection devices is provided, the method comprising: By setting out-of-standard internal communication bus parameters, different batches of relay protection devices are tested to perform reverse tracing tests. High-risk batches are identified by statistically analyzing the implicit communication failure rate. Combined with the analysis of fault phenomena and parameter correlation, the root cause of the fault is located. The internal communication bus parameters of the relay protection devices in high-risk batches are modified, and then tested under various environmental stresses to perform positive verification tests to verify whether the latent communication faults have been eliminated. Extreme pressure tests were conducted on relay protection devices that eliminate latent communication faults to determine the long-term stability of the communication function. Based on the above test results, the core logic affected by internal communication anomalies was functionally verified, and the impact of communication reliability on protection actions was analyzed.
[0007] Preferably, the out-of-specification internal communication bus parameter is the clock source frequency of the SPI controller. The clock source frequency is set to a frequency value higher than the upper limit of the recommended operating range in the chip datasheet, so that the internal communication bus enters a critical state with insufficient timing margin. The communication anomaly is monitored by SPI bus error statistics counting.
[0008] Preferably, during the forward verification test, the forward verification test includes: anomaly comparison test and bit error rate comparison test; the corrected internal communication bus parameters are the SPI controller clock source frequency, which is set to a stable operating frequency that is lower than the upper limit of the recommended operating range in the chip datasheet and has been verified to eliminate communication anomalies.
[0009] Preferably, when conducting the extreme pressure test, the test duration is not less than 168 hours, and the extreme conditions include high temperature environment and application of a preset percentage of rated electrical load.
[0010] Preferably, the core logic affected by internal communication anomalies undergoes functional verification, and the impact of communication reliability on protection actions is analyzed, including: Simulated SPI bus transmission delay to create sampling asynchronous conditions, simulated external faults in the presence of through load current, monitored and recorded differential current calculation value, braking current and action behavior of differential protection, in order to analyze the impact of communication reliability on protection action behavior; Among them, by comparing the differential current calculation value of the protection device under test with the risk parameter configuration and the optimized parameter configuration, and the differential current calculation value in the same fault simulation scenario outside the zone, the effect of parameter rectification on avoiding protection maloperation is quantified.
[0011] According to another aspect of the present invention, a test system for latent communication faults in relay protection devices is provided, the system comprising: The reverse tracing test module is used to test different batches of relay protection devices by setting out-of-standard internal communication bus parameters to perform reverse tracing tests. It identifies high-risk batches by statistically analyzing the implicit communication failure rate and locates the root cause of the failure by combining the analysis of failure phenomena and parameter correlation. The forward verification test module is used to correct the internal communication bus parameters of high-risk batches of relay protection devices. After correction, the devices are tested under various environmental stresses to perform forward verification tests and verify whether the latent communication faults have been eliminated. The ultimate pressure test module is used to perform ultimate pressure tests on relay protection devices that eliminate latent communication faults, and to determine the long-term stability of the communication function. The core protection function association verification module is used to verify the core logic affected by internal communication anomalies based on the above test results, and to analyze the impact of communication reliability on protection action behavior.
[0012] Preferably, the out-of-specification internal communication bus parameter is the clock source frequency of the SPI controller. The clock source frequency is set to a frequency value higher than the upper limit of the recommended operating range in the chip datasheet, so that the internal communication bus enters a critical state with insufficient timing margin. The communication anomaly is monitored by SPI bus error statistics counting.
[0013] Preferably, in the forward verification test module, the forward verification test includes: anomaly comparison test and bit error rate comparison test; the corrected internal communication bus parameters are the SPI controller clock source frequency, which is set to a stable operating frequency that is lower than the upper limit of the recommended operating range in the chip datasheet and has been verified to eliminate communication anomalies.
[0014] Preferably, in the extreme pressure test module, the duration of the extreme pressure test is not less than 168 hours, and the extreme conditions include: high temperature environment and application of a preset percentage of rated electrical load.
[0015] Preferably, the core protection function correlation verification module performs functional verification on the core logic affected by internal communication anomalies, and analyzes the impact of communication reliability on protection action behavior, including: Simulated SPI bus transmission delay to create sampling asynchronous conditions, simulated external faults in the presence of through load current, monitored and recorded differential current calculation value, braking current and action behavior of differential protection, in order to analyze the impact of communication reliability on protection action behavior; Among them, by comparing the differential current calculation value of the protection device under test with the risk parameter configuration and the optimized parameter configuration, and the differential current calculation value in the same fault simulation scenario outside the zone, the effect of parameter rectification on avoiding protection maloperation is quantified.
[0016] This invention provides a testing method and system for implicit communication faults in relay protection devices, comprising: testing different batches of relay protection devices by setting out-of-specification internal communication bus parameters to perform reverse tracing tests, identifying high-risk batches by statistically analyzing the implicit communication fault rate, and locating the root cause of the fault by combining fault phenomenon analysis with parameter correlation; correcting the internal communication bus parameters of the high-risk batches of relay protection devices, and then testing them under various environmental stresses to perform forward verification tests to verify whether the implicit communication fault has been eliminated; performing extreme stress tests on the relay protection devices whose implicit communication faults have been eliminated to determine the long-term stability of the communication function; and, based on the above test results, performing functional verification on the core logic affected by internal communication anomalies and analyzing the impact of communication reliability on protection action behavior. This invention is the first to construct a complete closed-loop test logic of "reverse tracing - forward verification - extreme stress - functional correlation," which can systematically reveal hidden defects throughout the entire chain from chip parameters to protection behavior. By introducing "reverse logic testing" and "batch comparison testing," it proactively stimulates the risks of insufficient design margin and supply chain fluctuations, breaking through the limitations of traditional testing in in-depth verification of hardware reliability. It can accurately reproduce sporadic faults caused by batch differences and critical parameter settings, and through functional correlation verification, it can quantitatively assess the specific impact of communication anomalies on power grid security. This invention takes differential protection as an example, but is not limited to it. It provides a standardized test process and evaluation criteria, which can be used for horizontal comparison and access assessment of the reliability of domestically produced protection devices from different manufacturers and models, thereby improving the overall quality level of the industry. Attached Figure Description
[0017] Exemplary embodiments of the present invention can be more fully understood by referring to the following figures: Figure 1 A flowchart of a test method 100 for a relay protection device with latent communication faults according to an embodiment of the present invention. Figure 2 This is a logic flowchart of the test method according to an embodiment of the present invention; Figure 3 This is a block diagram of the test equipment according to an embodiment of the present invention; Figure 4 This is a schematic diagram of the structure of a test system 400 for latent communication faults of a relay protection device according to an embodiment of the present invention. Detailed Implementation
[0018] Exemplary embodiments of the invention will now be described with reference to the accompanying drawings. However, the invention may be embodied in many different forms and is not limited to the embodiments described herein. These embodiments are provided to fully and completely disclose the invention and to fully convey its scope to those skilled in the art. The terminology used in the exemplary embodiments illustrated in the drawings is not intended to limit the invention. In the drawings, the same units / elements are referred to by the same reference numerals.
[0019] Unless otherwise stated, the terms used herein (including technical terms) have their common meaning as understood by one of ordinary skill in the art. Furthermore, it is understood that terms defined in commonly used dictionaries should be understood to have a meaning consistent with the context of their relevant field, and not to be interpreted as having an idealized or overly formal meaning.
[0020] This invention aims to provide a testing method and system for latent communication faults in relay protection devices, addressing the shortcomings of existing technologies in verifying the reliability of internal low-level communication. By designing a complete testing process that includes positive effect verification, reverse root cause tracing, and extreme stress testing, and particularly by introducing batch difference comparison and reverse logic stress testing, it is possible to systematically discover, reproduce, and verify latent faults in internal buses such as SPI caused by individual chip differences and improper parameter settings. This provides precise technical basis for device design optimization, parameter tuning, and quality consistency assessment.
[0021] Figure 1 This is a flowchart of a test method 100 for implicit communication faults in a relay protection device according to an embodiment of the present invention. Figure 1 As shown, the test method 100 for implicit communication faults of relay protection devices provided by the embodiments of the present invention starts from step 101. In step 101, by setting out-of-standard internal communication bus parameters, different batches of relay protection devices are tested to perform reverse tracing tests. By statistically analyzing the implicit communication fault rate, high-risk batches of relay protection devices and the root cause of the fault are identified.
[0022] Preferably, the out-of-specification internal communication bus parameter is the clock source frequency of the SPI controller. The clock source frequency is set to a frequency value higher than the upper limit of the recommended operating range in the chip datasheet, so that the internal communication bus enters a critical state with insufficient timing margin. The communication anomaly is monitored by SPI bus error statistics counting.
[0023] To address the challenges of reproducing and locating intermittent, latent faults, this invention proposes a closed-loop testing system: First, faults are actively induced in the laboratory through reverse tracing testing to pinpoint the root cause and sensitive batches; then, the effectiveness of corrective measures is confirmed through forward verification testing; finally, long-term reliability and the impact on system security are comprehensively evaluated through extreme stress testing and verification of protection functions.
[0024] Specifically, in combination Figure 2 As shown, in this invention, a reverse traceability test is first performed: the protection device under test is tested by actively setting out-of-standard internal communication bus parameters and testing on chips from different production batches to stimulate and count latent communication faults, identify the root cause of the fault and high-risk batches.
[0025] The reverse traceability test includes batch difference comparison test, which involves selecting multiple batches of chip boards, including early normal batches and recent high-risk batches, setting the communication parameters of all samples to out-of-specification values with known risks, running the test under the same environmental and electrical load conditions, and statistically comparing the communication anomaly rates of each batch of samples.
[0026] The out-of-standard internal communication bus parameter is the clock source frequency of the SPI controller. The clock source frequency is set to a value higher than the upper limit of the recommended operating range in the chip datasheet, according to the known risky frequency value. This causes the internal communication bus to enter a critical state with insufficient timing margin. Communication abnormalities are monitored by SPI bus error statistics.
[0027] In step 102, the internal communication bus parameters of the relay protection devices in the high-risk batch are corrected. After correction, the devices are tested under various environmental stresses to perform a positive verification test to verify whether the latent communication fault has been eliminated.
[0028] Preferably, during the forward verification test, the forward verification test includes: anomaly comparison test and bit error rate comparison test; the corrected internal communication bus parameters are the SPI controller clock source frequency, which is set to a stable operating frequency that is lower than the upper limit of the recommended operating range in the chip datasheet and has been verified to eliminate communication anomalies.
[0029] Combination Figure 2 As shown, in this invention, a forward verification test is performed: after the internal communication bus parameters of the protection device under test are corrected, tests are conducted under various environmental stresses to verify whether the latent communication fault has been eliminated.
[0030] The forward verification test includes: anomaly comparison test and bit error rate comparison test; the corrected internal communication bus parameters are SPI controller clock source frequency 120MHz.
[0031] In step 103, an extreme pressure test is performed on the relay protection device for eliminating latent communication faults to determine the long-term stability of the communication function.
[0032] Preferably, when conducting the extreme pressure test, the test duration is not less than 168 hours, and the extreme conditions include: high temperature environment and application of a preset percentage of the rated electrical load.
[0033] Combination Figure 2 Therefore, in this invention, an extreme stress test is performed: the device that has completed the forward verification test is placed under extreme operating conditions of high temperature, full load, and periodic disturbances for a long period of continuous operation to evaluate the long-term stability of its communication system. The duration of the long-term continuous operation test is no less than 168 hours, and the extreme operating conditions include a 70°C high-temperature environment and the application of 80%-100% of the rated electrical load.
[0034] In step 104, based on the above test results, the core logic affected by internal communication anomalies is functionally verified, and the impact of communication reliability on protection action behavior is analyzed.
[0035] Preferably, the core logic affected by internal communication anomalies undergoes functional verification, and the impact of communication reliability on protection actions is analyzed, including: Simulated SPI bus transmission delay to create sampling asynchronous conditions, simulated external faults in the presence of through load current, monitored and recorded differential current calculation value, braking current and action behavior of differential protection, in order to analyze the impact of communication reliability on protection action behavior; Among them, by comparing the differential current calculation value of the protection device under test with the risk parameter configuration and the optimized parameter configuration, and the differential current calculation value in the same fault simulation scenario outside the zone, the effect of parameter rectification on avoiding protection maloperation is quantified.
[0036] Combination Figure 2 As shown, in this invention, the core protection function correlation verification is performed: based on the test status of the above steps, the core logic affected by internal communication anomalies is functionally verified, and the impact of communication reliability on protection action behavior is analyzed.
[0037] The core protection function correlation verification specifically targets the line fiber optic differential protection. The verification process includes: simulating SPI bus transmission delay to create sampling asynchrony conditions; simulating an external fault in the presence of through-load current; and monitoring and recording the differential current calculation value, restraining current, and operating behavior of the differential protection. Furthermore, the differential current calculation value of the protection device under test under risk parameter configuration and optimized parameter configuration is compared with that under the same external fault simulation scenario to quantify the effect of parameter rectification on avoiding protection maloperation.
[0038] likeFigure 3 As shown, in this invention, the hardware system includes: an environmental stress application unit (high and low temperature test chamber), an electrical load and disturbance injection unit (relay protection tester), an internal communication monitoring unit (bus monitoring tool), a device status monitoring unit, and the connection and control relationship between the central control and data analysis platform.
[0039] The system includes: an environmental stress application unit to provide high-temperature environmental stress to the device under test; an electrical load and disturbance injection unit to apply rated voltage and current loads and programmable fault disturbance signals to the device under test; an internal communication monitoring unit to connect to the internal debugging interface of the device under test, read and record error statistics of the internal communication bus in real time; a device status monitoring unit to collect the operating logs, alarm signals and protection action events of the device under test in real time; and a central control and data analysis platform to control the collaborative work of each unit to automatically execute test case sequences, and to correlate and analyze communication error statistics and protection action event data to generate test reports.
[0040] The testing method of the present invention has the following significant advantages: 1) Systematic and complete. For the first time, a complete test logic closed loop of "reverse tracing - forward verification - extreme stress - functional correlation" has been constructed, which can systematically reveal hidden defects across the entire chain from chip parameters to protection behavior.
[0041] 2) Highly proactive and in-depth. By introducing "reverse logic testing" and "batch comparison testing," it proactively addresses the risks of insufficient design margins and supply chain fluctuations, breaking through the limitations of traditional testing in in-depth verification of hardware reliability.
[0042] 3) It achieves accurate reproduction and quantitative assessment. It can accurately reproduce sporadic faults caused by batch differences and critical parameter settings, and through functional correlation verification, quantitatively assess the specific impact of communication anomalies on power grid security (such as the risk of differential protection maloperation).
[0043] 4) Strong standardization and engineering applicability. It provides a standardized testing process and evaluation criteria, which can be used for horizontal comparison and access assessment of the reliability of domestically produced protection devices from different manufacturers and models, thereby improving the overall quality level of the industry.
[0044] The following specific examples illustrate the embodiments of the present invention. In an embodiment of the present invention, taking a certain type of circuit protection device using a multi-core CPU chip as an example, the method of the present invention is applied for testing, including: Reverse tracing and root cause analysis: Five production batches were selected, including early batches (e.g., 2024) and recent batches. Twenty boards were randomly selected from each batch, and all boards were subjected to a high-temperature load test with the SPI clock source set to 600MHz and continuously running at 70℃ for 72 hours. The SPI error count was monitored. Results showed that the fourth batch had an error rate of 2%; the fifth batch had an error rate as high as 18%, while the first three batches had an error rate of 0%, accurately pinpointing the batch-sensitive issue.
[0045] Positive verification of corrective measures: After correcting the SPI clock source parameters of the fifth batch of devices to 120MHz, anomaly comparison tests and bit error rate comparison tests were performed. The tests showed that the original restart and white screen phenomena disappeared, and the SPI bit error count was zero during long-term operation at both room temperature and 70℃ high temperature, verifying the effectiveness of the corrective measures.
[0046] Extreme pressure long-term test: The modified device operated continuously and stably for 168 hours under extreme conditions of 70℃ high temperature and 80% rated current load. Throughout the process, no new SPI error counts were added, and the device did not experience any restarts, crashes, or other anomalies, demonstrating its long-term stability.
[0047] Protection Function Correlation Verification: A fiber optic differential protection test system was built. When the device was still using the 600MHz risk parameter, simulating SPI transmission delay to create sampling asynchrony resulted in an abnormal increase in the differential current value after injecting an external fault, posing a risk of false tripping. After optimizing the parameter to 120MHz, the differential current value returned to the normal range under the same test scenario, and the protection reliably did not trip, quantitatively demonstrating the crucial role of parameter rectification in ensuring power grid safety.
[0048] This testing method not only completed the entire closed-loop process of "identifying problems, locating root causes, verifying measures, and assessing risks," but also proved in principle that the original parameter settings had insufficient design margins on a specific batch of chips, providing key reliability design basis for subsequent chip selection, circuit design, and driver development.
[0049] Figure 4 This is a schematic diagram of the structure of a test system 400 for latent communication faults in a relay protection device according to an embodiment of the present invention. Figure 4 As shown, the test system 400 for implicit communication faults of relay protection devices provided in this embodiment of the invention includes: a reverse tracing test module 401, a forward verification test module 402, an extreme pressure test module 403, and a core protection function association verification module 404.
[0050] Preferably, the reverse tracing test module 401 is used to test different batches of relay protection devices by setting out-of-standard internal communication bus parameters to perform reverse tracing tests, and to identify high-risk batches by statistically analyzing the implicit communication failure rate, and to locate the root cause of the failure by combining the analysis of the failure phenomenon and the correlation of parameters.
[0051] Preferably, the out-of-specification internal communication bus parameter is the clock source frequency of the SPI controller. The clock source frequency is set to a frequency value higher than the upper limit of the recommended operating range in the chip datasheet, so that the internal communication bus enters a critical state with insufficient timing margin. The communication anomaly is monitored by SPI bus error statistics counting.
[0052] Preferably, the forward verification test module 402 is used to correct the internal communication bus parameters of the relay protection device in the high-risk batch, and then test it under various environmental stresses to perform forward verification test to verify whether the latent communication fault has been eliminated.
[0053] Preferably, in the forward verification test module, the forward verification test includes: anomaly comparison test and bit error rate comparison test; the corrected internal communication bus parameters are the SPI controller clock source frequency, which is set to a stable operating frequency that is lower than the upper limit of the recommended operating range in the chip datasheet and has been verified to eliminate communication anomalies.
[0054] Preferably, the ultimate pressure test module 403 is used to perform an ultimate pressure test on the relay protection device for eliminating latent communication faults to determine the long-term stability of the communication function.
[0055] Preferably, in the extreme pressure test module, the duration of the extreme pressure test is not less than 168 hours, and the extreme conditions include: high temperature environment and application of a preset percentage of rated electrical load.
[0056] Preferably, the core protection function association verification module 404 is used to perform functional verification on the core logic affected by internal communication anomalies based on the above test results, and to analyze the impact of communication reliability on protection action behavior.
[0057] Preferably, the core protection function correlation verification module performs functional verification on the core logic affected by internal communication anomalies, and analyzes the impact of communication reliability on protection action behavior, including: Simulated SPI bus transmission delay to create sampling asynchronous conditions, simulated external faults in the presence of through load current, monitored and recorded differential current calculation value, braking current and action behavior of differential protection, in order to analyze the impact of communication reliability on protection action behavior; Among them, by comparing the differential current calculation value of the protection device under test with the risk parameter configuration and the optimized parameter configuration, and the differential current calculation value in the same fault simulation scenario outside the zone, the effect of parameter rectification on avoiding protection maloperation is quantified.
[0058] The test system 400 for implicit communication faults of relay protection devices in an embodiment of the present invention corresponds to the test method 100 for implicit communication faults of relay protection devices in another embodiment of the present invention, and will not be described again here.
[0059] The present invention has been described with reference to a few embodiments. However, it will be apparent to those skilled in the art that other embodiments besides those disclosed above fall equivalently within the scope of the present invention.
[0060] Generally, all terms used in this invention are interpreted according to their ordinary meaning in the art, unless otherwise expressly defined herein. All references to “a / the / the [device, component, etc.]” are openly interpreted as at least one instance of said device, component, etc., unless otherwise expressly stated. The steps of any method disclosed herein need not be performed in the exact order disclosed, unless explicitly stated otherwise.
[0061] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.
[0062] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.
[0063] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.
[0064] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.
[0065] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of the present invention. Any modifications or equivalent substitutions that do not depart from the spirit and scope of the present invention should be covered within the protection scope of the present invention.
Claims
1. A test method for latent communication faults in relay protection devices, characterized in that, The method includes: By setting out-of-standard internal communication bus parameters, different batches of relay protection devices are tested to perform reverse tracing tests. High-risk batches are identified by statistically analyzing the implicit communication failure rate. Combined with the analysis of fault phenomena and parameter correlation, the root cause of the fault is located. The internal communication bus parameters of the relay protection devices in high-risk batches are modified, and then tested under various environmental stresses to perform positive verification tests to verify whether the latent communication faults have been eliminated. Extreme pressure tests were conducted on relay protection devices that eliminate latent communication faults to determine the long-term stability of the communication function. Based on the above test results, the core logic affected by internal communication anomalies was functionally verified, and the impact of communication reliability on protection actions was analyzed.
2. The method according to claim 1, characterized in that, The out-of-specification internal communication bus parameter is the clock source frequency of the SPI controller. The clock source frequency is set to a frequency value higher than the upper limit of the recommended operating range in the chip datasheet, so that the internal communication bus enters a critical state with insufficient timing margin. The communication anomaly is monitored by SPI bus error statistics and counting.
3. The method according to claim 1, characterized in that, During the forward verification test, the forward verification test includes: anomaly comparison test and bit error rate comparison test; the corrected internal communication bus parameters are the SPI controller clock source frequency, which is set to a stable operating frequency that is lower than the upper limit of the recommended operating range in the chip datasheet and has been verified to eliminate communication anomalies.
4. The method according to claim 1, characterized in that, When conducting extreme pressure tests, the test duration shall be no less than 168 hours, and the extreme conditions include: high temperature environment and application of a preset percentage of the rated electrical load.
5. The method according to claim 1, characterized in that, Functional verification was performed on the core logic affected by internal communication anomalies, and the impact of communication reliability on protection actions was analyzed, including: Simulated SPI bus transmission delay to create sampling asynchronous conditions, simulated external faults in the presence of through load current, monitored and recorded differential current calculation value, braking current and action behavior of differential protection, in order to analyze the impact of communication reliability on protection action behavior; Among them, by comparing the differential current calculation value of the protection device under test with the risk parameter configuration and the optimized parameter configuration, and the differential current calculation value in the same fault simulation scenario outside the zone, the effect of parameter rectification on avoiding protection maloperation is quantified.
6. A testing system for latent communication faults in relay protection devices, characterized in that, The system includes: The reverse tracing test module is used to test different batches of relay protection devices by setting out-of-standard internal communication bus parameters to perform reverse tracing tests. It identifies high-risk batches by statistically analyzing the implicit communication failure rate and locates the root cause of the failure by combining the analysis of failure phenomena and parameter correlation. The forward verification test module is used to correct the internal communication bus parameters of high-risk batches of relay protection devices. After correction, the devices are tested under various environmental stresses to perform forward verification tests and verify whether the latent communication faults have been eliminated. The ultimate pressure test module is used to perform ultimate pressure tests on relay protection devices that eliminate latent communication faults, and to determine the long-term stability of the communication function. The core protection function association verification module is used to verify the core logic affected by internal communication anomalies based on the above test results, and to analyze the impact of communication reliability on protection action behavior.
7. The system according to claim 6, characterized in that, The out-of-specification internal communication bus parameter is the clock source frequency of the SPI controller. The clock source frequency is set to a frequency value higher than the upper limit of the recommended operating range in the chip datasheet, so that the internal communication bus enters a critical state with insufficient timing margin. The communication anomaly is monitored by SPI bus error statistics and counting.
8. The system according to claim 6, characterized in that, In the forward verification test module, the forward verification test includes: anomaly comparison test and bit error rate comparison test; the corrected internal communication bus parameters are the SPI controller clock source frequency, which is set to a stable operating frequency that is lower than the upper limit of the recommended operating range in the chip datasheet and has been verified to eliminate communication anomalies.
9. The system according to claim 6, characterized in that, In the extreme pressure test module, the duration of the extreme pressure test is not less than 168 hours, and the extreme conditions include: high temperature environment and application of a preset percentage of rated electrical load.
10. The system according to claim 6, characterized in that, The core protection function correlation verification module verifies the core logic affected by internal communication anomalies and analyzes the impact of communication reliability on protection actions, including: Simulated SPI bus transmission delay to create sampling asynchronous conditions, simulated external faults in the presence of through load current, monitored and recorded differential current calculation value, braking current and action behavior of differential protection, in order to analyze the impact of communication reliability on protection action behavior; Among them, by comparing the differential current calculation value of the protection device under test with the risk parameter configuration and the optimized parameter configuration, and the differential current calculation value in the same fault simulation scenario outside the zone, the effect of parameter rectification on avoiding protection maloperation is quantified.