Configurable adaptive rs-422 serial communication method

Abstract

The application discloses a kind of configuration adaptive RS-422 serial interface communication method, comprising: S1, in the RS-422 serial port end configuration adaptive communication system;S2, through the opposite end of physical connection of RS-422 serial port realizes when communicating, both sides of communication complete configuration adaptation according to the configuration information in Link message.The application breaks through the limitation that physical link state cannot be identified and configuration adaptation cannot be realized in the process of existing RS-422 serial port communication transmission by the way of combination of hardware scheme and software logic, while inhibiting the damage caused by transient voltage to chip, more efficient, stable, extensive serial transmission is realized, and support is provided for application in complex scene.

Description

Technical Field

[0001] This invention relates to the field of communication technology. More specifically, this invention relates to a configuration-adaptive RS-422 serial communication method. Background Technology

[0002] In many fields such as modern industrial control, data acquisition, and communication testing, serial interface communication technology is an important means for data exchange between devices. Among them, RS-422 serial interface (hereinafter referred to as "serial port") communication occupies an important position due to its advantages of high transmission rate and long transmission distance. RS-422 serial port communication adopts differential transmission, and the receiving end determines the signal by judging the voltage difference. This design provides RS-422 serial port communication with strong anti-common-mode interference capability, enabling it to work stably in complex electromagnetic interference environments.

[0003] However, existing RS-422 serial communication technology has significant limitations in complex real-world application scenarios. First, traditional RS-422 serial ports cannot confirm whether the other end can receive data during transmission; the physical link status can only be confirmed when both parties correctly receive the service data. This communication method may lead to data loss during transmission. Second, existing RS-422 serial communication does not adequately consider the damage to chips caused by large transient voltages from lightning strikes, power fluctuations, inductive switches, and electrostatic discharge. Finally, before RS-422 serial communication, both parties need to pre-agree and set the same serial port configuration, including baud rate, data bits, stop bits, and parity bits. Inconsistent parameter configurations between the two parties will lead to communication failure or even interruption. Furthermore, if either party changes its configuration during communication, the other party, lacking an effective information synchronization mechanism, cannot obtain timely and accurate confirmation of the new configuration information. This information asymmetry can lead to communication link interruption and communication failure. Summary of the Invention

[0004] One object of the present invention is to solve at least the above-mentioned problems and / or defects, and to provide at least the advantages described below.

[0005] To achieve these objectives and other advantages of the present invention, an adaptive RS-422 serial communication method is provided, comprising: S1. Configure an adaptive communication system on the RS-422 serial port; S2. When communicating with each other via RS-422 serial port, the two communicating parties complete configuration adaptation based on the configuration information in the Link message. The configuration adaptation is determined to be complete based on the following conditions: Condition I: If the configuration information in the Link messages of both communicating parties is consistent, then the configurations of both parties are considered consistent, and configuration adaptation is completed; Condition II: When the configuration information in the Link message between the two communicating parties is inconsistent, and the RS-422 serial port of either end supports adaptive mode, the configuration adaptation is completed by updating the configuration and sending the Link message information to the other end. The configuration information includes: adaptive mode, serial port data transmission rate, data bits, stop bits, parity bits, and flow control.

[0006] Preferably, the adaptive communication system includes: A control management module for managing the status changes and configuration of RS-422 serial ports; A logic processing module for status detection and protocol conversion during communication of RS-422 serial ports; An interface conversion module used to convert between TTL level and RS-422 serial port standard differential level; An interface insertion detection module used to detect the insertion and removal status of an interface; Data input / output module used for connecting to other communication terminals and transmitting data via RS-422 serial port; The data input / output module is equipped with a protection circuit, which consists of a transient suppression protection diode I connected in parallel between the signal differential pairs of the RS-422 serial port, and a transient suppression protection diode II connected in series on the transmission link of each signal, so as to clamp the transient voltage on the signal link to a safe level.

[0007] Preferably, in the interface insertion detection module, the interface insertion detection signal Link_Sig is pulled up to the VCC voltage through a pull-up resistor, and a capacitor to reduce signal jitter interference is connected in series with ground to Link_Sig; The interface pin corresponding to Link_Sig is connected to the GND1 signal interface pin. When an interface is inserted, Link_Sig will be continuously pulled low. After the FPGA recognizes the change in level from high to low, it will execute the corresponding workflow.

[0008] Preferably, the control management module communicates with the logic processing module via a UART interface to distribute configurations or to report status via an RS-422 serial port. The logic processing module transmits TTL level signals via RS-422 serial port through the GPIO interface and the interface conversion module. The logic processing module transmits the interface insertion detection signal Link_Sig between itself and the interface insertion detection module via the GPIO interface; The interface conversion module, interface insertion detection module, and data input / output module communicate via the GPIO interface.

[0009] Preferably, in the adaptive communication system, the RS-422 serial port is defined with three states: waiting state, service state, and idle state. The waiting state refers to: no interface insertion is detected or an external interface access is detected, but no connection is established with the other end; The service status refers to: communicating with the peer via RS-422 serial port; The idle state refers to the following: when the RS-422 serial port is in a waiting state, it detects that an external interface is connected, reaches a configuration agreement through negotiation, establishes a connection with the other end, and is in an idle state waiting to send or receive data. After completing data transmission and reception in service mode, the RS-422 serial port is updated to idle mode.

[0010] Preferably, the method for changing from a waiting state to an idle state is as follows: After the FPGA detects a change in the level of the insertion detection signal Link_Sig, it sends a Link message containing configuration information to negotiate the configuration. After the negotiation is successful and a connection is established, the FPGA reports the connection status of the interface to the CPU so that the CPU can update the interface status from the waiting state to the idle state. If the FPGA does not receive a reply message from the other end for an extended period of time, it will abandon the current connection and wait for the next connection request, while the CPU continues to remain in a waiting state.

[0011] Preferably, the method for changing from a business state to an idle state is as follows: When the RS-422 serial port stops sending data and the FPGA determines that both communicating parties have completed sending data, the FPGA reports the port connection status to the CPU, and the CPU updates the interface status from the service status to the idle status. If the FPGA does not receive a reply message for a long time, it will abandon the current connection and wait for the next connection request. The CPU will then change from the service state to the waiting state. When the RS-422 serial port is idle, the FPGA periodically sends Link messages to maintain the link connection of the interface.

[0012] Preferably, in condition II, if the configuration information in the Link messages of the two communicating parties is inconsistent, but the local RS-422 serial port supports adaptive mode, the adaptive working mode is configured as follows: The FPGA checks whether the configuration supported by the local end includes the configuration of the peer end. If it does, the FPGA updates the configuration and sends the Link message information to the peer end. At the same time, it reports the configuration information to be changed to the CPU. After the CPU issues the configuration change command, the configuration adaptation is completed. If not included, but the other end supports adaptive mode, the FPGA periodically changes the configuration information according to the configuration priority and updates the Link message to send to the other end. When the configuration information in the Link messages of both communicating parties is consistent, the FPGA reports the pre-change configuration information to the CPU. After the CPU issues the change configuration instruction, the configuration adaptation is completed. If the configurations of the two communicating parties are still inconsistent after sending the lowest priority configuration information, the adaptation fails.

[0013] Preferably, in condition II, if the configuration information in the Link messages of the two communicating parties is inconsistent, and the local RS-422 serial port does not support adaptive mode, but the remote end does support adaptive mode, the adaptive working mode is configured as follows: Waiting for the Link message sent by the other end to update the configuration information. If the configuration information is consistent with the RS-422 serial port configuration information of this end after the other end updates the configuration information, the configuration adaptation is completed; otherwise, the configuration adaptation fails.

[0014] Preferably, the configuration adaptation further includes: When the RS-422 serial port changes its configuration in service mode, it first completes the transmission of the current data, then stops transmitting data. At the same time, the CPU updates the interface status to idle state, and the FPGA resends the Link message for configuration adaptation. After the configuration adaptation is completed, it continues to transmit data according to the changed configuration; otherwise, the CPU updates the interface status to waiting state.

[0015] The present invention has at least the following beneficial effects: This invention provides a complete RS-422 serial interface communication method that supports adaptive configuration. By combining hardware solutions with software logic, it solves the problems of not being able to identify the physical link status and not being able to achieve adaptive configuration during RS-422 serial communication transmission. It effectively suppresses the damage to the chip caused by transient voltage and extends the RS-422 serial interface communication method from a conventional configuration mode to an adaptive configuration mode.

[0016] Other advantages, objectives and features of the present invention will become apparent in part from the following description, and in part from those skilled in the art through study and practice of the invention. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the hardware solution of the present invention; Figure 2 This is a circuit diagram for the interface insertion detection of the present invention; Figure 3 This is a circuit diagram of the interface protection circuit of the present invention; Figure 4In one embodiment of the present invention, a flowchart of the waiting state change is provided. Figure 5 In one embodiment of the present invention, a flowchart of the business status change flow is provided. Figure 6 In one embodiment of the present invention, an adaptive configuration flowchart is provided; Figure 7 This is a flowchart illustrating the data transmission process in one embodiment of the present invention. Figure 8 This is a flowchart illustrating the data receiving process in one embodiment of the present invention. Detailed Implementation

[0018] The present invention will now be described in further detail with reference to the accompanying drawings, so that those skilled in the art can implement it based on the description.

[0019] This invention extends the communication mode of the RS-422 serial interface (hereinafter referred to as "RS-422 serial port") by designing an RS-422 serial interface communication method that supports configuration adaptation. It solves the problems of not being able to identify the physical link status and not being able to achieve configuration adaptation during RS-422 serial port communication transmission, while effectively suppressing damage to the chip caused by transient voltage. Specifically, the RS-422 serial interface communication method that supports configuration adaptation includes the following aspects: I. From the perspective of hardware implementation plan, such as Figure 1 As shown, it mainly consists of: a control management module 1, a logic processing module 2, an interface conversion module 3, an interface insertion detection module 4, and a data input / output module 5. It should be noted that the "interface" mentioned in this invention refers to the physical interface corresponding to the RS-422 serial interface.

[0020] Among them, the control and management module 1 (hereinafter referred to as "CPU") is mainly composed of a CPU chip, which realizes the status change and configuration management of the RS-422 serial port. The logic processing module 2 (hereinafter referred to as "FPGA") is mainly composed of FPGA chips, which realizes the status detection of RS-422 serial port, configuration information storage, configuration adaptation, protocol conversion and data cache management during the communication process. The interface conversion module 3 is mainly composed of an integrated isolated DC-DC converter serial transceiver chip, which realizes the conversion between TTL level and RS-422 serial port standard differential level, while achieving high-level insulation withstand voltage and good electromagnetic compatibility, reducing interference factors during signal transmission. The interface insertion detection module 4 mainly consists of detection signals to detect interface insertion and removal. In specific implementation, such as... Figure 2As shown, in this invention, the interface insertion detection signal (i.e., the Link_Sig signal) of the interface insertion detection module 4 is pulled up to the VCC voltage through a pull-up resistor 40 and connected to the FPGA. When an interface insertion is detected, the Link_Sig signal is continuously pulled low. At this time, after the FPGA receives the signal change, it enters the configuration adaptive process. A filter capacitor 41 is connected in series with ground to the Link_Sig signal to reduce signal jitter interference and prevent the FPGA from making false judgments. The interface pin corresponding to the detection signal Link_Sig should be connected to the GND1 signal interface pin. The data input / output module 5 mainly consists of serial port transceiver signals, enabling connection to other device interfaces and data transmission via the RS-422 serial port. For example... Figure 3 As shown, the data input / output module 5 connects a transient suppression protection diode I 50 in parallel between the signal differential pairs of the RS-422 serial port, and at the same time connects a transient suppression protection diode II 51 in series on the transmission link of each signal to clamp the transient voltage on the signal link to a safe level.

[0021] The modules should have at least the following interfaces to enable inter-module communication: Control management module 1 communicates with logic processing module 2 via a UART interface for RS-422 serial port status reporting and configuration distribution. Logic processing module 2 communicates with interface conversion module 3 via GPIO interface I for TTL level signal transmission of the RS-422 serial port. Logic processing module 2 communicates with interface insertion detection module 4 via GPIO interface II for transmission of the insertion detection signal Link_Sig. Interface conversion module 3, interface insertion detection module 4, and data input / output module 5 communicate via GPIO interface III for transmission of RS-422 serial port standard differential level signals and the insertion detection signal Link_Sig. Second, from the perspective of communication status management, this invention implements RS-422 serial port communication status management through hardware and software mechanisms for interface insertion detection. Specifically, the RS-422 serial port status is defined as follows: a) Waiting state: No interface insertion is detected, and the interface insertion detection signal Link_Sig shows no level change; or an external interface is detected, but no connection is established with the other end due to reasons such as incompatibility in configuration.

[0022] b) Service status: RS-422 serial port communicates with the peer.

[0023] c) Idle state: When the RS-422 serial port is in the waiting state, it detects that an external interface is connected, causing a change in the level of the interface insertion detection signal Link_Sig. After reaching a configuration agreement through negotiation, it establishes a connection with the other end and waits for data to be sent or received; or the RS-422 serial port updates to the idle state after completing data transmission and reception in the service state. Furthermore, the change and management from a waiting state to an idle state should meet the following requirements: After the FPGA detects a change in the Link_Sig insertion detection signal level, it begins to... v l The Link message, containing configuration information, is sent at a certain rate. Once the configurations of both communicating parties are agreed upon, and the FPGA continuously receives... x When two Link messages with the same configuration items are received, the system checks if the message contains a Connect_Ack request. If not, a Connect_Ack request is sent. When the peer receives the Connect_Ack request, it replies with a Connect_Ack request. When the FPGA receives the peer's Connect_Ack reply, it sends a Connect_Ack response message to establish a connection with the peer interface. At this point, the FPGA reports the interface's connection status to the CPU, and the CPU updates the interface status from waiting to idle. If the FPGA does not receive a Connect_Ack reply message or a Connect_Ack response message from the peer for an extended period, it abandons the current connection and waits for the next connection request, while the CPU continues to remain in a waiting state. Furthermore, the change and management of status from active to idle should meet the following requirements: When the RS-422 serial port stops transmitting data, the FPGA checks whether an End_Ack request response message has been sent. If not, the FPGA sends an End_Ack request message and waits for a response from the other end. Once the other end finishes transmitting data, it sends a secondary End_Ack request message, and the FPGA sends a response message to the secondary End_Ack request. At this point, both communicating parties have completed data transmission, and the FPGA reports the port connection status to the CPU. The CPU updates the interface status from the active state to the idle state. If the FPGA does not receive a response to the secondary End_Ack request or a secondary End_Ack request message from the other end for an extended period, it abandons the current connection and waits for the next connection request. The CPU then updates its status from the active state to the waiting state.

[0024] Specifically, when the RS-422 serial port is idle, the FPGA periodically sends Link messages to maintain the link connection of the interface.

[0025] Thirdly, from the perspective of implementing the configuration adaptation scheme, this invention achieves configuration adaptation by designing a software mechanism for negotiated configuration. Specifically, it adds RS-422 serial port configuration information and adaptation information to the Link message sent by the FPGA. Both communicating parties complete configuration adaptation based on the configuration information in the Link message. It should be noted that the serial port adaptation information indicates whether the serial port supports adaptation, categorized as either supported or not. Typically, this can be identified through a predetermined length of encoding, such as setting 00 encoding for not supported and 01 encoding for supported. This encoding segment can be placed at the beginning or end of the Link message as needed. The configuration information typically includes: adaptation mode, serial port data transmission rate, data bits, stop bits, parity bits, and flow control, etc. Whether configuration adaptation is completed satisfies the following: a) When the configuration information in the Link message between the two communicating parties is consistent, the configurations of both parties are consistent, and the configuration adaptation is completed.

[0026] b) When the configuration information in the Link message between the two communicating parties is inconsistent, and the current RS-422 serial port supports adaptive mode.

[0027] The FPGA checks if the current supported configuration includes the specified configuration. If the configuration is supported, the FPGA updates the configuration and sends a Link message to the peer. Simultaneously, the FPGA reports the pre-modified configuration information to the CPU. After the CPU issues a configuration change command, the configuration adaptation is completed.

[0028] When the FPGA's supported configuration does not include the configuration in the Link message, and the peer supports adaptive mode, the FPGA periodically changes the configuration information according to the configuration priority (customizable, confirmed by the peer's Link message information to determine if a change has been made), updates the Link message, and sends it to the peer. When the configuration information in the Link messages of both communicating parties is consistent, the FPGA reports the pre-modified configuration information to the CPU. After the CPU issues a configuration change command, configuration adaptation is completed. If the configurations of both communicating parties are still inconsistent after sending the lowest priority configuration information, adaptation fails.

[0029] c) When the RS-422 serial port does not support adaptive mode, but the peer does, wait for the peer to send a Link message to check if the configuration information has been updated. If the peer updates the configuration information and it matches the RS-422 serial port configuration, then the adaptive configuration is complete. Otherwise, the adaptive configuration fails.

[0030] d) If neither communicating party supports adaptive mode and their configurations are inconsistent, the adaptive configuration will fail.

[0031] e) Furthermore, when the RS-422 serial port changes its configuration while in service mode, it will stop sending data after completing the current data transmission. At this time, the CPU will update the interface status to idle, and the FPGA will resend the Link message for configuration adaptation. After configuration adaptation is complete, data transmission will continue according to the changed configuration; otherwise, the CPU will update the interface status to waiting. IV. From the perspective of RS-422 serial interface data conversion implementation, when the RS-422 serial port transmits specified service data (hereinafter referred to as "service data") in service mode, the FPGA needs to convert the service data into the data format supported by the RS-422 serial port (hereinafter referred to as "serial port data").

[0032] When the RS-422 serial port receives a service data transmission request, the FPGA first encapsulates the service data into serial data according to the specified protocol. If the encapsulated serial data cannot be transmitted in one go, the untransmitted serial data is buffered. Transmission continues only after the previous serial data transmission is complete, until all current data has been transmitted. Furthermore, when the RS-422 serial port receives a data transmission request and has buffered serial data, the current service data is temporarily buffered, waiting for the previous service data transmission to complete before encapsulation and transmission.

[0033] When the RS-422 serial port receives a serial data receive request, it parses the serial data. If the serial data size matches the service data size, the FPGA directly encapsulates and receives it according to the specified protocol. If the parsed serial data size does not match the service data size, the serial data is buffered first, and the FPGA encapsulates and returns the serial data after the serial data size matches the service data size. Example: (1) such as Figure 1 As shown, from a hardware perspective, the adaptive communication system includes a control and management module, a logic processing module, an interface conversion module, an interface insertion detection module, and a data input / output module.

[0034] Among them, such as Figure 2 As shown, the Link_Sig signal is pulled up to VCC voltage through a 4.7K resistor and connected to the FPGA. Simultaneously, a 10μF capacitor is connected in series with ground to reduce signal jitter interference and prevent misjudgment by the FPGA. Since the interface pin corresponding to the detection signal Link_Sig is connected to the GND1 signal interface pin, when an interface is inserted, the Link_Sig signal is continuously pulled low. The FPGA recognizes the change from high to low level and then executes configuration adaptation and subsequent workflow.

[0035] (2) Define the following three states to implement the communication state management of RS-422 serial port.

[0036] a) Waiting state: After normal power-on, no external interface is detected, and the interface insertion detection signal Link_Sig has no level change; or an external interface is detected, but a connection is established with the other end due to reasons such as incompatibility in configuration.

[0037] b) Service status: RS-422 serial port communicates with the peer.

[0038] c) Idle State: When the RS-422 serial port is in the waiting state, it detects an external interface connection, causing a change in the level of the interface insertion detection signal Link_Sig. After negotiating and achieving configuration consistency, it establishes a connection with the peer and waits for data transmission or reception. The process of the RS-422 serial port updating from the waiting state to the idle state is as follows: Figure 4 Alternatively, after completing data transmission and reception in service mode, the RS-422 serial port is updated to idle mode. The process for updating the RS-422 serial port from service mode to idle mode is as follows: Figure 5 .

[0039] In the process of updating the RS-422 serial port from a waiting state to an idle state, the FPGA first checks whether the Link_Sig signal level has changed. When it detects a change from high to low, it sends a Link message to the other end. The Link message length is... L 1. Includes interface configuration information, ConnectAck_bit information for Connect_Ack acknowledgment, and EndAck_bit information for End_Ack acknowledgment. The interface configuration information includes adaptive mode, serial data transmission rate, data bits, stop bits, parity bits, and flow control. The Link message uses... v l Rate of transmission, when v l≤100kps At that time, the Link message can meet the maximum transmission distance.

[0040] Once the RS-422 serial port synchronously receives a Link message from the peer, it enters the configuration adaptive process. At this point, both communicating parties exchange Link messages until their configurations are consistent, at which point they enter the configuration confirmation process. The configuration confirmation process is as follows: When the FPGA continuously receives xWhen (custom number, default set to 3) Link messages with the same configuration items are received, check if the message contains a Connect_Ack request. If not, update the ConnectAck_bit field and send the Link message. When the peer receives this message, update the Link message and reply with a Connect_Ack request. When the FPGA receives the peer's Connect_Ack reply message, it sends a Connect_Ack response message to establish a connection with the peer device. The FPGA reports the port's connection status to the CPU, and the CPU updates the interface status to idle.

[0041] If the FPGA does not receive a response message to the Connet_Ack request or a reply message from the other end during the Connet_Ack acknowledgment process, it will abandon the current connection and wait for the next connection request, while the CPU continues to remain in a waiting state.

[0042] If the RS-422 serial port times out after the Connect_Ack wait time... t w1 ≥ Connect_Ack timeout t d1 If no consecutive identical Link messages are received, the FPGA abandons the current connection and waits for the next connection request, while the CPU resumes its waiting state. The timeout period is determined by the Link message length, rate, and the number of Link messages with the same custom configuration item. t d1 ≥ xL 1 / v l ; Figure 5 middle t 1 represents the time to wait for the next message, used to determine the number of Link messages with the same custom configuration within the response timeout period. This value is calculated based on the message rate. For example, if two messages with the same custom configuration are specified, the timeout period is 2. t 1, and: t 1≥ L 1 / v l .

[0043] After the RS-422 serial port finishes sending data, its status changes from service to idle. The process is as follows: The FPGA checks if an End_Ack request response message has been sent. If not, it sends an End_Ack request message and waits for a response from the peer. After receiving the peer's End_Ack request response message, the FPGA waits for the peer to complete data transmission. After the peer completes data transmission, it sends a secondary End_Ack request message. Upon receiving this message, the FPGA responds by sending a message confirming the secondary End_Ack request to the peer. At this point, both communicating parties have completed data transmission. The FPGA reports the port connection status to the CPU, and the CPU updates the interface status to idle.

[0044] If the FPGA does not receive a response to the End_Ack request from the other end during the End_Ack confirmation process, or a message responding to the End_Ack secondary request, it will abandon the current connection and wait for the next connection request. The CPU will change from the service state to the waiting state.

[0045] If the RS-422 serial port confirms that no data has been received, and the second End_Ack request times out (i.e., the End_Ack waiting time), then... t w2 ≥ End_Ack timeout t d2 If no End_Ack secondary request message is received from the other end, the FPGA abandons the current connection and waits for the next connection request. The CPU changes from the service state to the waiting state. The timeout period is specified in the original text. t d2 The length and rate of the Link message, and the amount of serial data transmitted. n ,length L 2. Rate v d Joint decision: t w2 ≥ L 1 / v l + n × L 2 / v l .

[0046] When the interface is idle, the FPGA periodically (customizable, set to 1 second) sends Link messages to acknowledge Connet_Ack and End_Ack to maintain the link connection of the interface.

[0047] (3) When the RS-422 serial port changes from the waiting state to the idle state, it needs to complete the configuration adaptation with the peer device. The process is as follows: Figure 6 As shown.

[0048] When the RS-422 serial port receives a Link message from the peer device, it parses the message and checks whether the current configuration matches the configuration of the peer device. If the configurations of both communicating parties match, configuration adaptation is completed.

[0049] When the configuration in the received Link message is inconsistent with the current configuration, the following situations apply: a) When the current RS-422 serial port supports adaptive mode, and the supported configuration items include the configuration in the Link message, the FPGA updates the configuration information in the Link message and sends it to the peer. Simultaneously, the FPGA reports the configuration information that needs to be changed to the CPU, and the CPU issues a configuration change command to complete the configuration adaptation.

[0050] b) The current RS-422 serial port supports adaptive mode, and the configuration supported by the current RS-422 serial port does not include the configuration in the Link message, and the peer also supports adaptive mode. The FPGA periodically changes the configuration information according to the configuration priority and updates the Link message sent to the peer. When the configuration information in the Link messages of both communicating parties is consistent, the FPGA reports the pre-modified configuration information to the CPU. After the CPU issues the change configuration command, the configuration adaptation is completed. If the configurations of the two communicating parties still cannot be consistent after sending the lowest priority configuration information, the adaptation fails.

[0051] c) The current RS-422 serial port does not support adaptive mode, while the peer device does. Waiting. t After 2 hours, check if the Link message sent by the other end has updated the configuration information. If the configuration information is updated by the other end and is consistent with the current RS-422 serial port configuration, the configuration adaptation is completed; otherwise, the adaptation fails.

[0052] d) If neither communicating party supports adaptive mode, the adaptive configuration will fail.

[0053] (4) When the RS-422 serial port receives a configuration change command from the CPU while in service mode, it stops sending data after the current data transmission is completed. The CPU first updates the interface status to idle state, and the FPGA resends the Link message for configuration adaptation. After configuration adaptation is completed, data transmission continues according to the changed configuration; otherwise, the CPU updates the interface status to waiting state.

[0054] (5) such as Figure 7-8 As shown, when the RS-422 serial port communicates in service mode, the FPGA needs to complete the conversion between service data and serial port data.

[0055] When the serial communication rate is lower than the service communication rate, the next service data must be sent only after the previous service data has been sent. Therefore, FPGA reserves data buffer 1 as a service data buffer.

[0056] When the size of the serial communication data is smaller than the service communication data, the FPGA cannot send all the serial data at once after encapsulating the service data into serial data. It needs to temporarily store some of the serial data and send the next serial data after the previous serial data is sent. Therefore, the FPGA reserves data buffer 2 as a serial data sending buffer.

[0057] During serial port data reception, if the size of the received serial port data is smaller than the size of the service data, it is necessary to wait for all the current serial port data to be received before encapsulating it back into service data. Therefore, the FPGA reserves data buffer 3 as a serial port data reception buffer.

[0058] When the RS-422 serial port receives a service data transmission request and confirms that there is no serial data buffer in data buffer 2, the FPGA first encapsulates the service data into serial data according to the specified protocol. If the encapsulated serial data cannot be transmitted in one go, the untransmitted serial data is stored in data buffer 2. The serial data in data buffer 2 then waits... t 2. Duration: After the previous serial port data transmission is completed, transmission continues until all current data has been transmitted. t 2. Determined by the serial port data length and transmission rate: t 2= L 2 / v D When data buffer 2 contains serial port data and data buffer 1 has sufficient memory, the FPGA temporarily stores the current service data in data buffer 1, while waiting... t 3. Duration: After the previous business data is sent, the data encapsulation process begins. t 3. Data buffer 2 memory size C 1. The serial communication rate determines the speed: t 3= C 1 / v D When the memory in data cache 1 is insufficient, the business data will be discarded.

[0059] When the RS-422 serial port receives a serial data receive request, it first parses whether the serial data size matches the service data size. If the serial data size matches the service data size, the FPGA directly encapsulates the serial data into service data according to the specified protocol and returns it. If the serial data size does not match the service data size, the FPGA first stores the serial data in data buffer 3 and waits... t After 4 hours, the serial port data is encapsulated into business data and returned, wheret 4. Determined by the size of business data L 3. The serial communication rate is determined by: t 4= L 2 / v D .

[0060] This embodiment overcomes the limitations of existing RS-422 serial communication transmission, which cannot identify the physical link status and cannot achieve configuration self-adaptation, by combining hardware solutions with software logic. At the same time, it suppresses the damage caused by transient voltage to the chip, and achieves more efficient, stable and wide-ranging serial transmission, providing support for applications in complex scenarios.

[0061] The above solution is merely an illustration of a preferred example and is not limited thereto. When implementing this invention, appropriate substitutions and / or modifications can be made according to the user's needs.

[0062] Although embodiments of the present invention have been disclosed above, they are not limited to the applications listed in the specification and embodiments. It can be applied to various fields suitable for the present invention. Other modifications can be readily made by those skilled in the art. Therefore, without departing from the general concept defined by the claims and their equivalents, the present invention is not limited to the specific details and examples shown and described herein.

Claims

1. A configuration-adaptive RS-422 serial communication method, characterized in that, include: S1. Configure an adaptive communication system on the RS-422 serial port; S2. When communicating with each other via RS-422 serial port, the two communicating parties complete configuration adaptation based on the configuration information in the Link message. The configuration adaptation is determined to be complete based on the following conditions: Condition I: If the configuration information in the Link messages of both communicating parties is consistent, then the configurations of both parties are considered consistent, and configuration adaptation is completed; Condition II: When the configuration information in the Link message between the two communicating parties is inconsistent, and the RS-422 serial port of either end supports adaptive mode, the configuration adaptation is completed by updating the configuration and sending the Link message information to the other end. The configuration information includes: adaptive mode, serial port data transmission rate, data bits, stop bits, parity bits, and flow control.

2. The adaptive RS-422 serial communication method as described in claim 1, characterized in that, The adaptive communication system includes: A control management module for managing the status changes and configuration of RS-422 serial ports; A logic processing module for status detection and protocol conversion during communication of RS-422 serial ports; An interface conversion module used to convert between TTL level and RS-422 serial port standard differential level; An interface insertion detection module used to detect the insertion and removal status of an interface; Data input / output module used for connecting to other communication terminals and transmitting data via RS-422 serial port; The data input / output module is equipped with a protection circuit, which consists of a transient suppression protection diode I connected in parallel between the signal differential pairs of the RS-422 serial port, and a transient suppression protection diode II connected in series on the transmission link of each signal, so as to clamp the transient voltage on the signal link to a safe level.

3. The adaptive RS-422 serial communication method as described in claim 2, characterized in that, In the interface insertion detection module, the interface insertion detection signal Link_Sig is pulled up to the VCC voltage through a pull-up resistor, and a capacitor to reduce signal jitter interference is connected in series with ground to Link_Sig. The interface pin corresponding to Link_Sig is connected to the GND1 signal interface pin. When an interface is inserted, Link_Sig will be continuously pulled low. After the FPGA recognizes the change in level from high to low, it will execute the corresponding workflow.

4. The adaptive RS-422 serial communication method as described in claim 2, characterized in that, The control and management module communicates with the logic processing module via the UART interface to distribute configurations or to report status via the RS-422 serial port. The logic processing module transmits TTL level signals via RS-422 serial port through the GPIO interface and the interface conversion module. The logic processing module transmits the interface insertion detection signal Link_Sig between itself and the interface insertion detection module via the GPIO interface; The interface conversion module, interface insertion detection module, and data input / output module communicate via the GPIO interface.

5. The adaptive RS-422 serial communication method as described in claim 1, characterized in that, In the adaptive communication system, the RS-422 serial port is defined with three states: waiting state, service state, and idle state. The waiting state refers to: no interface insertion is detected or an external interface access is detected, but no connection is established with the other end; The service status refers to: communicating with the peer via RS-422 serial port; The idle state refers to the following: when the RS-422 serial port is in a waiting state, it detects that an external interface is connected, reaches a configuration agreement through negotiation, establishes a connection with the other end, and is in an idle state waiting to send or receive data. After completing data transmission and reception in service mode, the RS-422 serial port is updated to idle mode.

6. The adaptive RS-422 serial communication method as described in claim 5, characterized in that, The method to change from a waiting state to an idle state is as follows: After the FPGA detects a change in the level of the insertion detection signal Link_Sig, it sends a Link message containing configuration information to negotiate the configuration. After the negotiation is successful and a connection is established, the FPGA reports the connection status of the interface to the CPU so that the CPU can update the interface status from the waiting state to the idle state. If the FPGA does not receive a reply message from the other end for an extended period of time, it will abandon the current connection and wait for the next connection request, while the CPU continues to remain in a waiting state.

7. The adaptive RS-422 serial communication method as described in claim 5, characterized in that, The method to change from a business status to an idle status is as follows: When the RS-422 serial port stops sending data and the FPGA determines that both communicating parties have completed sending data, the FPGA reports the port connection status to the CPU, and the CPU updates the interface status from the service status to the idle status. If the FPGA does not receive a reply message for a long time, it will abandon the current connection and wait for the next connection request. The CPU will then change from the service state to the waiting state. When the RS-422 serial port is idle, the FPGA periodically sends Link messages to maintain the link connection of the interface.

8. The adaptive RS-422 serial communication method as described in claim 1, characterized in that, In condition II, if the configuration information in the Link messages of the two communicating parties is inconsistent, but the local RS-422 serial port supports adaptive mode, the adaptive working mode is configured as follows: The FPGA checks whether the configuration supported by the local end includes the configuration of the peer end. If it does, the FPGA updates the configuration and sends the Link message information to the peer end. At the same time, it reports the configuration information to be changed to the CPU. After the CPU issues the configuration change command, the configuration adaptation is completed. If not included, but the other end supports adaptive mode, the FPGA periodically changes the configuration information according to the configuration priority and updates the Link message to send to the other end. When the configuration information in the Link messages of both communicating parties is consistent, the FPGA reports the pre-change configuration information to the CPU. After the CPU issues the change configuration command, the configuration adaptation is completed. If the configurations of the two communicating parties are still inconsistent after sending the lowest priority configuration information, the adaptation fails.

9. The adaptive RS-422 serial communication method as described in claim 1, characterized in that, In condition II, if the configuration information in the Link messages of the two communicating parties is inconsistent, and the local RS-422 serial port does not support adaptive mode, but the remote end does support adaptive mode, the adaptive working mode is configured as follows: Waiting for the Link message sent by the other end to update the configuration information. If the configuration information is consistent with the RS-422 serial port configuration information of this end after the other end updates the configuration information, the configuration adaptation is completed; otherwise, the configuration adaptation fails.

10. The configuration-adaptive RS-422 serial communication method as described in claim 5, characterized in that, The adaptive configuration also includes: When the RS-422 serial port changes its configuration in service mode, it first completes the transmission of the current data, then stops transmitting data. At the same time, the CPU updates the interface status to idle state, and the FPGA resends the Link message for configuration adaptation. After the configuration adaptation is completed, it continues to transmit data according to the changed configuration; otherwise, the CPU updates the interface status to waiting state.

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