GaN dc-dc converter, system architecture and vehicle lamp supporting ethernet communication

Abstract

The application provides a GaN DC-DC converter supporting Ethernet communication, a system architecture and a vehicle lamp, comprising: a power supply component containing a GaN FET power stage unit for realizing DC-DC power conversion; a communication component containing an Ethernet physical layer interface and a hardware Ethernet frame analysis circuit. The Ethernet physical layer interface is used for connecting an external Ethernet bus, and the hardware Ethernet frame analysis circuit is used for directly analyzing instructions from the Ethernet and generating control signals to control the working state of the power supply component. The application realizes an MCU-free vehicle lamp control scheme, has high bandwidth and low delay communication capability, simultaneously utilizes the high-frequency and high-efficiency characteristics of the GaN FET to improve the system integration and power density, significantly simplifies the system architecture and wiring harness, and is suitable for the field of intelligent vehicle lamp control.

Description

Technical Field

[0001] This invention relates to the field of automotive lighting controller technology, specifically to a GaN DC-DC converter supporting Ethernet communication, a system architecture, and an automotive lighting system. Background Technology

[0002] The automotive lighting controller module provides a stable power current output to the LEDs of automotive lights to meet relevant regulations. Currently, the automotive lighting controller module mainly consists of a DC-DC converter and its application circuitry. In addition, the converter integrates communication functions, facilitating functional control and fault monitoring by an external master control chip. Commonly used communication buses include UART, SPI, and I2C.

[0003] With the development of intelligent and electric vehicles, the vehicle's electronic and electrical architecture is rapidly transforming from distributed control to a "domain-centralized" or even "centralized computing + regional control" architecture. This trend requires eliminating the independent master control chips in each sensor and actuator node and integrating their software functions into the regional controller to achieve a master control chip-free (MCU-free) solution, thereby reducing the complexity of development, testing, maintenance, and OTA upgrades.

[0004] However, existing automotive lighting DC-DC converters, after eliminating the main control chip, suffer from insufficient interference immunity and stability, making it impossible to establish a reliable connection directly with the vehicle domain controller and failing to meet the development requirements of MCU-free systems. Furthermore, traditional converters often use silicon-based MOSFETs, resulting in high switching losses and limiting system efficiency improvements. Additionally, the physical separation of power conversion and data communication in existing solutions leads to larger system size and more complex wiring, hindering the miniaturization and weight reduction of automotive lighting control modules.

[0005] Therefore, there is an urgent need for a DC-DC converter solution that can communicate directly with the vehicle domain controller, support high bandwidth, simplify system architecture, and achieve efficient integration, in order to adapt to the transformation and upgrading of automotive electronic and electrical architecture. Summary of the Invention

[0006] To address the shortcomings of existing technologies, the purpose of this invention is to provide a GaN DC-DC converter, system architecture, and automotive lighting that supports Ethernet communication.

[0007] According to the present invention, a GaN DC-DC converter supporting Ethernet communication is integrated into the same chip, comprising: Power supply components, including GaN FET power stage units, are used to implement DC-DC power conversion; Communication components, including Ethernet physical layer interface and hardware Ethernet frame parsing circuitry; The Ethernet physical layer interface is used to connect to an external Ethernet bus, and the hardware Ethernet frame parsing circuit is used to parse instructions from the Ethernet and generate control signals according to the instructions. The control signals are output to the power supply component to control its working state.

[0008] Preferably, the power supply component further includes analog circuitry and a gate drive circuitry; The analog circuit receives the control signal and generates a PWM signal, and the gate drive circuit drives the GaN FET power stage unit according to the PWM signal.

[0009] Preferably, the communication component further includes a media access control circuit; The media access control circuit is connected between the Ethernet physical layer interface and the hardware Ethernet frame parsing circuit, and is used to process Ethernet data link layer protocols and support time-sensitive network standards.

[0010] Preferably, the communication component further includes a low-dropout linear regulator; The input of the low-dropout linear regulator is connected to an external power supply pin, and the output is connected to the Ethernet physical layer interface and the hardware Ethernet frame parsing circuit to provide a low-noise core voltage.

[0011] Preferably, it also includes an electrically erasable programmable read-only memory; The electrically erasable programmable read-only memory is connected to the hardware Ethernet frame parsing circuit and is used to store operating parameter configuration information and Ethernet MAC address.

[0012] Preferably, the hardware Ethernet frame parsing circuit is implemented as a pure hardware logic circuit, used to directly convert the control instructions in the received Ethernet frame into the control signal, without the need for an external microcontroller to participate in the parsing.

[0013] Preferably, the analog circuit includes an error amplifier for comparing the voltage or current signal detected by the feedback pin at the output of the power supply component with an internal set value, and outputting an error signal. The error signal is then used to control the duty cycle of the PWM signal after passing through a compensation network connected to the COMP pin.

[0014] Preferably, the converter is a boost converter, which includes a VOUT pin and a SW pin; The SW pin is connected to the input terminal of the GaN FET power stage unit to receive power input from the outside; The VOUT pin is connected to the output of the GaN FET power stage as a boost output.

[0015] Preferably, the converter is a buck converter, which includes a VIN pin and an SW pin; The SW pin is connected to the output terminal of the GaN FET power stage unit, and outputs a constant voltage to the subsequent load; The VIN pin is connected to the input terminal of the GaN FET power stage unit, serving as the power input terminal.

[0016] According to the present invention, a GaN DC-DC converter system architecture supporting Ethernet communication is provided, comprising: At least one of the aforementioned boost converters; At least one of the aforementioned buck converters; And an Ethernet bus connecting the boost converter and the buck converter; The output of the boost converter is connected to the input of the buck converter; both the boost converter and the buck converter are connected to the same Ethernet bus to enable direct communication with the domain controller. The Ethernet bus uses a PLCA polling mechanism for communication, where the domain controller acts as the PLCA master node and the converter acts as the PLCA slave node, sending diagnostic data within their respective allocated fixed time slots.

[0017] According to the present invention, a vehicle light includes the GaN DC-DC converter supporting Ethernet communication, or includes the GaN DC-DC converter system architecture supporting Ethernet communication.

[0018] Compared with the prior art, the present invention has the following beneficial effects: 1. The converter disclosed in this invention integrates an Ethernet physical layer interface and a hardware Ethernet frame parsing circuit, enabling it to directly establish Ethernet communication with the vehicle domain controller without relying on an external main control chip. This eliminates the software redundancy, development and maintenance complexity issues caused by independent MCUs in traditional solutions, and realizes an MCU-free vehicle lighting control solution.

[0019] 2. This invention employs Ethernet communication technology, which offers advantages such as high bandwidth and simplified wiring, and supports time-sensitive networking standards, enabling low-latency, deterministic transmission of critical control commands. Simultaneously, it integrates a physical layer collision avoidance mechanism, fundamentally preventing data conflicts through time slot allocation. This ensures that multiple converters operate stably and reliably in parallel on the same bus, significantly improving the system's anti-interference capability and communication stability.

[0020] 3. This invention encapsulates the GaN FET with the DC-DC control circuit and integrates it with the Ethernet communication circuit. This not only utilizes the high frequency and high efficiency characteristics of the GaN FET to reduce the loss and size of the power conversion section, but also reduces the number of external components and PCB area occupied through functional integration, effectively reducing the overall size, weight and manufacturing cost of the vehicle lighting control module.

[0021] 4. This invention achieves constant voltage or constant current output control by combining current sampling and voltage feedback with an external compensation network, meeting the high standards required for automotive LED driving. Simultaneously, the integrated diagnostic and protection circuitry can monitor abnormal states such as overvoltage, overcurrent, and overtemperature in real time and feed this information back to the domain controller via Ethernet, further enhancing safety. Attached Figure Description

[0022] Other features, objects, and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings: Figure 1 This is a block diagram of an Ethernet boost GaN FET converter chip in an embodiment of the present invention; Figure 2 This is a block diagram of an Ethernet buck GaN FET converter chip in an embodiment of the present invention; Figure 3 This is a schematic diagram of the first system architecture provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of a second system architecture provided in an embodiment of the present invention. Detailed Implementation

[0023] The present invention will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present invention, but do not limit the invention in any way. It should be noted that those skilled in the art can make several changes and improvements without departing from the concept of the present invention. These all fall within the scope of protection of the present invention.

[0024] This invention provides a GaN DC-DC converter that supports Ethernet communication. Through the Ethernet physical layer and link layer hard processing mechanism, combined with the digital core MCU-free Ethernet frame parsing design, it enables the vehicle body domain controller to directly control the vehicle headlight DC-DC converter, thereby promoting the realization of a truly MCU-free automotive electronic and electrical architecture for the entire vehicle.

[0025] Specifically, this converter comprises two main parts: a power supply component and a communication component. The power supply component includes GaN FET power stage units for DC-DC power conversion. The communication component includes an Ethernet physical layer interface and a hardware Ethernet frame parsing circuit. The Ethernet physical layer interface is used to connect to an external Ethernet bus, and the hardware Ethernet frame parsing circuit is used to parse instructions from the Ethernet and generate control signals based on the instructions. The control signals are output to the power supply component to control its operating state.

[0026] The GaN DC-DC converter supporting Ethernet communication provided by this invention can be specifically divided into boost converters and buck converters, which will be described in detail below.

[0027] Example 1: Reference Figure 1 As shown, this embodiment provides a boost GaN DC-DC converter that supports Ethernet communication.

[0028] 1.1 Detailed Structure of Power Supply Components The power supply components further include: GaN FET power stage unit: includes upper MOSFET 7-1 and lower MOSFET 7-2, wherein the source of upper MOSFET 7-1 and the drain of lower MOSFET 7-2 are connected to the SW pin, the drain of upper MOSFET 7-1 is connected to the VOUT pin, and the source of lower MOSFET 7-2 is grounded to PGND.

[0029] By replacing traditional silicon MOSFETs with GaN FET power stage units, high-frequency and low-loss characteristics are utilized to achieve efficient power conversion. GaN FETs can significantly improve switching frequency and power density, reduce switching losses, and meet the needs of miniaturized and high-efficiency automotive lighting control modules.

[0030] Gate Driver: The gate driver circuit is connected to the gate of both the analog circuit and the GaN FET power stage unit. It receives the PWM signal from the analog circuit that controls the GaN FET and converts the input PWM signal into a voltage signal that can drive the GaN FET, typically up to 6.5V.

[0031] The gate drive circuit is crucial for the efficient and reliable operation of GaN FETs. It integrates the following functions: ① Dead-time control: automatically generates and adjusts the brief delay between the upper and lower transistors to prevent shoot-through and ensure system safety. ② Level conversion: converts low-voltage control signals into high-voltage (or negative-voltage) signals suitable for GaN gate driving, ensuring accurate and rapid switching. ③ Charge pump function: generates a stable high voltage for reliably turning on the upper GaN FET.

[0032] Analog circuitry: Receives control requests from the hardware Ethernet frame parsing circuitry and outputs a switching PWM signal to the gate drive circuitry to drive the GaN FET. It also includes a diagnostic and protection circuit section, which returns information such as diagnostic status from the analog circuitry to the digital core circuitry (e.g., overvoltage, overcurrent, and overtemperature alarm information).

[0033] 1.2 Detailed Structure of Communication Components The communication components further include: Ethernet Physical Layer Interface (PHY): This module is located at the front end of Ethernet communication. It connects to external interface circuits via differential signals (ETH+, ETH-) to achieve modulation, demodulation, and driving between the 10Mbps digital signal defined by the Ethernet IEEE 802.3cg standard and the analog signal on the cable. Furthermore, according to the standard definition, it also integrates a Physical Layer Collision Avoidance (PLCA) sublayer. This mechanism uses a polling mechanism where an external Ethernet master node sends beacons, and converter nodes allocate fixed time slots, fundamentally avoiding data collisions on the physical lines. This allows multiple converters within the headlights to connect and operate on the same Ethernet bus.

[0034] Media Access Control (MAC): The Media Access Control circuit is connected between the Ethernet physical layer interface and the hardware Ethernet frame parsing circuit. It is used to process Ethernet data link layer protocols and supports time-sensitive network standards. It can perform precise time scheduling and priority management of data traffic to ensure low-latency, deterministic transmission of critical control commands or diagnostic data.

[0035] Hardware Ethernet frame parsing circuit (Digital Core with Ethernet Interface): This is a pure hardware logic implementation that does not require the participation of an external MCU. It directly converts the control commands in the Ethernet frame into control signals for analog circuits to achieve functions such as DC-DC output (boost or buck output voltage setting) and processing protection logic.

[0036] Low Dropout Linear Regulator (LDO): This power management module provides a stable, low-noise core voltage (typically 1.8V) to the internal digital core circuitry from the main power input (VDDA). This ensures that the Ethernet communication link operates in a clean and stable power environment, improving the stability and interference immunity of Ethernet communication.

[0037] Electrically Erasable Programmable Read-Only Memory (EEPROM): Used to store user-configured information for converter operating parameters (such as output voltage settings, overcurrent and overvoltage protection thresholds, etc.). It also stores Ethernet communication-related configuration parameters, such as the MAC address. Upon power-up, the digital circuitry loads the EEPROM information to control the analog circuitry to drive the GaN FET, loads the Ethernet communication-related configuration, and initializes the circuitry to begin Ethernet communication.

[0038] 1.3 Pin Definitions and Function Descriptions VOUT pin: Connected to the upper transistor of the internal GaN FET, serving as the boost output terminal to provide a stable boost voltage to the outside.

[0039] SW pin: Connected to the input terminal of the GaN FET power stage unit, it receives power input from the outside and is the switching node of the boost circuit.

[0040] COMP pin: External RC network used to stabilize the voltage / current feedback control loop and prevent system oscillation.

[0041] VFB pin: Feedback voltage pin, with an internal integrated resistor network, directly connected to the output terminal for output voltage monitoring.

[0042] CSP / CSN pins: Current sampling pins, which detect the input current in real time by measuring the voltage difference across the resistor, and are used for functions such as overcurrent protection.

[0043] XO / XI pins: External crystal oscillator pins, connecting to a crystal oscillator (e.g., 25MHz) to provide a precise clock for Ethernet communication.

[0044] VCC / VDDA pins: VCC supplies power to the analog circuit and gate drive circuit; VDDA supplies power to the Ethernet analog circuit.

[0045] ETH+ / ETH- pins: Ethernet differential signal pins, used to connect to an external Ethernet bus.

[0046] 1.4 Workflow Description Power-on startup: External power is input via VCC / VDDA, and after being regulated by a low-dropout linear regulator, it powers modules such as the hardware Ethernet frame parsing circuit, media access control circuit, and Ethernet physical layer interface.

[0047] Ethernet communication: The differential signal is demodulated by the Ethernet physical layer interface and sent to the media access control circuit, and then the hardware Ethernet frame parsing circuit extracts the control commands (such as output voltage setting, enable signal, etc.).

[0048] Power conversion control: The hardware Ethernet frame parsing circuit controls the analog circuit to generate PWM according to the instructions, which drives the upper and lower GaN FETs through the gate to realize boost conversion.

[0049] In a preferred embodiment, the boost converter operates as follows: under the control of the gate drive circuit, the upper and lower transistors are alternately turned on to achieve a stable voltage boost. Specifically, the upper transistor acts as a synchronous rectifier, connected between the inductor and the output terminal (VOUT). When the lower transistor is off and the upper transistor is on, the inductor is connected in series with the input power supply, jointly transferring energy to the load and output capacitor on the output side, thereby achieving boosted output. Conversely, when the upper transistor is off and the lower transistor is on, one end of the inductor is grounded, the input power supply stores energy in the inductor, and the output voltage is maintained by the output capacitor. Through the alternating conduction of the upper and lower transistors, the circuit can continuously and stably output the boosted voltage.

[0050] Feedback control: The output voltage is fed back to the analog circuit via the VFB pin and compensated by the external network via the COMP pin, ensuring that the entire control loop is both fast-responding and stable without oscillation. Combined with input commands from the EEPROM configuration and external Ethernet communication, control signals are transmitted to the analog circuit section, ultimately generating a suitable duty cycle PWM control signal which is output to the subsequent stage to achieve stable boost control.

[0051] Protection and Diagnosis: The analog circuit detects current through CSP / CSN to achieve overcurrent protection. The current regulation method is similar to the voltage regulation section in the feedback control. Diagnostic status (such as overvoltage, overtemperature) is reported to Ethernet through the digital core.

[0052] Example 2: Reference Figure 2 As shown, this embodiment provides a step-down GaN DC-DC converter that supports Ethernet communication.

[0053] The basic structures of the power supply component and the communication component are the same as those in Embodiment 1, and will not be described in detail. The difference lies in the connection method of the pins.

[0054] This embodiment of the step-down GaN DC-DC converter includes the following key pins: VIN pin: Connected to the drain of the internal GaN FET 7-1, serving as the power input terminal to receive external power.

[0055] SW pin: Connected to the source of the upper transistor 7-1 and the drain of the lower transistor 7-2 of the GaN FET power stage unit, serving as the output terminal of the GaN FET power stage unit, outputting a constant voltage or current to the subsequent load (such as an LED).

[0056] COMP pin: External RC network for loop compensation.

[0057] VFB pin: Feedback voltage pin, with an internal integrated resistor network for output voltage monitoring.

[0058] CSP / CSN pins: Current sampling pins, used to detect the current flowing through the load, support current closed-loop control, and achieve stable constant current output.

[0059] XO / XI pins: External crystal oscillator pins, providing a clock for Ethernet communication.

[0060] VCC / VDDA pins: provide power to the analog circuit and the Ethernet analog circuit, respectively.

[0061] ETH+ / ETH- pins: Ethernet differential signal pins.

[0062] 2.4 Workflow Description Power-on startup: Same as in Example 1.

[0063] Ethernet communication: Same as in Example 1.

[0064] Power conversion control: The digital core controls the analog circuit to generate PWM according to instructions, which drives the GaN FET to achieve buck conversion.

[0065] In one specific implementation, the buck conversion works as follows: under the control of the gate drive circuit, the upper and lower transistors alternately conduct to achieve a stable voltage reduction. When the upper transistor is on and the lower transistor is off, the inductor is connected in series with the load, and current flows from the input terminal (VIN) through the upper transistor to the inductor, where the inductor stores energy and supplies power to the load. Conversely, when the upper transistor is off and the lower transistor is on, the lower transistor acts as a synchronous rectifier, providing a freewheeling path for the inductor current, and the inductor releases its stored energy to continue supplying power to the load. Through the alternating conduction of the upper and lower transistors, the circuit can continuously and stably output the bucked voltage. Feedback control: the output voltage is fed back through VFB, or the output current is fed back through CSP / CSN, and after COMP compensation, the PWM duty cycle is adjusted to achieve constant voltage or constant current output.

[0066] Protection and diagnosis: Same as in Example 1.

[0067] Example 3 This embodiment provides a GaN DC-DC converter system architecture that supports Ethernet communication, such as Figure 3 and Figure 4 As shown, it includes: at least one boost GaN DC-DC converter as described in Embodiment 1, at least one buck GaN DC-DC converter as described in Embodiment 2, and an Ethernet bus connecting the two.

[0068] The output of the boost converter is connected to the input of the buck converter. Both the boost and buck converters are connected to the same Ethernet bus for direct communication with the domain controller. The boost converter provides a stable constant voltage input to the buck converter to establish a reliable operating voltage environment. Based on constant voltage / constant current control characteristics, the buck converter is configured with two output channels in the system architecture. The first channel is set to constant voltage output mode to provide a stable voltage to subsequent circuits, and the second channel is set to constant current output mode to drive the critical load LEDs in automotive lighting applications. The Ethernet bus uses a PLCA polling mechanism for communication, with the domain controller acting as the PLCA master node and the converter acting as the PLCA slave node, sending diagnostic data within their respective allocated fixed time slots.

[0069] exist Figure 3 In the illustrated embodiment, both the boost converter and the buck converter utilize the integrated Ethernet communication function proposed in this invention, forming two Ethernet nodes. They are connected to the vehicle's Ethernet bus via a single pair of Ethernet differential lines (ETH+, ETH-). The differential lines form the bus topology internally through direct connection and are connected to the vehicle's Ethernet bus via an external physical interface.

[0070] exist Figure 4 The illustrated embodiment provides a scheme for a single node to access the vehicle's Ethernet bus. The Boost converter uses the integrated Ethernet communication function described in this invention, and is connected to the vehicle's Ethernet bus via a single pair of Ethernet differential lines (ETH+, ETH-). Figure 3 The implementation method differs in that the secondary-side Buck converter uses a conventional Buck chip without Ethernet communication capabilities. It typically employs an SPI communication interface (including CS, CLK, MOSI, and MISO signal lines) to form a typical four-wire board-level communication protocol. While the Boost converter connects to the Ethernet and executes received frame commands, it can also transmit operation commands that need to be executed by the Buck converter to the latter via the SPI interface. The advantages of this implementation method are: firstly, compared to... Figure 3 The solution uses two Ethernet nodes. Figure 4 This implementation effectively reduces the number of Ethernet nodes, freeing up node resources that can be used by other sensors or actuators in the vehicle, thereby reducing the overall cost of the vehicle design. On the other hand, under this architecture, the secondary Buck chip no longer needs to use a DC-DC converter with Ethernet communication capabilities, which not only broadens the selection of chips but also avoids the additional costs associated with redundant integration of Ethernet communication hardware.

[0071] Operating Principle: After the system powers on, both the boost converter and the buck converter receive external power through their respective VCC / VDDA pins. The internal LDO begins operation, providing a stable core voltage (e.g., 1.8V) to the digital core, MAC, PHY, and other low-voltage modules. Simultaneously, each converter loads its operating parameter configuration information (such as output voltage settings and overcurrent / overvoltage protection thresholds) and Ethernet MAC address from its internal EEPROM. The digital core initializes the analog circuitry and Ethernet communication module based on the loaded configuration, completing startup preparation.

[0072] The system employs a 10BASE-T1S Ethernet bus, with a physical layer integrated PLCA (Physical Collision Avoidance) mechanism. The domain controller, acting as the PLCA master node, periodically sends beacon signals on the bus, allocating fixed transmission time slots to each slave node (i.e., boost converters and buck converters). Each converter, acting as a PLCA slave node, synchronizes its local time slot counter upon receiving the beacon, transmitting data only within its assigned time slot, thus fundamentally avoiding data collisions and ensuring deterministic and real-time communication.

[0073] The domain controller sends control command frames to the target converter via the Ethernet bus. The command frames are first received by the converter's PHY and demodulated into a digital bitstream, then sent to the MAC for address filtering and error checking. After verification, the frame data is passed to the hardware Ethernet frame parsing circuit. This circuit is a pure hardware logic implementation, requiring no MCU involvement, directly parsing the IP header, UDP / TCP port number, and application layer data in the Ethernet frame to extract specific control commands (such as output voltage adjustment, enable switching, fault diagnosis reading, etc.). The parsed commands are immediately converted into control signals recognizable by the analog circuitry, adjusting the PWM duty cycle or switching operating modes.

[0074] A boost converter receives an input voltage (e.g., 12V) from a pre-amplifier power source (such as an automotive battery), boosts it using an internal GaN FET power stage, and outputs a stable intermediate bus voltage (e.g., 24V or 48V). This bus voltage directly serves as the input power supply (VIN) for a buck converter. Based on this bus voltage, and following instructions from the domain controller, the buck converter performs a step-down conversion using its internal GaN FET power stage to generate the voltage or current required by the subsequent stage. In both boost and buck topologies, the upper and lower transistors switch sequentially under the control of gate drive signals, respectively storing and releasing energy to achieve voltage conversion and stable output.

[0075] In typical applications, the buck converter can be configured with two output channels: the first channel is set to constant voltage output mode (e.g., 5V or 3.3V) to power sensors or logic circuits; the second channel is set to constant current output mode to directly drive the vehicle headlight LED load and ensure constant LED brightness.

[0076] During power conversion, the boost converter monitors the output voltage via the VFB pin and the input current via the CSP / CSN pin; the buck converter monitors the output voltage or load current via either the VFB or CSP / CSN pin. The feedback signal is sent to the analog circuit, compared with the internal setpoint to generate an error signal. This error signal is adjusted by an external compensation network connected to the COMP pin to control the PWM duty cycle, achieving precise voltage or current regulation. Simultaneously, the protection logic in the analog circuit monitors for abnormal states such as overvoltage, overcurrent, and overtemperature in real time. Once triggered, it immediately takes protective measures and records the fault information through the digital core.

[0077] During operation, each converter's digital core periodically collects diagnostic information from the analog circuitry (such as real-time voltage, current, and temperature values, as well as fault indicators). When the PLCA time slot for this node arrives, the digital core encapsulates the diagnostic data into an Ethernet frame and sends it to the Ethernet bus via the MAC and PHY. The domain controller receives this data within the time slots of each slave node, enabling real-time monitoring of the entire system's operating status. If an anomaly is detected, the domain controller can promptly issue commands for adjustments or trigger alarms.

[0078] Specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various changes or modifications within the scope of the claims, which do not affect the essence of the present invention. Unless otherwise specified, the embodiments and features described in this application can be arbitrarily combined with each other.

Claims

1. A GaN DC-DC converter supporting Ethernet communication, characterized in that, Integrated into the same chip, including: Power supply components, including GaN FET power stage units, are used to implement DC-DC power conversion; Communication components, including Ethernet physical layer interface and hardware Ethernet frame parsing circuitry; The Ethernet physical layer interface is used to connect to an external Ethernet bus, and the hardware Ethernet frame parsing circuit is used to parse instructions from the Ethernet and generate control signals according to the instructions. The control signals are output to the power supply component to control its working state.

2. The GaN DC-DC converter supporting Ethernet communication according to claim 1, characterized in that, The power supply component also includes analog circuitry and gate drive circuitry; The analog circuit receives the control signal and generates a PWM signal, and the gate drive circuit drives the GaN FET power stage unit according to the PWM signal.

3. The GaN DC-DC converter supporting Ethernet communication according to claim 1, characterized in that, The communication component also includes a media access control circuit. The media access control circuit is connected between the Ethernet physical layer interface and the hardware Ethernet frame parsing circuit, and is used to process Ethernet data link layer protocols and support time-sensitive networking standards. The communication components also include a low-dropout linear regulator; The input of the low-dropout linear regulator is connected to an external power supply pin, and the output is connected to the Ethernet physical layer interface and the hardware Ethernet frame parsing circuit to provide a low-noise core voltage.

4. The GaN DC-DC converter supporting Ethernet communication according to claim 1, characterized in that, It also includes electrically erasable programmable read-only memory; The electrically erasable programmable read-only memory is connected to the hardware Ethernet frame parsing circuit and is used to store operating parameter configuration information and Ethernet MAC address.

5. The GaN DC-DC converter supporting Ethernet communication according to claim 1, characterized in that, The hardware Ethernet frame parsing circuit is implemented as a pure hardware logic circuit, used to directly convert the control instructions in the received Ethernet frame into the control signal, without the need for an external microcontroller to participate in the parsing.

6. The GaN DC-DC converter supporting Ethernet communication according to claim 2, characterized in that, The analog circuit includes an error amplifier, which compares the voltage or current signal detected by the feedback pin from the power supply component with an internal set value and outputs an error signal. The error signal is then used to control the duty cycle of the PWM signal after passing through a compensation network connected to the COMP pin.

7. The GaN DC-DC converter supporting Ethernet communication according to claim 1, characterized in that, The converter is a boost converter, which includes a VOUT pin and a SW pin; The SW pin is connected to the input terminal of the GaN FET power stage unit to receive power input from the outside; The VOUT pin is connected to the output of the GaN FET power stage as a boost output.

8. The GaN DC-DC converter supporting Ethernet communication according to claim 1, characterized in that, The converter is a step-down converter, which includes a VIN pin and an SW pin; The SW pin is connected to the output terminal of the GaN FET power stage unit, and outputs a constant voltage to the subsequent load; The VIN pin is connected to the input terminal of the GaN FET power stage unit, serving as the power input terminal.

9. A GaN DC-DC converter system architecture supporting Ethernet communication, characterized in that, include: At least one boost converter as described in claim 8; At least one buck converter as described in claim 9; And an Ethernet bus connecting the boost converter and the buck converter; The output of the boost converter is connected to the input of the buck converter; both the boost converter and the buck converter are connected to the same Ethernet bus to enable direct communication with the domain controller. The Ethernet bus uses a PLCA polling mechanism for communication, where the domain controller acts as the PLCA master node and the converter acts as the PLCA slave node, sending diagnostic data within their respective allocated fixed time slots.

10. A vehicle light, characterized in that, It includes the GaN DC-DC converter supporting Ethernet communication as described in any one of claims 1-8, or it includes the GaN DC-DC converter system architecture supporting Ethernet communication as described in claim 9.

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