Vehicle-mounted domain controller high-order HDI circuit board and processing method thereof

Abstract

This invention relates to the field of circuit board technology and discloses a high-order HDI circuit board for an automotive domain controller and its processing method. The board includes a board body comprising several circuit layers and insulating dielectric layers stacked along its thickness direction. At least one of the circuit layers is a reference plane layer, providing a reference reference for high-speed signal fan-out around the chip pad group. By arranging multiple ground vias connected to the reference plane layer on the outer periphery of blind vias, with these ground vias spaced around the layer-switching interconnect channels, when a high-speed signal enters the blind via from a thin line and switches to an inner circuit layer, its return current establishes a continuous return path with the reference plane layer via the ground vias, reducing the distance the return current travels in the layer-switching area and weakening the electromagnetic coupling between adjacent layer-switching channels. This reduces signal reflection caused by impedance abrupt changes and suppresses crosstalk between high-speed signals, thereby improving the signal integrity and operational stability of the automotive domain controller.

Description

Technical Field

[0001] This invention relates to the field of circuit board technology, and more specifically, to a high-order HDI circuit board for an in-vehicle domain controller and its processing method. Background Technology

[0002] With the development of intelligent driving, vehicle networking, and multi-domain fusion architecture, automotive domain controllers are gradually evolving towards higher computing power and higher integration. The data exchange rate between the main control chip and high-speed memory, SerDes interface, and high-speed communication module is constantly increasing, which places higher demands on the high-density interconnection capability, high-speed signal transmission stability, and board-level electromagnetic compatibility performance of PCBs. High-density interconnect (HDI) circuit boards, due to their ability to interconnect with fine lines, small apertures, and multi-level blind and buried vias, have been widely used in automotive domain controllers, advanced driver assistance systems, and central computing platforms. Among these, the fan-out routing structure and layer-change interconnection structure of the chip pad area directly affect the transmission quality of high-speed signals and the overall stability of the board operation.

[0003] In existing high-end HDI circuit boards, blind vias are typically used to connect the chip pad area to the inner layer circuitry, and a grounding structure is set around them to improve electromagnetic compatibility performance. However, during the process of high-speed signals entering the blind via layer-switching channel from the chip pads through fine lines, the high local interconnect density in the fan-out area easily leads to the formation of discontinuous reference return paths in the layer-switching area. This is especially true during the layer-switching of high-speed differential signals or high-frequency signals, which can easily cause enhanced local electric field coupling and return path detours around the blind vias. This results in increased impedance fluctuations in the layer-switching area, further increasing signal reflection and crosstalk, and affecting the signal integrity and operational stability of the vehicle domain controller in high-speed data transmission scenarios.

[0004] Therefore, there is a need to provide a high-order HDI circuit board for vehicle domain controllers and its fabrication method to solve the problem of signal reflection and crosstalk caused by the unstable return path in the layer switching area of ​​existing high-order HDI circuit boards, which affects the signal transmission quality. Summary of the Invention

[0005] The main objective of this invention is to provide a high-order HDI circuit board for an in-vehicle domain controller and its processing method, aiming to solve the technical problems mentioned in the background section.

[0006] The present invention adopts the following technical solution: A high-order HDI circuit board for an in-vehicle domain controller and its processing method are disclosed. The board includes a board body, wherein the board body includes a plurality of circuit layers and insulating dielectric layers stacked along the thickness direction, and at least one of the circuit layers is a reference plane layer. A chip pad group is provided on one end face of the board. A fan-out area is provided on the outer periphery of the chip pad group. A fine line connected to the chip pad group is provided in the fan-out area. The fine line is connected to the inner circuit layer of the board through a blind via to form a layer switching interconnection channel. A grounding via is provided on the outer periphery of the blind via. Multiple grounding vias are connected to the reference plane layer and are distributed at intervals around the layer switching interconnection channel.

[0007] Furthermore, the blind vias include multiple levels of blind vias arranged sequentially from one end of the board inwards, with adjacent levels of blind vias communicating with different inner circuit layers respectively. The board is a 3rd-order HDI structure or a sequentially laminated HDI structure of higher than 3rd order, and at least some of the adjacent levels of blind vias form a stacked interconnect structure to enable high-density interconnection of the chip pad group to multiple inner circuit layers.

[0008] Furthermore, the reference plane layer includes a ground plane layer and / or a power plane layer, at least one of the circuit layers is a signal wiring layer, and at least one signal wiring layer is disposed adjacent to at least one reference plane layer, the insulating dielectric layer is located between adjacent circuit layers, wherein the total number of layers of the board is 6 to 16 layers.

[0009] Furthermore, the fine lines extend radially outward from the chip pad group and connect to the blind vias, with adjacent fine lines spaced apart in the fan-out area, and the line width of the fine lines is 50μm to 75μm.

[0010] Furthermore, the board body is also provided with through holes, which are distributed on the outer periphery of the grounding vias. The blind vias are provided between the chip pad group and the multiple grounding vias. The diameter of the blind vias is 0.075mm to 0.10mm, and the diameter of the through holes is 0.15mm to 0.20mm.

[0011] Furthermore, the thin line includes a differential thin line, which is disposed on the signal routing layer. The differential thin line and the reference plane adjacent to the signal routing layer form a differential impedance control structure. Multiple ground vias are distributed at intervals along the outer periphery of the connection between the differential thin line and the blind via. The impedance control tolerance of the differential thin line is ±8%.

[0012] Furthermore, the insulating dielectric layer is distributed between the signal wiring layer and the adjacent reference plane layer, wherein the insulating dielectric layer is a high-speed, low-loss material.

[0013] A method for fabricating an automotive domain controller high-order HDI circuit board, used to fabricate the automotive domain controller high-order HDI circuit board as described in any of the preceding claims, comprising: A laminated board is provided, with a chip pad group on one end face of the board, a fan-out area on the outer periphery of the chip pad group, and fine lines connected to the chip pad group in the fan-out area. The board includes at least one reference plane layer. Blind holes are machined at the end of the thin line, and multiple grounding vias are machined around the outer periphery of the blind hole at preset intervals, using the center of the blind hole as a reference. The blind vias and multiple grounding vias are plated with copper to make them conductive to the inner circuit layers of the board, and the multiple grounding vias are conductive to the reference plane layer.

[0014] Furthermore, the step of machining multiple grounding vias by using the center of the blind hole as a reference and performing circumferential positioning at preset intervals on the outer periphery of the blind hole includes: Establish a circumferential positioning reference with the center of the blind hole, control the drill bit to be perpendicular to the plate surface, and drill around the blind hole one by one in a staggered order from near to far to form multiple grounding vias.

[0015] Furthermore, during the processing of multiple grounding vias, directional airflow is simultaneously applied to the drilling area of ​​the board, and the directional airflow is arranged along the board surface in a direction away from the blind holes.

[0016] Beneficial effects: In this invention, by setting stacked circuit layers and insulating dielectric layers within the board body, and using at least one circuit layer as a reference plane layer, a reference reference is provided for the high-speed signal fan-out around the chip pad group. Fine lines within the fan-out area are connected to the inner circuit layer through blind vias, allowing high-density signals at the chip pad group to complete layer-switching interconnections within a smaller wiring space, adapting to the wiring requirements of densely packed chip pins and concentrated signal channels in automotive domain controllers. Furthermore, by arranging multiple ground vias connected to the reference plane layer on the outer periphery of the blind vias, and distributing these ground vias at intervals around the layer-switching interconnection channels, a surrounding ground reference structure is formed around the layer-switching location of the blind vias. When a high-speed signal enters a blind via through a thin line and switches to the inner circuit layer, its return current can establish a continuous return path with the reference plane layer through the ground via, reducing the distance the return current travels in the layer switching area and weakening the electromagnetic coupling between adjacent layer switching channels. This makes the electromagnetic field distribution around the layer switching interconnect channel more concentrated, reduces signal reflection caused by impedance abrupt changes, and suppresses crosstalk between high-speed signals, thereby improving the signal integrity and operational stability of the vehicle domain controller during high-speed data transmission. Attached Figure Description

[0017] Figure 1 This is a first partial structural schematic diagram of the high-order HDI circuit board of the vehicle domain controller of the present invention; Figure 2This is a second partial cross-sectional schematic diagram of the high-order HDI circuit board of the vehicle domain controller of the present invention; Figure 3 This is a schematic diagram of the third partial structure of the high-order HDI circuit board of the vehicle domain controller of the present invention; in: 1. Board body; 11. Circuit layer; 12. Insulating dielectric layer; 13. Reference plane layer; 131. Ground plane layer; 132. Power plane layer; 2. Chip pad group; 3. Fan-out area; 31. Fine line; 4. Blind via; 5. Ground via; 6. Through hole.

[0018] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0019] It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0020] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0021] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, a direct connection, or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0022] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0023] Reference Figures 1 to 3 The present invention proposes a high-order HDI circuit board for vehicle domain controller and its processing method, including a board body 1, wherein the board body 1 includes a plurality of circuit layers 11 and insulating dielectric layers 12 stacked along the thickness direction, and at least one of the plurality of circuit layers 11 is a reference plane layer 13. A chip pad group 2 is provided on one end face of the board body 1. A fan-out area 3 is provided on the outer periphery of the chip pad group 2. A fine line 31 connected to the chip pad group 2 is provided in the fan-out area 3. The fine line 31 is connected to the inner circuit layer 11 of the board body 1 through a blind hole 4 to form a layer switching interconnection channel. A grounding via 5 is provided on the outer periphery of the blind via 4. Multiple grounding vias 5 are connected to the reference plane layer 13, and multiple grounding vias 5 are distributed at intervals around the layer switching interconnection channel.

[0024] In the above embodiment, the board body 1 is composed of a plurality of circuit layers 11 and insulating dielectric layers 12 stacked sequentially along the thickness direction. Each circuit layer 11 includes a signal wiring layer and a reference plane layer 13. The reference plane layer 13 can be disposed on one or both sides of an adjacent signal wiring layer as a ground reference layer and / or a power reference layer, so that a stacked structure suitable for high-speed signal transmission is formed inside the board body 1.

[0025] One end face of the board 1 is provided with a chip pad group 2. The chip pad group 2 can be centrally arranged to correspond to the pin areas of the main control chip or high-speed device. A fan-out area 3 is formed on its outer periphery. Fine lines 31 extending outward from the chip pad group 2 are provided in the fan-out area 3. The fine lines 31 can be distributed radially, parallelly, or with partial bends to complete the pad lead-out within a limited area. The end of the fine lines 31 is connected to a blind via 4. The blind via 4 extends from the surface layer of the board 1 to the inner circuit layer 11, so that the fan-out signal from the surface layer can be transferred to the inner circuit layer 11, forming a layer switching interconnection channel. This layer switching interconnection channel can be set for a single signal channel or for differential signal pairs arranged in parallel, thereby meeting the wiring requirements of high-density pins, high-speed interfaces, and multi-channel parallel transmission in the vehicle domain controller. The insulating dielectric layer 12 separates adjacent circuit layers 11 from each other, maintaining a predetermined electrical isolation relationship between the fine lines 31, the inner circuit layers 11 and the reference plane layer 13, and ensuring that the board 1 still has a stable interlayer support structure under multilayer interconnection conditions.

[0026] Multiple grounding vias 5 are provided on the outer periphery of the blind via 4. These grounding vias 5 are connected to the reference plane layer 13 and are distributed at intervals around the layer switching interconnection channel. The multiple grounding vias 5 can be arranged in a ring shape, a semi-ring shape, or an encircling arrangement along the periphery of the layer switching interconnection channel, so that the area where the blind via 4 is located forms a local enclosure-type grounding reference structure. The grounding vias 5 can be directly connected to the adjacent reference plane layer 13, or they can be connected to different reference plane layers 13 across multiple layers, thereby establishing a relatively concentrated return current path around the blind via 4. When a high-speed signal enters the blind via 4 along the thin line 31 and switches to the inner circuit layer 11, its corresponding return current can be coupled to the grounding vias 5 nearby around the blind via 4 and return to the reference plane layer 13, reducing the return current detour and the outward expansion of the field distribution at the layer switching position.

[0027] After multiple grounding vias 5 form circumferential constraints on the layer-swapping interconnect channels, they can also isolate the coupling between adjacent thin lines 31 and adjacent layer-swapping channels, making the electric field distribution in the layer-swapping region more convergent. Therefore, the high-order HDI circuit board in this embodiment can not only achieve high-density fan-out and multi-layer layer-swapping interconnection in the chip pad area, but also make the reference relationship at the layer-swapping position clearer, which is conducive to maintaining the continuity and stability of high-speed signals during fan-out, layer-swapping and inner layer transmission. It is suitable for automotive domain controller applications that require high-speed, high-density and high-reliability electrical connections.

[0028] In one embodiment, the blind via 4 includes multiple levels of blind vias 4 arranged sequentially from one end of the board body 1 inwards. The blind vias 4 of adjacent levels are respectively connected to different inner circuit layers 11. The board body 1 is a 3rd-order HDI structure or a sequentially laminated HDI structure of higher than 3rd order. At least some of the blind vias 4 of adjacent levels form a stacked interconnect structure to enable high-density interconnection of the chip pad group 2 to multiple inner circuit layers 11.

[0029] In the above embodiment, the blind via 4 includes multiple levels of blind via 4 arranged sequentially from one end of the board 1 inwards. The multiple levels of blind via 4 are arranged in layers along the thickness direction corresponding to different inner circuit layers 11. Adjacent levels of blind via 4 are respectively connected to different inner circuit layers 11. The bottom area of ​​the upper level blind via 4 located on the outer side is opposite to the opening area of ​​the lower level blind via 4 located on the inner side. At least some adjacent levels of blind via 4 form a stacked interconnect structure with vertical connections at the interlayer connection position. The board 1 can be a 3rd-order HDI structure or a sequential lamination HDI structure higher than 3rd order. In this type of structure, the blind vias 4 of different levels can respectively undertake the signal transfer function from the surface layer to the shallow layer, from the shallow layer to the middle layer, and from the middle layer to the deeper layer, so that the signal brought out from the chip pad group 2 is not limited to a single layer transfer depth, but can be diverted to multiple inner circuit layers 11 according to the degree of wiring congestion.

[0030] Furthermore, the multi-level blind vias 4 can be partitioned around the area where the chip pad group 2 is located, so that some blind vias 4 are preferentially directed to the inner layer channels close to the reference plane layer 13, and some blind vias 4 are directed to deeper functional circuit areas, thereby forming a vertically unfolded interconnect network within a limited board area. After two adjacent levels of blind vias 4 form a stacked interconnect, the connection path between the chip pad group 2 and the target inner circuit layer 11 is more concentrated, avoiding excessive congestion in the fan-out area 3 caused by excessively long extension of the surface layer fine lines 31; at the same time, the multi-level blind vias 4 can also be allocated according to different signal categories, such as directing high-speed signals, control signals or power supply related leads to different layers, so as to enhance the wiring hierarchy between layers in the board, and enable the high-order HDI structure to maintain high interconnect capability in high pin density scenarios.

[0031] In one example, the reference plane layer 13 includes a ground plane layer 131 and / or a power plane layer 132, at least one of the circuit layers 11 is a signal wiring layer, and at least one signal wiring layer is disposed adjacent to at least one reference plane layer 13, and the insulating dielectric layer 12 is located between adjacent circuit layers 11, wherein the total number of layers of the board 1 is 6 to 16.

[0032] In the above embodiments, the reference plane layer 13 includes a ground plane layer 131 and / or a power plane layer 132. At least one of the circuit layers 11 is a signal routing layer, and at least one signal routing layer is disposed adjacent to at least one reference plane layer 13. An insulating dielectric layer 12 is located between adjacent circuit layers 11, so that a stacked relationship of alternating signal layers, reference layers, and insulating layers is formed inside the board 1. The total number of layers in the board 1 is 6 to 16. With a lower number of layers, it can meet the main control, storage, and interface connection requirements of a general domain controller. With a higher number of layers, it can accommodate more high-speed interfaces, differential pairs, and power distribution networks. The reference plane layer 13 can be laid out continuously across the entire surface, or it can form windows or clearance areas in local areas to avoid devices and vias. However, it is still continuously distributed next to the signal routing layer to provide a stable reference during signal transmission. The signal routing layer can be located between the ground plane layer 131 and the power plane layer 132, or it can be located adjacent to the ground plane layer 131 only. The specific arrangement can be adjusted according to the signal attributes of different areas. The signal routing layer located in the fan-out direction of the chip pad group 2 can be preferentially adjacent to the reference plane layer 13, so that the fine lines 31, blind vias 4 and inner layer conductors are in a relatively clear reference environment before and after the layer change. In addition to its interlayer isolation function, the insulating dielectric layer 12 also supports and limits the positional relationship of each circuit layer 11, so that the board 1 maintains a stable interlayer thickness in the multilayer structure.

[0033] In one example, the fine lines 31 extend radially outward from the chip pad group 2 and connect to the blind via 4. Adjacent fine lines 31 are spaced apart in the fan-out area 3. The line width of the fine lines 31 is 50μm to 75μm.

[0034] In the above embodiment, the fine lines 31 extend radially outward from the chip pad group 2 and connect to the blind vias 4. Adjacent fine lines 31 are spaced apart in the fan-out area 3, and the linewidth of the fine lines 31 is 50μm to 75μm. Radial extension means that each fine line 31 extends outward in different directions from the chip pad group 2 as the center or from the edge of the pad array as the starting area, forming a wiring pattern that radiates outward from the inside. This corresponds to the array distribution of the chip pad group 2, allowing both the inner and outer pads to obtain their own lead-out channels within the fan-out area 3. Maintaining a predetermined interval between adjacent fine lines 31 allows each line to remain relatively independent during the fan-out process, avoiding excessive proximity between lines at local turning points. The blind vias 4 can be set at the end or adjacent area of ​​each fine line 31, allowing the fine lines 31 to quickly enter the interlayer transition after completing the surface layer lead-out.

[0035] The radial fine lines 31 can form straight extension sections, arc transition sections, or zigzag transition sections according to the shape of the pad group. The parts near the pads can be shorter and densely distributed, while the parts near the blind vias 4 can gradually increase in spacing to accommodate the circumferential distribution of the blind vias 4. The line width is controlled within the range of 50μm to 75μm, which is beneficial for arranging more lines within a limited fan-out area and also ensures good continuity of the lines themselves, preventing them from occupying too much channel space due to excessive width. After the corresponding connections between each fine line 31 and the blind via 4, a regular fan-out network can be formed around the chip pad group 2, making the path relationship of signals from the pads into the fine lines 31 and then into the blind vias 4 clearer, facilitating orderly surface layer lead-out and inner layer distribution in high-density device areas.

[0036] In one example, the board body 1 is further provided with through holes 6, which are distributed on the outer periphery of the grounding vias 5. The blind holes 4 are provided between the chip pad group 2 and the multiple grounding vias 5. The diameter of the blind holes 4 is 0.075mm to 0.10mm, and the diameter of the through holes 6 is 0.15mm to 0.20mm.

[0037] In the above embodiment, in addition to the blind vias 4 used for fan-out layer switching of the chip pad group 2, the board body 1 is also provided with through vias 6 that penetrate at least part of the stacked structure. The through vias 6 are located in the outer periphery of multiple ground vias 5, and can form an outer channel distribution band along the periphery of the chip pad group 2. The blind vias 4 are located between the chip pad group 2 and the ground vias 5, and are used to receive the high-density fine lines 31 led out from the pad group, and to preferentially complete the short-distance layer switching from the surface layer to the inner layer; the ground vias 5 form a local reference constraint around the area where the blind vias 4 are located; the through vias 6 are further provided outside the ground vias 5, so that a hierarchical via structure is formed in the board body from the inside out, namely the chip pad group 2, the blind via 4 area, the ground via 5 area, and the through via 6 area. The blind vias 4 mainly undertake the task of fast layer switching of high-density signals, while the through vias 6 can undertake electrical connections across more layers, auxiliary ground connections, or conduction of remote functional areas, so that different types of interlayer connections are clearly partitioned inside the board body 1.

[0038] The diameter of blind via 4 is smaller than that of through via 6, allowing blind via 4 to be arranged closer to chip pad group 2 and fan-out fine lines 31, adapting to the space constraints of high-density lead-out areas; the diameter of through via 6 is relatively larger, which can improve its longitudinal conductivity stability and facilitate the establishment of connections with deeper layers. Through via 6 can be distributed in a ring, row and column, or along the functional area boundary. When working together with peripheral ground via 5, it can also form a further structural isolation layer around the layer-changing area, distinguishing the fine interconnects close to chip pad group 2 from the larger interlayer connections on the periphery.

[0039] In one example, the thin line 31 includes a differential thin line 31 disposed on the signal routing layer. The differential thin line 31 and the reference plane adjacent to the signal routing layer form a differential impedance control structure. A plurality of ground vias 5 are distributed at intervals along the outer periphery of the connection between the differential thin line 31 and the blind via 4. The impedance control tolerance of the differential thin line 31 is ±8%.

[0040] In the above embodiment, the thin lines 31 include paired differential thin lines 31, which are laid on the signal routing layer. The two parallel lines can be led out from the corresponding differential pads in the chip pad group 2, and maintain a basically consistent extension direction and similar line length within the fan-out region 3. A reference plane layer 13 is provided below or adjacent to the differential thin lines 31. The reference plane layer 13 can be a continuous ground plane layer 131, or a reference conductor layer that maintains overall continuity after partially avoiding other structures, so that a relatively stable differential impedance control relationship is formed between the differential thin lines 31 and the reference plane. The two differential thin lines 31 may include a lead-out section near the pad group, a parallel transmission section located in the fan-out region 3, and a transition section before connecting the blind via 4. The transition section can adopt a symmetrical bend, arc buffer, or equal length compensation form to ensure that the two lines maintain a relatively consistent electrical state before entering the connection area of ​​the blind via 4.

[0041] On the outer periphery of the connection between the differential thin line 31 and the blind via 4, multiple grounding vias 5 are spaced apart along the connection area. The grounding vias 5 do not directly contact the differential thin line 31, but instead form a local grounding constraint boundary around the differential layer switching position, ensuring that the surrounding reference environment remains relatively continuous when the differential signal switches from the surface layer to the inner layer. The blind vias 4 corresponding to the differential thin line 31 can be arranged in pairs or side-by-side, provided the spacing requirements are met, so that the layer switching positions of the two lines correspond to each other. After limiting the impedance control tolerance to ±8%, the interlayer relationship between the differential thin line 31 and the adjacent reference plane, the line spacing, and the transition shape of the layer switching position are coordinated, resulting in good parameter consistency for the differential pair during fan-out, parallel transmission, and layer switching processes.

[0042] In one embodiment, the insulating dielectric layer 12 is distributed between the signal wiring layer and the adjacent reference plane layer 13, wherein the insulating dielectric layer 12 is a high-speed, low-loss material.

[0043] In the above embodiments, the insulating dielectric layer 12 is disposed between the signal routing layer and the adjacent reference plane layer 13, and exists as an interlayer support medium between the two. The insulating dielectric layer 12 can adopt a sheet-like laminated structure, which is continuously laid out in the planar direction inside the board body 1, keeping the signal routing layer and the reference plane layer 13 separated at predetermined intervals, so that the adjacent conductive layers have both electrical insulation relationship and stable geometric correspondence. For the signal routing layer near the chip pad group 2 and the fan-out area 3, the insulating dielectric layer 12 not only undertakes the basic isolation function, but also enables the reference plane layer 13 below or adjacent to the fine line 31 to maintain a relatively fixed positional relationship, thereby forming a more defined hierarchical structure of the fine line 31 in the fan-out area 3, the layer switching area of ​​the blind via 4, and the inner layer conductors in the thickness direction of the board body 1. The insulating dielectric layer 12 can cover the interlayer space between the blind via 4 and the ground via 5, and together with other insulating dielectric layers 12 in the board, it forms a multilayer stacked system. Furthermore, the insulating dielectric layer 12 is a high-speed, low-loss material, specifically having a low dielectric constant and dielectric loss factor, which can reduce dielectric loss and signal distortion during high-speed signal transmission. It can be a modified epoxy resin substrate, or a low-dielectric material such as hydrocarbon resin or polytetrafluoroethylene, so that the plate 1 maintains a relatively uniform interlayer electrical environment under high-frequency and high-speed application conditions.

[0044] The present invention also provides a method for fabricating a high-order HDI circuit board for an in-vehicle domain controller, for fabricating the high-order HDI circuit board for an in-vehicle domain controller as described in any of the preceding claims, comprising: A laminated board 1 is provided. A chip pad group 2 is provided on one end face of the board 1. A fan-out area 3 is provided on the outer periphery of the chip pad group 2. A fine line 31 connected to the chip pad group 2 is provided in the fan-out area 3. The board 1 includes at least one reference plane layer 13. A blind hole 4 is machined at the end of the thin line 31, and multiple grounding vias 5 are machined around the outer periphery of the blind hole 4 at a preset interval, with the center of the blind hole 4 as a reference. Blind via 4 and multiple grounding vias 5 are copper-plated on their walls to connect blind via 4 to the inner circuit layer 11 of board 1, and to connect multiple grounding vias 5 to the reference plane layer 13.

[0045] In the above embodiment, a high-order HDI circuit board is formed. A laminated board body 1 is provided, with circuit layers 11 and insulating dielectric layers 12 stacked along the thickness direction already formed inside the board body 1, wherein at least one circuit layer 11 is provided as a reference plane layer 13. A chip pad group 2 is formed on one end face of the board body 1, with a fan-out area 3 reserved around the periphery of the chip pad group 2. A thin line 31 connected to the chip pad group 2 is provided within the fan-out area 3, extending outward to a predetermined layer-switching position, with its end corresponding to the area where a subsequent blind via 4 is located. A blind via 4 is formed at the end of the thin line 31, providing a channel basis for signals from the surface layer to switch to the inner circuit layer 11 of the board body 1. Simultaneously, using the center position of the formed blind via 4 as a circumferential positioning reference, multiple grounding vias 5 are distributed in the corresponding area on its outer periphery.

[0046] After the blind vias 4 and multiple grounding vias 5 are formed, copper plating is applied to the walls of each via to create a continuous conductive layer. The blind via 4 is connected to the corresponding inner circuit layer 11 through the metal layer of its wall, forming a signal layer switching channel. The multiple grounding vias 5 are connected to the reference plane layer 13, forming a circumferential grounding structure connected to the reference plane around the blind via 4. The chip pad group 2, the fan-out area 3 fine lines 31, the layer switching structure of the blind via 4, and the peripheral grounding vias 5 on the surface of the board 1 form a corresponding processing relationship, so that the layer switching interconnection area and the reference conductive area are established synchronously in space, which is suitable for forming a stable interlayer connection structure in the high-density fan-out area 3 around the chip.

[0047] In one embodiment, the step of machining multiple grounding vias 5 by using the center of the blind via 4 as a reference and performing circumferential positioning at preset intervals on the outer periphery of the blind via 4 includes: Establish a circumferential positioning reference with the center of blind hole 4, control the drill bit to be perpendicular to the surface of plate 1, and drill around blind hole 4 one by one in order from near to far and with adjacent holes staggered to form multiple grounding via holes 5.

[0048] In the above embodiment, a circumferential positioning reference is established with the geometric center of the blind hole 4. The circumferential positioning reference can correspond to a single circular distribution trajectory or a local arc distribution trajectory set around the blind hole 4. After positioning, the drill bit is controlled to cut perpendicularly to the surface of the plate 1, so that the axial direction of each grounding via 5 is basically consistent with the thickness direction of the plate 1, thereby forming a relatively regular three-dimensional distribution relationship around the blind hole 4. The multiple grounding vias 5 are drilled one by one in the order of surrounding the blind hole 4 from near to far, with adjacent holes staggered. The grounding vias 5 close to the blind hole 4 first form a local reference boundary, and then the remaining holes are completed outward in sequence, so that the circumferential surrounding structure is gradually formed around the blind hole 4. After the adjacent holes are drilled in an alternating manner, the adjacent hole areas will not be subjected to repeated drilling in a short period of time, and the stress state of the local hole group on the plate surface is more uniform. After the multiple grounding vias 5 are drilled, they can be distributed in a ring, semi-ring, or open surrounding pattern on the plane, as long as they are located on the outer periphery of the blind hole 4 and maintain a distance from the blind hole 4.

[0049] In one embodiment, during the processing of multiple grounding vias 5, a directional airflow is simultaneously applied to the drilling area of ​​the plate 1, and the directional airflow is arranged along the plate surface of the plate 1 in a direction away from the blind holes 4.

[0050] In the above embodiment, during the processing of multiple grounding vias 5, a directional airflow is simultaneously applied to the drilling area of ​​the plate 1. The directional airflow is arranged along the surface of the plate 1 in a direction away from the blind holes 4. Specifically, the directional airflow can form a blowing path close to the plate surface along the fan-out area 3. Its airflow direction is basically consistent with the extension direction of the blind hole 4 to the outer area of ​​the grounding via 5, so that the fine debris, dust or residual particles generated during the drilling process are preferentially deflected to the outer area of ​​the grounding via 5, and are not easily gathered back to the periphery of the blind hole 4. The directional airflow can cover one or more hole positions to be processed, and the blowing area is adjusted accordingly as the drilling position changes.

[0051] Since the blind via 4 is located between the chip pad group 2 and the multiple ground vias 5, the directional airflow, directed away from the blind via 4, maintains a relatively clean local environment around the blind via 4, reducing debris buildup at the opening of the blind via 4, the connection area at the end of the fine line 31, and the adjacent fan-out area 3. A directional debris dispersion relationship is formed between the processing area of ​​the ground via 5 and the layer-change area of ​​the blind via 4, which helps maintain the clarity of the structural boundary around the blind via 4 and provides better processing transition conditions for the outer periphery of the multiple ground vias 5 when distributed around the blind via 4, thus making subsequent hole wall processing and conductive structure formation more stable.

[0052] The above description is merely a preferred embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A high-order HDI circuit board for an in-vehicle domain controller, characterized in that, The plate includes a board (1), which includes a plurality of circuit layers (11) and insulating dielectric layers (12) stacked along the thickness direction, wherein at least one of the circuit layers (11) is a reference plane layer (13). A chip pad group (2) is provided on one end face of the board (1). A fan-out area (3) is provided on the outer periphery of the chip pad group (2). A fine line (31) connected to the chip pad group (2) is provided in the fan-out area (3). The fine line (31) is connected to the inner circuit layer (11) of the board (1) through a blind hole (4) to form a layer switching interconnection channel. The outer periphery of the blind hole (4) is provided with a grounding via (5), and multiple grounding vias (5) are connected to the reference plane layer (13), and multiple grounding vias (5) are distributed at intervals around the layer switching interconnection channel.

2. The high-order HDI circuit board for an in-vehicle domain controller according to claim 1, characterized in that, The blind via (4) includes multiple levels of blind vias (4) arranged sequentially from one end of the board (1) inward. The blind vias (4) of adjacent levels are respectively connected to different inner circuit layers (11). The board (1) is a 3rd-order HDI structure or a sequentially laminated HDI structure of higher than 3rd order. At least some of the blind vias (4) of adjacent levels form a stacked interconnect structure to enable the chip pad group (2) to be interconnected to multiple inner circuit layers (11) at high density.

3. The high-order HDI circuit board for an in-vehicle domain controller according to claim 1, characterized in that, The reference plane layer (13) includes a ground plane layer (131) and / or a power plane layer (132). At least one of the circuit layers (11) is a signal wiring layer, and at least one signal wiring layer is disposed adjacent to at least one reference plane layer (13). The insulating dielectric layer (12) is located between adjacent circuit layers (11). The total number of layers of the board (1) is 6 to 16.

4. The high-order HDI circuit board for an in-vehicle domain controller according to claim 1, characterized in that, The fine lines (31) extend radially outward from the chip pad group (2) and connect to the blind via (4). Adjacent fine lines (31) are arranged at intervals in the fan-out area (3). The line width of the fine lines (31) is 50μm to 75μm.

5. The high-order HDI circuit board for an in-vehicle domain controller according to claim 1, characterized in that, The board body (1) is also provided with through holes (6), which are distributed on the outer periphery of the grounding vias (5). The blind holes (4) are provided between the chip pad group (2) and the multiple grounding vias (5). The diameter of the blind holes (4) is 0.075mm to 0.10mm, and the diameter of the through holes (6) is 0.15mm to 0.20mm.

6. The high-order HDI circuit board for an in-vehicle domain controller according to claim 3, characterized in that, The fine line (31) includes a differential fine line (31), which is disposed on the signal routing layer. The differential fine line (31) and the reference plane adjacent to the signal routing layer form a differential impedance control structure. Multiple ground vias (5) are distributed at intervals along the outer periphery of the connection between the differential fine line (31) and the blind via (4). The impedance control tolerance of the differential fine line (31) is ±8%.

7. The high-order HDI circuit board for an in-vehicle domain controller according to claim 1, characterized in that, The insulating dielectric layer (12) is distributed between the signal wiring layer and the adjacent reference plane layer (13), wherein the insulating dielectric layer (12) is a high-speed, low-loss material.

8. A method for fabricating a high-order HDI circuit board for an in-vehicle domain controller, characterized in that, For fabricating the high-order HDI circuit board for an in-vehicle domain controller as described in any one of claims 1 to 7, comprising: A laminated board is provided, with a chip pad group on one end face of the board, a fan-out area on the outer periphery of the chip pad group, and fine lines connected to the chip pad group in the fan-out area. The board includes at least one reference plane layer. Blind holes are machined at the end of the thin line, and multiple grounding vias are machined around the outer periphery of the blind hole at preset intervals, using the center of the blind hole as a reference. The blind vias and multiple grounding vias are plated with copper to make them conductive to the inner circuit layers of the board, and the multiple grounding vias are conductive to the reference plane layer.

9. A method for fabricating a high-order HDI circuit board for an in-vehicle domain controller according to claim 8, characterized in that, The step of machining multiple grounding vias by using the center of the blind hole as a reference and performing circumferential positioning at preset intervals on the outer periphery of the blind hole includes: Establish a circumferential positioning reference with the center of the blind hole, control the drill bit to be perpendicular to the plate surface, and drill around the blind hole one by one in a staggered order from near to far to form multiple grounding vias.

10. A method for fabricating a high-order HDI circuit board for an in-vehicle domain controller according to claim 8, characterized in that, During the processing of multiple grounding vias, directional airflow is applied simultaneously to the drilling area of ​​the board, and the directional airflow is arranged along the board surface in a direction away from the blind holes.

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