Signal pad fan-out via layout structure and circuit board

Abstract

The application discloses a signal pad fan-out via layout structure and a circuit board, and relates to the technical field of circuit boards. The signal pad fan-out via layout structure comprises a plurality of signal pad fan-out via array groups, and the signal pad fan-out via array groups are arranged on a PCB substrate. Each signal pad fan-out via array group comprises a plurality of vias and a plurality of first pads. The plurality of vias and the plurality of first pads are horizontally spaced, and the vias are offset towards the center of the signal pad fan-out via array group relative to the first pads. The technical scheme of the application does not change the original BGA packaging size, the number of vias and the like, offsets the vias towards the center of the signal pad fan-out via array group relative to the first pads, changes the spacing between the vias, and then can select fan-out wires with a larger line width and increase the spacing between the fan-out wires, so as to adapt to the conventional high-speed process capacity of a circuit board processing factory and reduce the processing difficulty.

Description

Technical Field

[0001] This invention relates to the field of circuit board technology, and in particular to a signal pad fan-out via layout structure and circuit board. Background Technology

[0002] In existing differential signal fan-out solutions for 0.84mm×0.84mm pitch BGAs, a uniform fan-out direction along the positive Y-axis of the BGA pad array is commonly used. This is a common design method in the industry. In this fan-out layout, the BGA pads are fanned out vertically to vias vias through leads. The vias are arranged in a uniform vertical direction along the center of the pads, forming a regular via array.

[0003] However, due to the spacing between adjacent vias and the requirements of back-drilling, the available routing channel between two vias in the X direction is 9.07mil. The neckmode routing of differential signals (critical constraint section between vias in the BGA area) can only use the extreme process parameters of 3mil line width and 3mil line spacing. Such processing places extremely high demands on the precision of the board material, the exposure equipment, and the uniformity of etching. It is prone to defects such as line width deviation, short circuits, and incomplete etching, which leads to a decrease in PCB trial production yield and an increase in scrap rate during mass production, significantly increasing manufacturing costs. Summary of the Invention

[0004] The main objective of this invention is to propose a signal pad fan-out via layout structure and circuit board, aiming to solve the technical problem of increased processing difficulty caused by the differential signal fan-out scheme for 0.84mm×0.84mm pitch BGA in existing applications.

[0005] To achieve the above objectives, the present invention proposes a signal pad fan-out via layout structure, comprising: Multiple signal pad fan-out via arrays are arranged on a PCB substrate. The signal pad fan-out via array group includes multiple vias and multiple first pads. The multiple vias and multiple first pads are arranged laterally at intervals, and the vias are offset relative to the first pads toward the center of the signal pad fan-out via array group.

[0006] In one embodiment, a plurality of first pads are arranged at equal intervals, and a via is disposed on one side of a first pad, the via being offset relative to the first pad toward the center of the via array group of signal pads.

[0007] In one embodiment, the via includes two differential pair vias, which are arranged adjacent to each other and are close to each other relative to the first pad.

[0008] In one embodiment, a first spacing is provided between two adjacent differential pair vias, and the center distance between two adjacent differential pair vias ranges from 0.707 mm to 0.719 mm.

[0009] In one embodiment, the via further includes a grounding via, which is disposed on the side of the differential pair via away from the center of the signal pad fan-out via array group, and the grounding via is offset relative to the first pad toward the center of the signal pad fan-out via array group.

[0010] In one embodiment, a second spacing is provided between the grounding vias on both sides of the differential pair via, and the center distance between the two grounding vias ranges from 2.426 mm to 2.486 mm.

[0011] In one embodiment, a spacer pad fan-out via group is provided between two adjacent signal pad fan-out via array groups; The spaced pad fan-out via group and the grounding via group, as well as the grounding via and the differential pair via group, are provided with trace channels, and the spacing of the trace channels ranges from 9.72 mil to 10.90 mil.

[0012] In one embodiment, the differential pair via is connected to a neckmode trace, the neckmode trace passes through the trace channel, and a third spacing is provided between the neckmode traces. The grounding via and the differential pair via are offset to increase the spacing of the third spacing and the line width of the neckmode trace.

[0013] In one embodiment, the third spacing ranges from 3.2 to 4.5 mil, and the line width of the neckmode trace ranges from 3.2 to 3.8 mil.

[0014] The present invention also proposes a circuit board including the aforementioned signal pad fan-out via layout structure.

[0015] The technical solution of this invention is an array of signal pad fan-out via arrays, with multiple vias and the first pad arranged in an orderly manner. Without changing the original BGA package size, number of vias, etc., the vias are offset relative to the first pads towards the center of the signal pad fan-out via array, thereby changing the spacing between the vias. As a result of the increased spacing between the vias, fan-out traces with larger line widths can be selected and the spacing between fan-out traces can be increased, thus adapting to the conventional high-speed process capabilities of circuit board manufacturing plants and reducing processing difficulty while ensuring production efficiency and quality. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0017] Figure 1 A schematic diagram of an embodiment of the signal pad fan-out via layout structure provided by the present invention; Figure 2 This is a schematic diagram of another embodiment of the signal pad fan-out via layout structure provided by the present invention.

[0018] Explanation of icon numbers: 10. Grounding via; 20. Trace path; 30. Differential pair via; 40. First spacing; 50. Circuit board; 60. Third spacing; 70. Neckmode trace; 80. Fan-out via group with spaced pads; 81. Spaced via; 82. Second pad; 90. First pad.

[0019] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0020] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0021] It should be noted that if the embodiments of the present invention involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a specific posture. If the specific posture changes, the directional indicators will also change accordingly.

[0022] Furthermore, if the embodiments of this invention involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the use of "and / or" or "and / or" throughout the text includes three parallel solutions. For example, "A and / or B" includes solution A, solution B, or a solution where both A and B are satisfied simultaneously. Furthermore, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this invention.

[0023] In existing differential signal fan-out solutions for 0.84mm×0.84mm pitch BGAs, a uniform fan-out direction along the positive Y-axis of the BGA pad array is commonly used. This is a common design method in the industry. In this fan-out layout, the BGA pads are fanned out vertically to vias vias through leads. The vias are arranged in a uniform vertical direction along the center of the pads, forming a regular via array.

[0024] However, due to the spacing between adjacent vias and the requirements of back-drilling, the available routing channel between two vias in the X direction is 9.07mil. The neckmode routing of differential signals (critical constraint section between vias in the BGA area) can only use the extreme process parameters of 3mil line width and 3mil line spacing. Such processing places extremely high demands on the precision of the board material, the exposure equipment, and the uniformity of etching. It is prone to defects such as line width deviation, short circuits, and incomplete etching, which leads to a decrease in PCB trial production yield and an increase in scrap rate during mass production, significantly increasing manufacturing costs.

[0025] This invention proposes a signal pad fan-out via layout structure.

[0026] Please see Figure 1 In one embodiment of the present invention, the signal pad fan-out via layout structure includes: Multiple signal pad fan-out via arrays are arranged on a PCB substrate. The signal pad fan-out via array group includes multiple vias and multiple first pads 90. The multiple vias and multiple first pads 90 are arranged laterally at intervals, and the vias are offset relative to the first pads 90 toward the center of the signal pad fan-out via array group.

[0027] like Figure 1 As shown, the surface of circuit board 50 is defined with its horizontal direction as the first direction and its vertical direction as the second direction.

[0028] Thus, when multiple signal pad fan-out via arrays are arrayed on the surface of circuit board 50, the multiple signal pad fan-out via arrays are arrayed in the first direction and the second direction respectively, so that the signal pad fan-out via arrays are arranged in an orderly manner on the surface of circuit board 50.

[0029] Furthermore, multiple vias are spaced apart in the first direction, multiple first pads 90 are spaced apart in the second direction, and a first pad 90 is provided on one side of a via in the second direction.

[0030] Understandably, the number of vias and the number of first pads 90 remain unchanged, in order to reduce the processing difficulty of the PAD segments.

[0031] At the same time, by offsetting the vias, the spacing between the vias is increased, which facilitates the installation of fan-out traces. Moreover, due to the increased spacing, larger-width neckmode traces can be selected, and the spacing between neckmode traces can be increased, thereby reducing the difficulty of the fan-out process and improving the production efficiency of the circuit board.

[0032] The technical solution of this invention is an array of signal pad fan-out via arrays, with multiple vias and the first pad 90 arranged in an orderly manner. Without changing the original BGA package size, number of vias, etc., the vias are offset relative to the first pad 90 towards the center of the signal pad fan-out via array, thereby changing the spacing between the vias. As a result of the increased spacing between the vias, a larger-width neckmode trace can be selected and the spacing between the neckmode traces can be increased, thus adapting to the conventional high-speed process capabilities of circuit board manufacturing plants and reducing the processing difficulty while ensuring production efficiency and quality.

[0033] In one embodiment, a plurality of first pads 90 are arranged at equal intervals, and a via is disposed on one side of a first pad 90, the via being offset relative to the first pad 90 toward the center of the signal pad fan-out via array group.

[0034] like Figure 1 As shown, multiple first pads 90 are spaced apart in a first direction, and multiple signal pad fan-out via arrays are arranged in an array, so that multiple first pads 90 are arrayed on the circuit board.

[0035] Furthermore, the spacing between the two first pads 90 in the first direction is equivalent to the spacing between the two first pads 90 in the second direction.

[0036] In one embodiment, the spacing between the two first pads 90 is 0.84 mm.

[0037] Understandably, by not changing the 0.84mm pitch BGA package size, the number of vias, or the total number of PCB stack-ups, the circuit board design can be directly adapted to existing 0.84mm pitch BGA chips without modifying the chip package or hardware architecture, thus improving compatibility. Furthermore, by shifting the vias towards the center of the fan-out via array group towards the signal pads, the gap between the vias is widened, achieving the fan-out process while reducing the difficulty of circuit board manufacturing.

[0038] It should be noted that the first pad 90 is connected to its adjacent via via a fan-out trace.

[0039] In one embodiment, the via includes two differential pair vias 30, which are arranged adjacent to each other and are close to each other relative to the first pad 90.

[0040] In one embodiment, a first spacing 40 is provided between two adjacent differential pair vias 30, and the center distance between two adjacent differential pair vias 30 ranges from 0.707 mm to 0.719 mm.

[0041] like Figure 1 As shown, a first spacing 40 is provided between the two differential pair vias 30. Because the two differential pair vias 30 are close to each other, the first spacing 40 is smaller than that of a regular via array formed by vias arranged in the same vertical direction along the center of the pad. This provides a wider spacing between the vias on the adjacent side of the differential pair vias 30.

[0042] Furthermore, such as Figure 2 As shown, the center distance range between two adjacent differential pair vias 30 is defined so that the neckmode trace 70 connected to the differential pair via can be led out from the first spacing 40.

[0043] In one embodiment, the via further includes a ground via 10, which is disposed on the side of the differential pair via 30 away from the center of the signal pad fan-out via array group, and the ground via 10 is offset relative to the first pad 90 toward the center of the signal pad fan-out via array group.

[0044] In one embodiment, a second spacing is provided between the grounding vias 10 on both sides of the differential pair via 30, and the center distance between the two grounding vias 10 ranges from 2.426 mm to 2.486 mm.

[0045] like Figure 1 As shown, the grounding via 10 is located on the side of the differential pair via 30 away from the center of the signal pad fan-out via array group, and a second spacing is provided between the grounding via 10 and the differential pair via 30.

[0046] Furthermore, the two differential pair vias 30 are positioned close to each other, and the ground via 10 is offset toward the differential pair vias 30. Both the differential pair vias 30 and the ground via 10 are offset relative to the first pad 90.

[0047] Understandably, the two differential vias 30 are close to each other, and the ground via 10 is also offset toward the differential vias 30, thereby expanding the numerical range of the second pitch. This allows for more space to accommodate larger-width neckmode traces 70 and larger neckmode trace pitches when the neckmode traces 70 are routed through the second pitch, reducing the difficulty of circuit board production in the factory while improving production efficiency and quality.

[0048] Furthermore, the reduced spacing between the two differential pair vias further lowers the via impedance, thereby improving signal quality.

[0049] In one embodiment, a spacer pad fan-out via group 80 is provided between two adjacent signal pad fan-out via array groups; In this embodiment, a trace channel 20 is provided between the spaced pad fan-out via group 80 and the ground via 10, and between the ground via 10 and the differential pair via 30. The spacing of the trace channel 20 ranges from 9.72 mil to 10.90 mil.

[0050] like Figure 1 As shown, the spaced pad fan-out via group 80 includes a spaced via 81 and a second pad 82. The spaced via is disposed on the side of the grounding via 10 away from the differential pair via 30. The second pad 82 is disposed on the side of the spaced via 81 in the second direction and is spaced apart from the first pad 90. The second pad 82 and the spaced via 81 are disposed in the same vertical direction.

[0051] Understandably, because the grounding via 10 is offset toward the differential pair via 30, the spacing between the trace channels 20 is increased, which facilitates the design of the trace width of the neckmode trace 70 and the spacing between the neckmode traces 70, thus making it suitable for the conventional high-speed process capabilities of the circuit board manufacturer, and making it easier for the circuit board manufacturer to better control the processing impedance error.

[0052] In one embodiment, the differential pair via 30 is connected to a neckmode trace 70, the neckmode trace 70 passes through the trace channel 20, and a third spacing 60 is provided between the neckmode traces 70. The offset of the grounding via 10 and the differential pair via 30 is set to increase the spacing of the third spacing 60 and the line width of the neckmode trace 70.

[0053] In one embodiment, the third spacing 60 ranges from 3.2 to 4.5 mil, and the line width of the neckmode trace 70 ranges from 3.2 to 3.8 mil.

[0054] It is understandable that, such as Figure 2 As shown, the neckmode traces 70 connected to the two differential pair vias 30 pass through the trace channel 20. The widened trace channel facilitates both the design of larger trace widths and the design of wider spacing between the neckmode traces 70, which helps to optimize impedance.

[0055] For example, based on the differential impedance formula:

[0056] Single-ended impedance formula for stripline:

[0057] Where k is the coupling coefficient between traces (0-1), εr is the dielectric constant, H is the total dielectric layer height, W is the trace width, and T is the trace thickness.

[0058] When the trace width value of neckmode 70 increases, the impedance value decreases. When the third spacing value of 60 increases, the coupling coefficient between traces decreases, resulting in a slight increase in impedance.

[0059] In one embodiment, the third spacing 60 is 3.2 mil, and the neckmode trace 70 has a line width of 3.5 mil.

[0060] Understandably, when the trace width of the neckmode 70 is 3.5mil and the third spacing 60 is 3.2mil, the influence of the trace width is greater than that of the spacing, the differential line impedance is reduced and approaches 85Ω, thereby improving impedance continuity.

[0061] The present invention also proposes a circuit board, which includes a signal pad fan-out via layout structure. The specific structure of the signal pad fan-out via layout structure is as described in the above embodiments. Since the circuit board adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, which will not be described in detail here.

[0062] The above description is merely an exemplary embodiment of the present invention and does not limit the scope of protection of the present invention. Any equivalent structural transformations made based on the technical concept of the present invention and the contents of the specification and drawings of the present invention, or direct / indirect applications in other related technical fields, are included within the scope of protection of the present invention.

Claims

1. A signal pad fan-out via layout structure, characterized in that, include: Multiple signal pad fan-out via arrays are arranged on a PCB substrate. The signal pad fan-out via array group includes multiple vias and multiple first pads. The multiple vias and multiple first pads are arranged laterally at intervals, and the vias are offset relative to the first pads toward the center of the signal pad fan-out via array group.

2. The signal pad fan-out via layout structure as described in claim 1, characterized in that, Multiple first pads are arranged at equal intervals, and a via is disposed on one side of a first pad. The via is offset relative to the first pad towards the center of the via array group of signal pads.

3. The signal pad fan-out via layout structure as described in claim 2, characterized in that, The via includes two differential pair vias, which are arranged adjacent to each other and are close to each other relative to the first pad.

4. The signal pad fan-out via layout structure as described in claim 3, characterized in that, A first spacing is provided between two adjacent differential pair vias, and the center distance between two adjacent differential pair vias ranges from 0.707mm to 0.719mm.

5. The signal pad fan-out via layout structure as described in claim 3, characterized in that, The via also includes a grounding via, which is located on the side of the differential pair via away from the center of the signal pad fan-out via array group, and the grounding via is offset relative to the first pad toward the center of the signal pad fan-out via array group.

6. The signal pad fan-out via layout structure as described in claim 5, characterized in that, A second spacing is provided between the grounding vias on both sides of the differential pair via, and the center distance between the two grounding vias ranges from 2.426mm to 2.486mm.

7. The signal pad fan-out via layout structure as described in claim 5, characterized in that, A spacer pad fan-out via group is provided between two adjacent signal pad fan-out via array groups; The spaced pad fan-out via group and the grounding via group, as well as the grounding via and the differential pair via group, are provided with trace channels, and the spacing of the trace channels ranges from 9.72 mil to 10.90 mil.

8. The signal pad fan-out via layout structure as described in claim 7, characterized in that, The differential pair via is connected to a neckmode trace, which passes through the trace channel and has a third spacing between it. The grounding via and the differential pair via are offset to increase the spacing of the third spacing and the width of the neckmode trace.

9. The signal pad fan-out via layout structure as described in claim 8, characterized in that, The third spacing ranges from 3.2 to 4.5 mil, and the line width of the neckmode trace ranges from 3.2 to 3.8 mil.

10. A circuit board, characterized in that, Includes the signal pad fan-out via layout structure as described in any one of claims 1 to 9.

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