A board-level fusion integrated electronic system architecture for computing power satellite

Abstract

The application discloses a kind of board-level fusion integrated electronic system architecture for computing satellite, it is related to spacecraft electronic system design field, including: for being set in the structure heat dissipation integrated bottom plate of the interior of satellite configuration;The upper surface of structure heat dissipation integrated bottom plate is equipped with local heat dissipation boss;Each functional fusion board card is installed on local heat dissipation boss by heat-conducting interface material, and each functional fusion board card is not set independent metal shell and electric box structure;Signal interconnection and power distribution are carried out between any adjacent functional fusion board card by multilayer flexible circuit board;Heat pipe network is pre-embedded in structure heat dissipation integrated bottom plate, heat pipe network is heat-conducting connected with local heat dissipation boss, for transmitting the heat generated by each functional fusion board card to satellite heat dissipation surface, the application breaks the barrier of traditional single machine computing power monopoly, so that the utilization rate of whole satellite computing power is improved, meet the demand of intelligent task to flexible computing power.

Description

Technical Field

[0001] This invention relates to the field of spacecraft electronic system design, and more particularly to a board-level integrated electronic system architecture for computing satellites. Background Technology

[0002] With the rapid growth in demand for satellite intelligence and autonomy, the need for on-orbit real-time data processing and artificial intelligence computing capabilities has increased dramatically. Traditional satellite electronic systems adopt a discrete, stand-alone design, with functional subsystems such as the satellite computer, attitude control computer, and power management unit each being a physical stand-alone unit with an independent metal casing. These units are interconnected via a cable network. While this architecture is adequate for traditional satellites with lower computing power requirements, it faces structural bottlenecks in scenarios involving high-performance computing chips and on-orbit AI processing capabilities: the independent unit casings and electrical enclosures occupy significant weight and space resources, accounting for 25% to 35% of the total satellite dry weight, thus limiting the deployment of computing payloads; the long thermal resistance links between the boards and heat dissipation surfaces restrict the heat dissipation capabilities of high-power computing chips with thermal design power ranging from 15 to 100 watts; and the exclusive and uneven utilization of computing power by each unit makes it difficult to meet the flexible computing power requirements of intelligent missions.

[0003] To address the aforementioned issues, several existing technologies have attempted to improve the system from different perspectives. Existing technology one discloses a modular micro / nano satellite integrated electrical system suitable for mass production and its assembly method (CN120264664A). It utilizes a semi-open electrical box structure and modular circuit boards, employing an electromechanical-thermal integrated design approach to integrate multiple electronic modules into a single electronic system. This breaks down the functional boundaries of traditional satellite subsystems and reduces the weight of cables and connectors between electronic modules. Existing technology two discloses a highly integrated satellite integrated platform architecture (CN115483963A), including an interface processing board, core processing board, power supply subsystem, and front-end transceiver components. Functional integration reduces manufacturing and launch costs. Existing technology three discloses a spacecraft integrated intelligent information system (CN114513244A), employing an integrated modular architecture based on a shared resource mechanism, constructed from standardized and universal hardware modules. Existing technology four discloses a multifunctional structural board (CN107985630A), integrating circuit boards, heat pipes, and structural frames into a single unit, achieving partial fusion of structure, thermal control, and electronics.

[0004] However, each of the aforementioned existing technologies has its shortcomings. Existing Technology 1's semi-open electrical enclosure essentially retains the physical packaging boundary of the electrical enclosure structure. Modular circuit boards are installed inside the enclosure, failing to eliminate independent single-unit housings and not employing a physical architecture where boards are directly laid flat on the satellite's main structural surface. The boards are separated from the satellite structure by the electrical enclosure structure and mounting brackets, and it does not address the integration and heat dissipation issues of high-performance chips such as graphics processors or neural network processors. Existing Technology 2's overall architecture remains at the single-unit level, retaining the physical packaging boundaries of independent functional boards such as interface processing boards and core processing boards. Each board is still installed within a traditional chassis or structural frame, failing to achieve board-level integration. Existing Technology 3's integrated modularization focuses on the standardized reuse of hardware modules, essentially still based on a modular architecture of standard chassis, failing to achieve board-level physical integration and pooled sharing of computing resources. Existing Technology 4's concept focuses on the multi-functionality of a single structural board, failing to solve the board-level integration problem of the entire satellite's electronic system, and also failing to use flexible circuit boards to achieve high-density signal interconnection. Even if the above-mentioned existing technologies are combined, it is difficult for those skilled in the art to obtain a solution that eliminates the electrical box structure and reconstructs the entire satellite electronic system into a fusion board laid flat on the same base plate, because eliminating the electrical box will face technical contradictions such as decreased electromagnetic compatibility performance, thermal coupling management of multiple boards on the same base plate, and ensuring the integrity of high-speed signals in short-distance interconnection.

[0005] Therefore, there is a need to provide a board-level integrated electronic system architecture for computing satellites to solve the problems of insufficient architecture integration, long heat dissipation paths, inability to dynamically share computing resources, and signal interconnection redundancy in the existing technologies. Summary of the Invention

[0006] This invention aims to address the shortcomings of existing technologies and specifically provides a board-level integrated electronic system architecture for computing satellites, applied to satellite configurations, including: an integrated structural heat dissipation base plate for installation inside the satellite configuration; The upper surface of the integrated heat dissipation base plate is provided with local heat dissipation protrusions; Each functional integration board is mounted on a local heat dissipation protrusion by laying a thermal interface material, and each functional integration board does not have an independent metal shell and electrical box structure. Any adjacent functional integration boards are interconnected for signal and power distribution via multi-layer flexible circuit boards; The integrated heat dissipation base plate has a pre-embedded heat pipe network inside, which is thermally connected to the local heat dissipation bosses to transfer the heat generated by each functional fusion board to the satellite heat dissipation surface.

[0007] The beneficial effects of the board-level fusion integrated electronic system architecture for computing satellites provided by this invention when applied to satellite configurations are as follows: This architecture eliminates the separate metal casings and electrical enclosures of each integrated functional board, directly mounting all integrated functional boards onto a single integrated heat dissipation baseplate. This eliminates redundant casings and brackets found in traditional architectures, significantly reducing the overall satellite weight and freeing up weight and space resources for deploying more computing power expansion boards. The back of the integrated functional boards directly contacts localized heat dissipation protrusions on the baseplate via a thermally conductive interface material. Heat is transferred to the satellite's heat dissipation surface via a pre-embedded heat pipe network within the baseplate, shortening the heat dissipation path from seven to nine thermal resistance stages in traditional architectures to five to six, creating effective heat dissipation conditions for high-power computing chips. Signal interconnection and power distribution between any adjacent integrated functional boards are achieved through multi-layer flexible circuit boards, replacing traditional discrete cable networks, reducing the number of connectors, and improving signal transmission reliability. The information processing board uses virtualization technology to incorporate heterogeneous computing resources on the computing power expansion board into a unified computing resource pool, and dynamically allocates computing resources to the satellite management function module, attitude control function module, or telemetry and communication function module. This breaks the barrier of traditional single-machine computing power monopoly, improves the utilization rate of the entire satellite's computing power, and meets the demand of intelligent tasks for elastic computing power.

[0008] Based on the above scheme, the board-level integrated electronic system architecture for computing satellites can be further improved in the following ways when applied to satellite configurations.

[0009] Furthermore, all functional integration boards include at least an information processing board and a computing power expansion board. The information processing board uses virtualization technology to incorporate the heterogeneous computing power resources on the computing power expansion board into a unified computing power resource pool, and dynamically allocates the computing power resources in the unified computing power resource pool to at least one of the following functional modules: the space service management functional module, the attitude control functional module, and the telemetry, tracking and command (TT&C) functional module.

[0010] The beneficial effects of adopting the above-mentioned further solution are as follows: The information processing board, through virtualization technology, integrates the heterogeneous computing resources on the computing power expansion board into a unified computing resource pool, breaking down the barriers of independent configuration and non-sharing of computing power among various functional subsystems in traditional satellites. The computing resources in the unified computing resource pool can be dynamically allocated to the satellite management module, attitude control module, or telemetry and communication module, transforming physical exclusivity into logical sharing of computing power. When a functional module is under low load, its released computing resources can be immediately utilized by other functional modules requiring computing power, thereby improving the overall utilization rate of the satellite's heterogeneous computing power. Simultaneously, the dynamic allocation mechanism can flexibly adjust the computing power supply according to task priority and real-time load, meeting the deterministic response requirements of hard real-time tasks such as attitude control, and providing effective resource guarantees for computing satellites to perform flexible intelligent tasks in orbit.

[0011] Furthermore, the positions of the local heat dissipation protrusions on the upper surface of the integrated heat dissipation base plate correspond one-to-one with the positions of the high heat flux density chips on each functional fusion board. The heat pipe network includes multiple heat pipes, one end of each heat pipe is thermally connected to the corresponding local heat dissipation protrusion, and the other end of each heat pipe extends to the heat dissipation surface of the satellite configuration.

[0012] The beneficial effects of adopting the above-mentioned further solution are as follows: the location of the local heat dissipation protrusions on the surface of the integrated heat dissipation base plate corresponds one-to-one with the location of the high heat flux density chips on each functional fusion board, ensuring that each high heat flux density chip has an independent local heat dissipation protrusion directly below it for heat collection. One end of each heat pipe is thermally connected to the corresponding local heat dissipation protrusion, and the other end extends to the heat dissipation surface of the satellite configuration, establishing a dedicated low thermal resistance heat transfer channel from the heat source to the heat dissipation surface for each high heat flux density chip. This one-to-one heat conduction structure avoids heat interference between different chips, ensuring that the heat generated by each high heat flux density chip can be independently transferred to the satellite heat dissipation surface along the shortest path, thereby improving the overall heat dissipation capacity of the satellite and creating effective thermal control conditions for deploying multiple high-power computing chips.

[0013] Furthermore, the multilayer flexible circuit board adopts a four-layer structure, which includes a high-speed signal layer, a medium-speed control layer, a power distribution layer, and a ground shielding layer. The high-speed signal layer uses differential pair wiring, the power distribution layer uses wide copper foil traces, and the ground shielding layer is a complete copper foil. The multilayer flexible circuit board adopts a gradient line width design at the position where it connects to the functional integration board, and the multilayer flexible circuit board corresponding to the critical signal is equipped with dual-channel backup redundancy.

[0014] The beneficial effects of adopting the above-mentioned further solution are as follows: The multilayer flexible circuit board adopts a four-layer structure consisting of a high-speed signal layer, a medium-speed control layer, a power distribution layer, and a ground shielding layer. The high-speed signal layer achieves low-loss transmission of high-speed data through differential pair wiring; the power distribution layer uses wide copper foil traces to ensure the high-current power supply capability of each functional integration board; and the ground shielding layer, as a complete copper foil, provides a low-impedance signal return path and electromagnetic shielding. The multilayer flexible circuit board uses a gradient linewidth design at the connection points with the functional integration boards, reducing signal reflection and impedance abrupt changes, and ensuring signal transmission quality. The multilayer flexible circuit board corresponding to critical signals is equipped with dual-channel backup redundancy. When the main channel malfunctions, it can automatically switch to the backup channel, improving the reliability of signal transmission. All of the above designs collectively ensure the signal integrity of the interconnections between boards after eliminating the independent metal casing and electrical box structure.

[0015] Furthermore, the multilayer flexible circuit board adopts a symmetrical stacked structure, with the high-speed signal layer and the medium-speed control layer located on both sides of the ground shielding layer. The differential pair traces in the high-speed signal layer adopt equal-length wiring, and cross-copper shielding is provided between the high-speed signal layer and the adjacent layers.

[0016] The beneficial effects of adopting the above-mentioned further scheme are as follows: The multilayer flexible circuit board adopts a symmetrical stacked structure, placing the high-speed signal layer and the medium-speed control layer on opposite sides of the ground shielding layer. The ground shielding layer physically isolates the upper and lower signal layers, reducing electromagnetic crosstalk from the high-speed signal layer to the medium-speed control layer. The differential pair traces in the high-speed signal layer use equal-length wiring, ensuring consistent transmission delays for both positive and negative differential signals and avoiding signal distortion. Cross-copper shielding is used between the high-speed signal layer and adjacent layers, further suppressing inter-layer coupling interference and improving the transmission quality of high-speed signals. This design effectively ensures the signal integrity of the multilayer flexible circuit board without requiring an independent metal casing shield, providing a physical basis for high-speed and reliable interconnection between information processing boards and computing expansion boards in the computing power satellite board-level fusion architecture.

[0017] Furthermore, the satellite configuration can be a flat-panel satellite configuration, a cube satellite configuration, a cylindrical satellite configuration, or a deployable satellite configuration. When the satellite configuration is a flat-panel satellite configuration, each functional fusion board is laid flat along the thickness direction of the flat-panel satellite configuration, and the surface of each functional fusion board is parallel to the main structural surface of the flat-panel satellite configuration. When the satellite configuration is a cube satellite configuration, each functional fusion board is laid flat on the integrated structural heat dissipation base plate. When the satellite configuration is a cylindrical satellite configuration, each functional fusion board is arranged radially around the central axis of the cylindrical satellite configuration. When the satellite configuration is a deployable satellite configuration, the integrated structural heat dissipation base plate is set on the deployable panel of the deployable satellite configuration.

[0018] The beneficial effects of adopting the above-mentioned further solutions are: enabling the board-level integrated electronic system architecture to adapt to various satellite configurations. In a planar satellite configuration, the integrated functional boards are laid flat along the thickness direction with the board surface parallel to the main structural surface, making full use of the flat space. In a cubic satellite configuration, the integrated functional boards are laid flat on a structural heat dissipation integrated base plate, adapting to a standardized modular layout. In a cylindrical satellite configuration, the integrated functional boards are arranged radially around the central axis, matching the rotationally symmetrical internal space. In a deployable satellite configuration, the structural heat dissipation integrated base plate is set on the deployable panel, obtaining a larger installation and heat dissipation area as the panel unfolds. By providing corresponding arrangement methods for different configurations, the versatility and deployment flexibility of the technical solution on different satellite platforms are improved, expanding the application scope.

[0019] Furthermore, the information processing board and the computing power expansion board share a unified processor instruction set architecture. The information processing board runs virtualization software to abstract the heterogeneous computing power resources on the computing power expansion board into a unified computing power resource pool, and realizes the scheduling of computing power resources in the unified computing power resource pool through a unified software ecosystem.

[0020] The beneficial effects of adopting the above-mentioned further solutions are as follows: the information processing board and the computing power expansion board share a unified processor instruction set architecture, enabling the compiled program code to execute seamlessly on different boards, reducing the complexity of software development and porting. The virtualization software running on the information processing board abstracts the heterogeneous computing resources on the computing power expansion board into a unified computing resource pool, shielding the differences in underlying hardware and freeing upper-layer functional modules from concern themselves with the specific type of computing chip. Through a unified software ecosystem, the scheduling of computing resources in the unified computing resource pool is achieved. Developers can use the same set of compilation tools, runtime libraries, and scheduling interfaces to manage all heterogeneous computing resources, improving the convenience and efficiency of computing power scheduling, and providing a unified software support environment for the rapid deployment and flexible iteration of on-board intelligent missions.

[0021] Furthermore, the computing power expansion board integrates at least one dedicated computing power chip among graphics processors, neural network processors, and field-programmable gate arrays. The dedicated computing power chip is interconnected with the information processing board via a high-speed bus, and the dedicated computing power chip dynamically loads artificial intelligence inference models or data processing algorithms according to task requirements.

[0022] The beneficial effects of adopting the above-mentioned further scheme are as follows: The computing power expansion board integrates at least one dedicated computing chip from among graphics processors, neural network processors, and field-programmable gate arrays, providing the satellite with diverse heterogeneous computing capabilities to adapt to different task requirements such as parallel vector operations, deep learning inference, and flexible reconfigurable data processing. The dedicated computing chip is interconnected with the information processing board via a high-speed bus, ensuring low-latency, high-bandwidth data transmission between boards, enabling the information processing board to quickly access dedicated computing resources. The dedicated computing chip dynamically loads artificial intelligence inference models or data processing algorithms according to task requirements, allowing the same dedicated computing chip to execute different intelligent tasks or data processing flows at different times, achieving time-division multiplexing of hardware resources and improving the on-orbit task adaptability and utilization efficiency of the computing power expansion board.

[0023] Furthermore, all functional integration boards also include an energy management board, which integrates a solar array power regulation unit, a battery charging and discharging management unit, a load power distribution unit, and a power consumption monitoring unit. The energy management board collects power consumption data from the information processing board, computing power expansion board, and other functional integration boards in real time, and participates in the unified power consumption budget management of the entire satellite based on the collected power consumption data.

[0024] The beneficial effects of adopting the above-mentioned further solution are as follows: The energy management board integrates a solar array power regulation unit, a battery charging and discharging management unit, a load power distribution unit, and a power consumption monitoring unit, concentrating the functions of power generation, storage, distribution, and monitoring onto a single board, simplifying the physical implementation of the entire satellite's energy system. The energy management board collects power consumption data in real time from the information processing board, computing power expansion board, and other functional integration boards, providing accurate real-time input for unified power consumption budget management across the entire satellite. Based on the collected power consumption data, the unified power consumption budget management of the entire satellite allows for dynamic adjustment of computing power scheduling strategies or temporary shutdown of non-critical loads when power generation is insufficient, preventing power outages or battery over-discharge, and ensuring the safe and stable operation of the computing satellite under limited power resources. Simultaneously, continuous power consumption monitoring helps detect abnormal power spikes or overcurrent events, providing timely evidence for fault isolation and improving the reliability of the entire satellite's energy system and its support capability for high-power computing boards.

[0025] Furthermore, the integrated heat dissipation base plate is made of high thermal conductivity aluminum alloy, magnesium-lithium alloy, carbon fiber composite material or aluminum-based silicon carbide.

[0026] The beneficial effects of adopting the above-mentioned further solutions are as follows: The integrated structural heat dissipation base plate uses high thermal conductivity aluminum alloy, magnesium-lithium alloy, carbon fiber composite material, or aluminum-based silicon carbide, providing flexible material selection space for different mission requirements. High thermal conductivity aluminum alloy ensures good thermal conductivity and ease of processing, making it suitable for most computing satellite scenarios. Magnesium-lithium alloy has a lower density, which can further reduce the weight of the base plate while meeting heat dissipation requirements, increasing the overall satellite weight margin. Carbon fiber composite material has excellent specific strength and specific stiffness, providing higher structural load-bearing capacity at the same weight, making it suitable for satellite platforms with prominent lightweight requirements. Aluminum-based silicon carbide combines the processing adaptability of aluminum alloy with the high thermal conductivity and low expansion characteristics of ceramic materials, which is beneficial for matching the thermal deformation requirements of high heat flux density chips. Through material substitution, a balanced optimization between structural strength, heat dissipation efficiency, and weight is achieved, improving the adaptability of the board-level integrated electronic system architecture to different mission requirements and launch platforms. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments of the present invention will be briefly introduced below: Figure 1 This is one of the structural schematic diagrams of a board-level integrated electronic system architecture for computing satellites according to an embodiment of the present invention; Figure 2 This is a structural diagram of a flat-panel satellite configuration; Figure 3 This is the second schematic diagram of a board-level integrated electronic system architecture for computing satellites according to an embodiment of the present invention. Detailed Implementation

[0028] The principles and features of the present invention are described below. The examples given are only for explaining the present invention and are not intended to limit the scope of the present invention.

[0029] The technical solution of the present invention and how the technical solution of the present invention solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of the present invention will now be described with reference to the accompanying drawings.

[0030] like Figure 1 As shown in the figure, an embodiment of the present invention provides a board-level integrated electronic system architecture for computing satellites, which is applied to a satellite configuration. The architecture includes: an integrated structural heat dissipation base plate for being installed inside the satellite configuration; a local heat dissipation protrusion is provided on the upper surface of the integrated structural heat dissipation base plate; each functional fusion board is installed on the local heat dissipation protrusion by being laid flat with a thermally conductive interface material, and each functional fusion board does not have an independent metal shell and electrical box structure. The integrated structural heat dissipation baseplate is a rectangular flat plate made of high thermal conductivity aluminum alloy. The planar dimensions of this plate match the internal cross-sectional dimensions of the flat-panel satellite configuration, and the thickness of the plate is set according to the overall structural mechanical and heat dissipation requirements of the satellite. Multiple localized heat dissipation protrusions are precision-machined on the upper surface of the plate. These protrusions are rectangular or circular, and their placement on the upper surface of the integrated structural heat dissipation baseplate corresponds one-to-one with the physical location of the high heat flux density chips on the functional integration board to be mounted on it. The surface of each localized heat dissipation protrusion is flattened to ensure a tight fit with the back of the functional integration board.

[0031] An embedded heat pipe network is pre-installed within the integrated heat dissipation base plate. This network consists of multiple independent, flat heat pipes. One end of each heat pipe extends inside the base plate and terminates directly below a local heat dissipation protrusion, achieving a thermally conductive connection with the bottom of that protrusion. The other end of each heat pipe extends outward from the base plate, reaching the edge of the heat dissipation surface of the flat-panel satellite configuration or contacting the inner wall of the satellite-side heat dissipation panel. In this way, the heat pipe network physically and thermally connects each local heat dissipation protrusion to the final heat dissipation surface of the satellite configuration.

[0032] During satellite assembly, the first step is to install the pre-fabricated integrated structural heat dissipation base plate inside the flat-panel satellite configuration. The specific installation method is as follows: align the four edges of the integrated structural heat dissipation base plate with the inner mounting surface of the main structural frame of the flat-panel satellite configuration. Then, use multiple screws through the mounting holes on the edges of the base plate to securely fasten it to the satellite's main structural frame. At this point, the lower surface of the integrated structural heat dissipation base plate, or the extension of its internal heat pipe network, remains in contact with the inner side of the satellite configuration's heat dissipation panel or is filled with thermally conductive filler. Once the base plate is fixed, the installation of the base plate inside the satellite configuration is complete.

[0033] Next, the functional integration boards are installed. Each functional integration board, such as an information processing board or a computing power expansion board, does not have an independent metal casing or electrical enclosure. A layer of thermal interface material is pre-applied to the back of each functional integration board on the projection area of ​​its high heat flux density chip. Then, this functional integration board is placed directly on the integrated structural heat dissipation base plate, ensuring that the thermal interface material on the back of the board is in direct contact with the upper surface of the corresponding pre-set local heat dissipation protrusions on the base plate. Each functional integration board is then secured to its four corners or edges using screws or other fasteners in the corresponding threaded holes on the integrated structural heat dissipation base plate. At this point, the heat generated by each functional integration board is first transferred from the high heat flux density chip to the board's printed circuit board, then through the thermal interface material, and reaches the local heat dissipation protrusions in direct contact. The heat then enters the pre-embedded heat pipe network inside the integrated structural heat dissipation base plate from the local heat dissipation protrusions. The heat pipe network utilizes the phase change cycle of the internal working fluid to efficiently transfer heat to the other end of the heat pipe, and finally release it onto the heat dissipation surface of the flat-panel satellite configuration.

[0034] Through the above process, the integrated structural heat dissipation base plate not only serves as a physical mounting platform for all functional integrated boards without independent housings within the satellite configuration, but also acts as a highly efficient heat conduction hub, converging and guiding dispersed heat to the heat dissipation surface of the satellite configuration, thus achieving integrated structural support and heat dissipation functions. All functional integrated boards are interconnected via multi-layer flexible circuit boards for signal interconnection and power distribution, while the integrated structural heat dissipation base plate independently handles mechanical fixation and thermal management tasks.

[0035] In this context, satellite configuration refers to the overall structural form and external outline layout of the satellite. In this technical solution, the satellite configuration can be a flat-panel configuration, a cube-shaped configuration, a cylindrical configuration, or a deployable configuration. Taking a flat-panel configuration as an example, its shape is a relatively thin plate with a large planar dimension, typically with an overall thickness controlled between 100mm and 150mm. This configuration provides a basis for the flat layout of the internal electronic systems, allowing the various functional integration boards to be arranged along the thickness direction.

[0036] The integrated structural heat dissipation base plate is a foundation component that simultaneously bears the structural load of the satellite and provides overall heat dissipation. It is made of high thermal conductivity materials, such as high thermal conductivity aluminum alloy, magnesium-lithium alloy, carbon fiber composite material, or aluminum-based silicon carbide. Structurally, the base plate is a flat plate of a certain thickness, with a pre-embedded heat pipe network inside. Its upper surface is machined with multiple localized heat dissipation protrusions corresponding to the locations of high heat flux density chips on the integrated functional boards. This base plate replaces the dispersed chassis, mounting brackets, and independent heat dissipation structures found in traditional satellites, becoming the sole mechanical mounting base and unified heat dissipation base for all integrated functional boards.

[0037] In this invention, the metal casing refers to the protective metal enclosure provided for each independent functional unit in a traditional satellite electronic system. This casing is typically made of lightweight metal materials such as aluminum alloy, with a wall thickness of approximately 1.5mm to 2.0mm, and is a hexagonal, enclosed box shape used to enclose the circuit boards and electronic components inside the unit. The main functions of the metal casing are to provide electromagnetic shielding, physical protection, and a heat conduction path. In traditional satellites, each functional unit, such as the satellite computer, attitude control computer, or power management unit, has its own independent metal casing, and these casings are electrically interconnected via cables and connectors. Because each unit requires an independent casing, these metal casings and their associated mounting brackets occupy a significant proportion of the weight and space of the entire satellite. In this invention, all functional integration boards no longer have such independent metal casings; instead, they are directly mounted flat on an integrated structural heat dissipation base plate.

[0038] In this context, the electrical enclosure structure refers to the integrated frame or chassis in traditional satellite electronic systems used to centrally mount multiple functional circuit boards. This structure typically consists of a metal enclosure with multiple slots or mounting positions, internally containing a backplate, rails, and heat dissipation ducts or conductive heat dissipation paths. The electrical enclosure structure itself possesses independent electromagnetic shielding capabilities and mechanical strength. Multiple circuit boards are modularly inserted into the enclosure, interconnected via the enclosure's backplate or internal cables. The external components of the electrical enclosure structure generally require connection to the satellite's main structure via mounting brackets. Compared to the separate metal casings of traditional individual units, the electrical enclosure structure encapsulates multiple circuit boards within a single enclosure, but it still essentially retains a physical enclosure boundary, isolating the circuit boards from the satellite's main structure. In this invention, the functional integration boards are no longer mounted inside any electrical enclosure structure, but are directly laid flat and fixed to the integrated heat dissipation base plate, thus eliminating the intermediate layer of the electrical enclosure structure.

[0039] Signal interconnection and power distribution between any adjacent functional integration boards are achieved through multi-layer flexible circuit boards.

[0040] The multilayer flexible circuit board adopts a four-layer structure, including a high-speed signal layer, a medium-speed control layer, a power distribution layer, and a ground shielding layer. The high-speed signal layer uses differential pair routing, the power distribution layer uses wide copper foil traces, and the ground shielding layer is a full copper foil. The multilayer flexible circuit board uses a tapered linewidth design at the connection points with the functional integration board, and the multilayer flexible circuit boards corresponding to critical signals are equipped with dual-channel backup redundancy. The multilayer flexible circuit board adopts a symmetrical stack-up structure, with the high-speed signal layer and the medium-speed control layer located on opposite sides of the ground shielding layer. The differential pair traces in the high-speed signal layer use equal-length routing, and cross-plated copper shielding is used between the high-speed signal layer and adjacent layers.

[0041] Within the flat-panel satellite configuration, all functional integration boards do not have independent metal housings or electrical enclosures. Each functional integration board is directly mounted flat on the integrated structural heat dissipation base plate, with the board plane parallel to the satellite's main structural surface. Multiple functional integration boards are arranged sequentially along the satellite's thickness or planar direction, forming an adjacent relationship. Taking the information processing board and computing power expansion board as examples, two boards are arranged side-by-side adjacent to each other, with the gap between them controlled within the range of 5mm to 20mm.

[0042] At the edge of each functional integration board, a dedicated interface area is provided for connecting multilayer flexible circuit boards. This interface area contains a series of metal pads or solder terminals, the spacing and size of which match the lead spacing at the end of the multilayer flexible circuit board. For high-speed signals, the pads are arranged in differential pairs, with the two pads of each differential signal pair closely adjacent to each other.

[0043] The multilayer flexible circuit board is manufactured individually. Each multilayer flexible circuit board has a flat, elongated shape, with a length slightly greater than the straight-line distance between the interfaces of two adjacent functional integration boards. Both ends of the multilayer flexible circuit board have exposed copper leads or gold fingers, and these ends are reinforced to increase mechanical strength. The middle section of the multilayer flexible circuit board retains flexibility and can be bent according to the height or angle difference between two boards.

[0044] During assembly, the first functional integration board is first mounted and fixed onto the integrated structural heat dissipation base plate. Then, one end of the multilayer flexible circuit board is aligned with the interface pads on the edge of this board, and each pin of the multilayer flexible circuit board end is securely soldered to its corresponding pad on the board using thermoforming or manual soldering. After soldering, the solder joints are cleaned and inspected. Next, the adjacent second functional integration board is placed in position, maintaining the preset gap and alignment between the two boards. The other end of the multilayer flexible circuit board is bent and guided to the interface pads of the second board, and the same alignment and soldering operation is performed. Finally, the second functional integration board is fixed to the integrated structural heat dissipation base plate with screws.

[0045] The multilayer flexible circuit board contains four independent conductive layers. The high-speed signal layer transmits high-speed differential signals between information processing boards and computing expansion boards, such as high-speed bus signals for peripheral component interconnects, with signal rates reaching 16 gigabits per second to 32 gigabits per second. The medium-speed control layer transmits control signals for integrated circuit buses, serial peripheral interface buses, and controller area network buses. The power distribution layer supplies primary power voltage, such as 5V or 3.3V, from the power management board to other functional integration boards; the width of the wide copper foil traces is designed according to the current carrying capacity, typically ranging from 1mm to 5mm. The grounding shield layer, as a complete copper foil layer, covers the entire planar area of ​​the multilayer flexible circuit board, providing a low-impedance signal return path for the high-speed signal layer and the medium-speed control layer, while also shielding against external electromagnetic interference.

[0046] At the connection points between the multilayer flexible circuit board and the functional integration board, a gradient linewidth design is employed. The width of the lead-out lines at the ends of the multilayer flexible circuit board gradually transitions from a smaller width for internal traces to a larger width for the pads, thereby reducing signal reflection and impedance abrupt changes. For critical signals, such as high-speed clock signals or command control signals, the satellite electronic system design employs two independent multilayer flexible circuit board channels, each with independent routing. One channel serves as the primary channel, and the other as a backup channel. When a signal anomaly or open circuit occurs in the primary channel, the system automatically switches to the backup channel to continue signal transmission.

[0047] The multilayer flexible circuit board adopts a symmetrical stack-up structure. The stack-up order from top to bottom is: high-speed signal layer, ground shield layer, medium-speed control layer, and power distribution layer. Alternatively, another symmetrical order can be used: high-speed signal layer, ground shield layer, power distribution layer, ground shield layer, and medium-speed control layer. The ground shield layer is located between the high-speed signal layer and the medium-speed control layer, serving as an isolation layer. Differential pairs in the high-speed signal layer use equal-length routing, with the length difference between the two traces in each differential signal pair not exceeding 5 mils (0.127 mm). A cross-plated copper shield is used between the high-speed signal layer and the adjacent ground shield layer; that is, the copper foil on the ground shield layer is distributed in a grid or cross pattern to further reduce crosstalk.

[0048] Any adjacent functional integration boards are interconnected via one or more multi-layer flexible circuit boards, establishing signal interconnection and power distribution pathways. Signal interconnection ensures data exchange and control coordination between processors, memories, and dedicated computing chips on different boards. Power distribution ensures that each functional integration board can obtain the necessary power from a unified energy management board, eliminating the need for separate power cables. The entire interconnection system eliminates the discrete cable networks and numerous circular connectors used in traditional satellites, achieving high-density, low-loss, and high-reliability electrical connections between boards.

[0049] In this context, a functional fusion board refers to an electronic component that integrates the circuits and functions of multiple independent functional units in a traditional satellite onto a single printed circuit board. In this technical solution, the functional fusion board includes information processing boards, computing power expansion boards, telemetry and data transmission RF boards, and energy management boards. Each functional fusion board does not have an independent metal casing or electrical enclosure; its back is directly mounted on a localized heat dissipation platform on an integrated structural heat dissipation base plate via a thermally conductive interface material. The functional fusion board is shaped like a rectangular printed circuit board, with interface pads or board-to-board connectors on its edges for connecting to multi-layer flexible circuit boards.

[0050] Signal interconnection refers to establishing electrical connections between different functional integration boards to enable the transmission of data and control signals. Signal interconnection includes high-speed data signals (such as PCIe, DDR4 / 5), medium- and low-speed control signals (such as SPI, I2C, CAN), and clock synchronization signals. In this technical solution, signal interconnection is achieved through a high-speed signal layer and a medium-speed control layer in a multi-layer flexible circuit board. The signal originates from the driver chip on one functional integration board, travels through the printed lines on the board to the connection interface, and then through corresponding traces on the multi-layer flexible circuit board to the receiving interface on the adjacent functional integration board, where it is finally received by the target chip.

[0051] Power distribution refers to the process of transferring DC power generated by the satellite power system from one functional fusion board to another. Power distribution includes power rails of different voltage levels, such as core voltage, input / output interface voltage, and analog voltage. In this technical solution, power distribution is achieved through a power distribution layer on a multi-layer flexible circuit board. The power distribution layer uses wide copper foil traces to reduce resistance and voltage drop, ensuring efficient power transmission. Power originates from the output of a power supply board (such as an energy management board), travels through the power distribution layer on the multi-layer flexible circuit board, reaches the adjacent functional fusion board requiring power, and is then supplied to the various chips via power conversion circuits on the board.

[0052] The integrated heat dissipation base plate has a pre-embedded heat pipe network inside, which is thermally connected to the local heat dissipation bosses to transfer the heat generated by each functional fusion board to the satellite heat dissipation surface.

[0053] The integrated heat dissipation base plate is made of high thermal conductivity aluminum alloy and is a rectangular flat plate. During the manufacturing process, multiple grooves for embedding the heat pipe network are pre-cut in the mold or machining stage. These grooves start directly below each local heat dissipation protrusion on the base plate and extend in a converging or parallel manner to the area corresponding to the satellite heat dissipation surface at the edge of the base plate. The cross-sectional shape of the grooves is rectangular or circular, and the dimensions are matched to the shape of the selected heat pipes.

[0054] The heat pipe network consists of multiple independent, flat heat pipes. Each heat pipe is divided into an evaporation section, an adiabatic section, and a condensation section in the heat transfer direction. The outer surface of the heat pipes is nickel-plated or chrome-plated to enhance adhesion to the base plate material. During the assembly of the heat pipe network, the evaporation section of each heat pipe is first pre-bent or shaped to fit the bottom of each local heat dissipation protrusion. Then, the heat pipes are placed one by one into the grooves on the base plate. The evaporation sections of the heat pipes are positioned directly below the corresponding local heat dissipation protrusions in the grooves, while the condensation sections extend along the grooves to the edge of the base plate, corresponding to the inner side of the satellite heat dissipation surface.

[0055] To achieve a thermally conductive connection between the heat pipe network and the local heat dissipation boss, a soldering process is used for fixation. After the heat pipe is placed, the local heat dissipation boss is pressed onto the top of the heat pipe evaporation section, and high temperature is applied to melt the solder paste, welding the outer wall of the heat pipe evaporation section to the bottom of the local heat dissipation boss and the inner wall of the groove in the base plate, forming a single unit. After soldering, the solder fills the tiny gaps between the heat pipe, the base plate, and the boss, forming a low thermal resistance thermally conductive connection. For material combinations that cannot be soldered, a clamping method is used: a layer of high thermal conductivity filler is placed on top of the heat pipe, and then the local heat dissipation boss is pressed from above with screws, firmly clamping the heat pipe between the boss and the base plate.

[0056] After the heat pipe network and the local heat dissipation protrusions are thermally connected, the processing of the integrated heat dissipation base plate continues. The upper surface of the base plate is milled flat to expose the upper surface of the local heat dissipation protrusions and achieve uniform flatness requirements. The lower surface of the base plate is left as is or further weight-reduced. At this point, the heat pipe network is completely embedded inside the base plate, with the evaporation section located directly below the local heat dissipation protrusions and the condensation section located at the edge of the base plate.

[0057] During satellite assembly, the integrated structural heat dissipation base plate is first fixed inside the satellite configuration. The edge of the base plate is rigidly connected to the inner frame of the satellite's heat dissipation surface. The edge area of ​​the base plate reached by the heat pipe network condensation section is in close contact with the inner surface of the satellite's heat dissipation surface. To improve heat transfer efficiency, a layer of thermally conductive silicone grease is applied between the outer surface of the base plate corresponding to the heat pipe condensation section and the inner surface of the satellite's heat dissipation surface, and screws are used to press the edge of the base plate firmly onto the satellite's heat dissipation surface, achieving a thermally conductive connection between the two.

[0058] When the functional fusion boards are mounted onto the integrated structural heat dissipation baseplate, the back of each functional fusion board is in direct contact with the upper surface of the corresponding local heat dissipation protrusion via a thermally conductive interface material. The heat generated by the high heat flux density chips on the functional fusion boards is first transferred to the boards themselves, then passes through the thermally conductive interface material into the local heat dissipation protrusion. After receiving the heat, the local heat dissipation protrusion rapidly flows into the heat pipe network due to the low thermal resistance thermal connection between the bottom of the protrusion and the heat pipe evaporation section. The working medium inside the heat pipe absorbs heat and vaporizes in the evaporation section, carrying the heat rapidly to the condensation section. In the condensation section, the heat is transferred through the heat pipe wall to the edge of the integrated structural heat dissipation baseplate, and then through thermal grease to the satellite heat dissipation surface. The satellite heat dissipation surface dissipates the heat into outer space via infrared radiation. After the working medium releases heat and liquefies in the condensation section, it returns to the evaporation section by capillary force, beginning the next cycle.

[0059] Through the above process, the heat generated by each functional fusion board is transferred step by step: from the functional fusion board to the local heat dissipation boss, from the local heat dissipation boss to the evaporation section of the heat pipe network, from the heat pipe network to the edge of the integrated structural heat dissipation base plate, and finally radiated from the satellite heat dissipation surface to the external space. In the entire heat transfer path, the local heat dissipation boss serves as a heat collection node, the heat pipe network serves as a heat transport channel, and the satellite heat dissipation surface serves as the final heat emission node. The three are connected by thermal conductivity to form a complete heat conduction system.

[0060] A heat pipe network is a heat transfer system composed of multiple independent heat pipes connected or arranged in a specific topology. Each heat pipe is a sealed metal tube filled with a phase change working medium, and its inner wall has a capillary structure. One end of the heat pipe is the evaporation section, the other end is the condensation section, and the middle is the adiabatic section. When the evaporation section is heated, the internal working medium vaporizes and absorbs heat. The vapor flows to the condensation section, releases heat, and condenses into a liquid. The liquid then returns to the evaporation section by capillary force, thus achieving efficient heat transfer through this cycle. In this technical solution, the heat pipe network is embedded inside the integrated structural heat dissipation base plate. The evaporation ends of multiple heat pipes are thermally connected to various local heat dissipation protrusions, and the condensation ends converge and extend to the satellite heat dissipation surface.

[0061] In satellite design, the heat dissipation surface refers to the external surface structure that radiates heat into outer space. In a flat-panel satellite configuration, the heat dissipation surface is typically a metal panel on the side or back of the satellite facing away from the sun. Its inner surface contacts the condensation end of the heat pipe network inside the integrated heat dissipation base plate, while its outer surface is covered with a coating or heat dissipation film with high infrared emissivity. The heat dissipation surface dissipates the heat transferred from the heat pipe network into the outer space environment through thermal radiation, thereby maintaining the temperature of the satellite's internal electronic equipment within permissible ranges. The location and area of ​​the satellite heat dissipation surface are designed according to the overall thermal control requirements of the satellite.

[0062] Optionally, in the above technical solution, all functional integration boards include at least an information processing board and a computing power expansion board. The information processing board uses virtualization technology to incorporate the heterogeneous computing power resources on the computing power expansion board into a unified computing power resource pool, and dynamically allocates the computing power resources in the unified computing power resource pool to at least one of the following functional modules: the space service management functional module, the attitude control functional module, and the telemetry, tracking and command (TT&C) functional module.

[0063] Within the flat-panel satellite configuration, all functional integration boards are directly mounted on the integrated structural heat dissipation base plate without separate metal housings or electrical enclosures. These functional integration boards include at least information processing boards and computing power expansion boards, as well as interface boards. The information processing boards and computing power expansion boards are arranged adjacent to each other, and high-speed signal interconnection between them is achieved through multi-layer flexible circuit boards. The interface boards are responsible for connecting to external satellite equipment or payloads, performing signal level conversion and interface protocol adaptation. Their backs are also in direct contact with localized heat dissipation protrusions on the integrated structural heat dissipation base plate via a thermally conductive interface material.

[0064] The information processing board uses a high-performance multi-core central processing unit (CPU) as its main chip. This CPU supports hardware virtualization expansion, allowing the operation of virtual machine monitors or container runtime environments. The information processing board also integrates a memory controller, a high-speed peripheral interconnect bus (PEBH) controller, and multiple direct memory access channels. The computing power expansion board integrates a graphics processing unit (GPU) and a neural network processor (NNF). The GPU has hundreds or thousands of stream processor cores, suitable for large-scale parallel vector computation. The NLF contains multiple tensor computation units and a multiply-accumulate array, specifically designed for deep learning inference tasks. Both types of computing chips are connected to the CPU on the information processing board via a high-speed PEBH. A high-speed signal layer in the multilayer flexible circuit board is specifically designed to carry differential signals from the high-speed PEBH, achieving transmission rates exceeding 16 GB / s.

[0065] The software system running on the information processing board includes the underlying operating system, the virtualization software layer, and the computing power scheduling middleware. The virtualization software layer is responsible for abstracting physical computing power resources. Specifically, during system startup, the central processing unit (CPU) of the information processing board enumerates all devices connected to the high-speed peripheral interconnect bus, including the graphics processor and neural network processor on the computing power expansion board. The virtualization software reads the capability register of each device to obtain its attributes such as the number of computing units, memory capacity, and supported instruction sets. Then, the virtualization software creates a corresponding virtual device instance for each device and manages these virtual device instances within a unified computing power resource pool. At the software level, the computing power resource pool is represented by a resource mapping table. Each entry in the table records the logical identifier, physical address, type (CPU core, graphics processor stream processor group, neural network processor tensor unit), current allocation status, and identifier of the occupied functional module of a virtual computing unit.

[0066] After the computing resource pool is established, the space service management module, attitude control module, and telemetry and communication module on the information processing board initiate computing power requests according to their respective operating cycles. The computing power scheduling middleware is responsible for dynamically allocating the computing resources in the computing resource pool to these functional modules.

[0067] Taking the attitude control module as an example, when the satellite enters attitude maneuvering mode, the attitude control algorithm needs to perform high-frequency matrix inversion and Kalman filter iteration operations, resulting in a sharp increase in computing power demand. The attitude control module sends a computing power request to the computing power scheduling middleware. The request parameters include the required calculation type being floating-point matrix operations, the required number of computing units being 32 stream processor cores of the graphics processor, and an estimated execution time of 5ms. The computing power scheduling middleware checks the number of currently available stream processor groups in the computing power resource pool. If the available number meets the requirements, the scheduling middleware marks the 32 stream processor groups from idle to allocated to the attitude control module and returns the corresponding virtual device handles. The attitude control module submits a computing task to the graphics processor through this handle: transmitting the attitude matrix data to the graphics processor's video memory via the high-speed peripheral component interconnect bus, starting the kernel function to execute parallel matrix operations, and reading the results after the calculation is completed. After the task is completed, the attitude control module actively releases the resources, and the scheduling middleware re-marks the corresponding stream processor groups as idle and returns them to the computing power resource pool.

[0068] In normal mode, the space management module requires only a small amount of computing power to perform status inspections and instruction processing. However, when global fault diagnosis and data-intensive analysis are needed, the space management module requests computing power resources from the neural network processor. The scheduling middleware dynamically allocates a portion of the neural network processor's tensor units to the space management module for performing neural network inference tasks for fault mode recognition. The computing power resources are released immediately after inference is completed.

[0069] When the telemetry, control, and communication module receives high-speed data transmission, it needs to perform real-time low-density parity check decoding. This decoding algorithm has high parallelism. The telemetry, control, and communication module requests a stream processor group from the graphics processor from the scheduling middleware. The scheduling middleware allocates currently unused computing units in the graphics processor to the telemetry, control, and communication module, and reclaims them after decoding is complete.

[0070] When multiple functional modules simultaneously request computing resources, the scheduling middleware arbitrates according to a preset priority strategy. The attitude control module, due to its hard real-time requirements, is set to the highest priority. The space operations management module has a medium priority. The telemetry, tracking, and command (TT&C) communication module has the lowest priority. If the resources in the computing resource pool are insufficient to satisfy all requests, according to the preset strategy, the attitude control module, due to its hard real-time requirements, is set to the highest priority, the space operations management module to a medium priority, and the TT&C communication module to the lowest priority. Requests from high-priority functional modules are fulfilled first, while low-priority requests are queued or rejected.

[0071] Through the above implementation process, the information processing board utilizes virtualization technology to abstract and incorporate the heterogeneous computing resources (graphics processors and neural network processors) on the computing power expansion board into a unified computing resource pool. Then, based on the real-time requirements of the satellite management module, attitude control module, and telemetry and communication module, the computing resources in the pool, such as the central processing unit core, graphics processor stream processor group, and neural network processor tensor unit, are dynamically allocated. The minimum allocation time unit can reach the millisecond level, thereby realizing on-demand sharing and elastic allocation of heterogeneous computing power within a single satellite. Simultaneously, the interface board, as one of the functional integration boards, conditions and forwards signals from external sensors or satellite-rocket interfaces to the information processing board, and receives control commands from the information processing board to drive external actuators, achieving complete information interaction between the entire satellite's electronic system and the external environment.

[0072] The information processing board is a functionally integrated board with a high-performance multi-core processor at its core. This board does not have a separate metal casing or electrical enclosure; its back is directly mounted on a localized heat dissipation platform on an integrated structural heat dissipation base plate via a thermally conductive interface material. The information processing board integrates the main processor, memory, storage chips, and a high-speed bus interface. This board is responsible for running satellite management software, attitude control algorithms, orbit determination and prediction software, mission planning software, etc., undertaking all the functions of the satellite's satellite computer, attitude control computer, and orbit determination unit. Simultaneously, the information processing board serves as the central hub for the satellite's overall computing power scheduling, managing the heterogeneous computing resources on other computing power expansion boards through software.

[0073] The computing power expansion board is a functional integration board that incorporates dedicated computing chips. This board also lacks a separate metal casing and electrical enclosure; its back is directly mounted on a localized heat dissipation platform on an integrated structural heat dissipation base plate via a thermally conductive interface material. The dedicated computing chips integrated on the computing power expansion board include at least one of a graphics processor, a neural network processor, and a field-programmable gate array (FPGA). These dedicated computing chips are interconnected with the information processing board via a high-speed bus. The computing power expansion board can dynamically load different artificial intelligence inference models or data processing algorithms according to task requirements, providing additional computing power to the entire satellite.

[0074] Virtualization technology is a software-level resource abstraction method. Virtualization software running on the information processing board abstracts and isolates physically existing computing resources (including processor cores, memory, dedicated computing chips, etc.), allowing upper-layer functional modules to be unconcerned about the specific physical location and type of the underlying hardware. Virtualization technology achieves logical partitioning, sharing, and isolation of resources through management programs or container technology. In this technical solution, the information processing board utilizes virtualization technology to uniformly abstract heterogeneous computing resources on the computing power expansion board into schedulable logical resources, shielding the hardware differences between different computing chips.

[0075] Heterogeneous computing resources refer to various computing resources existing within the same satellite electronic system that have different instruction set architectures or different computing characteristics. Specifically, these include the core computing power of the central processing unit on the information processing board, the parallel computing power of the graphics processing unit on the computing power expansion board, the deep learning inference computing power of the neural network processor, and the hardware-reconfigurable parallel processing computing power of the field-programmable gate array. These resources are physically distributed across different functional integration boards, each with its own emphasis in computing characteristics, and are collectively referred to as heterogeneous computing resources.

[0076] In this context, a computing resource pool refers to the integration of physically dispersed heterogeneous computing resources into a unified logical whole through software abstraction, which can be used on demand by any functional module. Within the computing resource pool, individual computing resources no longer belong to a specific function but exist as shared capacity. The capacity of the computing resource pool is equal to the sum of the computing capabilities of all heterogeneous computing resources within it. The virtualization software on the information processing board is responsible for maintaining the metadata of the computing resource pool, recording the type, capacity, current occupancy status, and health status of each computing resource.

[0077] Dynamic allocation refers to the process of flexibly allocating a portion of the computing resources in the pool to functional modules during operation based on their real-time computing power demands, and then reclaiming and redistributing these resources to other functional modules after use. Dynamic allocation differs from static binding; it does not permanently allocate a fixed computing resource to a specific function, but rather makes real-time decisions on allocation schemes based on factors such as task priority, deadline, and resource utilization. Dynamic allocation is executed by the computing power scheduling software on the information processing board, and the allocation granularity can be a single processor core, a computing unit of a graphics processing unit, or part of a neural network processor.

[0078] The satellite management module refers to the software functional unit that realizes satellite platform management and service scheduling. This module runs on the main processor of the information processing board and is responsible for satellite management tasks such as overall satellite status monitoring, command parsing and distribution, data management, time management, mission planning and scheduling, and fault detection and recovery. In traditional satellites, the satellite management module requires the entire computing power of a dedicated satellite computer. In this technical solution, it runs as a software module on the information processing board and can dynamically call upon computing power from the computing resource pool to complete computationally intensive satellite processing tasks.

[0079] The attitude control module is a software functional unit that realizes satellite attitude determination and control. This module runs on the main processor of the information processing board and is responsible for receiving attitude sensor data (such as gyroscopes, star sensors, and sun sensors), executing attitude determination algorithms (such as filtering, fusion, and attitude calculation), calculating control commands, and driving actuators (such as flywheels and magnetic torque converters). The attitude control module has strict real-time requirements, with algorithm cycles typically in the millisecond range. In this technical solution, this module can utilize computing power from the computing resource pool to accelerate complex attitude control algorithms, for example, by using a graphics processing unit to perform parallel computation of the Kalman filter matrix.

[0080] The telemetry, tracking, and command (TT&C) communication module refers to the software functional unit that realizes satellite-to-ground TT&C, data transmission, and inter-satellite communication. This module partially runs on the information processing board and partially on the TT&C data transmission RF board. The TT&C communication module on the information processing board is responsible for baseband signal processing tasks such as protocol processing, data packing and unpacking, channel coding and decoding, and encryption / decryption. These tasks may involve a large number of calculations such as convolution, interleaving, and fast Fourier transform, requiring significant computing power. In this technical solution, the TT&C communication module can dynamically call upon computing resources from the computing resource pool to accelerate baseband signal processing.

[0081] Optionally, in the above technical solution, the location of the local heat dissipation protrusion on the upper surface of the integrated heat dissipation base plate corresponds one-to-one with the location of the high heat flux density chip on each functional fusion board. The heat pipe network includes multiple heat pipes, one end of each heat pipe is thermally connected to the corresponding local heat dissipation protrusion, and the other end of each heat pipe extends to the heat dissipation surface of the satellite configuration.

[0082] During the design phase of the satellite electronic system, the first step is to plan the layout of all functional integration boards. Each functional integration board does not have an independent metal casing or electrical box structure; multiple electronic chips are soldered onto the upper surface of its printed circuit board, including several high heat flux density chips, such as the central processing unit on the information processing board and the graphics processor on the computing power expansion board. Designers measure the planar coordinate position of each high heat flux density chip on each functional integration board, that is, taking one corner of the board as the origin, and recording the lateral and longitudinal distances of the center point of each chip relative to the origin.

[0083] After completing the layout of the functional integration boards, an integrated structural heat dissipation baseplate was designed. This baseplate, made of high thermal conductivity aluminum alloy, is a rectangular flat plate with dimensions matching the internal space of the satellite configuration. During machining on the baseplate's surface, designers determined the locations of local heat dissipation protrusions based on the previously recorded coordinates of the high heat flux density chips on each functional integration board. The specific method is as follows: First, the mounting position of each functional integration board on the baseplate is fixed. Threaded holes for each board's mounting holes are pre-machined on the baseplate to ensure that the board's planar coordinates relative to the baseplate's origin are known after installation. Then, for each high heat flux density chip on each board, its relative coordinates on the board are superimposed with the board's mounting position coordinates on the baseplate to obtain the chip's absolute coordinates in the baseplate's coordinate system. A local heat dissipation protrusion is then machined at this absolute coordinate point in the baseplate's coordinate system. The localized heat dissipation protrusion is a rectangular platform, with its planar dimensions slightly larger than the package size of the corresponding high heat flux density chip. For example, if the chip package size is 20mm x 20mm, the upper surface of the localized heat dissipation protrusion will be machined to 25mm x 25mm. The height of the localized heat dissipation protrusion is 2mm to 5mm, and the top of the protrusion is precision milled flat, with a flatness controlled within 0.05mm. Through the above steps, the location of the localized heat dissipation protrusion on the upper surface of the integrated thermal management base plate corresponds one-to-one with the location of the high heat flux density chip on each functional integration board.

[0084] An embedded heat pipe network is embedded within the integrated heat dissipation base plate. This network consists of multiple independent, flat heat pipes. The heat pipes have a rectangular cross-section, with a width of 8mm to 12mm, a thickness of 2mm to 3mm, and a length determined by the base plate dimensions. One end of each heat pipe is positioned directly beneath a corresponding localized heat dissipation boss. To achieve this arrangement, during base plate manufacturing, multiple grooves are milled downwards onto the upper surface of the base plate blank. Each groove begins below the center area of ​​the localized heat dissipation boss at one end and extends towards the edge of the base plate at the other. The depth and width of the grooves match the dimensions of the heat pipes. The heat pipes are then placed into the grooves, with one end (the evaporation section) positioned directly beneath the localized heat dissipation boss.

[0085] One end of each heat pipe is thermally connected to a corresponding local heat dissipation boss. The specific process for this connection is as follows: High thermal conductivity solder paste or thermal adhesive is filled into the gaps between the upper surface of the heat pipe's evaporation section and the lower surface of the local heat dissipation boss, as well as between the heat pipe and the inner wall of the groove. Then, the local heat dissipation boss is pressed into the groove, and the solder paste is melted or the thermal adhesive is cured by heating, fixing the heat pipe, groove wall, and local heat dissipation boss together. After curing, heat can be directly transferred from the local heat dissipation boss to the evaporation section of the heat pipe, with a contact thermal resistance of less than 0.1℃ / W. For material combinations that cannot be soldered, a compression method is used: a 0.1mm thick thermal grease pad is placed above the heat pipe's evaporation section, and then the local heat dissipation boss is pressed into the base plate with screws, so that the bottom of the boss presses against the heat pipe through the pad, achieving a low thermal resistance thermal connection in the same way.

[0086] The other end of each heat pipe originates below a local heat dissipation boss and extends along a groove towards the edge of the base plate. The direction of extension is determined by the location of the heat dissipation surface in the satellite configuration. For a flat-panel satellite configuration, the heat dissipation surface is typically located on the back surface of the satellite or one of its side panels. Therefore, the condensation section of the heat pipe is guided to the edge of the integrated structural heat dissipation base plate, which is adjacent to the inner wall of the satellite's heat dissipation surface. The heat pipe may pass under other local heat dissipation bosses during its extension, but different heat pipes are separated by grooves and do not interfere with each other. To evenly transfer heat across the entire heat dissipation surface, the condensation ends of multiple heat pipes are arranged in parallel at the edge of the base plate, spaced 10mm to 15mm apart. After reaching the edge of the base plate, the end face of the heat pipe is flush with or slightly exposed to contact the satellite's heat dissipation surface.

[0087] During satellite assembly, an integrated heat dissipation base plate is fixed inside the satellite configuration. The area corresponding to the condenser end of the heat pipe at the edge of the base plate is fitted to the inner side of the heat dissipation surface of the satellite configuration. Specifically, a layer of thermally conductive grease is applied between the edge of the base plate and the inner wall of the satellite's heat dissipation surface. Then, screws are used to press the edge of the base plate firmly against the inner wall of the heat dissipation surface, allowing the condenser end of the heat pipe to form a low-thermal-resistance thermally conductive connection with the heat dissipation surface through the base plate material and the thermally conductive grease. If the heat pipe extends directly beyond the edge of the base plate, the condenser end of the heat pipe can be directly pressed against the inner wall of the heat dissipation surface and secured with a pressure plate.

[0088] Through the above implementation process, directly beneath each high heat flux density chip on each functional integration board, on the upper surface of the integrated thermal management base plate, there is a corresponding local heat dissipation protrusion. One end of each heat pipe is thermally connected to this local heat dissipation protrusion, and the other end extends to the heat dissipation surface of the satellite configuration. In this way, the heat generated by each high heat flux density chip is independently and efficiently transferred along the path of chip → thermally conductive interface material → local heat dissipation protrusion → corresponding heat pipe evaporation section → heat pipe internal phase change heat transfer → heat pipe condensation section → satellite heat dissipation surface, avoiding thermal interference between different chips and achieving precise point-to-point heat dissipation.

[0089] High heat flux density (HFLD) chips refer to electronic chips with high power generation per unit area. In computing satellites, typical HFLD chips include high-performance multi-core CPUs on information processing boards, graphics processors, neural network processors, and field-programmable gate arrays (FPGAs) on computing expansion boards. These chips typically have a thermal design power (TDP) in the range of 15 to 100 watts, while the small area on the top of the chip package allows for a heat flux density exceeding 10 watts per square centimeter. HFLD chips generate significant heat during operation, requiring efficient heat dissipation paths to keep the temperature within acceptable limits.

[0090] In this technical solution, the positions of the local heat dissipation protrusions on the upper surface of the integrated structural heat dissipation base plate correspond one-to-one with the positions of the high heat flux density chips on each functional fusion board. This means that for each high heat flux density chip on each functional fusion board, there is exactly one local heat dissipation protrusion directly below it on the upper surface of the integrated structural heat dissipation base plate. The number of these local heat dissipation protrusions is equal to the total number of high heat flux density chips on all functional fusion boards. Each protrusion serves a specific chip, preventing misalignment where one protrusion corresponds to multiple chips or multiple protrusions correspond to one chip.

[0091] Optionally, in the above technical solution, the satellite configuration is a flat-panel satellite configuration, a cube satellite configuration, a cylindrical satellite configuration, or a deployable satellite configuration; when the satellite configuration is a flat-panel satellite configuration, each functional fusion board is laid flat along the thickness direction of the flat-panel satellite configuration and the surface of each functional fusion board is parallel to the main structural surface of the flat-panel satellite configuration; when the satellite configuration is a cube satellite configuration, each functional fusion board is laid flat on the integrated structural heat dissipation base plate; when the satellite configuration is a cylindrical satellite configuration, each functional fusion board is arranged radially around the central axis of the cylindrical satellite configuration; when the satellite configuration is a deployable satellite configuration, the integrated structural heat dissipation base plate is set on the deployable panel of the deployable satellite configuration, specifically: 1) When the satellite configuration is a flat-panel design, the overall shape of the satellite is a flat plate, with an overall thickness controlled between 100mm and 150mm. The main structural surface of the satellite consists of two large, parallel planes. The upper surface is used to install solar cells, and the lower surface serves as a heat dissipation surface. Inside the flat-panel satellite configuration, an integrated structural heat dissipation base plate is fixedly installed on the side closest to the heat dissipation surface, with its upper surface parallel to the main structural surface. All functional integration boards, including information processing boards, computing power expansion boards, telemetry and data transmission RF boards, and energy management boards, do not have independent metal casings or electrical enclosures. These functional integration boards are arranged layer by layer along the thickness direction of the flat-panel satellite configuration. The lower surface of each functional integration board is in direct contact with the local heat dissipation protrusions on the integrated structural heat dissipation base plate through a thermally conductive interface material. The surface of each functional integration board remains parallel to the main structural surface of the flat-panel satellite configuration. The specific installation process is as follows: First, the integrated structural heat dissipation base plate is fixed to the inner wall of the satellite's heat dissipation surface with screws, with the upper surface of the base plate parallel to the main structural surface. Then, starting with the layer closest to the base plate, place the first functional integration board (e.g., an energy management board) on the base plate, aligning the back of the board with the corresponding local heat dissipation protrusion on the base plate. Secure it to the threaded holes on the base plate using screws through the mounting holes on the board. Next, on top of the first board, install the second functional integration board (e.g., an information processing board) using insulating pads or a lightweight support frame. The back of the second board also contacts another set of local heat dissipation protrusions on the base plate. Note that due to limited thickness dimensions, all boards need to dissipate heat through different protrusions on the base plate. Therefore, the boards are not directly stacked, but rather laid flat on the same base plate but staggered in layers along the thickness direction, or a stepped structure is used so that the back of each board can contact the base plate. In practice, for very thin flat-panel satellite configurations, all functional integration boards are usually laid side-by-side on the same plane rather than stacked, because there is insufficient space in the thickness direction to stack multiple boards. Therefore, it needs clarification: "Laying out along the thickness direction" means that the surface of each board is perpendicular to the thickness direction, i.e., the board is placed horizontally. However, multiple boards are arranged side-by-side in a horizontal direction (within a plane perpendicular to the thickness), not stacked vertically. A typical implementation involves dividing the upper surface of the integrated structural heat dissipation base plate into multiple rectangular areas. Each area houses a functional integration board, and the surfaces of all boards are parallel to the upper surface of the base plate (which is parallel to the main structural surface). Therefore, the surfaces of each board are also parallel to the main structural surface. The boards are interconnected via multi-layer flexible circuit boards. In this way, within the limited thickness of the flat-panel satellite configuration, all boards are laid out flat on the base plate, making full use of the base plate's area.

[0092] 2) When the satellite configuration is a cube satellite, the satellite's outer shape is cube-shaped, and its internal space is close to a cube. Inside the cube satellite configuration, one of the inner wall surfaces is selected as the mounting base. The integrated structural heat dissipation base plate is machined into a rectangular plate matching the internal cross-sectional dimensions of the cube satellite configuration. The base plate is fixed to this inner wall surface with screws, with its upper surface facing the interior of the satellite. The various functional integration boards are laid flat on the integrated structural heat dissipation base plate. Specifically, local heat dissipation bosses and mounting threaded holes are pre-machined on the upper surface of the base plate. Then, information processing boards, computing power expansion boards, etc., are fixed to the base plate one by one in a flat manner. The back of each board contacts the corresponding local heat dissipation boss through a thermally conductive interface material. Signal interconnection between boards is achieved through multi-layer flexible circuit boards. Since the internal space of the cube satellite configuration is relatively large, it is also possible to install them on multiple base plates in layers. However, this technical solution describes them as being laid flat on the same integrated structural heat dissipation base plate; therefore, all boards are arranged side-by-side on the base plate plane. The heat dissipation surface of a cube satellite configuration is usually chosen to be the opposite side of the base plate fixing surface, and the condensation end of the heat pipe network extends to this heat dissipation surface.

[0093] 3) When the satellite configuration is cylindrical, the satellite has a cylindrical shape and a central axis. Inside the cylindrical satellite configuration, the integrated structural heat dissipation base plate is designed as a circular or regular polygonal base plate, which is installed on one end face or the middle of the cylinder. The functional integration boards are arranged radially around the central axis of the cylindrical satellite configuration. Specifically, a central pillar or adapter is placed at the center of the integrated structural heat dissipation base plate, and the outer edge of the base plate maintains a certain gap with the inner wall of the cylindrical shell. On the upper surface of the base plate, local heat dissipation protrusions are arranged radially, with the centerline of the protrusions pointing towards the outer edge of the base plate. Each functional integration board is a rectangular plate, its length along the radial direction, with the inner end of the board close to the central axis and the outer end close to the cylindrical shell. The back of each functional integration board contacts the corresponding local heat dissipation protrusion on the base plate through a thermally conductive interface material. Signal interconnection between the boards is achieved through multi-layer flexible circuit boards, which converge in the central area of ​​the base plate. The heat pipe network is arranged radially inside the base plate. One end of each heat pipe corresponds to a local heat dissipation protrusion, and the other end extends to the outer edge of the base plate, where it connects thermally with the heat dissipation surface of the cylindrical satellite-shaped outer shell. In this way, all functional integrated boards are evenly distributed around the central axis like fan blades, making full use of the symmetry of the cylindrical space.

[0094] 4) When the satellite configuration is a deployable satellite, the satellite consists of a central module and multiple deployable panels. In the launch state, the deployable panels are folded and fitted around the central module. After entering orbit, the deployable panels unfold outwards via a hinged drive mechanism, forming a larger flat surface. In this technical solution, an integrated structural heat dissipation base plate is installed on the deployable panels of the deployable satellite configuration. Specifically, the inner surface of each deployable panel (i.e., the side facing the satellite center) is pre-machined with mounting interfaces. The external dimensions of the integrated structural heat dissipation base plate match the inner surface dimensions of the deployable panels, and the base plate is fixed to the inner surface of the deployable panels using screws or adhesive bonding. The upper surface of the base plate faces inwards from the panel, i.e., away from the outer surface of the panel. Functional integration boards are installed on the base plate in the aforementioned manner. When the deployable panels are in the folded state, the base plates and boards on each panel are close to each other but do not interfere with each other; when the panels are unfolded, each base plate unfolds to a different position with the panel, forming multiple independent mounting platforms. Each baseplate has a pre-embedded heat pipe network, with the condenser end of the heat pipes extending to the edge of the unfoldable panel and connecting to the outer surface heat dissipation surface of the panel. Signal interconnections between functional integration boards need to cross the hinge area, where highly flexible multilayer flexible circuit boards or cables are used for bridging. Because the unfoldable panel significantly increases in area after unfolding, more computing power expansion boards can be deployed, and the heat dissipation area also increases exponentially, which is beneficial for heat dissipation of high-power computing chips.

[0095] A planar satellite configuration refers to a satellite with an overall flat, plate-like structure. This configuration features two large planes (main structural surfaces) and four narrower sides, with an overall thickness much smaller than its length and width. Typical thicknesses range from 100mm to 150mm, while lengths and widths can reach 300mm to 600mm. The planar satellite configuration resembles a flat plate, with a flat internal cavity suitable for arranging multiple plate-shaped electronic components layered along its thickness. The back or sides of a planar satellite configuration typically feature large heat dissipation surfaces to facilitate heat radiation and dissipation.

[0096] A cubesat configuration refers to a satellite whose overall shape is cube-shaped or nearly cube-shaped. This configuration is typically based on standardized units (e.g., a 1U unit is 10 cm × 10 cm × 10 cm) and is commonly available in 1U, 3U, 6U, and 12U sizes. The internal space of a cubesat configuration is close to a cube, with a symmetrical structure and standardized mechanical interfaces. In this configuration, the integrated structural heat dissipation base plate can be designed as a rectangular plate that matches the internal cross-sectional dimensions of the satellite, and is laid flat on one of the satellite's inner walls. The various functional integration boards are installed vertically or parallel to the base plate.

[0097] A cylindrical satellite configuration refers to a satellite with an overall cylindrical shape. This configuration has a central axis, a circular radial cross-section, and an axial length that can be set as needed. Cylindrical satellite configurations are commonly found in spin-stabilized satellites or satellites carrying cylindrical payloads. The internal space is rotationally symmetrically distributed around the central axis. In this configuration, the integrated structural heat dissipation base plate can be designed as circular or polygonal and installed at the end or middle of the satellite. The various functional integrated boards are arranged radially around the central axis to fully utilize the cylindrical space.

[0098] Deployable satellite configurations refer to satellites that fold up during launch and unfold into larger structures after entering orbit via mechanical mechanisms. This configuration typically consists of a central module and multiple deployable panels. The deployable panels are rotatable plates attached to the central module; they fold and fit snugly against the module during launch and unfold outwards via hinges or motors after entering orbit. Electronic equipment can be mounted on the inner or outer surfaces of the deployable panels, gaining a larger mounting and heat dissipation area when the panels are unfolded. In this technical solution, an integrated structural heat dissipation base plate is mounted on the deployable panels and unfolds along with them.

[0099] In this context, the thickness direction refers to the direction perpendicular to the two main structural planes in a flat-panel satellite configuration. The main structural planes of a flat-panel satellite configuration are the two parallel planes with the largest area, such as the upper and lower surfaces. The thickness direction is the direction from the upper surface to the lower surface, or vice versa. In a flat-panel satellite configuration, the internal cavity has a small dimension (100mm to 150mm) in the thickness direction, but a larger dimension in the plane perpendicular to the thickness direction. Laying out the functional integration boards along the thickness direction means stacking multiple boards layer by layer like pages in a book, with the surface of each board perpendicular to the thickness direction, i.e., parallel to the main structural planes.

[0100] In satellite design, the main structural plane refers to the large-area plane that bears the main mechanical loads and forms the main shape of the satellite. For flat-panel satellites, the main structural planes typically refer to the back floor and top floor, which have the largest area and highest rigidity, and are used to install solar arrays, heat dissipation surfaces, payloads, and internal equipment. The main structural plane is the reference plane in the satellite structure, and the installation positions of other structural components and electronic components are all referenced to the main structural plane.

[0101] The deployable panel is a flat structural component in a deployable satellite configuration that can rotate and unfold relative to the central module. The deployable panel is typically made of honeycomb sandwich panels or carbon fiber composite panels, featuring lightweight and high rigidity. One side of the deployable panel is connected to the central module via a hinge, while the other side is folded and fixed during launch via a clamping release mechanism, and released and unfolded after entering orbit. Equipment can be installed on the inner surface of the deployable panel (the side facing the satellite's interior), while the outer surface is covered with solar cells or a heat-dissipating coating. In this technical solution, an integrated structural heat dissipation base plate is directly fixed to the inner surface of the deployable panel, providing greater installation space and heat dissipation area as the panel unfolds.

[0102] Optionally, in the above technical solution, the information processing board and the computing power expansion board share a unified processor instruction set architecture. The information processing board runs virtualization software to abstract the heterogeneous computing power resources on the computing power expansion board into a unified computing power resource pool, and realizes the scheduling of computing power resources in the unified computing power resource pool through a unified software ecosystem.

[0103] Within the flat-panel satellite configuration, the information processing board and the computing expansion board are arranged adjacently, without separate metal casings or electrical enclosures; they are directly mounted flat on an integrated structural heat dissipation base plate. The information processing board integrates a 64-bit multi-core central processing unit (CPU) supporting the ARM v8 instruction set architecture. The computing expansion board integrates a graphics processing unit (GPU) and a neural network processor (NNZ). These two dedicated computing chips also use a variant of the ARM v8 instruction set architecture, meaning they support the same integer and floating-point instruction sets as the CPU, but add extended instructions specifically for parallel vector computation and tensor operations. Because they share a unified processor instruction set architecture, the binary code compiled on the CPU can be directly executed on the general-purpose computing cores of the GPU and NNZ without instruction translation or simulation.

[0104] The information processing board and the computing expansion board are physically connected at high speed via a multi-layer flexible circuit board. The high-speed signal layer of the multi-layer flexible circuit board is specifically designed to carry differential signals for the high-speed peripheral component interconnect bus, connecting the central processing unit (CPU) of the information processing board and the graphics processing unit (GPU) and neural network processor (NNZ) of the computing expansion board within the same high-speed bus topology. The CPU directly accesses the chip registers, video memory, and internal memory of the computing expansion board via the high-speed bus, achieving low-latency data exchange.

[0105] During the boot process, the information processing board first loads the underlying operating system kernel. After the operating system kernel completes basic hardware initialization, it starts the virtualization software. The virtualization software runs on the central processing unit as a kernel module or an independent virtual machine monitor. The virtualization software first scans all devices on the high-speed peripheral interconnect bus, enumerating the graphics processors and neural network processors on the computing power expansion board. For each enumerated heterogeneous computing chip, the virtualization software reads its device configuration space to obtain parameters such as the number of computing units, instruction set characteristics, memory capacity, and cache size.

[0106] Next, the virtualization software performs abstraction operations. For the graphics processing unit (GPU), the virtualization software abstracts its 256 stream processor cores into 256 logical computing units (Logical Computation Units), each with the same floating-point arithmetic capability. For the neural network processor, the virtualization software abstracts its 16 tensor computing units into 16 Logical Computation Units, each with the same matrix multiplication-addition throughput. For the CPU of the information processing board itself, the virtualization software also abstracts its 8 processor cores into 8 Logical Computation Units. The virtualization software establishes a unified computing resource pool for all these Logical Computation Units. This unified computing resource pool is represented in the software as a resource management structure containing an array of length 280 (256+16+8). Each element of the array corresponds to a Logical Computation Unit, recording information such as the unit's type identifier (CPU core, stream processor core, or tensor unit), physical base address, current allocation flag, and occupying process identifier. The virtualization software also maintains a linked list of free units, linking all unallocated Logical Computation Units together.

[0107] A unified software ecosystem is built on the ARM v8 instruction set architecture. Ground developers use the same GCC compilation toolchain to write code for all functional modules on the satellite. For example, the matrix inversion algorithm in the attitude control module is written as a standard C language function and compiled into ARM v8 instruction code using a unified compiler. This instruction code can be loaded onto the central processing unit of the information processing board for execution, or, after minor adaptation, onto the graphics processing unit of the computing power expansion board, utilizing the parallel stream processor cores of the graphics processing unit for accelerated execution. The virtualization software provides a unified application programming interface, including interfaces for requesting computing resources, submitting tasks, waiting for synchronization, and releasing resources. The underlying implementations of these interfaces are adapted to different hardware: when an application calls the computing resource request interface to request vector-parallel computing resources, the virtualization software prioritizes selecting the stream processor logic unit of the graphics processing unit from the unified computing resource pool; when requesting tensor computing, it prioritizes selecting the tensor logic unit of the neural network processor.

[0108] During runtime, the virtualization software on the information processing board continuously receives computing power requests from the space management module, attitude control module, and telemetry and communication module. The scheduler within the virtualization software selects suitable logical computing units from the available units in the unified computing resource pool and allocates them to the requester according to priority and resource matching strategies. After allocation, the scheduler returns the corresponding physical address and access permissions to the requesting module. The requesting module, through the runtime library provided by the virtualization software, transmits the computing task code and data to the corresponding physical computing power expansion board via a high-speed bus and initiates execution. After execution, the module calls the resource release interface, and the scheduler marks the corresponding logical computing unit as available and returns it to the unified computing resource pool.

[0109] Because the information processing boards and computing power expansion boards share a unified processor instruction set architecture, the computational code of functional modules can run on different computing chips without recompiling. For example, the same Fast Fourier Transform code can be executed once on the central processing unit, and then the scheduler loads the same binary code onto the graphics processing unit for repeated execution, without requiring any modification to the code itself. The unified software ecosystem also includes unified debugging and performance analysis tools, allowing ground testers to monitor the load of the unified computing resource pool, the utilization rate of each logical computing unit, and the latency of task execution using a single software suite.

[0110] Through the above implementation process, the information processing board and the computing power expansion board maintain compatibility at the instruction set level. The virtualization software running on the information processing board abstracts the graphics processor and neural network processor on the computing power expansion board into logical computing units within a unified computing power resource pool, and utilizes a unified compiler, runtime library, and scheduler to achieve unified scheduling and management of computing power resources in the pool. Any functional module developed in accordance with the unified software ecosystem can transparently access and invoke all heterogeneous computing power resources within the pool.

[0111] The processor instruction set architecture (IPA) is the agreed-upon interface specification between the processor and software, defining the instruction types, register structures, memory access modes, and exception handling mechanisms supported by the processor. IPA serves as the boundary between software and hardware; software operating under the same IPA can run on different processors supporting that architecture without modification. Common IPA architectures include ARM, RISC-V, and x86. In this technical solution, the main processor on the information processing board and the dedicated computing chips (such as graphics processors and neural network processors) on the computing expansion board share a unified processor instruction set architecture. This means that these chips adhere to the same underlying instruction specifications, allowing compiled program code to be seamlessly executed or migrated between the two.

[0112] The virtualization software is a layer of software running on the main processor of the information processing board, responsible for abstracting and isolating physical hardware resources. Through a virtual machine monitor or container runtime environment, the virtualization software virtualizes the underlying physical processor cores, memory, input / output devices, and other resources into multiple independent virtual instances. Each virtual instance can run an independent operating system or bare-metal application. In this technical solution, the virtualization software running on the information processing board is specifically used to abstract heterogeneous computing resources (such as stream processors in a graphics processor and tensor units in a neural network processor) on the computing power expansion board into logical computing units, so that upper-layer software does not need to be aware of the physical location and hardware details of these resources.

[0113] Abstraction, in this context, refers to the process by which virtualization software shields the differences in underlying hardware, transforming different types of physical computing resources into a unified logical interface. Specifically, the virtualization software creates a device driver encapsulation layer for each type of hardware resource. This layer provides a standardized application programming interface (API) upwards and handles interactions with the real hardware, such as register read / write, memory mapping, and interrupt handling. Upper-layer functional modules (such as the space management module) access computing resources through this standardized interface without needing to know whether a graphics processor or a neural network processor is being used. Abstraction makes heterogeneous computing resources appear as homogeneous computing units to the software.

[0114] A unified computing resource pool refers to a collection of heterogeneous computing resources, such as the CPU computing power on information processing boards and the GPU and neural network processors on computing expansion boards, integrated into a single logical resource set after virtualization software abstraction. Within this unified pool, all computing resources are assigned a unified identifier and scheduling unit, for example, at the granularity of "computing cores" or "computing units." The pool's capacity is equal to the weighted sum of the computing capabilities of all heterogeneous computing resources within it. The unified computing resource pool maintains a resource mapping table that records the type, current allocation status, and ownership information of each logical computing unit.

[0115] A unified software ecosystem refers to a complete software system built on the same instruction set architecture and the same software development toolchain. This unified software ecosystem includes compilers, assemblers, linkers, runtime libraries, debugging tools, and application frameworks. In this technical solution, the information processing board and the computing power expansion board share a unified processor instruction set architecture, allowing developers to use the same compiler (e.g., the GCC toolchain for ARM or RISC-V) to write code for both boards. A unified software ecosystem also means that upper-layer applications (such as attitude control algorithms and AI inference models) can run on the central processing unit of the information processing board, or be compiled and loaded onto the graphics processing unit or neural network processor of the computing power expansion board for execution, without modifying the core algorithm logic of the code.

[0116] In virtualization software, scheduling refers to the process by which the resource scheduler selects suitable computing units from a unified computing resource pool and allocates them to requesters based on the computing power requests of functional modules, and then reclaims the resources after use. Scheduling needs to consider factors such as resource type matching (e.g., matrix operations are preferentially allocated to graphics processors or neural network processors), priority, load balancing, and real-time constraints. During runtime, the scheduler maintains a ready queue and a resource free list, making allocation decisions according to preset scheduling algorithms (such as priority preemption and fair sharing).

[0117] Optionally, in the above technical solution, the computing power expansion board integrates at least one dedicated computing power chip among a graphics processor, a neural network processor, and a field-programmable gate array. The dedicated computing power chip is interconnected with the information processing board through a high-speed bus, and the dedicated computing power chip dynamically loads artificial intelligence inference models or data processing algorithms according to task requirements.

[0118] Inside the flat-panel satellite configuration, the computing power expansion board is a rectangular printed circuit board, its length and width determined by the satellite's internal space, for example, 150mm × 120mm. The computing power expansion board does not have a separate metal casing or electrical enclosure; its back is directly mounted flat on a localized heat dissipation platform on the integrated structural heat dissipation base plate via a thermally conductive interface material. Multiple electronic components are soldered onto the front (top surface) of the computing power expansion board, including at least one dedicated computing chip. Depending on the satellite mission, the dedicated computing chip can be one or more of a graphics processor, a neural network processor, or a field-programmable gate array (FPGA). For example, in a computing satellite requiring extensive image recognition tasks, the computing power expansion board integrates both a graphics processor and a neural network processor; in another satellite requiring flexible handling of multiple communication protocols, the computing power expansion board integrates an FPGA.

[0119] The graphics processing unit (GPU) uses a ball grid array (BGA) package, with hundreds of solder balls on the bottom, which are soldered to corresponding pads on the computing expansion board using a reflow soldering process. The top of the GPU package is flat, used to attach thermal interface material. Neural network processors and field-programmable gate arrays (FPGAs) also use similar packaging and soldering methods. The placement of all dedicated computing chips on the computing expansion board is determined by the thermal design, typically located in the central area of ​​the board or near the edge, ensuring that each chip has a corresponding local heat dissipation bump on the integrated thermal management baseplate.

[0120] The dedicated computing chip is interconnected with the information processing board via a high-speed bus. In this technical solution, the high-speed bus is specifically a peripheral component interconnect high-speed bus, configured with four channels, each with a transmission rate of 16GB / s. From a physical connection perspective, the central processing unit on the information processing board outputs four sets of high-speed differential signal pairs (each set includes a pair of transmit differential lines and a pair of receive differential lines). These differential signal lines reach the interface pads at the edge of the information processing board via printed lines. One end of a multilayer flexible circuit board is soldered to the interface pads of the information processing board. The high-speed signal layer inside the multilayer flexible circuit board precisely routes these differential pairs, maintaining a differential impedance of 100Ω. The other end of the multilayer flexible circuit board extends to the edge pads of the computing expansion board, connecting to the peripheral component interconnect high-speed bus interface pins of the dedicated computing chip. To ensure signal quality, the distance between the information processing board and the computing expansion board is controlled within 20mm, and the length of the multilayer flexible circuit board does not exceed 30mm, thereby reducing signal attenuation and jitter.

[0121] In addition to physical connections, the high-speed bus logically enables the central processing unit (CPU) of the information processing board to control the dedicated computing chips through address mapping and direct memory access mechanisms. During startup, the operating system of the information processing board scans the high-speed bus interconnecting peripheral components, discovers the dedicated computing chips on the computing expansion board, and allocates a memory address space for each chip. The CPU can access the configuration registers and internal memory of the dedicated computing chips by reading and writing to these address spaces without requiring additional intermediate translation.

[0122] Dedicated computing chips dynamically load artificial intelligence inference models or data processing algorithms according to task requirements. The specific steps to achieve dynamic loading are as follows: First, all the pre-trained AI inference model files and the program code or hardware configuration bitstreams of various data processing algorithms required for use were pre-installed in a large-capacity non-volatile flash memory on the information processing board before satellite launch. Each model or algorithm file has a unique identifier and version number. For example, the AI ​​inference model file for cloud detection is named "cloud_detection_v2.npu", and the low-density parity-check code encoding algorithm file for high-speed data transmission is named "ldpc_encoder_v1.bit".

[0123] During satellite operation in orbit, the satellite management module running on the information processing board makes decisions based on the current mission scenario. For example, when the local area issues an instruction to the satellite to perform on-orbit target identification on optical images of a certain area, the satellite management module parses the instruction and determines the target identification artificial intelligence inference model that needs to be loaded. The satellite management module sends a request to the computing power scheduling middleware through the application programming interface of the virtualization software, requesting that the specified model be loaded into the neural network processor on the computing power expansion board.

[0124] The computing power scheduling middleware first checks the current state of the neural network processor. If the neural network processor is idle, the middleware locks it to prevent interference from other tasks. Then, the middleware sends a loading preparation instruction to the neural network processor via the high-speed bus, informing it of the size and starting address of the model to be loaded. Subsequently, the central processing unit (CPU) directly reads the "target_recognition_v1.npu" model file from flash memory and streams the model data to the on-chip memory of the neural network processor via direct memory access. During data transmission, the effective data bandwidth on the high-speed bus can reach 12GB / s, and a 20MB model can be transferred within 13ms. After the transfer is complete, the CPU sends a loading completion and execution start instruction to the neural network processor. The neural network processor parses the weights and structural information in the model file, configures each tensor unit into the corresponding convolutional, pooling, and fully connected layer computational pipelines, and then begins executing inference operations.

[0125] For Field Programmable Gate Arrays (FPGAs), the dynamic loading process is slightly different. When the ground needs to change the data transmission modulation scheme, the satellite management module sends a command to load a new modulation and demodulation algorithm. The computing power scheduling middleware reads the corresponding FPGA reconfiguration bitstream file (e.g., "qpsk_modem_v2.bit") from flash memory. The central processing unit (CPU) writes the bitstream frame by frame into the FPGA's configuration access port via a high-speed bus. After receiving the bitstream, the FPGA's internal reconfiguration controller dynamically changes the configuration of its internal logic blocks and interconnect resources, replacing the original demodulation circuit with the new modulation and demodulation circuit without affecting other running functional logic. The entire reconfiguration process can be completed within tens of milliseconds, after which the FPGA immediately processes the input signal data according to the new algorithm.

[0126] For graphics processing units (GPUs), dynamically loading AI inference models employs a kernel code loading method. The kernel code of the model, compiled by the ground software (usually in PTX or binary form), is stored in flash memory. The information processing board calls the GPU's driver to copy the kernel code into the GPU's instruction cache and allocate input / output buffers. Subsequently, the central processing unit (CPU) starts the GPU kernel, and hundreds of stream processor cores within the GPU execute the computational tasks defined by the model in parallel.

[0127] Because dedicated computing chips are interconnected with information processing boards via high-speed buses, data transmission latency is as low as microseconds, making the dynamic loading process virtually transparent to upper-layer tasks. The satellite management module can flexibly switch models based on task queues: for example, loading a ship detection model when the satellite flies over oceans and a farmland classification model when it flies over land; the same neural network processor can execute different AI inference tasks sequentially under time-division multiplexing. Similarly, field-programmable gate arrays (FPGAs) can load encryption algorithms during communication idle periods and demodulation / decoding algorithms before communication windows, enabling on-demand reconfiguration of hardware resources.

[0128] Through the above implementation process, the dedicated computing chips such as graphics processors, neural network processors, or field-programmable gate arrays integrated on the computing power expansion board achieve low-latency, high-bandwidth physical interconnection with the information processing board through a high-speed bus interconnecting peripheral components. Simultaneously, utilizing the non-volatile memory and scheduling software on the information processing board, these dedicated computing chips can dynamically load different artificial intelligence inference models or data processing algorithms according to task requirements during on-orbit operation, thereby achieving flexible reuse of hardware computing resources and task adaptability.

[0129] A graphics processing unit (GPU) is an integrated circuit chip specifically designed for parallel processing of image data and general-purpose computing. Compared to a traditional central processing unit (CPU), a GPU contains hundreds or thousands of streamlined computing cores, enabling it to perform a large number of identical arithmetic operations simultaneously. It is particularly well-suited for data-parallel tasks such as matrix multiplication, convolution, and fast Fourier transform. GPUs typically exist as independent packaged chips, soldered onto the printed circuit board of a computing expansion board, with thermal interface material and local heat dissipation bumps that can be applied to them. In this technical solution, the GPU is used to accelerate convolutional neural network calculations in artificial intelligence inference and matrix operations in attitude control.

[0130] The neural network processor (NNZ) is a dedicated integrated circuit chip designed specifically for deep learning algorithms. Internally, it contains numerous multiply-accumulate arrays, tensor computation units, and high-bandwidth on-chip memory, enabling efficient execution of operations such as convolution, pooling, fully connected layers, and activation functions within neural networks. Compared to graphics processing units (GPUs), NNZs achieve higher energy efficiency under low power consumption conditions. NNZs are also packaged as chips and mounted on computing expansion boards, typically exhibiting high heat flux density, requiring cooling through localized heat dissipation bumps. In this technical solution, the NNZ is used to execute onboard artificial intelligence inference models, such as tasks like target recognition, cloud detection, and anomaly detection.

[0131] Field-Programmable Gate Arrays (FPGAs) are reconfigurable hardware chips. Internally, an FPGA contains numerous configurable logic blocks, digital signal processing units, block random access memory (BRAM), and programmable input / output interfaces. Users can program the FPGA using a hardware description language to configure it as any digital logic circuit. FPGAs can be dynamically partially reconfigured during runtime, meaning that some logic functions can be changed without interrupting overall operation. FPGAs are suitable for implementing signal processing protocols requiring high throughput, low latency, and flexible customization. In this technical solution, the FPGA can dynamically load different data processing algorithms, such as high-speed serial demodulation, channel coding / decoding, and encryption / decryption.

[0132] Dedicated computing chips refer to integrated circuit chips specifically designed and optimized for specific types of computing tasks. Unlike general-purpose central processing units (CPUs), dedicated computing chips are architecturally customized for a particular type of algorithm (such as parallel vector computing, deep learning inference, and programmable logic operations) to achieve higher computing efficiency, lower power consumption, and smaller chip area. Graphics processors, neural network processors, and field-programmable gate arrays (FPGAs) all fall under the category of dedicated computing chips. In this technical solution, the computing expansion board integrates at least one or more of the above three types of chips to provide satellites with diverse dedicated computing capabilities.

[0133] High-speed buses are physical connection standards used for transmitting large amounts of data between chips and between boards. They typically use differential signal pairs for serial or parallel transmission, supporting data rates from megabits per second to gigabits per second. Common high-speed bus protocols include Peripheral Component Interconnect (PCI) High-Speed ​​Bus, Ethernet, and Serial Fast Input / Output (SHEO). In this technical solution, the dedicated computing chip interconnects with the information processing board via a high-speed bus, specifically the PCI High-Speed ​​Bus. Its physical layer is implemented using differential signal pairs on a multi-layer flexible circuit board, and its protocol layer supports memory-mapped input / output and direct memory access, allowing the central processing unit of the information processing board to directly access the registers and memory space of the dedicated computing chip.

[0134] Dynamic loading refers to the process of loading AI inference model files or data processing algorithm bitstreams stored in non-volatile memory into the execution unit of a dedicated computing chip in real time, without restarting the system or causing a power outage, based on changes in current mission requirements during satellite operation. Dynamic loading differs from static configuration; it allows the same dedicated computing chip to execute different algorithms at different times, thus achieving time-division multiplexing of hardware resources. Dynamic loading is initiated by the scheduling software on the information processing board, which transmits model parameters or configuration files to a designated storage area within the dedicated computing chip via a high-speed bus, triggering the chip's reconfiguration or loading mechanism.

[0135] Artificial intelligence (AI) inference models refer to pre-trained mathematical model files used for predicting or classifying new data. AI inference models typically contain weight parameters, bias parameters, activation function configurations, and model structure descriptions for multi-layered neural networks. Common AI inference models include convolutional neural networks, recurrent neural networks, and transformer models. On satellites, AI inference models are used to perform intelligent tasks such as on-orbit target recognition, image segmentation, data compression, and anomaly detection. The model files are stored in binary format in the flash memory of information processing boards or computing power expansion boards, and are dynamically loaded into graphics processors or neural network processors to perform inference operations when needed.

[0136] Data processing algorithms refer to software programs or hardware configurations that perform operations such as transformation, encoding, filtering, compression, demodulation, and encryption on raw data acquired by satellites (such as remote sensing images, telemetry and control data, and payload data). Data processing algorithms can be parallel processing kernel functions running on a graphics processing unit (GPU) or hardware logic bitstreams configured with field-programmable gate arrays (FPGAs). Common data processing algorithms include Fast Fourier Transform (FFT), Discrete Cosine Transform (DCT), Wavelet Transform (WCT), Reed-Solomon coding, Low-Density Parity-Check (LDPC) decoding, and Advanced Encryption Standard (AES) encryption / decryption. In this technical solution, the data processing algorithm is dynamically loaded onto a dedicated computing chip for execution based on the current communication link status or payload operating mode.

[0137] Optionally, in the above technical solution, all functional integration boards also include an energy management board. The energy management board integrates a solar cell array power regulation unit, a battery charging and discharging management unit, a load power distribution unit, and a power consumption monitoring unit. The energy management board collects power consumption data from the information processing board, the computing power expansion board, and other functional integration boards in real time, and participates in the unified power consumption budget management of the entire satellite based on the collected power consumption data.

[0138] Within the flat-panel satellite configuration, all functional integration boards are directly mounted on the integrated structural heat dissipation base plate without independent metal housings or electrical enclosures. Among these boards, the energy management board is a crucial component. The energy management board is a rectangular printed circuit board, with its length and width determined by the satellite's internal space (e.g., 200mm × 150mm), and a thickness ranging from 1.6mm to 2.0mm. The back of the energy management board directly contacts the localized heat dissipation protrusions on the integrated structural heat dissipation base plate via a thermally conductive interface material, ensuring rapid heat transfer from the power devices on the board to the base plate and heat pipe network. The energy management board features multiple connectors: an input connector for connecting the solar array cables, a battery connector for connecting the battery pack, and a set of output connectors for distributing power to other functional integration boards. Additionally, the energy management board has multiple screw mounting holes for secure mounting to the base plate.

[0139] On the surface of the printed circuit board of the energy management board, four main units are arranged according to functional areas: solar cell array power regulation unit, battery charge and discharge management unit, load power distribution unit, and power consumption monitoring unit.

[0140] The solar array power conditioning unit is located on the side of the energy management board near the solar array input connector. This unit consists of four independent power conditioning circuits, each corresponding to a set of solar array wings. At the core of each power conditioning circuit is a synchronous buck maximum power point tracking controller chip, paired with two high-power metal-oxide-semiconductor field-effect transistors, a power inductor, and multiple ceramic capacitors. These components are connected via wide copper traces, forming a power loop capable of handling currents exceeding 5A. The output of the solar array power conditioning unit is connected to a common primary bus, whose voltage is stabilized at 28V DC. Multiple large-capacity capacitors are connected in parallel on the bus to filter switching ripple and provide instantaneous energy buffering.

[0141] The battery charge / discharge management unit is located in the middle area of ​​the energy management board, near the battery pack connector. This unit consists of two parts: a charging circuit and a discharging circuit. The charging circuit uses a four-phase synchronous buck topology, with input taken from the primary bus and output connected to the battery pack. The charging circuit controller chip performs three-stage charging based on battery voltage and temperature: trickle charging, constant current charging, and constant voltage charging. The discharging circuit uses a synchronous boost topology, boosting the battery pack voltage (typically 20V to 32V) to 28V and feeding it back to the primary bus. The discharging circuit automatically starts when the bus voltage falls below a set threshold to replenish the lost power. The battery charge / discharge management unit also integrates battery protection functions: it immediately cuts off the charging and discharging path when overvoltage, undervoltage, overcurrent, or overtemperature is detected.

[0142] The load power distribution unit is located on the output side of the energy management board, near the output connector array. This unit comprises eight independent power distribution channels, each consisting of a solid-state power switch, a current-sensing resistor, and a fast-blow fuse connected in series. The solid-state power switch receives an enable signal from the energy management board's microcontroller and can independently turn each channel on or off. The voltage drop across the current-sensing resistor is sent to the power consumption monitoring unit. The output of the load power distribution unit is connected to the power distribution layer of a multilayer flexible circuit board via an output connector on the energy management board. The power distribution layer in the multilayer flexible circuit board uses wide copper foil traces (3mm to 5mm wide, 35 to 70 micrometers thick) to transmit the 28V primary bus and grounding loop to other functional integration boards such as the information processing board, computing power expansion board, and measurement and control data transmission RF board. After receiving power, each functional integration board generates different voltages (e.g., 5V, 3.3V, 1.8V, 0.9V) required by its own secondary power conversion circuitry.

[0143] The power consumption monitoring units are distributed across the entire energy management board, with each power distribution channel corresponding to an independent monitoring front-end. The core of the power consumption monitoring unit is an eight-channel high-side current / power monitoring chip, which connects to the microcontroller on the energy management board via an integrated circuit bus. A precise milliohm-level current sampling resistor (10mΩ to 50mΩ, 1% accuracy) is connected in series on the positive output line of each power distribution channel. The monitoring chip continuously measures the differential voltage across the sampling resistor to calculate the current value; simultaneously, it measures the voltage of the channel to ground. An internal multiplier in the monitoring chip multiplies the voltage and current to obtain the power value, and converts the voltage, current, and power parameters into digital quantities, storing them in an internal register.

[0144] The energy management board integrates a low-power microcontroller, which serves as the board's local processor. The microcontroller communicates with the power monitoring chips via an integrated circuit bus or serial peripheral interface bus and executes a real-time data acquisition program. An internal periodic timer with an interrupt period of 10ms is set within the microcontroller. Upon each interrupt, the microcontroller sequentially sends read commands to eight power monitoring chips, reading the voltage, current, and power values ​​of the corresponding power distribution channel from the information processing board, the corresponding channel from the computing power expansion board, and the corresponding channel from other functional integration boards (such as the measurement and control data transmission RF board). The read time for each channel is less than 1ms, thus a complete acquisition is completed within 8ms. The acquired power consumption data is timestamped in real time and stored in a circular buffer within the microcontroller, with a buffer capacity sufficient to hold at least the most recent 100 data acquisitions.

[0145] Meanwhile, the energy management board communicates with the information processing board through a medium-speed control layer on a separate multi-layer flexible circuit board. Every 100ms, the microcontroller packages the average power consumption data (including average current and average power of each channel) collected in the last 10 data acquisitions into a data frame and sends it to the satellite management function module on the information processing board via the integrated circuit bus or controller area network bus. After receiving this power consumption data, the information processing board updates the overall satellite power consumption database maintained by the satellite management function module.

[0146] The unified power consumption budget management process for the entire satellite is as follows: The satellite management module on the information processing board maintains two key values ​​in real time: the current total power generation of the entire satellite and the current total power consumption of the entire satellite. The current total power generation of the entire satellite is calculated by adding the output power of the solar array power regulation unit reported by the energy management board through another data channel to the discharge power of the battery charge / discharge management unit (discharge is positive, charging is negative). The current total power consumption of the entire satellite is obtained by summing the power data of all load distribution channels reported by the energy management board. The satellite management module calculates the power difference every 100ms: the power difference equals the total power generation minus the total power consumption.

[0147] If the power difference is positive and greater than a preset positive threshold, it indicates that power generation is sufficient. The star management function module sends an instruction to the computing power scheduling middleware to allow the workload of the computing power expansion board to be increased, such as loading larger and more complex neural network models or increasing the number of parallel tasks.

[0148] If the power difference is negative and its absolute value exceeds a preset negative threshold, it indicates insufficient power generation and that the battery reserves are being depleted. The space management module first checks the battery's state of charge (SOC). If the SOC is above 50%, the status quo is maintained temporarily, but the underpower event is recorded. If the SOC is below 50%, the space management module initiates power reduction measures: it sends a frequency reduction command to the computing power scheduling middleware, requesting a reduction in the operating frequency of the information processing board and computing power expansion board, or suspending low-priority inference tasks; simultaneously, it sends a command to the load power distribution unit, temporarily shutting down non-critical loads (such as backup telemetry and control receivers and some load sensors) through the microcontroller of the energy management board. Once the power difference returns to positive, computing power performance and load power supply are gradually restored.

[0149] The power consumption data collected in real time by the energy management board is also used for fault prediction. If the power consumption of a certain functional fusion board suddenly exceeds its normal operating range (for example, the power of the computing power expansion board jumps from 20 watts to 80 watts and lasts for more than 5 seconds), the power consumption monitoring unit detects the anomaly and immediately sends an interrupt to the microcontroller. The microcontroller sends an overpower alarm to the information processing board through the data channel. After receiving the alarm, the space management function module can command the load power distribution unit to immediately disconnect the power supply channel of the board, record the fault log, and wait for ground instructions or automatically attempt to power it back on.

[0150] Through the above implementation process, the energy management board integrates a solar array power regulation unit, a battery charging and discharging management unit, a load power distribution unit, and a power consumption monitoring unit, all of which work collaboratively. The energy management board collects voltage, current, and power data from the information processing board, computing power expansion board, and other integrated functional boards in real time at 10ms intervals, and reports this power consumption data to the satellite management module on the information processing board. The satellite management module uses this data to perform unified power budget management for the entire satellite, dynamically adjusting the computing power scheduling strategy and load access status based on the real-time balance between power generation and consumption, thereby ensuring the safe and efficient operation of the computing satellite with limited power resources.

[0151] The energy management board is a functional integration board specifically responsible for the generation, storage, distribution, and monitoring of the entire satellite's power. Like the information processing board and computing power expansion board, the energy management board does not have a separate metal casing or electrical box structure. Its back is directly mounted on a localized heat dissipation platform on the integrated structural heat dissipation base plate via a thermally conductive interface material. The energy management board is a rectangular printed circuit board, on which circuits for power regulation, charge / discharge management, power distribution, and monitoring are soldered. One end of the board connects to the solar array and battery pack via a cable or flexible circuit board, while the other end supplies operating voltage to all other functional integration boards through the power distribution layer of a multi-layer flexible circuit board.

[0152] The solar array power regulation unit is an electronic circuit module integrated on the energy management board, used to convert the electrical energy generated by the solar array into a stable voltage required by the satellite. The voltage and current output by the solar array fluctuate drastically under sunlight, varying with the angle of illumination, temperature, and load. The solar array power regulation unit employs maximum power point tracking (MPPT) technology to adjust the operating point in real time to maximize the output power of the solar array, while simultaneously converting the fluctuating input into a stable primary bus voltage (e.g., 28V DC). This unit mainly consists of power MOSFETs, inductors, capacitors, and a pulse width modulation controller chip, located on the energy management board near the solar array input interface.

[0153] The battery charge / discharge management unit is an electronic circuit module integrated on the energy management board, responsible for controlling the charging and discharging of the satellite's battery pack. During sunlight exposure, this unit charges the battery pack with excess energy generated by the solar array power regulation unit according to a preset charging curve (such as constant current / constant voltage). During shadow periods, this unit boosts or deboosts the battery pack's energy to replenish the primary bus, ensuring uninterrupted power supply to the entire satellite. The battery charge / discharge management unit includes a charging switch, a discharging switch, a current sensing resistor, a voltage detection divider network, and protection circuits (overcharge protection, over-discharge protection, and temperature protection). This unit works in conjunction with the solar array power regulation unit to maintain the primary bus voltage within allowable limits.

[0154] The load power distribution unit is a switch array and current protection circuit integrated on the energy management board, used to distribute the primary bus voltage to various functional integration boards and other load devices on the satellite. The load power distribution unit contains multiple independent power distribution channels, each equipped with a solid-state power switch (e.g., a metal-oxide-semiconductor field-effect transistor) and a current-limiting protector. The output of each channel is connected to the power input of the corresponding functional integration board (e.g., an information processing board, a computing power expansion board, or a telemetry and data transmission RF board) via a connector on the energy management board or a power distribution layer in a multi-layer flexible circuit board. The load power distribution unit can independently turn each load channel on or off according to commands, achieving power-on timing control and fault isolation.

[0155] The power consumption monitoring unit is a multi-channel voltage and current measurement circuit integrated on the energy management board, used to monitor the output voltage and current of each power distribution channel in real time. The power consumption monitoring unit typically uses a dedicated power monitoring chip or a high-precision analog-to-digital converter in conjunction with shunt resistors. Each monitoring channel independently measures the supply voltage and current values ​​of the corresponding functional fusion board and converts these analog quantities into digital quantities. The power consumption monitoring unit transmits the digitized voltage, current, and calculated power values ​​to the microcontroller on the energy management board via the on-board integrated circuit bus or other low-speed serial bus.

[0156] Power consumption data refers to quantified values ​​characterizing the power consumption of the integrated functional boards, including instantaneous voltage (V), instantaneous current (A), and instantaneous power (W). Power consumption data may also include cumulative energy consumption over a period of time (W·h). For each integrated functional board, such as the information processing board and the computing power expansion board, the power consumption monitoring unit generates independent power consumption data. This data reflects the energy consumption characteristics of each board under different operating modes (idle mode, full-load computing mode, standby mode) and serves as the fundamental input for overall satellite power consumption budget management.

[0157] The unified power consumption budget management for the entire satellite refers to a management method that aggregates the real-time power consumption of all power-consuming devices on the satellite (including all functional integration boards, attitude actuators, telemetry and communication RF front-ends, heaters, etc.), compares it with the satellite's currently available power generation capacity (solar array output power plus available battery discharge power), and dynamically adjusts the operating status or computing power scheduling strategy of each device based on the comparison results. The unified power consumption budget management for the entire satellite is jointly performed by the microcontroller on the energy management board and the satellite management function module on the information processing board. The energy management board is responsible for providing real-time power consumption data, while the information processing board is responsible for running the power consumption budget algorithm and issuing control commands.

[0158] This invention eliminates the independent single-unit housings and electrical boxes of each functional subsystem in traditional satellite electronic systems. It physically reconstructs the entire satellite electronic system into several functionally integrated boards. All functionally integrated boards are directly laid flat on the same integrated heat dissipation base plate of the flat-panel satellite configuration. There are no housings, electrical box panels, or independent mounting brackets between the functionally integrated boards and the integrated heat dissipation base plate, achieving a physical architecture reconstruction from a "two-level structure of housing-board" to a "one-level structure of base plate-board." Figure 2 As shown, the satellite adopts a flat-panel satellite configuration. The overall thickness is controlled between 100-150mm. All functional integration boards are laid flat along the satellite's thickness direction, with the board planes parallel to the main structural surface of the flat-panel satellite configuration. All boards are mechanically fixed and thermally conducted through an integrated structural heat dissipation base plate. The back of the boards directly contacts the base plate's localized heat dissipation protrusions via a thermally conductive interface material, forming the shortest heat dissipation path.

[0159] Figure 2 This invention demonstrates the flat-panel satellite configuration (i.e., Figure 2 The "satellite body" in the text, solar cell array (i.e. Figure 2 The solar panels ("solar sails") are symmetrically arranged on both sides of the flat-panel satellite configuration to receive solar energy and convert it into electricity during orbit. The overall shape of the flat-panel satellite configuration is flat and plate-like, with an overall thickness controlled between 100 mm and 150 mm. Its hollow interior is used to install electronic systems. Inside the flat-panel satellite configuration, an integrated structural heat dissipation base plate is fixedly installed on the side closest to the satellite's heat dissipation surface. The upper surface of this base plate has multiple local heat dissipation protrusions. All functional integration boards (including information processing boards, computing power expansion boards, telemetry and data transmission RF boards, energy management boards, and interface boards) do not have independent metal shells or electrical enclosures. Their backs are directly laid flat on the integrated structural heat dissipation base plate through a thermally conductive interface material, and the surface of each functional integration board remains parallel to the main structural surface of the flat-panel satellite configuration. The functional integration boards are interconnected and power distributed through multi-layer flexible circuit boards. The integrated structural heat dissipation base plate has a pre-embedded heat pipe network, which is thermally connected to local heat dissipation bosses to transfer the heat generated by each functional integrated board to the heat dissipation surface of the flat-panel satellite configuration. Through this arrangement, Figure 2 The flat-panel satellite configuration shown provides a flat physical space for the board-level integrated electronic system architecture, realizing the three-in-one integration of structure, heat dissipation and electronics.

[0160] like Figure 3As shown, all functional integration boards have eliminated independent metal casings and electrical enclosures, and are directly mounted flat on the same integrated structural and heat dissipation base plate. Located at the bottom layer, this integrated base plate serves as the sole mechanical mounting base and unified heat dissipation base for all functional integration boards. It is made of high thermal conductivity aluminum alloy or carbon fiber composite material, with an internal heat pipe network. The upper surface features localized heat dissipation protrusions precisely corresponding to the locations of high heat flux density chips on each board. This base plate simultaneously bears the structural load-bearing function of the satellite and the overall heat dissipation function, achieving a three-in-one integration of structure, heat dissipation, and electronics. On the upper surface of the integrated structural and heat dissipation base plate, the following boards are sequentially mounted: energy management board, information processing board, three computing power expansion boards, telemetry and data transmission RF board, and interface board. The information processing board, serving as the central hub for the satellite's computing power scheduling, connects to three computing power expansion boards via a high-speed bus. The dedicated computing chips (graphics processor, neural network processor, and field-programmable gate array) of these expansion boards are integrated into a unified computing resource pool. The information processing board also connects to the telemetry, tracking, and command (TT&C) data transmission RF board, enabling satellite-to-ground communication and data transmission. The energy management board supplies power to all other boards via power distribution lines and collects real-time power consumption data from each board for overall satellite power budget management. The interface board is responsible for connecting to external satellite devices or payloads. All adjacent boards are interconnected via multi-layer flexible circuit boards for signal interconnection and power distribution. Figure 3 The multiple connecting lines represent the multi-layer flexible circuit board connected between the energy management board and the first computing power expansion board, between the first computing power expansion board and the information processing board, between the information processing board and the second computing power expansion board, between the second computing power expansion board and the third computing power expansion board, between the third computing power expansion board and the measurement and control data transmission RF board, and between the information processing board and the interface board. The data flow path is as follows: After receiving ground commands, the telemetry, tracking, and command (TT&C) data transmission RF board transmits them to the information processing board via a multi-layer flexible circuit board. The information processing board parses the commands and uses virtualization technology to schedule dedicated computing chips on the computing power expansion board from a unified computing resource pool to execute artificial intelligence inference or data processing algorithms. The calculation results are then aggregated by the information processing board and transmitted back to the ground via the TT&C data transmission RF board. Simultaneously, the energy management board supplies power to each board through the power distribution layer in the multi-layer flexible circuit board and reads the voltage and current data of each board in real time through the medium-speed control layer, reporting the power consumption information to the information processing board. The latter then dynamically adjusts the computing power scheduling strategy to maintain the overall satellite power consumption balance. The back of all functional integration boards is in direct contact with localized heat dissipation protrusions on the integrated structural heat dissipation base plate via a thermally conductive interface material. Heat is transferred to the satellite's heat dissipation surface through the internal heat pipe network of the base plate, thus forming a complete integrated electronic architecture.

[0161] Interface boards serve as transitional circuit boards connecting the satellite's internal functional fusion boards to external devices or signals. These interface boards do not have independent metal housings or electrical enclosures; their backs are directly mounted on an integrated heat dissipation base plate using a thermally conductive interface material, and they interconnect with the information processing boards via multi-layer flexible circuit boards. The main functions of the interface boards include: level conversion, signal conditioning, interface protocol adaptation, and filtering / isolation of external signals of different levels and protocols from satellite external sensors, actuators, payloads, or satellite-rocket interfaces, converting them into a unified signal format recognizable by the internal functional fusion boards; and amplifying and outputting control commands and data signals from the information processing boards or computing power expansion boards to external devices. Interface boards typically integrate isolation operational amplifiers, level conversion chips, electrostatic discharge protection devices, connector pads, and necessary passive filtering circuits. Through the interface board's transition, the information processing boards do not need to directly interact with diverse external interfaces, thus ensuring the versatility and reusability of the core functional fusion board design, while simultaneously achieving electrical isolation and physical protection between the onboard electronic systems and the external environment.

[0162] In a board-level converged architecture, the signal interconnection distance between boards is significantly shortened by eliminating independent single-unit housings and electrical boxes. This invention uses multilayer flexible printed circuit boards (FPCs) to achieve high-density interconnection between boards, replacing traditional cable networks. The multilayer flexible printed circuit board contains four functional traces: a high-speed signal layer (differential pair wiring, supporting PCIe, DDR4 / 5, speed: 16-32Gbps), a medium-speed control layer (SPI, I2C, CAN, etc.), a power distribution layer (wide copper foil for high-current power supply), and a grounding shielding layer (complete copper foil grounding).

[0163] This invention applies multi-layer flexible circuit boards to the board-level fusion architecture of computing satellites, which differs from the cable replacement solution of flat-panel satellite cable networks: the interconnection of multi-layer flexible circuit boards is an integral part of the board-level fusion architecture of this invention. It utilizes the short-distance interconnection advantage brought by the flat layout of the boards (the distance between boards is less than 50mm, which is much smaller than the cable length between traditional chassis greater than 500mm) to achieve low-loss transmission of high-speed signals, reduce the number of connectors by 60% to 80%, and reduce the cable weight by more than 70%.

[0164] All functional integration boards share a unified processor instruction set architecture and software ecosystem. The main processor of the information processing board serves as the "computing power scheduling center" for the entire satellite, pooling computing resources through virtualization technology. The GPU / NPU on the computing power expansion board acts as a "computing power acceleration node," accessing the computing power resource pool through a unified high-speed interconnect network. Unlike constellation-level resource pooling schemes, the computing power resource pooling of this invention is strictly limited to within a single computing power satellite. It is optimized for real-time constraints (interconnection delay of multiple flexible circuit boards between boards less than 1μs) and thermal safety constraints within a single satellite, meeting the deterministic response requirements of hard real-time tasks such as attitude control algorithms.

[0165] In board-level converged architectures, signal integrity is paramount due to the elimination of independent chassis shielding between boards. This invention employs the following four levels of protection: multi-layer flexible circuit board with symmetrical stack-up design (impedance control of 100 ohms ±10% differential, 50 ohms ±10% single-ended); high-speed differential pair equal-length wiring (accuracy ≤ 5 mils); gradient linewidth design at the connection between the multi-layer flexible circuit board and the rigid board; and redundant design of backup channels for critical signals using dual multi-layer flexible circuit boards.

[0166] Optionally, in the above technical solution, the material of the integrated heat dissipation base plate is a high thermal conductivity aluminum alloy, magnesium-lithium alloy, carbon fiber composite material or aluminum-based silicon carbide.

[0167] It should be noted that: 1) In addition to graphics processing units (GPUs) and neural network processors (NPUs), computing power expansion boards can also use the following dedicated computing power chips: ① Field-programmable gate arrays (FPGAs) are suitable for scenarios that require hardware-level parallel processing and flexible protocol customization; ② Digital signal processors (DSPs) are suitable for scenarios that require a large number of multiply-accumulate operations but are power-sensitive; ③ Application-specific integrated circuits (ASICs) are suitable for scenarios with fixed algorithms and large batches, which can further reduce power consumption and cost.

[0168] 2) In addition to ARM or RISC-V, the unified processor instruction set architecture can also adopt the following architectures: ① x86 architecture, which is suitable for scenarios that need to be compatible with the ground software ecosystem; ② heterogeneous architecture of multi-core digital signal processor plus microcontroller, which is suitable for scenarios that require both hard real-time control and complex algorithm processing; ③ Loongson, Phytium and other architectures, which are suitable for scenarios with strict requirements for independent controllability.

[0169] In another embodiment, any adjacent functional integration boards can also be interconnected via high-density board-to-board connectors; they can also be interconnected via short-range wireless connections, suitable for scenarios requiring electrical isolation; and they can also be interconnected via fiber optic connections, suitable for scenarios requiring ultra-high-speed data transmission.

[0170] The beneficial effects of this invention are as follows: 1) In traditional satellite electronic systems, each functional unit is equipped with an independent metal casing (typical single-unit casing weight 200-500g, wall thickness 1.5-2.0mm, material aluminum alloy), mounting bracket (typical weight 50-150g), and electrical box structure (typical weight 1.0-2.5kg). These structural components occupy a large amount of space and weight resources inside the satellite. Taking a 30kg-class micro-nano satellite as an example, the total weight of the electronic system structural components under the traditional architecture is about 5-8kg, accounting for 25%-35% of the total dry weight of the satellite, and only 1-2 computing power expansion cards can be deployed.

[0171] This invention eliminates the aforementioned independent packaging structure through a board-level fusion architecture, reconstructing the entire satellite's electronic system into several functional fusion boards directly laid flat on a single integrated heat dissipation base plate. Taking a 300mm×300mm×120mm flat-panel satellite configuration as an example, 4-6 functional fusion boards can be laid flat on the base plate, reducing the total weight of the electronic system structural components to 2-3kg (mainly the base plate weight of 1.5-2.5kg plus the weight of the printed circuit boards themselves), and the weight ratio to 8%-12%. Under the same volume and weight constraints, the number of computing power expansion boards deployed increases from 1-2 to 2-3. Combined with computing power resource pooling, the utilization rate increases from 30%-50% to 70%-85%, improving the overall satellite's effective computing power density. Simultaneously, the information processing board, as the main computing power scheduling hub, pools the entire satellite's computing power resources through virtualization technology. Each functional module can dynamically call upon computing power resources as needed, avoiding the problems of monopolistic computing power and uneven utilization of individual machines in traditional architectures. For example, the attitude control algorithm only requires 10% of the computing power during the stable operation period of the satellite, and the remaining 90% of the computing power can be temporarily allocated to artificial intelligence inference tasks, thereby improving the effective utilization density of the satellite's computing power resources.

[0172] 2) In traditional satellite electronic systems, the independent unit housings, mounting brackets, and electrical enclosures account for a significant portion (25%-35%) of the overall satellite dry weight, and there is a large amount of repetitive design (each unit has its own independent housing and bracket). This invention eliminates these independent packaging structures and supporting mounting brackets. All functional integrated boards are directly mounted flat on a single integrated heat dissipation base plate, eliminating repetitive structural supports and redundant packaging boundaries. Taking a 30kg-class micro / nano satellite as an example, the weight of the electronic system structure is reduced from 5-8kg to 2-3kg, and the overall satellite dry weight can be reduced by 3-6kg. This weight reduction means that, under the same launch weight constraint, more weight margin (approximately 3-6kg) can be reserved for computing power payloads (each additional computing power expansion board adds approximately 0.5-1.0kg), propellant, or other mission resources, which is beneficial for improving the overall mission efficiency of the satellite.

[0173] 3) In traditional architectures, the board and the satellite heat dissipation surface are separated by multiple interfaces, including the chassis, mounting brackets, and thermal pads, resulting in a long and complex thermal resistance path. A typical thermal resistance path is: chip → printed circuit board → thermal pad 1 → single-machine baseboard → thermal pad 2 → mounting bracket → thermal pad 3 → satellite structure → heat dissipation surface, totaling 7-9 thermal resistance links. Heat must undergo multiple conduction and interface transitions to reach the satellite heat dissipation surface. The board-level fusion architecture of this invention allows the back of the functionally integrated board to directly contact the local heat dissipation protrusions of the integrated structural heat dissipation baseboard through a thermally conductive interface material, forming a short-path heat conduction channel from the chip heat source to the heat dissipation baseboard. This channel is: chip → printed circuit board → thermal pad → local heat dissipation protrusions on the baseboard → heat pipe network → satellite heat dissipation surface, totaling 5-6 thermal resistance links. The board-level fusion architecture allows the board to directly contact the heat dissipation baseboard, shortening the heat dissipation path from 7-9 thermal resistance links in the traditional architecture to 5-6, creating physical conditions for heat dissipation of high-power computing chips.

[0174] 4) Traditional satellites rely on numerous discrete cables and connectors to interconnect signals between individual components. Connectors and cable joints are among the most frequent sources of on-orbit failure in spacecraft. Statistics show that connector-related failures account for 25%-35% of satellite electronic system failures, and problems such as poor contact, solder joint fatigue, and cable wear are prone to occur in the vibration environment during launch. A typical satellite electronic system contains 100-500 cable connectors, each of which is a potential failure point. This invention uses multilayer flexible circuit boards to replace traditional cable networks, reducing the number of connectors by 60%-80% (from 100-500 to 20-100), directly reducing the systemic risk caused by connector failure. Multilayer flexible circuit boards have excellent vibration and bending resistance, enabling them to adapt to the mechanical environment during launch. Furthermore, a dual multilayer flexible circuit board backup channel redundancy is designed for critical signals, automatically switching to the backup channel when the main channel malfunctions, further improving the reliability of signal transmission.

[0175] 5) Traditional satellite electronic systems adopt a "mission-specific customization, stand-alone development" model, requiring the redesign of independent stand-alone hardware for each mission. The typical development cycle is 18-24 months, including requirements analysis, scheme design, detailed design, printed circuit board layout design, board fabrication, debugging, environmental testing, and qualification acceptance. This process is lengthy and has high iteration costs. The board-level fusion architecture of this invention realizes a "hardware platformization, software functionalization" design paradigm. The functional fusion boards use a unified hardware platform (unified baseboard, unified board size series, unified multi-layer flexible circuit board interface specifications, and unified interconnect architecture). Once the hardware design is completed, it can be dynamically adapted to different satellite mission requirements through software function configuration and algorithm loading, eliminating the need to redesign independent stand-alone hardware for each mission. After hardware platformization, the new mission adaptation cycle is shortened to 6-10 months (mainly for software development and algorithm optimization), and the development cycle is shortened by 40%-60%, which is beneficial for the rapid deployment, mass production, and on-orbit functional iteration of computing satellite constellations.

[0176] 6) In traditional satellite electronic systems, the computing resources (central processing unit, digital signal processor, etc.) of each subsystem are configured for exclusive use and are physically distributed across different individual machines, with no communication between them. Even if a subsystem is under low load, its surplus computing power cannot be utilized by other subsystems, resulting in a computing power utilization rate of only 30%-50%. This invention, through the physical foundation created by a board-level fusion architecture—where all functional fusion boards are laid flat on the same baseboard, interconnected via high-speed multilayer flexible circuit boards, and sharing a unified processor instruction set architecture (ISA) and software ecosystem—achieves the integration of heterogeneous computing resources (central processing unit, graphics processing unit, neural network processor, field-programmable gate array) into a unified computing resource pool within a single satellite. Combined with virtualization technology and computing power scheduling middleware, the computing power utilization rate is increased to 70%-85%, and it supports flexible dynamic allocation based on task load. For example, during the satellite's orbit insertion phase, priority is given to attitude control computing power, while during on-orbit operation, surplus computing power is used for artificial intelligence inference. This effect is impossible to achieve in existing technologies because existing technologies lack the physical interconnection foundation for board-level fusion.

[0177] The above description is merely a preferred embodiment of the present invention and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of disclosure in this invention is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-disclosed concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this invention.

[0178] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A board-level integrated electronic system architecture for computing satellites, applied to satellite configurations, characterized in that, include: An integrated heat dissipation base plate for installation inside the satellite configuration; The upper surface of the integrated heat dissipation base plate is provided with local heat dissipation protrusions; Each functional fusion board is mounted flat on the local heat dissipation protrusion through a thermally conductive interface material, and each functional fusion board does not have an independent metal casing or electrical box structure. Any adjacent functional integration boards are interconnected for signal and power distribution via multi-layer flexible circuit boards; The integrated heat dissipation base plate has a pre-embedded heat pipe network inside, which is thermally connected to the local heat dissipation protrusion to transfer the heat generated by each of the functional fusion boards to the satellite heat dissipation surface.

2. The board-level integrated electronic system architecture for computing satellites according to claim 1, characterized in that, All functional integration boards include at least an information processing board and a computing power expansion board. The information processing board uses virtualization technology to incorporate the heterogeneous computing power resources on the computing power expansion board into a unified computing power resource pool, and dynamically allocates the computing power resources in the unified computing power resource pool to at least one of the following functional modules: the space service management functional module, the attitude control functional module, and the telemetry, tracking and command (TT&C) functional module.

3. The board-level integrated electronic system architecture for computing satellites according to claim 1, characterized in that, The location of the local heat dissipation protrusion on the upper surface of the integrated heat dissipation base plate corresponds one-to-one with the location of the high heat flux density chip on each of the functional fusion boards. The heat pipe network includes multiple heat pipes, one end of each heat pipe is thermally connected to the corresponding local heat dissipation protrusion, and the other end of each heat pipe extends to the heat dissipation surface of the satellite configuration.

4. The board-level integrated electronic system architecture for computing satellites according to claim 1, characterized in that, The multilayer flexible circuit board adopts a four-layer structure, which includes a high-speed signal layer, a medium-speed control layer, a power distribution layer, and a ground shielding layer. The high-speed signal layer uses differential pair wiring, the power distribution layer uses wide copper foil traces, and the ground shielding layer is a complete copper foil. The multilayer flexible circuit board adopts a gradient line width design at the position where it connects to the functional fusion board, and the multilayer flexible circuit board corresponding to the critical signals is equipped with dual-channel backup redundancy.

5. The board-level integrated electronic system architecture for computing satellites according to claim 4, characterized in that, The multilayer flexible circuit board adopts a symmetrical stacked structure. The high-speed signal layer and the medium-speed control layer are located on both sides of the ground shielding layer, respectively. The differential pair traces in the high-speed signal layer adopt equal-length wiring, and the high-speed signal layer is provided with cross copper pour shielding between the high-speed signal layer and the adjacent layer.

6. The board-level integrated electronic system architecture for computing satellites according to claim 1, characterized in that, The satellite configuration can be a flat-panel satellite configuration, a cube satellite configuration, a cylindrical satellite configuration, or a deployable satellite configuration. When the satellite configuration is a flat-panel satellite configuration, each of the functional fusion boards is laid flat along the thickness direction of the flat-panel satellite configuration, and the surface of each functional fusion board is parallel to the main structural surface of the flat-panel satellite configuration. When the satellite configuration is a cube satellite configuration, each of the functional fusion boards is laid flat on the integrated structural heat dissipation base plate. When the satellite configuration is a cylindrical satellite configuration, each of the functional fusion boards is arranged radially around the central axis of the cylindrical satellite configuration. When the satellite configuration is a deployable satellite configuration, the integrated structural heat dissipation base plate is disposed on the deployable panel of the deployable satellite configuration.

7. The board-level integrated electronic system architecture for computing satellites according to claim 2, characterized in that, The information processing board and the computing power expansion board share a unified processor instruction set architecture. The information processing board runs virtualization software to abstract the heterogeneous computing power resources on the computing power expansion board into the unified computing power resource pool, and realizes the scheduling of computing power resources in the unified computing power resource pool through a unified software ecosystem.

8. The board-level integrated electronic system architecture for computing satellites according to claim 2, characterized in that, The computing power expansion board integrates at least one dedicated computing power chip among a graphics processor, a neural network processor, and a field-programmable gate array. The dedicated computing power chip is interconnected with the information processing board via a high-speed bus, and the dedicated computing power chip dynamically loads artificial intelligence inference models or data processing algorithms according to task requirements.

9. The board-level integrated electronic system architecture for computing satellites according to claim 2, characterized in that, All functional integration boards also include an energy management board, which integrates a solar array power regulation unit, a battery charging and discharging management unit, a load power distribution unit, and a power consumption monitoring unit. The energy management board collects power consumption data from the information processing board, the computing power expansion board, and other functional integration boards in real time, and participates in the unified power consumption budget management of the entire satellite based on the collected power consumption data.

10. The board-level integrated electronic system architecture for computing satellites according to claim 1, characterized in that, The integrated heat dissipation base plate is made of high thermal conductivity aluminum alloy, magnesium-lithium alloy, carbon fiber composite material or aluminum-based silicon carbide.

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