Semiconductor device and method of manufacturing the same, storage system

Abstract

The present disclosure provides a semiconductor device and a preparation method thereof, and a storage system, and relates to the technical field of semiconductor chips, and aims to reduce the coupling effect between contact columns on the basis of improving the storage density. The semiconductor device comprises a bit line, a contact column and a first insulating layer. A plurality of bit lines are arranged along a first direction; the first direction is the thickness direction of the semiconductor device. The contact column extends to the target bit line along the first direction and is connected with the target bit line. A conductor layer is arranged around at least part of the contact column. The first insulating layer is arranged between the contact column and the conductor layer. The above semiconductor device is applied to a storage system.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor chip technology, and in particular to a semiconductor device and its fabrication method and storage system. Background Technology

[0002] Planar semiconductor devices (such as memory) can be scaled to smaller sizes by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of semiconductor devices approaches its lower limit, planar processes and manufacturing technologies become challenging and costly. 3D semiconductor device architectures can address some of the density limitations in planar semiconductor devices, such as flash memory devices.

[0003] 3D semiconductor devices can be formed by stacking semiconductor wafers or dies and vertically interconnecting them. Compared with conventional planar semiconductor devices, 3D semiconductor devices have smaller size and higher density, thus achieving performance improvements. Summary of the Invention

[0004] On one hand, a semiconductor device is provided. The semiconductor device includes bit lines, contact pillars, and a first insulating layer. A plurality of bit lines are arranged along a first direction; the first direction is the thickness direction of the semiconductor device. The contact pillars extend along the first direction to a target bit line and are connected to the target bit line. A conductor layer is disposed around at least a portion of the contact pillars. The first insulating layer is disposed between the contact pillars and the conductor layer.

[0005] In some embodiments, a first insulating layer is disposed around a contact post, and a conductor layer is disposed around the first insulating layer.

[0006] In some embodiments, the semiconductor device further includes an insulating pattern. In a first direction, the insulating pattern is located between a conductor layer and a target bit line, and the conductor layer is insulated from the target bit line.

[0007] In some embodiments, along a first direction, the contact post has a first end and a second end, the second end being closer to the target bit line than the first end; an insulating pattern is disposed around the second end of the contact post.

[0008] In some embodiments, the conductor layer includes a first portion and a second portion interconnected. The first portion is a cylindrical structure extending along a first direction. The second portion is located on the side of the first portion near the target bit line and extends along a fourth direction, which intersects the first direction. An insulating pattern is located between the second portion and the target bit line. The first insulating layer has a first edge portion and a second edge portion arranged along the first direction. The second edge portion is closer to the target bit line than the first edge portion; the second edge portion of the first insulating layer penetrates the second portion of the conductor layer and connects to the insulating pattern.

[0009] In some embodiments, the semiconductor device further includes a second insulating layer. The second insulating layer is disposed around the conductor layer.

[0010] In some embodiments, the second insulating layer is located between the contact post and the bit line in a direction perpendicular to the first direction.

[0011] In some embodiments, the insulating pattern is made of the same material as the second insulating layer.

[0012] In some embodiments, the semiconductor device includes a first surface and a second surface opposite each other in a first direction. A contact post extends from the first surface along a first direction to a target bit line. The contact post penetrates the bit line located on the side of the target bit line near the first surface. A conductor layer and a first insulating layer penetrate the bit line located on the side of the target bit line near the first surface.

[0013] In some embodiments, the plurality of bit lines include a first bit line and a second bit line, with the first bit line being closer to the first surface than the second bit line. A plurality of contact posts include a first contact post and a second contact post, with the first contact post connected to the first bit line and the second contact post extending at least through the first bit line and connecting to the second bit line. The semiconductor device includes a memory region having a plurality of memory cells. Along a third direction, the first contact post is further away from the memory region than the second contact post, and this third direction is the extension direction of the bit lines.

[0014] In some embodiments, a bit line includes a contact portion located at one end of the bit line. A contact post is connected to the contact portion of the target bit line. The contacts of multiple bit lines are staggered sequentially in a third direction, which is the direction in which the bit lines extend. The semiconductor device also includes a dielectric layer that covers the contacts of the multiple bit lines. A conductor layer and a first insulating layer penetrate the dielectric layer.

[0015] In some embodiments, the semiconductor device includes a memory region having a plurality of memory cells. Bit line contacts are located outside the memory region. Specifically, along a third direction and from the memory region towards the bit line contacts, the dimensions of the plurality of contact pillars gradually increase along a first direction, and the dimensions of the multilayer conductor layer also gradually increase along the first direction.

[0016] In some embodiments, the semiconductor device includes: a multilayer memory layer stacked in a first direction. The memory layer includes a plurality of memory cells arranged in a third direction, which is the direction in which bit lines extend. Each memory cell includes a transistor and a capacitor arranged along a second direction, the capacitor being connected to the transistor. The second direction is perpendicular to both the first and third directions. A bit line is connected to the transistors of the plurality of memory cells arranged in the third direction in one layer of the memory layer. The gates of the transistors of the plurality of memory cells overlapping in the first direction in the multilayer memory layer are connected to form a gate line.

[0017] In some embodiments, the semiconductor device further includes peripheral devices connected to bit lines. These peripheral devices are connected to a conductor layer and also to contact posts.

[0018] On the other hand, a storage system is provided. The storage system includes a controller and a semiconductor device as described above. The controller is coupled to the semiconductor device.

[0019] In another aspect, a method for fabricating a semiconductor device is provided. The method includes: forming bit lines; forming contact pillars, a conductor layer, and a first insulating layer. Multiple bit lines are arranged along a first direction, which is the thickness direction of the semiconductor device. Contact pillars extend along the first direction to a target bit line and connect to the target bit line. A conductor layer is disposed around at least a portion of the contact pillars. The first insulating layer is disposed between the contact pillars and the conductor layer.

[0020] In some embodiments, forming a contact post, a conductor layer, and a first insulating layer includes: forming a contact hole extending along a first direction to a target bit line; forming a conductor layer covering the hole wall and bottom surface of the contact hole; forming a first through hole penetrating the conductor layer located at the bottom of the contact hole to expose the target bit line; forming a first insulating layer covering the conductor layer and the exposed target bit line; forming a second through hole penetrating the first insulating layer located at the bottom of the contact hole to expose the target bit line; and forming a contact post within the contact hole and the gap enclosed by the first insulating layer, the contact post passing through the second through hole and connecting to the target bit line. The diameter of the first through hole is larger than the diameter of the second through hole.

[0021] In some embodiments, prior to forming the conductor layer, the fabrication method further includes: forming a third insulating layer that covers the hole wall and bottom surface of the contact hole. The first through-hole also penetrates the third insulating layer located at the bottom of the contact hole; a portion of the third insulating layer covering the hole wall forms a second insulating layer, and a portion of the third insulating layer located at the bottom surface of the contact hole forms an insulating pattern. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual process of the method, etc. involved in the embodiments of this disclosure.

[0023] Figure 1 This is a structural diagram of a semiconductor device provided according to some embodiments;

[0024] Figure 2 This is a structural diagram of a memory cell array provided according to some embodiments;

[0025] Figure 3AThis is an equivalent circuit diagram of a semiconductor device provided according to some embodiments;

[0026] Figure 3B This is yet another equivalent circuit diagram of a semiconductor device provided according to some embodiments;

[0027] Figure 4A This is yet another structural diagram of a semiconductor device provided according to some embodiments;

[0028] Figure 4B This is yet another structural diagram of a semiconductor device provided according to some embodiments;

[0029] Figure 5A This is yet another structural diagram of a semiconductor device provided according to some embodiments;

[0030] Figure 5B This is a graph showing the variation of the sensing margin of the bit line according to some embodiments;

[0031] Figure 6 This is yet another structural diagram of a semiconductor device provided according to some embodiments;

[0032] Figure 7 This is yet another structural diagram of a semiconductor device provided according to some embodiments;

[0033] Figure 8 This is yet another structural diagram of a semiconductor device provided according to some embodiments;

[0034] Figure 9 This is yet another structural diagram of a semiconductor device provided according to some embodiments;

[0035] Figure 10 This is yet another structural diagram of a semiconductor device provided according to some embodiments;

[0036] Figure 11A This is yet another structural diagram of a semiconductor device provided according to some embodiments;

[0037] Figure 11B This is yet another structural diagram of a semiconductor device provided according to some embodiments;

[0038] Figure 12 This is yet another structural diagram of a semiconductor device provided according to some embodiments;

[0039] Figure 13A This is a structural diagram of a storage system provided according to some embodiments;

[0040] Figure 13B This is another structural diagram of a storage system provided according to some embodiments;

[0041] Figure 14 This is a structural diagram of an electronic device provided according to some embodiments;

[0042] Figure 15 This is yet another structural diagram of an electronic device provided according to some embodiments;

[0043] Figure 16 This is a flowchart of a method for fabricating a semiconductor device according to some embodiments;

[0044] Figures 17A to 18D This diagram illustrates some steps in a method for fabricating a semiconductor device according to some embodiments. Detailed Implementation

[0045] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0046] In the description of this disclosure, it should be understood that the terms “center,” “upper,” “lower,” “front,” “rear,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” and “outer,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0047] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0048] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0049] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0050] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0051] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0052] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0053] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0054] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0055] In this disclosure, the meanings of “on,” “above,” and “above” should be interpreted in the broadest possible sense, such that “on” means not only “directly on” something, but also includes “on” something with intermediate features or layers in between, and that “above” or “above” means not only “above” or “above” something, but also “above” or “above” something without intermediate features or layers in between (i.e., directly on something).

[0056] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0057] It should be noted that the "A / B" designations in the attached diagrams indicate that structure / region A and structure / region B can be referred to as the same structure / region. For example, Figure 4A In the diagram, "210 / 210X" refers to both bit line 210 and target bit line 210X, which can be represented by this structure. The labels "A~B" in the attached diagram indicate that structure / region A belongs to structure / region B; that is, the structure referred to by this label is both structure A and structure B. For example, Figure 8 The designation “251-250” indicates that the structure referred to by the designation is that the first edge portion 251 belongs to the first insulating layer 250.

[0058] As used in this disclosure, whether a component (e.g., a layer, structure, or device) is "on," "above," or "below" another component (e.g., a layer, structure, or device) of a semiconductor device is determined relative to the substrate of the semiconductor device in the first direction X, when the substrate is located in the lowest plane of the semiconductor device in the first direction X. The same concepts are applied throughout this disclosure to describe spatial relationships.

[0059] The semiconductor devices involved in the embodiments of this disclosure can be memory structures or memory structures connected (e.g., bonded) to peripheral devices. The memory structure and the peripheral devices connected to it constitute a memory, which includes, but is not limited to, Dynamic Random Access Memory (DRAM). The following description uses DRAM as an example only. However, it should be noted that the following descriptions of DRAM are only used to illustrate some embodiments of this disclosure and are not intended to limit the scope of some embodiments of this disclosure.

[0060] Figure 1 This is a possible structural diagram of the semiconductor device 200 in some embodiments. (Refer to...) Figure 1 The semiconductor device 200 includes a memory cell 100. The memory cell 100 includes a transistor 110 and a capacitor 120, which are connected together.

[0061] In some embodiments, each memory cell 100 includes a transistor 110 and a capacitor 120. In this case, the semiconductor device 200 has an architecture of one transistor (T) and one capacitor (C) (1T1C). Its main working principle is to use the amount of charge stored in the capacitor 120, or the high and low voltage difference across the capacitor 120, to represent logical 1 and 0.

[0062] Figure 2 This is a schematic diagram of the structure of a 100G storage cell array in some embodiments. (Refer to...) Figure 2 The semiconductor device 200 includes a plurality of memory cells 100 that can form a memory cell array 100G. Here, the memory cell array 100G can be any suitable memory cell array. For example, the memory cell array 100G can be a DRAM cell array, and the capacitor 120 is a capacitor for storing charge as binary information stored by the respective DRAM cells.

[0063] Exemplarily, the capacitor 120 can have various structures. For example, the capacitor 120 can be cup-shaped, cylindrical, or pillar-shaped. That is, the capacitor 120 can be any one of a cup-shaped capacitor, a cylindrical capacitor, and a pillar-shaped capacitor. Each of the cup-shaped capacitor, cylindrical capacitor, and pillar-shaped capacitor includes a first electrode, a second electrode, and a first dielectric layer. The first electrode and the second electrode are at least partially opposite to each other, and the first dielectric layer is located between the opposite portions of the first electrode and the second electrode.

[0064] For example, the material of the first electrode and / or the second electrode may include at least one of titanium nitride (TiN), titanium silicon nitride (TiSiN), ruthenium oxide (RuO), and the rare metal gold (Au). Moreover, the materials of the first electrode and the second electrode may be the same or different.

[0065] For example, the material of the first dielectric layer can be a dielectric material with a high dielectric constant.

[0066] In some examples, refer to Figure 2 The transistor 110 includes a source 111, a drain 112, and a channel structure 113. The channel structure 113 can also be called a semiconductor pillar, with the source 111 and drain 112 respectively located at its two ends. One of the first electrode and the second electrode can be coupled to either the source 111 or the drain 112. In this case, the capacitor 120 and its corresponding transistor 110 can constitute a memory cell 100.

[0067] For example, refer to Figure 2 The transistor 110 also includes a gate oxide layer 115 and a gate 114. The gate oxide layer 115 is disposed on the side of the channel structure 113, and the gate 114 is disposed on the side of the gate oxide layer 115 away from the channel structure 113.

[0068] In some embodiments, refer to Figure 1 and Figure 2 The semiconductor device 200 also includes a bit line 210 and a gate line 220, with the gate 114 electrically connected to the gate line 220. In this configuration, the transistor 110, capacitor 120, gate line 220, and bit line 210 can form a circuit structure to perform read or write operations on a memory (e.g., a dynamic random access memory). The working principle of the circuit structure will be illustrated below.

[0069] Figure 3A This is an equivalent circuit diagram of a semiconductor device provided in some embodiments, the semiconductor device employing a 1T1C architecture. (Refer to...) Figure 3A One of the drain and source terminals of transistor T is electrically connected to the bit line BL, and the other is electrically connected to one electrode of capacitor C. The other electrode of capacitor C can be connected to a reference voltage. The gate of transistor T is connected to the gate line WL (also called the word line). Applying a voltage to the gate line WL controls whether transistor T is turned on or off. The bit line BL is used to perform read or write operations on the information stored in capacitor C when transistor T is turned on. In other words, the on and off states of transistor T determine whether reading and writing of the information stored in capacitor C is allowed or prohibited. Capacitor C is used to store data written to the memory cell.

[0070] although Figure 3A An equivalent circuit diagram of a semiconductor device employing a 1T1C architecture is shown. However, it should be understood that this disclosure does not limit the architecture of the semiconductor device 200. For example, in other examples, the architecture of the semiconductor device 200 can be 1TnC, nT1C, 2TnC, or mTnC, where m and n can be the same or different; in other words, the semiconductor device 200 can be in a 1TnC, nT1C, 2TnC, or mTnC configuration. For example, refer to... Figure 3B In a 1TnC configuration, the memory cell of a semiconductor device may include n capacitors C-1, C-2, ..., Cn coupled to either the source or drain of a transistor T. That is, one electrode of each capacitor C-1, C-2, ..., Cn may be coupled to the same source / drain of the transistor T, and the other electrode of each capacitor C-1, C-2, ..., Cn may be coupled to a corresponding plate line among n plate lines CL-1, CL-2, ..., CL-n, such that each capacitor C-1, C-2, ..., or Cn can be individually controlled by the corresponding plate line CL-1, CL-2, ..., CL-n.

[0071] In some examples, refer to Figure 2 Transistor 110 includes a vertical gate, which reduces the area occupied by transistor 110, simplifies the layout of gate line 220 and bit line 210, and allows bit line 210 and capacitor 120 to be located on opposite sides of transistor 110, thus reducing the process margin of bit line 210.

[0072] In the transistor 110 including the vertical gate, the gate 114 is disposed on one or more sides of the channel structure 113. In some examples, see... Figure 2In some examples, the channel structure 113 of transistor 110 is surrounded by an annular gate 114, and transistor 110 can also be called a gate all around (GAA) transistor. In other examples, the gate 114 of transistor 110 is located on three sides of the channel structure 113, and transistor 110 can also be called a tri-gate transistor. In other examples, the gate 114 of transistor 110 is located on both sides of the channel structure 113, and transistor 110 can also be called a double-gate transistor. In other examples, the gate 114 of transistor 110 is located on one side of the channel structure 113, and transistor 110 can also be called a single-gate transistor. In other examples, the channel structures 113 of adjacent transistors 110 are separated by an isolation structure, and the gate 114 is located on the side of the channel structure 113 away from the isolation structure. The gates 114 of adjacent transistors 110 are mirror-symmetrically distributed, and transistor 110 can also be called a mirror single-gate transistor.

[0073] With the iteration of memory (e.g., DRAM) technology, in order to achieve higher storage density, memory with 3D architecture (e.g., 3D DRAM) has been proposed.

[0074] In some embodiments, refer to Figure 1 In the semiconductor device 200, the transistors 110 and capacitors 120 included in the memory cell 100 are arranged along a second direction Y, which is perpendicular to the first direction X, and the first direction X is the thickness direction of the semiconductor device 200.

[0075] Here, the thickness direction of the semiconductor device 200 can be understood as the thickness direction of the wafer (also called the substrate) used to form the semiconductor device 200.

[0076] For example, the unit cell size of the storage cell 100 is, for example, 4F² (2F×2F, also known as 4F² cell size), that is, the cell configuration size of the storage cell 100 is greater than or equal to four times the square of the minimum feature size F. In other words, the storage cell array 100G can be arranged in an orthogonal layout with a cross-point orthogonal layout having a 4F² cell size.

[0077] With a unit cell size of 4F2, compared to a unit cell size of 8F2 or 6F2, the unit cell size of the storage cell 100 can be smaller, which is beneficial to improving storage density.

[0078] Understandably, based on the above structure, the storage cell 100 can be laid flat and stacked in multiple layers along the first direction X. In this way, the semiconductor device 200 can have a 3D architecture, which is beneficial for the compression of the size (e.g., diesize) of the semiconductor device 200 and can improve the storage density.

[0079] As mentioned above, refer to Figure 1 and Figure 2 The semiconductor device 200 includes multiple memory cells 100 that can form a memory cell array 100G. The arrangement directions of the multiple memory cells 100 in the memory cell array 100G include two mutually perpendicular directions. In this case, in the memory cell array 100G, multiple memory cells 100 arranged along one direction can share a bit line 210, and multiple memory cells 100 arranged along another direction can share a gate line 220.

[0080] When the transistors 110 and capacitors 120 included in the memory cell 100 are arranged along the second direction Y, the arrangement direction of the plurality of memory cells 100 in the memory cell array 100G may include a first direction X and a third direction Z, wherein the third direction Z is perpendicular to the second direction Y and perpendicular to the first direction X. In this case, based on the extension direction of the bit line 210 and the gate line 220, the semiconductor device 200 can be at least divided into a vertical bit line semiconductor device and a vertical gate line semiconductor device.

[0081] In some examples, the semiconductor device 200 is a vertical bit-line semiconductor device, with bit lines 210 extending along the thickness direction of the semiconductor device 200 (i.e., the first direction X); the extension direction of the gate line 220 can be the third direction Z. In this case, multiple bit lines 210 are arranged along the third direction Z, and the bit lines 210 can be connected to multiple memory cells 100 arranged along the first direction X.

[0082] In some other examples, semiconductor device 200 is a vertical gate line semiconductor device, see reference. Figure 1 Bit lines 210 extend along a third direction Z; gate lines 220 extend in a first direction X. At this time, multiple bit lines 210 are arranged along the first direction X, and the bit lines 210 can be connected to multiple memory cells 100 arranged along a third direction Z.

[0083] When bit line 210 is connected to multiple memory cells 100, bit line 210 can be configured to perform read or write operations on information stored in capacitor 120 connected to the turned-on transistor 110 when one or more transistors 110 in the multiple memory cells 100 are turned on. Here, the number of transistors 110 connected to bit line 210 is not limited.

[0084] It should be understood that any two bit lines 210 among the plurality of bit lines 210 are insulated from each other. Exemplarily, the semiconductor device 200 also includes an insulating structure (e.g., a dielectric layer 291 described in detail below, which may be referred to) located between adjacent two bit lines 210 among the plurality of bit lines 210. Figure 10 This can improve the insulation performance between bit lines 210.

[0085] In the case where the semiconductor device 200 is a vertical gate line semiconductor device, in some embodiments, refer to Figure 4A and Figure 4B The semiconductor device 200 also includes a contact post 230 (also referred to as a bit line pickup). The contact post 230 extends along a first direction X to a target bit line 210X and is connected to the target bit line 210X.

[0086] When the contact post 230 is connected to the target bit line 210X, the contact post 230 can be used to access the bit line signal of the target bit line 210X. One of the multiple contact posts 230 is connected to one of the multiple bit lines 210 (i.e., the target bit line 210X), so that the multiple bit lines 210 can be accessed with bit line signals respectively.

[0087] In some examples, refer to Figure 4A and Figure 4B The semiconductor device 200 includes a first surface 200a and a second surface 200b opposite each other in a first direction X. Contact posts 230 extend from the first surface 200a along the first direction X to a target bit line 210X and are connected to the target bit line 210X. Since the distances between each bit line 210 and the first surface 200a are not equal, the lengths of the plurality of contact posts 230 along the first direction X are not equal.

[0088] In some embodiments, the number of layers of the memory cell 100 stacked along the first direction X is relatively large, and correspondingly, the number of bit lines 210 arranged along the first direction X is also relatively large. On the one hand, among the multiple contact posts 230, the contact post 230 connected to the bit line 210 that is farther away from the first surface 200a has a larger size along the first direction X, so that the face-to-face area between the contact post 230 and the adjacent contact post 230 is larger, the coupling effect is stronger, and the sense margin corresponding to the bit line 210 that is farther away from the first surface 200a is relatively lower. On the other hand, among the multiple contact posts 230, the contact post 230 connected to the bit line 210 closer to the first surface 200a has a smaller dimension along the first direction X. This results in a smaller facing area between the contact post 230 and its adjacent contact posts 230, leading to a relatively weaker coupling effect. Consequently, the consistency of the sensing margin corresponding to the bit line 210 farther from the first surface 200a and the bit line 210 closer to the first surface 200a is poor (which can also be understood as the sensing margin corresponding to multiple bit lines 210 not converging). Moreover, as the number of stacked layers of bit lines 210 increases, the difference in sensing margin becomes more significant. Therefore, the sensing margin of the vertical gate line semiconductor device needs to be optimized.

[0089] For example, refer to Figure 4A and Figure 4B The multiple contact posts 230 include contact posts 230A, 230B, 230C, and 230D. The facing area between contact posts 230A and 230B is relatively small, resulting in a relatively weak coupling effect; the facing area between contact posts 230C and 230D is relatively large, resulting in a relatively strong coupling effect. Figure 4B In the diagram, the structure indicated by the number 293 is the fourth insulating layer 293.

[0090] For example, refer to Figure 5A and Figure 5B Multiple bit lines 210 are distributed in a multi-layer bit line layer arranged along the first direction X. Among the multi-layer bit line layer, the bit line layer closest to the first surface 200a includes multiple bit lines 210A spaced apart along the second direction Y, and the bit line layer furthest from the first surface 200a includes multiple bit lines 210B spaced apart along the second direction Y. The change curve of the sensing margin of the multiple bit lines 210A is shown in the figure. Figure 4B As shown in curve a, the change curves of the sensing margin of multiple bit lines 210B are as follows: Figure 4BAs shown in curve b, curves a and b reveal that the sensing margin of multiple bit lines 210B is relatively low, and the convergence of the sensing margin of multiple bit lines 210B is worse than that of multiple bit lines 210B; moreover, the convergence between the sensing margins of multiple bit lines 210B and their adjacent sensing margins is also poor. In some cases, when multiple bit lines 210 are stacked to 100 layers, the coupling strength between bit line 210B and its adjacent bit lines 210 is 99 times that between bit line 210A and its adjacent bit lines 210, significantly affecting the consistency of the sensing margins corresponding to the multiple bit lines 210.

[0091] Figure 6 This is a structural diagram of a semiconductor device 200 provided in some embodiments. Figure 7 This is a structural diagram of a semiconductor device 200 provided in some other embodiments.

[0092] Based on the above, in some embodiments, reference is made to Figure 6 and Figure 7 The semiconductor device 200 further includes a conductor layer 240 and a first insulating layer 250. The conductor layer 240 is disposed around at least a portion of the contact post 230. The first insulating layer 250 is disposed between the contact post 230 and the conductor layer 240.

[0093] It should be understood that when the material of conductor layer 240 includes a conductor material, conductor layer 240 can be used to connect a preset voltage (also referred to as a fixed potential). This preset voltage is, for example, derived from the external circuit 200M (see reference...). Figure 12 The preset voltage is introduced. For example, the preset voltage is 2.0V.

[0094] For example, the material of the conductor layer 240 includes a conductor material, such as a metal material and / or tantalum nitride; wherein the metal material is, for example, tungsten. When the conductor material includes, for example, tungsten and / or tantalum nitride, the advantages of the above materials, such as ease of filling and high conductivity, can be utilized to improve the process feasibility of forming the conductor layer 240 between two adjacent bit lines 210 and to improve the reliability when a preset voltage is applied to the conductor layer 240.

[0095] For example, the material of the first insulating layer 250 includes at least one of silicon oxide (SiOx), silicon oxynitride (SiON), and silicon nitride (SiNy), wherein the values ​​of x and y are not limited here.

[0096] For example, a transmission electron microscope (TEM) can be used to inspect the conductor layer 240 and / or the first insulating layer 250 included in the semiconductor device 200. Of course, other inspection methods can also be selected.

[0097] Understandably, by including the conductor layer 240 in the semiconductor device 200, a preset voltage can be applied to the conductor layer 240, converting the coupling between adjacent contact posts 230 into coupling between the contact post 230 and the preset voltage. This weakens the coupling between two adjacent contact posts 230, avoiding the impact of coupling on the sensing margin, thus improving the sensing margin of the semiconductor device 200 and enhancing the consistency of the sensing margins corresponding to multiple bit lines 210, making the sensing margins corresponding to multiple bit lines 210 more convergent. Furthermore, when the first insulating layer 250 is located between the contact post 230 and the conductor layer 240, the first insulating layer 250 can form an insulating effect between the conductor layer 240 and the contact post 230. This prevents interference between the preset voltage and the bit line signal, improving the reliability when the preset voltage is applied to the conductor layer 240 and the bit line signal is applied to the contact post 230.

[0098] In some embodiments, the conductor layer 240 is disposed around a portion of the contact post 230.

[0099] Here, the contact post 230 surrounded by the conductor layer 240 is simply referred to as the target contact post 230X. When the conductor layer 240 partially surrounds the target contact post 230X, the portion of the side of the target contact post 230X surrounded by the conductor layer 240 can be selected based on the position of the adjacent contact post 230 (adjacent contact post 230L) to position the conductor layer 240 between the target contact post 230X and the adjacent contact post 230L. In other words, the portion of the side of the target contact post 230X directly opposite the adjacent contact post 230L is covered by the conductor layer 240. The relative positional relationship between the target contact post 230X and the adjacent contact post 230L can be referred to... Figure 7 .

[0100] It should be noted that "target" and "adjacent" in "target contact post 230X" and "adjacent contact post 230L" are relative concepts and are used only for descriptive purposes to make the position of conductor layer 240 clearer. In actual applications, target contact post 230X and adjacent contact post 230L can be any two adjacent contact posts 230 among multiple contact posts 230. Moreover, depending on the conductor layer 240 being described, a certain contact post 230 may be either target contact post 230X or adjacent contact post 230L.

[0101] In some examples, there are multiple adjacent contact posts 230L, with a conductor layer 240 provided between one adjacent contact post 230L and the target contact post 230X. Alternatively, at least two of the multiple adjacent contact posts 230L are provided with conductor layers 240 between themselves and the target contact post 230X. In the latter case, the conductor layer 240 can be a patterned conductor layer 240. In other words, the conductor layer 240 can include multiple conductor patterns spaced apart (e.g., spaced apart circumferentially along the target contact post 230X), with one conductor pattern located between one adjacent contact post 230L and the target contact post 230X.

[0102] In some embodiments, refer to Figure 6 and Figure 7 The first insulating layer 250 is disposed around the contact post 230, and the conductor layer 240 is disposed around the first insulating layer 250.

[0103] With the above configuration, the shielding effect between the target contact post 230X and multiple adjacent contact posts 230L can be achieved using a single conductor layer 240. Compared with the case where the conductor layer 240 is a patterned conductor layer 240, the structural complexity of the conductor layer 240 can be reduced. Thus, the formation process of the conductor layer 240 can be simplified while ensuring the shielding effect of the conductor layer 240.

[0104] In some examples, the dimension of the first insulating layer 250 along the first direction X is smaller than the dimension of the contact post 230 along the first direction X, and the dimension of the conductor layer 240 along the first direction X is smaller than the dimension of the contact post 230 along the first direction X. In this case, the portion of the conductor layer 240 near the target bit line 210X can be spaced apart from the target bit line 210X to achieve insulation between the conductor layer 240 and the target bit line 210X.

[0105] For example, the portion of conductor layer 240 near target bit line 210X can be insulated from target bit line 210X by a first insulating structure (not shown) located between them, and the first insulating structures disposed on one side of each conductor layer 240 are interconnected. The first insulating structure is, for example, the dielectric layer 280 described in detail below, which can be referred to... Figure 7 .

[0106] In some embodiments, refer to Figure 6 and Figure 7 The semiconductor device 200 also includes an insulating pattern 260. In the first direction X, the insulating pattern 260 is located between the conductor layer 240 and the target bit line 210X, and the conductor layer 240 is insulated from the target bit line 210X.

[0107] For example, the material of the insulating pattern 260 includes at least one of silicon oxide (SiOx), silicon oxynitride (SiON), and silicon nitride (SiNy), wherein the values ​​of x and y are not limited here.

[0108] For example, a transmission electron microscope can be used to inspect the insulating pattern 260 included in the semiconductor device 200; of course, other inspection methods can also be selected.

[0109] With the above configuration, the conductor layer 240 and the target bit line 210X can be insulatedly connected via the insulating pattern 260. This avoids interference between the preset voltage applied to the conductor layer 240 and the bit line signal connected to the target bit line 210X, thus improving the reliability of both the preset voltage applied to the conductor layer 240 and the bit line signal applied to the target bit line 210X. Furthermore, this configuration allows for better connection of the contact hole Q1 (see reference 260) used to form the contact post 230. Figure 17A The formation of an insulating pattern 260 within the conductor layer 240 can improve the controllability of the position and process parameters of the insulating pattern 260, which is beneficial to improving the reliability of the insulating connection between the conductor layer 240 and the target bit line 210X.

[0110] In some examples, the conductor layer 240 is a patterned film layer, in which case the insulating pattern 260 located on one side of a target bit line 210X can be matched with the pattern of the conductor layer 240, including multiple spaced insulator patterns.

[0111] In some embodiments, refer to Figure 6 and Figure 7 Along the first direction X, the contact post 230 has a first end 231 and a second end 232, the second end 232 being closer to the target position line 210X than the first end 231; an insulating pattern 260 is disposed around the second end 232 of the contact post 230.

[0112] For example, the cross-sectional dimension of the second end 232 of the contact post 230 perpendicular to the first direction X is smaller than the cross-sectional dimension of the first end 231 perpendicular to the first direction X.

[0113] It should be understood that when the insulating pattern 260 is arranged around the second end 232 of the contact post 230, the conductor layer 240 disposed outside the contact post 230 can be a solid layer structure, i.e., a non-patterned film layer; or, the conductor layer 240 disposed outside the contact post 230 can also be a patterned film layer, and there is no limitation here.

[0114] Understandably, when the insulating pattern 260 is arranged around the second end 232 of the contact post 230, compared to the case where the insulating pattern 260 includes multiple spaced insulator patterns, the structural complexity of the insulating pattern 260 can be reduced. Thus, the forming process of the insulating pattern 260 can be simplified while ensuring its insulating function. Furthermore, when the conductor layer 240 is arranged around the contact post 230, the above arrangement allows the annular structure of the insulating pattern 260 to match the annular structure of the conductor layer 240, enabling the insulating pattern 260 to completely cover the surface of the conductor layer 240 near the target bit line 210X, thereby enhancing the insulation effect between the conductor layer 240 and the target bit line 210X.

[0115] The morphology of conductor layer 240 will be described below by way of example.

[0116] As one possible method for forming the conductor layer 240 and the first insulating layer 250, refer to Figure 17A First, a contact hole Q1 can be formed extending from the first surface 200a along the first direction X to the target bit line 210X; then, referring to Figure 17C The material of conductor layer 240 is deposited on the hole wall and bottom surface of contact hole Q1; then, referring to Figure 17D and Figure 18A A first through-hole K1 is formed, penetrating the portion of the conductor layer 240 located at the bottom surface of the contact hole Q1 to expose the target bit line 210X; then, referring to Figure 17E and Figure 18B A first insulating layer 250 is formed covering the conductor layer 240 and the exposed target bit line 210X.

[0117] In the above formation method, refer to Figure 17D The size D3 of the first through hole K1 can be relatively large, so that there is no step difference between the inner surface of the conductor layer 240 remaining on the bottom surface of the contact hole Q1 (refer to 19A) and the inner surface of the conductor layer 240 covering the hole wall of the contact hole Q1. At this time, the conductor layer 240 formed as a whole has the above-mentioned cylindrical structure extending along the first direction X. By setting it in this way, the space enclosed by the conductor layer 240 can be relatively large, so that the space used to form the first insulating layer 250 and the contact post 230 can be relatively large, which can reduce the process difficulty of forming the first insulating layer 250 and the contact post 230 to a certain extent.

[0118] Therefore, in some examples, the conductor layer 240 is generally in the form of a cylindrical structure extending along the first direction X. For example, see reference... Figure 6 and Figure 7The structure of conductor layer 240 can be a conical structure in which one end dimension (e.g., the end away from the target bit line 210X) is larger than the other end dimension; or, for example, the structure of conductor layer 240 can be a straight cylindrical structure in which both ends have the same dimension.

[0119] Alternatively, in the above-mentioned formation methods, refer to Figure 18A The size D3 of the first through hole K1 can be relatively small, so that it remains in the contact hole Q1 (see reference). Figure 17A The inner surface of the conductor layer 240 at the bottom of the contact hole Q1 is closer to the contact post 230 than the inner surface of the conductor layer 240 covering the hole wall of the contact hole Q1. In this case, the overall structure of the conductor layer 240 is not a cylindrical structure extending along the first direction X. An example will be given below.

[0120] Figure 8 This is a structural diagram of the semiconductor device 200 provided in some other embodiments. (Refer to...) Figure 8 In some embodiments, the conductor layer 240 includes a first portion 241 and a second portion 242 interconnected. The first portion 241 is a cylindrical structure extending along a first direction X. The second portion 242 is located on the side of the first portion 241 near the target bit line 210X and extends along a fourth direction P, which intersects the first direction X. An insulating pattern 260 is located between the second portion 242 and the target bit line 210X. The first insulating layer 250 has a first edge portion 251 and a second edge portion 252 arranged along the first direction X. The second edge portion 252 is closer to the target bit line 210X than the first edge portion 251; the second edge portion 252 of the first insulating layer 250 penetrates the second portion 242 of the conductor layer 240 and connects to the insulating pattern 260.

[0121] Here, the first portion 241 of the conductor layer 240 is the portion covering the contact hole Q1 in the above-described forming method (see reference). Figure 17A The conductor layer 240 of the hole wall, and the second part 242 of the conductor layer 240, are the first through hole K1 formed in the above-described forming method (see reference). Figure 18B After that, the conductor layer 240 is retained on the bottom surface of the contact hole Q1.

[0122] With this configuration, in the method of forming the conductor layer 240 and the first insulating layer 250 described above, there is a step difference between the inner surface of the conductor layer 240 on the bottom surface of the contact hole Q1 and the inner surface of the conductor layer 240 covering the hole wall of the contact hole Q1. As a result, the opening accuracy requirement for the first through hole K1 is relatively low, as long as the target bit line 210X can be exposed through the first through hole K1. This reduces the process difficulty of forming the first through hole K1, and thus reduces the process difficulty of forming the conductor layer 240 and the first insulating layer 250. Moreover, by connecting the second edge portion 252 of the first insulating layer 250 through the second portion 242 of the conductor layer 240 and the insulating pattern 260, the second portion 242 of the conductor layer 240 can be covered by the first insulating layer 250 and the insulating pattern 260, so that the second portion 242 of the conductor layer 240 is insulated from the contact post 230.

[0123] In some examples, the surface of the conductor layer 240 remote from the first insulating layer 250 is covered with a dielectric material to achieve isolation between the conductor layer 240 and other structures in the semiconductor device 200. For example, see reference... Figure 7 The surface of the conductor layer 240 away from the first insulating layer 250 is covered by a dielectric layer 280. The dielectric layer 280 can form an isolation effect between the conductor layer 240 and other conductor structures (e.g., bit lines 210) in the semiconductor device 200. Moreover, the dielectric layers 280 outside the multiple conductor layers 240 are interconnected.

[0124] In some embodiments, refer to Figure 6 and Figure 9 The semiconductor device 200 also includes a second insulating layer 270. The second insulating layer 270 is disposed around the conductor layer 240.

[0125] For example, the material of the second insulating layer 270 includes at least one of silicon oxide (SiOx), silicon oxynitride (SiON), and silicon nitride (SiNy), wherein the values ​​of x and y are not limited here.

[0126] For example, a transmission electron microscope can be used to inspect the second insulating layer 270 included in the semiconductor device 200; of course, other inspection methods can also be selected.

[0127] With the above configuration, the conductor layer 240 and other conductor structures in the semiconductor device 200 can be mutually insulated at least through the second insulating layer 270. This prevents interference between the preset voltage applied to the conductor layer 240 and signals connected to other conductor structures in the semiconductor device 200, thereby improving the operational reliability of the semiconductor device 200. Furthermore, with the above configuration, the contact hole used to form the contact post 230 (e.g., contact hole Q1 described in detail below, refer to…) Figure 17A Forming a second insulating layer 270 within the conductor layer 240 improves the controllability of its location and process parameters, which is beneficial for enhancing the reliability of the insulation effect between the conductor layer 240 and other conductor structures in the semiconductor device 200. Furthermore, when the second insulating layer 270 is disposed around the conductor layer 240, the process for forming the second insulating layer 270 is simpler.

[0128] Here, the location and function of other conductor structures in the semiconductor device 200 are not limited. For example, other conductor structures in the semiconductor device 200 include adjacent contact pillars 230L (see reference). Figure 7 ) outer conductor layer 240.

[0129] In some embodiments, other conductor structures in the semiconductor device 200 include bit lines 210 other than the target bit line 210X. In this case, the second insulating layer 270 is located between the contact post 230 and the bit line 210 in a direction perpendicular to the first direction X.

[0130] With the above configuration, the second insulating layer 270 can at least form an insulating effect between the conductor layer 240 and the bit line 210, avoiding interference between the preset voltage and the bit line signal, thereby improving the reliability when the preset voltage is connected to the conductor layer 240 and the bit line signal is connected to the bit line 210.

[0131] In some examples, the semiconductor device 200 includes an insulating pattern 260 and a second insulating layer 270. In this case, the materials of the insulating pattern 260 and the second insulating layer 270 may also be different; for example, the insulating pattern 260 may be made of silicon oxynitride (SiON), and the second insulating layer 270 may be made of silicon nitride (SiNy). In this case, the insulating pattern 260 and the second insulating layer 270 may be formed in different steps; for example, they may be formed first in the contact hole Q1 (see reference...). Figure 17A A second insulating layer 270 is formed on the wall of the hole, and then an insulating pattern 260 is formed on the bottom surface of the contact hole Q1.

[0132] In some embodiments, the insulating pattern 260 is made of the same material as the second insulating layer 270.

[0133] For example, the materials of the insulating pattern 260 and the second insulating layer 270 both include at least one of silicon oxide (SiOx), silicon oxynitride (SiON), and silicon nitride (SiNy), wherein the values ​​of x and y are not limited here.

[0134] With the above configuration, the insulating pattern 260 and the second insulating layer 270 can be formed in the same steps, for example, in the contact hole Q1 (see reference). Figure 17A During the process of forming the second insulating layer 270 on the hole wall of the contact hole Q1, an insulating pattern 260 is formed on the bottom surface of the contact hole Q1; in this way, the process of forming the insulating pattern 260 and the second insulating layer 270 can be simplified, thereby simplifying the fabrication method of the semiconductor device 200.

[0135] The following will provide an exemplary description of different arrangements of bit lines 210, as well as the configuration of conductor layer 240 and related structures under different bit line 210 arrangements.

[0136] In some examples, refer to Figure 10 Multiple bit lines 210 have equal or approximately equal dimensions along the third direction Z, where the third direction Z is the extension direction of the bit lines 210.

[0137] In some embodiments, combined with Figure 10 , refer to Figure 6 and Figure 8 The semiconductor device 200 includes a first surface 200a and a second surface 200b opposite each other in a first direction X. A contact post 230 extends from the first surface 200a along the first direction X to a target bit line 210X. The contact post 230 passes through the bit line 210 located on the side of the target bit line 210X closer to the first surface 200a.

[0138] With this configuration, bit line 210 can be led out using a self-align contact (SCT) architecture to achieve electrical connection between bit line 210 and other structures (e.g., interconnect structures).

[0139] In some examples, the contact post 230 penetrates the bit line 210, creating coupling between the contact post 230 and the bit line 210. Furthermore, since multiple contact posts 230 extend from the first surface 200a to the target bit line 210X, the distances between each bit line 210 and the first surface 200a are different. This results in a larger number of contact posts 230 coupled to bit lines 210 relatively close to the first surface 200a, and a smaller number of contact posts 230 coupled to bit lines 210 relatively far from the first surface 200a. Consequently, the number of contact posts 230 coupled to each bit line 210 varies, leading to inconsistent sensing margins corresponding to different bit lines 210.

[0140] For example, refer to Figure 4B The multiple bit lines 210 include bit line 210E and bit line 210F. Bit line 210E is coupled to contact post 230B, contact post 230C, and contact post 230D, with the coupling between bit line 210E and contact post 230 being relatively strong; bit line 210F is coupled only to contact post 230D, with the coupling between bit line 210F and contact post 230 being relatively strong.

[0141] Based on this, in some embodiments, reference is made to Figure 6 and Figure 8 The conductor layer 240 and the first insulating layer 250 penetrate the bit line 210 located on the side of the target bit line 210X near the first surface 200a.

[0142] In some examples, the semiconductor device 200 also includes a second insulating layer 270 that extends through the bit line 210 located on the side of the target bit line 210X near the first surface 200a.

[0143] In some examples, the semiconductor device 200 includes a plurality of contact posts 230 and a plurality of conductor layers 240, wherein the plurality of conductor layers 240 are connected to a preset voltage that is equal or substantially equal.

[0144] With the above configuration, when the conductor layer 240 passes through the bit line 210 located on the side of the target bit line 210X near the first surface 200a, the coupling effect between the bit line 210 and the contact post 230 can be converted into the coupling effect between the bit line 210 and the preset voltage. Moreover, the coupling effect between the bit line 210 and the preset voltage does not change with the number of stacked layers of the bit line 210. In this way, the coupling effect between the bit line 210 and the contact post 230 can be weakened, thereby improving the sensing margin of the semiconductor device 200 and enhancing the consistency of the sensing margin corresponding to multiple bit lines 210. This makes the sensing margin corresponding to multiple bit lines 210 more convergent and more stable.

[0145] In some examples, refer to Figure 10 The semiconductor device 200 includes a storage area AA having a plurality of storage cells 100.

[0146] In some examples, bit line 210 includes a first sub-section 211 located in memory region AA and a second sub-section 212 located on one side of memory region AA along a third direction Z. The first sub-section 211 and the second sub-section 212 are connected and arranged along a third direction Z, which is the direction in which bit line 210 extends. The first sub-section 211 is connected to the transistor 110 of memory cell 100, and at least a portion of the second sub-section 212 is connected to the contact post 230.

[0147] In some examples, refer to Figure 10 Each bit line 210 includes two second sub-sections 212, which are distributed on both sides of the memory area AA along the third direction Z.

[0148] When the second sub-part 212 is located on the third-direction Z side of the storage area AA, the contact post 230 is connected to the second sub-part 212 outside the storage area AA. In this case, there are no restrictions on the arrangement of the multiple contact posts 230 outside the storage area AA.

[0149] The following example illustrates the arrangement of multiple contact posts 230 outside the storage area AA, using the first bit line 210C and the second bit line 210D as examples. The terms "first" and "second" in "first bit line 210C" and "second bit line 210D" are relative concepts used only for descriptive purposes to clarify the positions of the two bit lines 210. In practical applications, the first bit line 210C and the second bit line 210D can be any two bit lines 210 that are staggered in the first direction X. Furthermore, depending on the bit lines 210 described, a particular bit line 210 can be either the first bit line 210C or the second bit line 210D.

[0150] In some embodiments, combined with Figure 10 , refer to Figure 6 and Figure 8 Multiple bit lines 210 include a first bit line 210C and a second bit line 210D, with the first bit line 210C being closer to the first surface 200a than the second bit line 210D. Multiple contact posts 230 include a first contact post 230C and a second contact post 230D, with the first contact post 230C connected to the first bit line 210C and the second contact post 230D at least penetrating through the first bit line 210C and connecting to the second bit line 210D.

[0151] In some examples, along the third direction Z, the first contact post 230C is closer to the storage area AA than the second contact post 230D.

[0152] It should be understood that the portion of the second sub-section 212 of the first bit line 210C actually used for signal transmission is the part located between the first contact post 230C and the first sub-section 211 of the first bit line 210C. Similarly, the portion of the second sub-section 212 of the second bit line 210D actually used for signal transmission is the part located between the second contact post 230D and the first sub-section 211 of the second bit line 210D. Therefore, when the first contact post 230C is closer to the memory area AA than the second contact post 230D, along the third direction Z, the length of the portion of the second sub-section 212 of the first bit line 210C actually used for signal transmission is shorter than the length of the portion of the second sub-section 212 of the second bit line 210D actually used for signal transmission.

[0153] On the other hand, the first bit line 210C is closer to the first surface 200a than the second bit line 210D, making the length of the first contact post 230C shorter than the length of the second contact post 230D along the first direction X. Thus, the bit line signal of the first bit line 210C experiences a shorter transmission distance from the first contact post 210C to its first sub-section 211, while the bit line signal of the second bit line 210D experiences a longer transmission distance from the second contact post 230D to its first sub-section 211. This results in a significant difference in signal transmission distance between the first bit line 210C and the second bit line 210D, leading to inconsistent sensing margins for the two bit lines 210.

[0154] In some embodiments, combined with Figure 10 , refer to Figure 6 and Figure 8 Along the third direction Z, the first contact post 230C is farther away from the storage area AA than the second contact post 230D.

[0155] With this configuration, along the third direction Z, the length of the portion of the second sub-section 212 of the first bit line 210C actually used for signal transmission is longer than the length of the portion of the second sub-section 212 of the second bit line 210D actually used for signal transmission. Furthermore, along the first direction X, the length of the first contact post 230C is shorter than the length of the second contact post 230D. Thus, the two lengths can be combined to minimize the difference in signal transmission distance between the first bit line 210C and the second bit line 210D, resulting in more consistent sensing margins for the two bit lines 210.

[0156] In some examples, refer to Figure 11A and Figure 11B Along the direction away from the first surface 200a, the dimensions of multiple bit lines 210 gradually increase along the third direction Z, where the third direction Z is the extension direction of the bit lines 210.

[0157] For example, Figure 11B The line indicated by numeral 221 in the diagram shows the arrangement of the interconnects connected to the gate line 220.

[0158] In some embodiments, refer to Figure 7 and Figure 11A Bit line 210 includes a contact portion 213 located at one end of bit line 210. Contact post 230 is connected to the contact portion 213 of the target bit line 210X. The contact portions 213 of multiple bit lines 210 are staggered sequentially in a third direction Z, where the third direction Z is the extension direction of the bit line 210. Semiconductor device 200 also includes a dielectric layer 280, which covers the contact portions 213 of the multiple bit lines 210. Conductor layer 240 and first insulating layer 250 penetrate the dielectric layer 280.

[0159] For example, the material of the dielectric layer 280 includes at least one of silicon oxide (SiOx), silicon oxynitride (SiON), silicon germanide (SiGe), and silicon nitride (SiNy), wherein the values ​​of x and y are not limited here.

[0160] For example, when bit line 210 includes a second sub-part 212, contact portion 213 may constitute at least a portion of the second sub-part 212.

[0161] In some examples, each bit line 210 includes two contacts 213, which are distributed on both sides of the memory area AA along the third direction Z.

[0162] By staggering the contact portions 213 of the multiple bit lines 210 in the third direction Z, the distance between the contact post 230 and the bit line 210 located on the side of the target bit line 210X near the first surface 200a can be increased. This reduces the coupling effect between the contact 230 and the bit line 210 located on the side of the target bit line 210X near the first surface 200a. With the conductor layer 240 and the first insulating layer 250 penetrating the dielectric layer 280, the conductor layer 240 and the first insulating layer 250 can cover a larger area of ​​the contact post 230. This improves the shielding effect of the conductor layer 240 and enhances the consistency of the sensing margin corresponding to the multiple bit lines 210.

[0163] In some embodiments, refer to Figure 7 and Figure 11A The contact portion 213 of bit line 210 is located outside the storage area AA. Among them, along the third direction Z and from the storage area AA to the contact portion 213 of bit line 210, the size D1 of the plurality of contact posts 230 gradually increases along the first direction X.

[0164] With the above settings, the dimensions D1 of the multiple contact posts 230 along the first direction X can be matched with the positions of the contact portions 213 of the multiple position lines 210.

[0165] In the case where the size D1 of the plurality of contact posts 230 gradually increases along the first direction X in the contact portion 213 from the storage area AA to the bit line 210 in the third direction Z, the size D2 of the multilayer conductor layer 240 along the first direction X is not limited here.

[0166] For example, the dimensions D2 of the multilayer conductor layer 240 along the first direction X can be equal or approximately equal; for another example, along the third direction Z and from the storage area AA to the contact portion 213 of the bit line 210, the dimensions D2 of the multilayer conductor layer 240 along the first direction X gradually decrease.

[0167] In some embodiments, refer to Figure 7 and Figure 11A The dimension D2 of the multilayer conductor layer 240 gradually increases along the first direction X.

[0168] It should be understood that when the dimension D1 of the contact post 230 along the first direction X is large, its outer surface area is relatively large, making it easier to couple with more other conductor structures (e.g., adjacent contact posts 230L, or bit lines 210), resulting in a relatively large surface area to be shielded for the contact post 230 with a larger dimension D1 along the first direction X.

[0169] With the above settings, the variation of dimension D2 of the multilayer conductor layer 240 along the first direction X can be made the same as the variation of dimension D1 of the multiple contact posts 230 along the first direction X. In this way, the dimension D2 of the conductor layer 240 along the first direction X can be matched with the surface area of ​​the contact posts 230 to be shielded, which can improve the shielding effect of the multilayer conductor layer 240 on the multiple contact posts 230 and reduce the coupling effect between the contact posts 230 and the other conductor structures mentioned above. This can improve the consistency of the sensing margin corresponding to the multiple bit lines 210 and make the sensing margin corresponding to the multiple bit lines 210 more convergent.

[0170] In some embodiments, refer to Figure 10 and Figure 11A The semiconductor device 200 includes a plurality of memory layers 100GC stacked in a first direction X, and the memory layers 100GC include a plurality of memory cells 100 arranged in a third direction Z. A bit line 210 is connected to transistors 110 of the plurality of memory cells 100 arranged in the third direction Z in one memory layer 100GC. The gates 114 of the transistors 110 of the plurality of memory cells 100 stacked in the first direction X in the plurality of memory layers 100GC (see reference) Figure 2 The grid lines 220 are connected together.

[0171] It should be understood that when the semiconductor device 200 includes a memory cell array 100G, a plurality of memory layers 100GC arranged in the first direction X form the memory cell array 100G.

[0172] With the above configuration, multiple memory cells 100 arranged in the third direction Z can share a bit line 210, and multiple memory cells 100 arranged in the first direction X can share a gate line 220. In this way, a vertical gate line semiconductor device can be formed, so that the semiconductor device 200 has a 3D architecture, which can improve the storage density.

[0173] In some examples, refer to Figure 10 and Figure 11AThe semiconductor device 200 includes a plurality of memory cell arrays 100G arranged in the second direction Y. The adjacent memory cell arrays 100G are mirror-symmetrically distributed. At this time, the bit lines 210 corresponding to the two memory cell arrays 100G that are mirror-symmetrically distributed can be both set between the two memory cell arrays 100G, that is, the bit lines 210 corresponding to the two memory cell arrays 100G can share the area between the two memory cell arrays 100G.

[0174] For example, refer to Figure 10 and Figure 11A The memory cell array 100G on the left and the memory cell array 100G on the right are mirror-symmetrically distributed. At this time, the bit lines 210 corresponding to the two memory cell arrays 100G can be set between the two memory cell arrays 100G and arranged along the third direction Z (e.g., alternating stacking arrangement).

[0175] With the above configuration, the memory cell array 100G and bit lines 210 of the semiconductor device 200 can be optimally arranged, further improving memory density. In some examples, the bit lines 210 corresponding to two adjacent memory cell arrays 100G can share the same interconnect structure.

[0176] In some embodiments, refer to Figure 12 The semiconductor device 200 also includes a peripheral device 200M. The peripheral device 200M is connected to the bit line 210.

[0177] In some embodiments, the peripheral device 200M includes peripheral circuitry. The peripheral circuitry is configured to control and sense a plurality of memory cells 100 (see reference 100). Figure 1 Peripheral circuitry can be any suitable digital, analog, and / or mixed-signal control and sensing circuitry used to support the operation (or function) of the semiconductor device 200, including but not limited to page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive components of the circuitry (e.g., transistors, diodes, resistors, or capacitors). Peripheral circuitry may also include any other circuitry compatible with advanced logic processes, including logic circuitry (e.g., Programmable Logic Device, or PLD, processor, and programmable logic device) or memory circuitry (e.g., Static random-access memory, or SRAM).

[0178] In some embodiments, refer to Figure 12 The peripheral device 200M is connected to the conductor layer 240 and also to the contact post 230.

[0179] By connecting the peripheral device 200M to the conductor layer 240, the peripheral device 200M can apply a preset voltage to the conductor layer 240 to reduce the coupling effect between adjacent contact posts 230, thereby improving the sensing margin of the memory structure containing multiple memory cells 100. By connecting the peripheral device 200M to the contact posts 230, the peripheral device 200M can access bit line signals to each bit line 210 through the contact posts 230. In this way, under the control of the bit line signals, read or write operations can be performed on the information stored in the capacitor 120 connected to the turned-on transistor 110.

[0180] Some embodiments of this disclosure also provide a storage system 400. (See also...) Figure 13A and Figure 13B The storage system 400 includes a controller 410 and a semiconductor device 200 provided in any of the above embodiments. The controller 410 is coupled to the semiconductor device 200.

[0181] For example, when the semiconductor device 200 includes peripheral devices 200M, the semiconductor device 200 can also be referred to as memory 300 (see reference). Figure 15 At this time, the controller 410 can be used to control the memory 300 to store data.

[0182] In some embodiments, refer to Figure 13A The storage system 400 includes a semiconductor device 200, and the storage system 400 can be integrated into a memory card.

[0183] Memory cards include, for example, any of the following: PC card (Personal Computer Memory Card International Association, PCMCIA), Compact Flash (CF) card, Smart Media (SM) card, Memory Stick, Multimedia Card (MMC), Secure Digital Memory Card (SD) card, and UFS.

[0184] The storage system 400 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an Embedded Multi Media Card (eMMC) package). In other words, the storage system 400 can be applied to and packaged into different types of electronic products, such as mobile phones (e.g., cell phones), desktop computers, tablets, laptops, servers, in-vehicle devices, game consoles, printers, positioning devices, wearable devices, smart sensors, power banks, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic device containing storage.

[0185] In yet other embodiments, reference is made to Figure 13B The storage system 400 includes a controller 410 and a plurality of semiconductor devices 200 (e.g., the memory described above), which can be integrated into a solid state drive (SSD).

[0186] In some embodiments, the controller 410 is configured to operate in a low duty cycle environment, such as an SD card, CF card, Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, and mobile phones.

[0187] In other embodiments, controller 410 is configured to operate in a high duty cycle environment in an SSD or eMMC, which is used as data storage for mobile devices such as smartphones, tablets, and laptops, as well as enterprise storage arrays.

[0188] In some embodiments, the controller 410 may be configured to manage data stored in the semiconductor device 200 and communicate with external devices (e.g., a host).

[0189] In some embodiments, the controller 410 may also be configured to control the operation of the semiconductor device 200, such as read, erase and program operations.

[0190] In some embodiments, the controller 410 may also be configured to manage various functions relating to data stored or to be stored in the semiconductor device 200, including at least one of bad block management, garbage collection, logic-to-physical address translation, and wear leveling.

[0191] In some embodiments, the controller 410 is also configured to process error correction codes for data read from or written to the semiconductor device 200.

[0192] Of course, controller 410 can also perform any other suitable function, such as formatting memory 300; for example, controller 410 can communicate with external devices (e.g., hosts) through at least one of various interface protocols.

[0193] Here, the interface protocol may include at least one of the following: USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI High Speed ​​(PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronic Device (IDE) protocol, and Firewire protocol.

[0194] It is understood that the beneficial effects of the storage system provided by the above embodiments of this disclosure can be referred to the beneficial effects of the semiconductor devices mentioned above, and will not be repeated here.

[0195] Some embodiments of this disclosure also provide an electronic device 500, see reference to Figure 14 The electronic device 500 includes a storage system 400.

[0196] The electronic device 500 includes, but is not limited to, any one of the following: mobile phone, tablet, laptop, television, personal digital assistant (PDA), ultra-mobile personal computer (UMPC), netbook, wearable device (e.g., smartwatch, smart bracelet, smart glasses), etc. The embodiments of this application do not limit the type of electronic device.

[0197] Electronic device 500 may include the storage system 400 described above, and may also include at least one of a central processing unit (CPU) and a cache.

[0198] In some embodiments, refer to Figure 14 The electronic device 500 also includes a circuit board 510 (e.g., a printed circuit board), which is coupled to the storage system 400.

[0199] In some embodiments, circuit board 510 may be a printed circuit board. For example, circuit board 510 may be a multilayer printed circuit board.

[0200] It is understood that the beneficial effects of the electronic device provided by the above embodiments of this disclosure can be referred to the beneficial effects of the storage system described above, and will not be repeated here.

[0201] Figure 15 This is a possible cross-sectional view of an electronic device 500 that includes a storage system 400 in some embodiments, and can also be understood as a possible system block diagram of the electronic device 500. (Refer to...) Figure 15 The storage system 400 may also include an intermediate board 420. One or more memories 300 may be integrated on the intermediate board 420.

[0202] although Figure 15 The storage system 400 is shown to include two memories 300, but the concept of this disclosure is not limited thereto. For example, the storage system 400 may include one memory 300, or it may include three or more memories 300.

[0203] In some examples, the storage system 400 also includes a semiconductor chip 430 integrated on an interposer 420. The semiconductor chip 430 may be, for example, a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, or an application processor (AP) chip. In this case, the controller 410 may be a controller contained within the semiconductor chip 430.

[0204] The storage system 400 may further include a molding layer 440 surrounding the side surfaces of the memory 300 and the semiconductor chip 430. The molding layer 440 may include, for example, EMC (electromagnetic compatibility). In some embodiments, the molding layer 440 may cover the top surfaces of the memory 300 and the semiconductor chip 430. In some other embodiments, the molding layer 440 may not cover the top surfaces of the memory 300 and the semiconductor chip 430.

[0205] Exemplarily, the electronic device may also include a heat dissipation component. The heat dissipation component may be attached to the memory 300 and the semiconductor chip 430 using an intervening thermal interface material (TIM) layer. The TIM layer may be, for example, mineral oil, grease, sealant, phase change gel, phase change material pads, or particulate-filled epoxy resin. The heat dissipation component may be, for example, a heat sink, a heat pipe, or a liquid-cooled cold plate.

[0206] Figure 16 A flowchart illustrating a method for fabricating a semiconductor device 200 provided for some embodiments of this disclosure. Figures 17A to 18D The fabrication steps of the semiconductor device 200 provided for some embodiments of this disclosure are described below. Figure 16 and Figures 17A to 18DIt should be understood that the operations shown in the preparation method are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. It should be noted that... Figures 17A to 18D This is a partial schematic diagram obtained by omitting the part of the semiconductor device 200 except for the connection between bit line 210 and contact post 230.

[0207] In the following embodiments, the deposition process includes, but is not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or electroplating.

[0208] Some embodiments of this disclosure also provide a method for fabricating a semiconductor device 200, combined with Figure 6 , refer to Figure 16 , including S1 to S2.

[0209] S1: Forming bit lines 210. Multiple bit lines 210 are arranged along a first direction X, where the first direction X is the thickness direction of the semiconductor device 200.

[0210] S2: Forming a contact post 230, a conductor layer 240, and a first insulating layer 250. The contact post 230 extends along a first direction X to a target bit line 210X and is connected to the target bit line 210X; the conductor layer 240 is disposed around at least a portion of the contact post 230; the first insulating layer 250 is disposed between the contact post 230 and the conductor layer 240.

[0211] It is understood that the beneficial effects that can be achieved by the method for preparing the semiconductor device 200 provided in the above embodiments of this disclosure can be referred to the beneficial effects of the semiconductor device 200 mentioned above, and will not be repeated here.

[0212] In some embodiments, combined with Figure 1 and Figure 2 Before bit line 210 (i.e. S1) is formed, R1 is also included.

[0213] R1: Forms a memory cell 100. The memory cell 100 includes a transistor 110 and a capacitor 120 arranged along a second direction Y. The capacitor 120 is connected to the transistor 110. The second direction Y is perpendicular to the first direction X and perpendicular to the third direction Z.

[0214] In some examples, storage cell 100 (i.e., R1) is formed, including R1.1 and R1.2.

[0215] R1.1: Forms transistor 110.

[0216] In some examples, transistor 110 includes a vertical gate, in which case transistor 110 (i.e., R1.1) is formed including R1.1.1 to R1.1.4.

[0217] R1.1.1: Formation of channel structure 113 (refer to) Figure 2 ).

[0218] For example, the process of forming the channel structure 113 may include: first forming a stack of silicon oxide layer, silicon nitride layer and silicon oxide layer on a silicon substrate; then forming a plurality of openings arranged in an array, each opening extending vertically through the stack to the silicon substrate, so that a portion of the silicon substrate can be exposed from the openings; and then forming the channel structure 113 in the plurality of openings, the channel structure 113 being epitaxially grown from the corresponding exposed portion of the silicon substrate in the corresponding opening.

[0219] For example, the process of forming the silicon oxide layer, the silicon nitride layer, and the silicon oxide layer may include one or more thin film deposition processes.

[0220] For example, the process of forming multiple openings may include one or more dry etching and / or wet etching processes (e.g., reactive ion etching (RIE)) to etch openings through the silicon oxide layer, silicon nitride layer and silicon oxide layer until stopped by the silicon substrate.

[0221] For example, the process of epitaxially growing the channel structure 113 may include, but is not limited to, vapor-phase epitaxy (VPE), liquid-phase epitaxy (LPE), molecular-beam epitaxy (MPE), or any combination thereof.

[0222] For example, the channel structure 113 may have the same shape as the opening, such as a cube or a cylinder.

[0223] R1.1.2: A gate oxide layer 115 is formed on one or more sides of the channel structure 113 (see reference). Figure 2 ).

[0224] For example, the process of forming the gate oxide layer 115 may include a thin film deposition process.

[0225] R1.1.3: A conductive material is deposited on the side of the gate oxide layer 115 away from the channel structure 113 to form the gate 114 (see reference). Figure 2 ).

[0226] For example, the process of depositing conductive materials may include one or more thin film deposition processes.

[0227] R1.1.4: Doping the two ends of each channel structure 113 to form the source 111 and drain 112 (see reference). Figure 2 ).

[0228] For example, the doping methods of the source 111 and the drain 112 include ion implantation or diffusion processes, but are not limited thereto.

[0229] R1.2: A capacitor 120 is formed on one side of transistor 110.

[0230] In some examples, capacitor 120 (i.e., S1.2) is formed, including R1.2.1 to R1.2.3.

[0231] R1.2.1: A second dielectric layer is formed on one side of transistor 110.

[0232] For example, one or more deposition processes may be used to form the second dielectric layer.

[0233] R1.2.2: Forms a capacitor hole that penetrates the second dielectric layer, with one end of the capacitor hole connected to the source 111 or drain 112 of transistor 110.

[0234] For example, multiple capacitor holes penetrating the second dielectric layer can be formed by dry etching, wet etching, or acid etching.

[0235] R1.2.3: Form capacitor 120 inside the capacitor hole (refer to...) Figure 2 ).

[0236] For example, materials for a first electrode, a first dielectric layer, and a second electrode can be sequentially deposited within the capacitor hole to form a capacitor 120.

[0237] In some embodiments, bit line 210 (i.e. S1) is formed, including S1.1 to S1.3.

[0238] S1.1: Forming a second stacked structure, the second stacked structure comprising alternating layers of dielectric layers 291 (see reference). Figure 10 ) and sacrificial layer (not shown in the figure).

[0239] In some examples, the second stacked structure is formed on a substrate. The substrate is, for example, a silicon substrate.

[0240] For example, a thin-film deposition process can be used to alternately deposit the material of the dielectric layer 291 and the material of the sacrificial layer to form a second stacked structure.

[0241] For example, the material of the dielectric layer 291 includes at least one of silicon oxide (SiOx), silicon oxynitride (SiON), silicon germanide (SiGe), and silicon nitride (SiNy), wherein the values ​​of x and y are not limited here.

[0242] For example, when the contact portions 213 of multiple bit lines 210 are staggered in the third direction Z, the multiple dielectric layers 291 are connected to form a dielectric layer 280.

[0243] For example, the material of the sacrificial layer can be silicon (Si) or polycrystalline silicon (Poly-Si).

[0244] S1.2: Remove the sacrificial layer to form a cavity (not shown in the figure).

[0245] For example, the sacrificial layer can be removed by acid etching or wet etching to form a cavity.

[0246] S1.3: A bit line 210 is formed within the cavity. The dielectric layer 291 and the bit line 210 are alternately stacked to form a first stacked structure DD.

[0247] For example, conductive material can be deposited within the cavity to form bit lines 210.

[0248] For example, the conductive material deposited within the cavity (the material of bit line 210) includes tantalum nitride. Of course, the material of bit line 210 may also include other conductive materials, and there is no limitation herein.

[0249] In some examples, where the conductive material deposited in the cavity includes a metallic element, during the formation of bit line 210 in the cavity, the silicon material and the conductive material in the portion of the cavity near transistor 110 can react to generate metal silicide, thereby achieving ohmic contact between bit line 210 and the source 111 or drain 112 of transistor 110.

[0250] In some embodiments, a contact post 230, a conductor layer 240, and a first insulating layer 250 (i.e., S2) are formed, including S2.1 to S2.6.

[0251] S2.1: Reference Figure 17A A contact hole Q1 is formed, and the contact hole Q1 extends along the first direction X to the target bit line 210X.

[0252] For example, the process of forming contact hole Q1 may include one or more dry etching and / or wet etching processes (e.g., reactive ion etching) to penetrate the first stacked structure DD until it stops at target bit line 210X.

[0253] For example, refer to Figure 17AOf the two ends of the contact hole Q1 that are positioned opposite each other along the first direction X, the diameter of the end that is closer to the first surface 200a is larger than the diameter of the end of the contact hole Q1 that is farther away from the first surface 200a.

[0254] S2.2: Reference Figure 17C A conductor layer 240 is formed, which covers the hole wall and bottom surface of the contact hole Q1.

[0255] For example, a deposition process can be used to form the conductor layer 240.

[0256] S2.3: Reference Figure 17D or Figure 18A A first through hole K1 is formed, which penetrates the conductor layer 240 located at the bottom of the contact hole Q1, exposing the target bit line 210X.

[0257] For example, the process of forming the first via K1 may include one or more dry etching and / or wet etching processes to penetrate the conductor layer 240 until it stops at the target bit line 210X.

[0258] In some examples, refer to Figure 17D The diameter of the first through-hole K1 is relatively large, making the conductor layer 240 have a cylindrical structure extending along the first direction X. As mentioned above, this configuration provides a relatively large space for forming the first insulating layer 250 and the contact post 230, which can reduce the process difficulty of forming the first insulating layer 250 and the contact post 230 to a certain extent.

[0259] In some examples, refer to Figure 18A The aperture of the first via K1 is relatively small, causing the conductor layer 240 to include a first portion 241 and a second portion 242. For an understanding of the first portion 241 and the second portion 242, please refer to the preceding descriptions; they will not be repeated here. This configuration, as mentioned earlier, reduces the technological difficulty of forming the first via K1, thereby reducing the technological difficulty of forming the conductor layer 240 and the first insulating layer 250.

[0260] S2.4: Reference Figure 17E or Figure 18B A first insulating layer 250 is formed, which covers the conductor layer 240 and the exposed target bit line 210X.

[0261] For example, a deposition process can be used to form the first insulating layer 250.

[0262] S2.5: Reference Figure 17F or Figure 18C This forms a second through hole K2, which penetrates the contact hole Q1 (see reference). Figure 17A The first insulating layer 250 at the bottom exposes the target bit line 210X. The diameter D3 of the first through hole K1 is larger than the diameter D4 of the second through hole K2.

[0263] For example, the process of forming the second via K2 may include one or more dry etching and / or wet etching processes to penetrate the first insulating layer 250 until it stops at the target bit line 210X.

[0264] S2.6: Reference Figure 17G or Figure 18D Within the contact hole Q1, the gap Q2 formed by the first insulating layer 250 (refer to...) Figure 17F or Figure 18C A contact post 230 is formed inside the second through hole K2 and connected to the target position line 210X.

[0265] For example, the contact post 230 can be formed by depositing material of the contact post 230 in the void Q2 surrounded by the first insulating layer 250.

[0266] By configuring S2, including S2.1 to S2.6, a contact post 230, a conductor layer 240, and a first insulating layer 250 can be formed. The first insulating layer 250 is arranged around the contact post 230, and the conductor layer 240 is arranged around the first insulating layer 250. Thus, as mentioned above, the shielding effect between the target contact post 230X and multiple adjacent contact posts 230L can be achieved using a single conductor layer 240. This simplifies the formation process of the conductor layer 240 while ensuring its shielding effect.

[0267] Furthermore, by setting the aperture D3 of the first through hole K1 to be larger than the aperture D4 of the second through hole K2, the material of the first insulating layer 250 located inside the conductor layer 240 can be retained during the formation of the second through hole K2 in S2.5, so that the conductor layer 240 can be insulated from the contact post 230 formed in S2.6. In this way, interference between the preset voltage and the bit line signal can be avoided, thereby improving the reliability when the preset voltage is connected to the conductor layer 240 and the bit line signal is connected to the contact post 230.

[0268] In some embodiments, the preparation method further includes step S2.2F after forming the contact hole Q1 (i.e., S2.1) and before forming the conductor layer 240 (i.e., S2.2).

[0269] S2.2F: Combination Figure 17A , refer to Figure 17B This forms a third insulating layer 292. The third insulating layer 292 covers the hole wall and bottom surface of the contact hole Q.

[0270] The first through hole K1 also penetrates the third insulating layer 292 located at the bottom of the contact hole Q; the portion of the third insulating layer 292 covering the hole wall of the contact hole Q forms a second insulating layer 270, and the portion of the third insulating layer 292 located at the bottom surface of the contact hole Q forms an insulating pattern 260.

[0271] For example, a deposition process can be used to form the third insulating layer 292.

[0272] With the above configuration, a second insulating layer 270 can be formed on the side of the conductor layer 240 away from the first insulating layer 250, and an insulating pattern 260 can be formed between the conductor layer 240 and the target bit line 210X. Thus, as described above, the second insulating layer 270 prevents interference between the preset voltage applied to the conductor layer 240 and signals connected to other conductor structures in the semiconductor device 200; the insulating pattern 260 prevents interference between the preset voltage applied to the conductor layer 240 and the bit line signal connected to the target bit line 210X.

[0273] Furthermore, in S2.2F, the formed second insulating layer 270 is disposed around the conductor layer 240, and the formed insulating pattern 260 is disposed around the second end 232 of the contact post 230. In this way, the second insulating layer 270 and the insulating pattern 260 can be formed in one step of S2.2F, which simplifies the formation of the second insulating layer 270 and the insulating pattern 260 and simplifies the fabrication method of the semiconductor device 200.

[0274] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A semiconductor device, characterized in that, include: Bit lines, a plurality of said bit lines are arranged along a first direction; the first direction is the thickness direction of said semiconductor device; A contact post extends along the first direction to the target bit line and connects to the target bit line; A conductor layer is disposed around at least a portion of the contact post; A first insulating layer is disposed between the contact post and the conductor layer.

2. The semiconductor device according to claim 1, characterized in that, The first insulating layer is disposed around the contact post, and the conductor layer is disposed around the first insulating layer.

3. The semiconductor device according to claim 2, characterized in that, The semiconductor device further includes: An insulating pattern; in the first direction, the insulating pattern is located between the conductor layer and the target bit line, and the conductor layer is insulated from the target bit line.

4. The semiconductor device according to claim 3, characterized in that, Along the first direction, the contact post has a first end and a second end, the second end being closer to the target bit line than the first end; the insulating pattern is disposed around the second end of the contact post.

5. The semiconductor device according to claim 3, characterized in that, The conductor layer includes a first part and a second part that are interconnected. The first part is a cylindrical structure extending along the first direction. The second part is located on the side of the first part near the target bit line and extends along a fourth direction that intersects the first direction. The insulating pattern is located between the second portion and the target bit line; The first insulating layer has a first edge portion and a second edge portion arranged along the first direction, wherein the second edge portion is closer to the target bit line than the first edge portion; The second edge of the first insulating layer penetrates the second portion of the conductor layer and connects to the insulating pattern.

6. The semiconductor device according to claim 3, characterized in that, The semiconductor device further includes: A second insulating layer is disposed around the conductor layer.

7. The semiconductor device according to claim 6, characterized in that, In a direction perpendicular to the first direction, the second insulating layer is located between the contact post and the bit line.

8. The semiconductor device according to claim 6, characterized in that, The insulating pattern is made of the same material as the second insulating layer.

9. The semiconductor device according to any one of claims 1 to 8, characterized in that, The semiconductor device includes a first surface and a second surface opposite each other in the first direction, and the contact post extends from the first surface along the first direction to the target bit line; the contact post passes through the bit line located on the side of the target bit line closer to the first surface; The conductor layer and the first insulating layer penetrate the bit line located on the side of the target bit line near the first surface.

10. The semiconductor device according to claim 9, characterized in that, The plurality of bit lines include: a first bit line and a second bit line, wherein the first bit line is closer to the first surface than the second bit line; The plurality of contact posts include: a first contact post and a second contact post, wherein the first contact post is connected to the first bit line, and the second contact post at least penetrates the first bit line and is connected to the second bit line; The semiconductor device includes a storage region having a plurality of storage cells; along a third direction, the first contact post is farther away from the storage region than the second contact post, and the third direction is the extension direction of the bit line.

11. The semiconductor device according to any one of claims 1 to 8, characterized in that, The bit line includes a contact portion located at one end of the bit line, and the contact post is connected to the contact portion of the target bit line; The contact portions of the multiple bit lines are staggered sequentially in a third direction, where the third direction is the extension direction of the bit lines; The semiconductor device further includes: a dielectric layer covering the contact portion of the plurality of bit lines; The conductor layer and the first insulating layer penetrate the dielectric layer.

12. The semiconductor device according to claim 11, characterized in that, The semiconductor device includes a memory region having multiple memory cells, and the contact portion of the bit line is located outside the memory region; Among them, along the third direction and from the storage area to the bit line, the dimensions of the plurality of contact pillars gradually increase along the first direction, and the dimensions of the multiple conductor layers gradually increase along the first direction.

13. The semiconductor device according to any one of claims 1 to 8, characterized in that, The semiconductor device includes: a multilayer memory layer stacked in the first direction, the memory layer including a plurality of memory cells arranged in a third direction, the third direction being the extension direction of the bit line; The storage cell includes a transistor and a capacitor arranged along a second direction, the capacitor being connected to the transistor, the second direction being perpendicular to the first direction and also perpendicular to the third direction; One of the bit lines is connected to a transistor of a plurality of memory cells arranged in the third direction in one of the memory layers; In the multilayer memory layer, the gates of the transistors of a plurality of memory cells that are stacked in the first direction are connected to form a gate line.

14. The semiconductor device according to any one of claims 1 to 8, characterized in that, The semiconductor device further includes: Peripheral devices are connected to the bit line; The peripheral device is connected to the conductor layer and also to the contact post.

15. A storage system, characterized in that, include: The semiconductor device as described in any one of claims 1 to 14; The controller is coupled to the semiconductor device.

16. A method for fabricating a semiconductor device, characterized in that, include: Bit lines are formed, and multiple bit lines are arranged along a first direction, which is the thickness direction of the semiconductor device; A contact post, a conductor layer, and a first insulating layer are formed, wherein the contact post extends along the first direction to a target bit line and is connected to the target bit line; the conductor layer is disposed around at least a portion of the contact post; and the first insulating layer is disposed between the contact post and the conductor layer.

17. The method for fabricating a semiconductor device according to claim 16, characterized in that, The formation of the contact post, conductor layer, and first insulating layer includes: A contact hole is formed, the contact hole extending along the first direction to the target bit line; A conductor layer is formed, which covers the hole wall and bottom surface of the contact hole; A first through-hole is formed, which penetrates the conductor layer located at the bottom of the contact hole to expose the target bit line; A first insulating layer is formed, which covers the conductor layer and the exposed target bit line; A second through-hole is formed, which penetrates the first insulating layer located at the bottom of the contact hole, exposing the target bit line; A contact post is formed within the contact hole and the gap enclosed by the first insulating layer, and the contact post passes through the second through hole and connects to the target bit line; The diameter of the first through hole is larger than the diameter of the second through hole.

18. The method for fabricating a semiconductor device according to claim 17, characterized in that, Prior to forming the conductor layer, the fabrication method further includes: A third insulating layer is formed, which covers the hole wall and bottom surface of the contact hole; The first through hole also penetrates a third insulating layer located at the bottom of the contact hole; the portion of the third insulating layer covering the hole wall of the contact hole forms a second insulating layer, and the portion of the third insulating layer located at the bottom surface of the contact hole forms an insulating pattern.

Images