Semiconductor devices, methods and systems for fabricating the same, and methods of measuring overlay error

Abstract

This disclosure provides a semiconductor device and its fabrication method and system, as well as a method for measuring overlay error. The semiconductor device includes at least two semiconductor bodies, a conductive structure, and an insulating structure. The semiconductor bodies extend along a first direction, and the two semiconductor bodies are arranged in a second direction. The conductive structure is located between the two semiconductor bodies and extends along a third direction. The conductive structure includes a first side, a second side, and a connecting portion, wherein the first side and the second side are disposed opposite to each other in the second direction, and the connecting portion is connected to the ends of the first side and the second side in the first direction. The insulating structure extends along the first direction from the side of the first side facing away from the connecting portion and contacts the first side. The first direction, the second direction, and the third direction intersect each other.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a semiconductor device, a memory system, a method for fabricating a semiconductor device, and a method for measuring overlay error. Background Technology

[0002] Semiconductor devices can be used in memory, such as Dynamic Random Access Memory (DRAM). DRAM is widely used in electronic devices such as computers and mobile phones due to its simple structure, large capacity, high density, low power consumption, and high speed. During the fabrication of semiconductor devices, the accuracy of overlay between different process layers affects the yield of the semiconductor device. Summary of the Invention

[0003] In a first aspect, some embodiments of this disclosure provide a semiconductor device. The semiconductor device includes at least two semiconductor bodies, a conductive structure, and an insulating structure. The semiconductor bodies extend along a first direction, and the two semiconductor bodies are arranged in a second direction. The conductive structure is located between the two semiconductor bodies and extends along a third direction. The conductive structure includes a first side, a second side, and a connecting portion, wherein the first side and the second side are disposed opposite to each other in the second direction, and the connecting portion is connected to the ends of the first side and the second side in the first direction. The insulating structure extends along the first direction from the side of the first side facing away from the connecting portion and contacts the first side. The first direction, the second direction, and the third direction intersect each other.

[0004] In an exemplary embodiment, in the first direction, the surface of the insulating structure facing away from the connection portion is coplanar with the end face of the semiconductor body.

[0005] In an exemplary embodiment, the dimension of the insulating structure in the second direction is equal to the dimension of the first side portion in the second direction.

[0006] In an exemplary embodiment, the material of the insulating structure includes silicon nitride.

[0007] In an exemplary embodiment, in the first direction, the surface of the second side facing away from the connecting portion is located between the opposing surfaces of the insulating structure in the first direction.

[0008] In an exemplary embodiment, the semiconductor device further includes a dielectric layer. The dielectric layer is located between the insulating structure and the semiconductor body; wherein the material of the dielectric layer is different from the material of the insulating structure.

[0009] In an exemplary embodiment, a plurality of insulating structures are arranged at intervals in a third-direction upward direction, with a first side extending between adjacent insulating structures.

[0010] In an exemplary embodiment, the distance between adjacent insulating structures on the third side is greater than 500 nm.

[0011] In an exemplary embodiment, the insulating structure extends along a third direction.

[0012] In an exemplary embodiment, two first sides of adjacent conductive structures in the second direction and corresponding insulating structures are symmetrically arranged with respect to a row of semiconductor bodies arranged in the third direction.

[0013] In an exemplary embodiment, two first sides of an adjacent conductive structure in the second direction are located between two second sides.

[0014] In an exemplary embodiment, the semiconductor device further includes a storage container, wherein, in a plane perpendicular to the first direction, the storage container includes a first region and a second region surrounding the first region, with an insulating structure located within the second region.

[0015] In an exemplary embodiment, the insulating structure is located on opposite sides of the first region in the third direction and arranged in the second direction.

[0016] In an exemplary embodiment, multiple storage repositories are arranged in an array on a plane perpendicular to the first direction, and an insulating structure is disposed within a second zone of one or more storage repositories.

[0017] Secondly, some embodiments of this disclosure provide a memory system. The memory system includes a memory and a controller, the memory including semiconductor devices as mentioned in any of the embodiments described above. The controller is coupled to the memory and is used to control the memory to store data.

[0018] Thirdly, some embodiments of this disclosure provide a method for fabricating a semiconductor device. The method includes: forming at least two semiconductor bodies, wherein the semiconductors extend along a first direction, and the two semiconductor bodies are arranged in a second direction to form a trench extending along a third direction; forming a conductive layer on the sidewalls and bottom of the trench, and forming a first insulating layer inside the conductive layer, wherein the first insulating layer extends to one side of the semiconductor body in the first direction; etching the first insulating layer to form a marking opening, wherein the marking opening exposes a portion of the conductive layer formed on one sidewall of the trench; and replacing the portion of the conductive layer formed on one sidewall with an insulating structure via the marking opening; wherein the first direction, the second direction, and the third direction intersect each other.

[0019] In an exemplary embodiment, multiple marker openings are arranged at intervals in the third direction upwards, and the distance between adjacent marker openings in the third direction upwards is greater than 500 nm.

[0020] In an exemplary embodiment, the marking opening extends along a third direction.

[0021] In an exemplary embodiment, the marking opening and the semiconductor body are aligned in a first direction.

[0022] In an exemplary embodiment, after replacing a portion of the conductive layer formed on one sidewall with an insulating structure via a marked opening, the fabrication method further includes: removing a portion of the first insulating layer extending to one side of the semiconductor body in a first direction; and removing a portion of the remaining conductive layer located at the opening of the trench.

[0023] Fourthly, some embodiments of this disclosure also provide a method for measuring overlay error. This method includes: forming at least two semiconductor bodies, wherein the semiconductors extend along a first direction, and the two semiconductor bodies are arranged in a second direction to form a trench extending along a third direction; forming a conductive layer on the sidewalls and bottom of the trench, and forming a first insulating layer inside the conductive layer, wherein the first insulating layer extends to one side of the semiconductor body in the first direction; etching the first insulating layer to form a marking opening, wherein the marking opening exposes a portion of the conductive layer formed on one sidewall of the trench; and measuring the overlay error based on the marking opening; wherein the first direction, the second direction, and the third direction intersect each other.

[0024] In an exemplary embodiment, multiple marker openings are arranged at intervals in the third direction upwards, and the distance between adjacent marker openings in the third direction upwards is greater than 500 nm.

[0025] In an exemplary embodiment, the marking opening extends along a third direction.

[0026] In an exemplary embodiment, measuring overlay error based on the marking openings includes: acquiring optical information of multiple marking openings using a light spot. Attached Figure Description

[0027] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. Wherein:

[0028] Figure 1A This is a cross-sectional schematic diagram of a semiconductor device provided in an embodiment of this disclosure;

[0029] Figure 1B yes Figure 1A An enlarged schematic diagram of region A is shown;

[0030] Figure 1C It is along Figure 1B The diagram shows a cross-section cut by line I-I'.

[0031] Figure 1DThis is a three-dimensional schematic diagram of the conductive and insulating structures in the semiconductor device provided in the embodiments of this disclosure;

[0032] Figure 2A A cross-sectional schematic diagram of a semiconductor device provided in another embodiment of this disclosure;

[0033] Figure 2B It is along Figure 2A The diagram shows a cross-section cut by line I-I'.

[0034] Figure 2C This is a three-dimensional schematic diagram of the conductive and insulating structures in a semiconductor device provided in another embodiment of this disclosure;

[0035] Figure 3 This is a schematic flowchart of a method for fabricating a semiconductor device according to an embodiment of this disclosure;

[0036] Figures 4A to 8 This is a cross-sectional schematic diagram of the semiconductor device provided in the embodiments of this disclosure during the fabrication process;

[0037] Figures 9A to 13 This is a cross-sectional schematic diagram of the semiconductor device provided in the embodiments of this disclosure during the fabrication process;

[0038] Figure 14 This is a schematic flowchart of the overlay error measurement method provided in the embodiments of this disclosure;

[0039] Figure 15 This is a schematic block diagram of a system with a memory system provided in the embodiments of this disclosure; and

[0040] Figure 16A and Figure 16B This is a schematic block diagram of a memory system provided in an embodiment of this disclosure. Detailed Implementation

[0041] To better understand this disclosure, various aspects of this disclosure will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this disclosure and are not intended to limit the scope of this disclosure in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0042] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features, especially not any order of precedence. Therefore, without departing from the teachings of this disclosure, the first side discussed herein may also be referred to as the second side, and vice versa.

[0043] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. As used herein, the terms “approximately,” “about,” and similar terms are used as expressions of approximation, not as expressions of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0044] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this disclosure, the word "may" is used to mean "one or more embodiments of this disclosure." And the term "exemplary" is intended to refer to an example or illustration.

[0045] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should also be understood that, unless expressly stated in this disclosure, terms as defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0046] It should be noted that, unless otherwise specified, the embodiments and features described in this disclosure can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this disclosure are not limited to the order in which they are described, but can be performed in any order or in parallel.

[0047] Furthermore, when the term “connection” or “linkage” is used in this disclosure, it may indicate direct or indirect contact between the corresponding components, unless otherwise expressly defined or deduced from the context.

[0048] This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0049] This disclosure provides a semiconductor device through some embodiments. Figure 1A This is a cross-sectional schematic diagram of a semiconductor device provided in an embodiment of this disclosure. Figure 1B yes Figure 1A An enlarged schematic diagram of region A is shown. Figure 1C It is along Figure 1B The diagram shows a cross-section cut by line I-I'. Figure 1D This is a three-dimensional schematic diagram of the conductive and insulating structures in the semiconductor device provided in the embodiments of this disclosure.

[0050] It should be noted that the D1 direction (corresponding to the first direction), D2 direction (corresponding to the second direction), and D3 direction (corresponding to the third direction) in the following figures illustrate the spatial relationships of the components in the semiconductor device. For example, D1 may be the extension direction of the semiconductor body, and the D2 and D3 directions may be two directions that intersect (e.g., are perpendicular) to each other on planes that intersect (e.g., are perpendicular) to the aforementioned extension directions. The same concepts will be used throughout this disclosure to describe the spatial relationships of the components in the semiconductor device.

[0051] like Figures 1A to 1D As shown, the semiconductor device 100 may include at least two semiconductor bodies 110, a conductive structure 120, and an insulating structure 130. The semiconductor bodies 110 extend along the D1 direction, and the two semiconductor bodies 110 are arranged in the D2 direction. The conductive structure 120 is located between the two semiconductor bodies 110 and extends along the D3 direction. The conductive structure 120 includes a first side portion 121, a second side portion 122, and a connecting portion 123. The first side portion 121 and the second side portion 122 are disposed opposite each other in the D2 direction. The connecting portion 123 is connected to the ends of the first side portion 121 and the second side portion 122 in the D1 direction. The insulating structure 130 extends along the D1 direction from the side of the first side portion 121 facing away from the connecting portion 123 and contacts the first side portion 121.

[0052] Compared to some embodiments that add additional overlay marks (typically located in the dicing area), the insulating structure 130 in the semiconductor device 100 serves as the overlay mark structure. The insulating structure 130 can be associated with the position of a component with a similar actual function (i.e., the conductive structure 120), thereby enabling more accurate overlay error.

[0053] In some implementations, such as Figures 1A to 1D As shown, the semiconductor body 110 may have a larger dimension in the D1 direction than its dimension in the D2 direction and may also have a larger dimension in the D3 direction, so that the semiconductor body 110 can extend generally along the D1 direction. For example, the semiconductor body 110 may be generally columnar (e.g., a tetragonal prism).

[0054] In some embodiments, the material of the semiconductor body 110 may include silicon, germanium, silicon germanium, silicon carbide, gallium nitride, or any other suitable semiconductor material. For example, the material of the semiconductor body 110 may be silicon (e.g., single-crystal silicon).

[0055] In some embodiments, a plurality of semiconductor bodies 110 may be arranged at intervals in the D2 and D3 directions. For example, some semiconductor bodies 110 arranged in the D3 direction may be referred to as a row of semiconductor bodies 110. Some semiconductor bodies 110 arranged in the D2 direction may be referred to as a column of semiconductor bodies 110. For instance, a row of semiconductor bodies 110 may be aligned with each other in the D3 direction, and a column of semiconductor bodies 110 may be aligned with each other in the D2 direction.

[0056] In some embodiments, when the semiconductor device 100 is in its current placement position, a plurality of semiconductor bodies 110 may be located above the semiconductor layer 141. The semiconductor layer 141 may extend along the D2 and D3 directions. The semiconductor layer 141 and the semiconductor bodies 110 may be made of the same material. Thus, there may be no obvious interface between the semiconductor layer 141 and the semiconductor bodies 110, and they may be a single integrated structure. Alternatively, the semiconductor device 100 may not have the semiconductor layer 141, and the bottoms of a row of semiconductor bodies 110 may be connected to each other, while the bottoms of a line of semiconductor bodies 110 may be spaced apart (not shown).

[0057] In some embodiments, the dimensions of the first side portion 121 of the conductive structure 120 in both the D3 and D1 directions are larger than its dimension in the D2 direction. The first side portion 121 may be a plate-like structure having thickness in the D2 direction. The first side portion 121 may include an extension 1211 and a plurality of protrusions 1212. The extension 1211 may extend in the D3 direction and contact the connecting portion 123. The plurality of protrusions 1212 may be located on the side of the extension 1211 facing away from the connecting portion 123 in the D1 direction and may contact the extension 1211. The plurality of protrusions 1212 may be spaced apart in the D3 direction. For example, the dimensions l1 of each protrusion 1212 in the D3 direction may be equal. The dimensions of adjacent protrusions 1212 in the D3 direction may be equal. As another example, the surfaces of the plurality of protrusions 1212 facing away from the extension 1211 in the D1 direction are coplanar (e.g., substantially flush). When the semiconductor device 100 is in its current position, the upper surface of the protrusion 1212 is lower than the upper surface of the semiconductor body 110.

[0058] In some embodiments, the dimensions of the second side 122 of the conductive structure 120 in both the D3 and D1 directions are larger than its dimension in the D2 direction. The second side 122 may be a plate-like structure having thickness in the D2 direction. For example, when the semiconductor device 100 is in its current placement position, the upper surface of the second side 122 may be lower than the upper end face of the semiconductor body 110. The upper surface of the second side 122 is coplanar with (e.g., substantially flush with) the upper surface of the protrusion 1212.

[0059] In some embodiments, the first side portion 121 and the second side portion 122 may be arranged substantially parallel to each other. For example, viewed from the D3 direction, the first side portion 121, the second side portion 122, and the connecting portion 123 may be substantially U-shaped.

[0060] In some embodiments, the material of the conductive structure 120 may include one or more of titanium, titanium nitride, tantalum, tantalum nitride, tungsten, molybdenum, copper, aluminum, ruthenium, or any other suitable conductive material. For example, the first side 121, the second side 122, and the connecting portion 123 may be made of the same material, and there may be no obvious interface between them, and they may be an integral structure.

[0061] In some embodiments, there may be multiple insulating structures 130. These multiple insulating structures 130 may be spaced apart in the D3 direction. A first side portion 121 (e.g., a protrusion 1212) may extend between adjacent insulating structures 130. For example, each insulating structure 130 contacts an extension 1211 in the first side portion 121 in the D1 direction and contacts the protrusion 1212 in the D3 direction. Alternatively, each insulating structure 130 may have approximately the same dimensions in the D3 direction.

[0062] In some embodiments, the distance l1 between adjacent insulating structures 130 in the D3 direction can be greater than 500 nm. For example, this distance l1 can be 510 nm, 550 nm, 600 nm, 650 nm, 700 nm, 750 nm, 800 nm, 850 nm, 900 nm, 950 nm, 1000 nm, 1050 nm, 1100 nm, etc. This disclosure does not impose specific limitations on the value of the distance l1. When the distance l1 is greater than 500 nm, not only can the density requirements for overlay error measurement be met, but the structural stability of the semiconductor device 100 can also be guaranteed, which helps to improve the yield of the semiconductor device 100.

[0063] In some embodiments, the dimension of the insulating structure 130 in the D2 direction may be equal to the dimension of the first side portion 121 in the D2 direction. For example, the dimensions of the extension 1211 and the protrusion 1212 in the D2 direction in the first side portion 121 may be equal. The opposing surfaces of the insulating structure 130 in the D2 direction are coplanar with the opposing surfaces of the first side portion 121 in the D2 direction.

[0064] In some embodiments, in the D1 direction, the surface of the insulating structure 130 facing away from the connection portion 123 may be coplanar with the end face of the semiconductor body 110. For example, the end face of the semiconductor body 110 may be the end face of the semiconductor body 110 facing away from the semiconductor layer 141 in the D1 direction.

[0065] In some embodiments, in the D1 direction, the surface of the second side 122 facing away from the connection portion 123 is located between the opposing surfaces of the insulating structure 130 in the D1 direction. For example, when the semiconductor device 100 is in its current placement position, the upper surface of the insulating structure 130 is higher than the upper surface of the second side 122, and the lower surface of the insulating structure 130 may be lower than the upper surface of the second side 122.

[0066] In some embodiments, the material of the insulating structure 130 may include one or more of silicon oxide, silicon nitride, silicon oxynitride, high dielectric constant materials, or any other suitable insulating material. High dielectric constant materials may include aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, or zirconium oxide. For example, the material of the insulating structure 130 may be silicon nitride.

[0067] In some implementations, such as Figures 1A to 1D As shown, the semiconductor device 100 may further include a dielectric layer 142. The dielectric layer 142 may be located between the insulating structure 130 and the semiconductor body 110. For example, the dielectric layer 142 may be in contact with the insulating structure 130 and the semiconductor body 110. Optionally, the dielectric layer 142 may also be located between the conductive structure 120 and the semiconductor body 110. For example, the dielectric layer 142 may also be in contact with the conductive structure 120 and the semiconductor body 110.

[0068] In some embodiments, the material of dielectric layer 142 may include one or more of silicon oxide, silicon nitride, silicon oxynitride, high dielectric constant materials, or any other suitable insulating material. The material of dielectric layer 142 may differ from the material of insulating structure 130. For example, the material of dielectric layer 142 may be silicon oxide.

[0069] In some implementations, such as Figures 1A to 1D As shown, there can be multiple conductive structures 120. These conductive structures 120 are arranged at intervals in the D2 direction. Each conductive structure 120 can be located between two adjacent rows of semiconductor bodies 110 in the D2 direction. Two first sides 121a, 121b of adjacent conductive structures 120 in the D2 direction, and corresponding insulating structures 130a, 130b, are symmetrically arranged with respect to a row of semiconductor bodies 110 (e.g., mirror image). In other words, two first sides 121a, 121b of adjacent conductive structures 120 in the D2 direction can be located between two second sides 122a, 122b.

[0070] In some implementations, such as Figures 1A to 1DAs shown, the semiconductor device 100 may further include a storage bank. For a single storage bank, on a plane perpendicular to the D1 direction, the storage bank may include a first region R1 (white area) and a second region R2 (gray area). The second region R2 may surround the first region R1. For example, the first region R1 and the second region R2 may be insulated from each other. The insulating structure 130 described above may be located within the second region R2. For example, the memory cell for implementing the storage function may be located within the first region R1, which may also be referred to as the storage area. Some components located within the second region R2 may be similar to some components located within the first region R1 (e.g., conductive structures), but do not include memory cells. The second region R2 may also be referred to as a dummy storage area. In this embodiment, the insulating structure 130 being located within the second region R2 allows for the use of a dummy storage area to set up an overlay label structure (i.e., the insulating structure 130) without occupying a storage area, thus helping to improve the utilization rate of the dummy storage area.

[0071] In some implementations, such as Figure 1A and Figure 1B As shown, multiple insulating structures 130 can be provided within region A. In a single storage bank, multiple regions A can be located on opposite sides of the first region R1 in the D3 direction and arranged in the D2 direction. In this embodiment, providing multiple regions A containing multiple insulating structures 130 within the second region R2 can further achieve more accurate overlay errors through higher-order compensation.

[0072] In some implementations, there may be multiple storage banks. Multiple storage banks may be arranged in an array on a plane perpendicular to the D1 direction. For example, the areas of the multiple storage banks perpendicular to the D1 direction may be the same or different. Multiple regions A containing multiple insulating structures 130 may be located within a second region R2 of one or more storage banks. For example, each storage bank's second region R2 may contain the same number and location of regions A, and each region A may contain the same number of insulating structures 130.

[0073] Figure 2A This is a cross-sectional schematic diagram of a semiconductor device provided in another embodiment of this disclosure. Figure 2B It is along Figure 2A The diagram shows a cross-section cut by line I-I'. Figure 2C This is a three-dimensional schematic diagram of the conductive and insulating structures in a semiconductor device according to another embodiment of this disclosure. For the purpose of brevity, the same content as in the previous embodiment will not be repeated in this embodiment.

[0074] like Figures 2A to 2CAs shown, the semiconductor device 200 may include at least two semiconductor bodies 210, a conductive structure 220, and an insulating structure 230. The semiconductor bodies 210 extend along the D1 direction, and the two semiconductor bodies 210 are arranged in the D2 direction. The conductive structure 220 is located between the two semiconductor bodies 210 and extends along the D3 direction. The conductive structure 220 includes a first side portion 221, a second side portion 222, and a connecting portion 223. The first side portion 221 and the second side portion 222 are disposed opposite each other in the D2 direction. The connecting portion 223 is connected to the ends of the first side portion 221 and the second side portion 222 in the D1 direction. The insulating structure 230 extends along the D1 direction from the side of the first side portion 221 facing away from the connecting portion 223 and contacts the first side portion 221.

[0075] In some embodiments, the dimensions of the first side portion 221 of the conductive structure 220 in the D1 direction can be the same along the D3 direction. When the semiconductor device 200 is in its current placement position, the upper surface of the first side portion 221 is lower than the upper surface of the semiconductor body 210 and also lower than the upper surface of the second side portion 222.

[0076] In some embodiments, the insulating structure 230 may extend along the D3 direction. For example, the dimension of the insulating structure 230 in the D3 direction may be equal to the dimension of the first side portion 221 in the D3 direction. When the semiconductor device 200 is in its current placement position, the lower surface of the insulating structure 230 may contact the upper surface of the first side portion 221. In this embodiment, the insulating structure 230 can ensure the structural stability of the semiconductor device 200, which helps to improve the yield of the semiconductor device 200.

[0077] In some embodiments, there may be multiple conductive structures 220. The multiple conductive structures 220 are arranged at intervals in the D2 direction. Each conductive structure 220 may be located between two adjacent rows of semiconductor bodies 210 in the D2 direction. Two first sides (not shown) of adjacent conductive structures 220 in the D2 direction and corresponding insulating structures 230a, 230b are symmetrically arranged with respect to a row of semiconductor bodies 210 (e.g., mirror image). In other words, two first sides (not shown) of adjacent conductive structures 220 in the D2 direction are located between two second sides 222a, 222b.

[0078] It should be noted that the insulation structure 230 mentioned above may be located in Figure 1A The second region R2 is shown. In some embodiments, where the semiconductor device 200 includes multiple storage banks, the type and number of insulating structures 130 or 230 located in the second region R2 of different storage banks may be different, and this disclosure does not impose specific limitations on this.

[0079] This disclosure also provides a method for fabricating a semiconductor device in some embodiments. Figure 3 This is a schematic flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this disclosure. Figure 3 As shown, the semiconductor device fabrication method 300 (hereinafter referred to as fabrication method 300) may include the following steps.

[0080] S310, forming at least two semiconductor bodies, wherein the semiconductor bodies extend along a first direction, and the two semiconductor bodies are arranged in a second direction to form a trench extending along a third direction.

[0081] S320, a conductive layer is formed on the trench sidewalls and bottom, and a first insulating layer is formed inside the conductive layer, wherein the first insulating layer extends to one side of the semiconductor body in a first direction.

[0082] S330, etching the first insulating layer to form a marking opening, wherein the marking opening exposes a portion of the conductive layer formed on one sidewall of the trench.

[0083] S340, through a marked opening, replaces a portion of the conductive layer formed on one sidewall with an insulating structure.

[0084] In the fabrication method 300 provided in this disclosure, the overlay error between the mark opening and the trench is determined by forming a mark opening, in order to evaluate the overlay accuracy between the process layer forming the trench and the process layer forming the mark opening. The internal structure of the trench (e.g., a conductive layer) can be used as an actual functional component through subsequent processing. Compared to some embodiments that add additional overlay marks (usually located in the cut track area) to measure overlay error, fabrication method 300 does not require additional overlay marks, but directly measures the pattern (e.g., the trench) associated with the actual functional component, thereby obtaining a more accurate overlay error.

[0085] Figures 4A to 8 This is a cross-sectional schematic diagram of the semiconductor device provided in the embodiments of this disclosure during the fabrication process. Specifically, Figure 4A and Figure 4B The intermediate structure is shown after the formation of the semiconductor body, the conductive layer, and the first insulating layer. Among them, Figure 4B It can be along Figure 4A The diagram shows a cross-section cut by line I-I'. Figure 5A and Figure 5B The intermediate structure after the marking opening is formed is shown. Among them, Figure 5B It can be along Figure 5A The diagram shows a cross-section cut by line I-I'. Figures 6A to 6C The intermediate structure after removing part of the first insulating layer is shown. Among them, Figure 6B It can be along Figure 6AThe diagram shows a cross-section cut by line I-I'. Figure 6C It can be along Figure 6B The diagram shows a cross-section taken by line II-II'. Figure 7 The intermediate structure after the formation of the second insulating layer is shown. Figure 8 The semiconductor device is shown after the insulating structure has been formed.

[0086] The following is combined Figures 4A to 8 The preparation method 300, which includes steps S310 to S340, will be described by way of example.

[0087] Preparation method 300 begins with step S310. In some embodiments, such as Figure 4A and Figure 4B As shown, a semiconductor body 410 extending along the D1 direction can be formed by etching a semiconductor layer 441. Exemplarily, the semiconductor layer 441 can extend along both the D2 and D3 directions. For example, the semiconductor layer 441 can be a semiconductor substrate. In forming the semiconductor body 410, firstly, a plurality of first trenches (not shown) extending along the D2 direction can be formed by etching one side of the semiconductor layer 441 in the D1 direction. Next, an insulating material can be filled into the first trenches. Then, the semiconductor layer 441 and the insulating material can be etched on one side of the semiconductor layer 441 in the D1 direction to form a plurality of second trenches 451 extending along the D3 direction. Since the extension directions of the first trenches and the second trenches 451 intersect (e.g., are perpendicular), a plurality of semiconductor bodies 410 spaced apart in the D2 and D3 directions can be formed, and each semiconductor body 410 can extend along the D1 direction. For example, two adjacent semiconductor bodies 410 in the D3 direction can be isolated by an insulating material.

[0088] In some implementations, reference continues. Figure 4A and Figure 4B A dielectric layer 442 can be formed on the inner wall of the second trench 451. Optionally, the dielectric layer 442 can extend to the top surface of the semiconductor body 410. As an example, the dielectric layer 442 can be formed by an oxidation process. As another example, the dielectric layer 442 can be formed by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0089] It should be noted that the term "top surface" or "top side" as used in this disclosure refers to the surface or side on which one component is located on top of another component when each intermediate structure is in the placement position shown in the corresponding drawings.

[0090] Preparation method 300 proceeds to step S320. For example... Figure 4A and Figure 4B As shown, a conductive layer 454 can be formed on the sidewalls and bottom of the second trench 451 using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. Optionally, the conductive layer 454 can extend to the top side of the semiconductor body 410. For example, the conductive layer 454 can be formed on the top surface of the dielectric layer 442. In other words, the conductive layer 454 can be in contact with the dielectric layer 442. Further, a first insulating layer 455 can be formed inside the conductive layer 454 using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. The first insulating layer 455 can extend to one side (e.g., the top side) of the semiconductor body 410 in the D1 direction. For example, the first insulating layer 455 can fill the inner space of the conductive layer 454 and cover the surface of the conductive layer 454 extending to the top side of the semiconductor body 410. After the above process, the first insulating layer 455 can provide a flat surface perpendicular to the D1 direction.

[0091] In some embodiments, the material of the first insulating layer 455 may include one or more of silicon oxide, silicon nitride, silicon oxynitride, or any other suitable insulating material. For example, the material of the first insulating layer 455 may be silicon oxide.

[0092] Preparation method 300 proceeds to step S330. In some embodiments, such as... Figure 4A and Figure 4B As shown, a first mask layer 452 and a second mask layer 453 can be sequentially formed on the top side (e.g., the top surface) of the first insulating layer 455 by spin coating, thin film deposition processes such as CVD, PVD, ALD, or any combination thereof. For example, the first mask layer 452 can be a hard mask. The second mask layer 453 can be a photoresist.

[0093] In some embodiments, the first mask layer 452 may be made of a single material or a composite material, and this disclosure does not impose specific limitations on this. For example, the first mask layer 452 may be composed of two layers made of carbon and silicon oxynitride. The carbon layer may be in contact with the first insulating layer 455.

[0094] In some embodiments, a plurality of first openings 456 can be formed by patterning the second mask layer 453 using a photolithography process. Further, a plurality of marking openings 457 can be formed by etching the first mask layer 452 and the first insulating layer 455 through the first openings 456, such as... Figure 5A and Figure 5BAs shown. The marking opening 457 exposes a portion of the conductive layer 454 formed on one sidewall of the second trench 451. Exemplarily, the dimension l2 of the marking opening 457 in the D2 direction may be larger than the dimension l3 of the conductive layer 454 located on two adjacent sidewalls of two adjacent second trenches 451 in the D2 direction. In the D1 direction, the marking opening 457 and the semiconductor body 410 are aligned. For example, viewed from the D3 direction, the axis of symmetry of the marking opening 457 and the axis of symmetry of the semiconductor body 410 substantially coincide.

[0095] In some implementations, such as Figure 5A As shown, multiple marking openings 457 are arranged at intervals in the D3 direction. For example, the distance l1 between adjacent marking openings 457 in the D3 direction is greater than 500 nm. For example, this distance l1 can be 510 nm, 550 nm, 600 nm, 650 nm, 700 nm, 750 nm, 800 nm, 850 nm, 900 nm, 950 nm, 1000 nm, 1050 nm, 1100 nm, etc. This disclosure does not impose specific limitations on the value of the distance l1.

[0096] In some implementations, overlay error can be measured based on the marked opening 457. Overlay error is an important parameter describing the accuracy of overlay between the current process layer and a reference process layer. As mentioned above, the marked opening 457 can be formed, for example, by photolithography and etching processes. During this process, the size and position of the marked opening 457 may deviate from design requirements. Using the formation of the second trench 451 as a reference process layer, the overlay error between the marked opening 457 and the second trench 451 is determined by judging whether the marked opening 457 exposes a portion of the conductive layer 454 formed on a sidewall of the second trench 451, in order to evaluate the overlay accuracy between the process layer forming the second trench 451 and the process layer forming the marked opening 457. The internal structure of the second trench 451 (e.g., conductive layer 454) can be used as an actual functional component through subsequent processing. Compared with some embodiments that add additional overlay marks (usually located in the cutting area) to measure overlay error, the preparation method 300 provided in this disclosure does not require adding additional overlay marks, but directly measures the pattern associated with the actual functional component (e.g., the second trench 451), thereby obtaining a more accurate overlay error.

[0097] In some implementations, optical information of multiple marking openings 457 can be acquired using a light spot. For example, optical information of multiple marking openings 457 can be obtained through optical diffraction or image recognition techniques. When the distance l1 between adjacent marking openings 457 is greater than 500 nm, the design requirements for the number and area of ​​marking openings 457 can be met within a preset area, enabling a single light spot to acquire optical information of a greater number of marking openings 457, thereby helping to increase the accuracy and efficiency of overlay error measurement.

[0098] Preparation method 300 proceeds to step S340. In some embodiments, such as... Figures 6A to 6C As shown, a portion of the conductive layer 454 located on one sidewall of the second trench 451 can be removed via an etching process (e.g., wet etching) and through a marked opening 457 to form a gap 458. For example, the gap 458 exposes the dielectric layer 442 and the first insulating layer 455 in the D2 direction. Further, as... Figure 8 As shown, a second insulating layer 459 can be formed in the gap 458 by a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. Optionally, the second insulating layer 459 may extend to the top surface of the dielectric layer 442 and the first insulating layer 455. For example, the material of the second insulating layer 459 may include silicon nitride.

[0099] After the above process, the portion of the conductive layer 454 formed on one sidewall of the second trench 451 can be replaced with the insulating structure 430 (see reference). Figure 8 The insulating structure 430 can be used to fill the gap 458 with the second insulating layer 459 (see reference). Figure 6B () part.

[0100] It should be noted that, as Figures 6A to 6C As shown, during the etching process that forms gap 458, the etching material (e.g., etchant) may travel along... Figure 6A and Figure 6B The directions of arrows ① and ② shown indicate that the conductive layer 454 has been over-etched, thereby enabling... Figure 6A The first insulating layer 455 within the dashed box shown collapses, increasing the risk of structural damage. When the distance l1 between adjacent marked openings 457 is greater than 500 nm, this risk of structural damage can be reduced, contributing to improved stability and yield of the semiconductor device.

[0101] In some embodiments, the preparation method 300 may further include the following steps. For example... Figure 7 and Figure 8As shown, firstly, the portion of the second insulating layer 459 extending to the top surface of the dielectric layer 442 and the first insulating layer 455 can be removed by an etching process. Next, the portion of the first insulating layer 455 extending to one side (e.g., the top side) of the semiconductor body 410 in the D1 direction can be removed by an etching process. Subsequently, the portion of the conductive layer 454 located at the opening of the second trench 451 can be removed by an etching process. Thus, the remaining conductive layer 454 can be a conductive structure 420.

[0102] Figures 9A to 13 This is a cross-sectional schematic diagram of a semiconductor device during fabrication according to another embodiment of this disclosure. Specifically, Figure 9A and Figure 9B The intermediate structure is shown after the formation of the semiconductor body, the conductive layer, and the first insulating layer. Among them, Figure 9B It can be along Figure 9A The diagram shows a cross-section cut by line I-I'. Figure 10A and Figure 10B The intermediate structure after the marking opening is formed is shown. Among them, Figure 10B It can be along Figure 10A The diagram shows a cross-section cut by line I-I'. Figures 11A to 11C The intermediate structure after removing part of the first insulating layer is shown. Among them, Figure 11B It can be along Figure 11A The diagram shows a cross-section cut by line I-I'. Figure 11C It can be along Figure 11B The diagram shows a cross-section taken by line II-II'. Figure 12 The intermediate structure after the formation of the second insulating layer is shown. Figure 13 The semiconductor device is shown after the insulating structure has been formed.

[0103] The following is combined Figures 9A to 13 The preparation method 300, which includes steps S310 to S340, will be described by way of example. For the purpose of brevity, the same content as in the previous embodiment will not be repeated in this embodiment.

[0104] Preparation method 300 begins with step S310. In some embodiments, such as Figure 9A and Figure 9B As shown, the semiconductor body 510 extending along the D1 direction can be formed by etching the semiconductor layer 541. For example, a plurality of semiconductor bodies 510 spaced apart in the D2 and D3 directions can be formed. The second trench 551 extending along the D3 direction can be defined by two semiconductor bodies 510 arranged in the D2 direction.

[0105] In some implementations, reference continues. Figure 9A and Figure 9BA dielectric layer 542 may be formed on the inner wall of the second trench 551. Optionally, the dielectric layer 542 may extend to the top surface of the semiconductor body 510.

[0106] Preparation method 300 proceeds to step S320. For example... Figure 9A and Figure 9B As shown, a conductive layer 554 can be formed on the sidewalls and bottom of the second trench 551 by a thin film deposition process such as CVD, PVD, ALD, or any combination thereof, and a first insulating layer 555 can be formed inside the conductive layer 554. The first insulating layer 555 can extend to one side (e.g., the top side) of the semiconductor body 510 in the D1 direction.

[0107] Preparation method 300 proceeds to step S330. In some embodiments, such as... Figure 9A and Figure 9B As shown, a first mask layer 552 and a second mask layer 553 may be sequentially formed on the top side (e.g., the top surface) of the first insulating layer 555.

[0108] In some embodiments, a plurality of first openings 556 can be formed by patterning the second mask layer 553 using a photolithography process. Further, marking openings 557 extending along the D3 direction can be formed by etching the first mask layer 552 and the first insulating layer 555 through the first openings 556. Figure 10A and Figure 10B As shown. The marking opening 557 exposes a portion of the conductive layer 554 formed on one sidewall of the second trench 551. Exemplarily, the dimension l2 of the marking opening 557 in the D2 direction may be larger than the dimension l3 of the conductive layer 554 located on two adjacent sidewalls of two adjacent second trenches 551 in the D2 direction. In the D1 direction, the marking opening 557 and the semiconductor body 510 are aligned. For example, viewed from the D3 direction, the axis of symmetry of the marking opening 557 and the axis of symmetry of the semiconductor body 510 substantially coincide.

[0109] In some embodiments, overlay error can be measured based on the marked opening 557. The overlay error between the marked opening 557 and the second trench 551 is determined by judging whether the marked opening 557 exposes a portion of the conductive layer 554 formed on a sidewall of the second trench 551, thereby assessing the overlay accuracy between the process layer forming the second trench 551 and the process layer forming the marked opening 557. The internal structure of the second trench 551 (e.g., the conductive layer 554) can be used as an actual functional component through subsequent processing, thus eliminating the need for additional overlay marks and allowing direct measurement of the pattern associated with the actual functional component (e.g., the second trench 551), thereby obtaining a more accurate overlay error.

[0110] Preparation method 300 proceeds to step S340. In some embodiments, such as... Figures 11A to 11C As shown, a portion of the conductive layer 554 located on one sidewall of the second trench 551 can be removed via an etching process (e.g., wet etching) and through a marked opening 557 to form a gap 558. For example, the gap 558 exposes the dielectric layer 542 and the first insulating layer 555 in the D2 direction. Further, as... Figure 12 As shown, a second insulating layer 559 can be formed in the gap 558 by a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. Optionally, the second insulating layer 559 may extend to the top surface of the dielectric layer 542 and the first insulating layer 555.

[0111] After the above process, the portion of the conductive layer 554 formed on one sidewall of the second trench 551 can be replaced with an insulating structure 530 (see reference). Figure 13 The insulating structure 530 can be used to fill the gap 558 with the second insulating layer 559 (see reference). Figure 11B () part.

[0112] It should be noted that, as Figures 11A to 11C As shown, during the etching process that forms the gap 558, since the marking opening 557 extends along the D3 direction, the gap 558 also extends along the D3 direction. Therefore, there is no problem of the first insulating layer 555 collapsing due to over-etching of the conductive layer 554, which significantly reduces the risk of structural damage and helps to improve the stability and yield of semiconductor devices.

[0113] In some embodiments, the preparation method 300 may further include the following steps. For example... Figure 12 and Figure 13 As shown, firstly, the portion of the second insulating layer 559 extending to the top surface of the dielectric layer 542 and the first insulating layer 555 can be removed by an etching process. Next, the portion of the first insulating layer 555 extending to one side (e.g., the top side) of the semiconductor body 510 in the D1 direction can be removed by an etching process. Subsequently, the portion of the conductive layer 554 located at the opening of the second trench 551 can be removed by an etching process. Thus, the remaining conductive layer 554 can be a conductive structure 520.

[0114] Some embodiments of this disclosure also provide a method for measuring overlay error. Figure 14 This is a schematic flowchart of the overlay error measurement method provided in an embodiment of this disclosure. Figure 14 As shown, the overlay error measurement method 600 may include the following steps.

[0115] S610, forming at least two semiconductor bodies, wherein the semiconductor bodies extend along a first direction, and the two semiconductor bodies are arranged in a second direction to form a trench extending along a third direction.

[0116] S620, a conductive layer is formed on the trench sidewall and bottom, and a first insulating layer is formed inside the conductive layer, wherein the first insulating layer extends to one side of the semiconductor body in a first direction.

[0117] S630, the first insulating layer is etched to form a marking opening, wherein the marking opening exposes a portion of the conductive layer formed on one sidewall of the trench.

[0118] S640 replaces a portion of the conductive layer formed on one sidewall with an insulating structure via a marked opening.

[0119] In the overlay error measurement method 600 provided in this disclosure embodiment, the overlay error between the mark opening and the trench is determined by forming a mark opening, so as to evaluate the overlay accuracy between the process layer forming the trench and the process layer forming the mark opening. The internal structure of the trench (e.g., a conductive layer) can be used as an actual functional component through subsequent processing. Compared with some embodiments that add additional overlay marks (usually located in the dicing area) for overlay error measurement, the overlay error measurement method 600 does not require additional overlay marks, but directly measures the pattern (e.g., the trench) associated with the actual functional component, thereby obtaining a more accurate overlay error.

[0120] In some embodiments, multiple marker openings are spaced apart in the third direction, with a distance greater than 500 nm between adjacent marker openings in the third direction. In other embodiments, the marker openings extend along the third direction.

[0121] In some implementations, optical information of multiple marking openings can be obtained using a light spot, thereby enabling measurement of overlay error.

[0122] This disclosure also provides a memory system. Figure 15 This is a schematic block diagram of a system with a memory system provided in an embodiment of this disclosure. Figure 16A and Figure 16B This is a schematic block diagram of a memory system provided in an embodiment of this disclosure.

[0123] like Figure 15 As shown, system 10 can be a mobile phone, desktop computer, laptop computer, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device (which has a memory system 11 located therein). Figure 15As shown, system 10 may include a host 14 and a memory system 11, the memory system 11 having one or more memories 12 and a controller 13. The host 14 may be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). The host 14 may be configured to send or receive data to and from the memory 12.

[0124] Memory 12 may include, for example, the semiconductor devices described in any embodiment of this disclosure. According to some embodiments, controller 13 is coupled to memory 12 and host 14 and is configured to control memory 12. Controller 13 can manage data stored in memory 12 and communicate with host 14. In some embodiments, controller 13 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, compact flash (CF) card, universal serial bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, controller 13 is designed to operate in a high duty cycle environment, such as an SSD or embedded multi-media card (eMMC) used as a data storage device in mobile devices such as smartphones, tablets, laptops, etc. Controller 13 may be configured to control operations of memory 12, such as read, erase, and program operations. Controller 13 may also be configured to manage various functions related to data stored in or to be stored in memory 12, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, controller 13 is further configured to process error correction codes (ECCs) related to data read from or written to memory 12. Controller 13 may also perform any other appropriate functions, such as formatting memory 12. Controller 13 may communicate with external devices (e.g., host 14) according to specific communication protocols. For example, controller 13 may communicate with external devices via at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronic Devices (IDE), Firewire, etc.

[0125] The controller 13 and one or more memories 12 can be integrated into various types of memory systems, for example, included in the same package (such as a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 11 can be implemented and packaged into different types of end electronic products. Figure 16AIn one example shown, controller 13 and a single memory 12 may be integrated into memory card 15. Memory card 15 may include PC card (PCMCIA, Personal Computer Memory Card International Association), CF card, Smart Media (SM) card, memory stick, multimedia card (MMC, RS-MMC, MMCmicro), SD card (SD, miniSD, microSD, SDHC), UFS, etc. Memory card 15 may further include a connector for connecting memory card 15 to a host computer (e.g., Figure 15 The host 14) is coupled to the memory card connector 16. In such a way... Figure 16B In another example shown, controller 13 and multiple storage units 12 may be integrated into SSD 17. SSD 17 may further include components for connecting SSD 17 to a host (e.g., Figure 15 The host 14) is coupled to the SSD connector 18. In some embodiments, the storage capacity and / or operating speed of the SSD 17 is higher than that of the memory card 15.

[0126] The above description is merely an illustration of the embodiments of this disclosure and the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the technical concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features disclosed in this disclosure that have similar functions.

Claims

1. A semiconductor device, comprising: At least two semiconductor bodies, the semiconductor bodies extending along a first direction, and the two semiconductor bodies arranged in a second direction; A conductive structure, located between two semiconductor bodies and extending in a third direction, includes a first side, a second side, and a connecting portion, wherein the first side and the second side are disposed opposite each other in a second direction, and the connecting portion is connected to the ends of the first side and the second side in the first direction; and An insulating structure extends from the side of the first side away from the connecting portion in the first direction along the first direction and contacts the first side; The first direction, the second direction, and the third direction intersect each other.

2. The semiconductor device according to claim 1, wherein, In the first direction, the surface of the insulating structure facing away from the connection portion is coplanar with the end face of the semiconductor body.

3. The semiconductor device according to claim 1, wherein, The dimension of the insulating structure in the second direction is equal to the dimension of the first side portion in the second direction.

4. The semiconductor device according to claim 1, wherein, The insulating structure is made of silicon nitride.

5. The semiconductor device according to claim 1, wherein, In the first direction, the surface of the second side facing away from the connecting portion is located between the opposing surfaces of the insulating structure in the first direction.

6. The semiconductor device according to claim 1, wherein, The semiconductor device further includes: A dielectric layer is located between the insulating structure and the semiconductor body; The dielectric layer is made of a different material than the insulating structure.

7. The semiconductor device according to claim 1, wherein, The plurality of said insulating structures are arranged at intervals in the third direction, with the first side extending between adjacent said insulating structures.

8. The semiconductor device according to claim 7, wherein, The distance between the third party and the adjacent insulating structures is greater than 500 nm.

9. The semiconductor device according to claim 1, wherein, The insulating structure extends along the third direction.

10. The semiconductor device according to any one of claims 1 to 9, wherein, The two first sides of the adjacent conductive structures in the second direction and the corresponding insulating structures are symmetrically arranged with respect to a row of semiconductor bodies arranged in the third direction.

11. The semiconductor device according to any one of claims 1 to 9, wherein, In the second direction, two of the first sides of the conductive structure adjacent to each other are located between two second sides.

12. The semiconductor device according to any one of claims 1 to 9, wherein, The semiconductor device further includes a storage container, wherein, in a plane perpendicular to the first direction, the storage container includes a first region and a second region surrounding the first region, and the insulating structure is located within the second region.

13. The semiconductor device according to claim 12, wherein, The insulating structure is located on opposite sides of the first region in the third direction and is arranged in the second direction.

14. The semiconductor device according to any one of claims 12, wherein, On a plane perpendicular to the first direction, a plurality of the storage arrays are arranged, and the insulating structure is disposed within the second zone of one or more of the storage arrays.

15. A memory system, comprising: The memory includes the semiconductor device as described in any one of claims 1 to 14; as well as A controller, coupled to the memory, is used to control the memory to store data.

16. A method for fabricating a semiconductor device, comprising: At least two semiconductor bodies are formed, wherein the semiconductors extend along a first direction, and the two semiconductor bodies are arranged in a second direction to form a trench extending along a third direction. A conductive layer is formed on the sidewalls and bottom of the trench, and a first insulating layer is formed inside the conductive layer, wherein the first insulating layer extends to one side of the semiconductor body in the first direction; Etching the first insulating layer forms a marking opening, wherein the marking opening exposes a portion of the conductive layer formed on one sidewall of the trench; and The portion of the conductive layer formed on one of the sidewalls is replaced with an insulating structure via the marked opening; The first direction, the second direction, and the third direction intersect each other.

17. The preparation method according to claim 16, wherein, The plurality of the marked openings are arranged at intervals in the third direction, and the distance between adjacent marked openings in the third direction is greater than 500 nm.

18. The preparation method according to claim 16, wherein, The marked opening extends along the third direction.

19. The preparation method according to claim 16, wherein, In the first direction, the marking opening and the semiconductor body are aligned.

20. The preparation method according to any one of claims 16 to 19, wherein, After replacing the portion of the conductive layer formed on one of the sidewalls with an insulating structure via the marked opening, the fabrication method further includes: Remove the portion of the first insulating layer extending to one side of the semiconductor body in the first direction; and Remove a portion of the conductive layer located at the opening of the trench.

21. A method for measuring overlay error, comprising: At least two semiconductor bodies are formed, wherein the semiconductor bodies extend along a first direction, and the two semiconductor bodies are arranged in a second direction to form a trench extending along a third direction. A conductive layer is formed on the sidewalls and bottom of the trench, and a first insulating layer is formed inside the conductive layer, wherein the first insulating layer extends to one side of the semiconductor body in the first direction; Etching the first insulating layer forms a marking opening, wherein the marking opening exposes a portion of the conductive layer formed on one sidewall of the trench; and The overlay error is measured based on the marked opening; The first direction, the second direction, and the third direction intersect each other.

22. The measurement method according to claim 21, wherein, The plurality of the marked openings are arranged at intervals in the third direction, and the distance between adjacent marked openings in the third direction is greater than 500 nm.

23. The measurement method according to claim 21, wherein, The marked opening extends along the third direction.

24. The measurement method according to any one of claims 21 to 23, wherein measuring the overlay error based on the marked opening comprises: Optical information of multiple marked openings is obtained using a light spot.

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