Semiconductor structure and method of manufacturing the same

Abstract

A semiconductor structure and a method of manufacturing the same are provided. The semiconductor structure includes a semiconductor device, a plurality of contact structures, and a plurality of first signal lines. The contact structures are located in the semiconductor device. A shape of a vertical projection of at least one of the plurality of contact structures on the semiconductor device includes a concave side. The plurality of first signal lines are located on the plurality of contact structures, and at least one of the plurality of first signal lines overlaps the concave side.

Description

Technical Field

[0001] This invention relates to a semiconductor structure and its manufacturing method. Background Technology

[0002] With the rapid advancement of technology, in order to achieve the trend of electronic devices becoming lighter, thinner, shorter, and smaller, the size of the semiconductor structures within these devices must also continue to shrink. Generally, photolithography is used to precisely define the pattern and structure of the components when fabricating these tiny and precise semiconductor structures. Currently, semiconductor manufacturers are actively investing in the development of technologies to further reduce the feature size of components, thereby improving device performance and integration. Summary of the Invention

[0003] This invention provides a semiconductor structure and its manufacturing method, which can reduce the feature size of the contact structure.

[0004] At least one embodiment of the present invention provides a method for manufacturing a semiconductor structure, comprising the following steps: forming a first mask structure over a semiconductor device; forming a second mask structure over the first mask structure; forming a first opening pattern in the second mask structure; forming a third mask structure on the second mask structure and in the first opening pattern; removing at least a portion of the second mask structure surrounded by the third mask structure using the third mask structure as a mask to form a second opening pattern in the third mask structure; etching the first mask structure located below the third mask structure through the second opening pattern to form a third opening pattern in the first mask structure; etching the semiconductor device through the third opening pattern to form a fourth opening pattern in the semiconductor device; forming a filler material layer in the fourth opening pattern; forming a plurality of signal lines on the filler material layer; and etching the filler material layer using the plurality of signal lines as a mask to form a plurality of contact structures.

[0005] At least one embodiment of the present invention provides a semiconductor structure including a semiconductor device, a plurality of contact structures, and a plurality of first signal lines. The contact structures are located within the semiconductor device. The shape of at least one of the plurality of contact structures in its vertical projection onto the semiconductor device includes a concave side. The plurality of first signal lines are located on the plurality of contact structures, and at least one of the plurality of first signal lines overlaps the concave side. Attached Figure Description

[0006] Figure 1 This is a top view schematic diagram of a semiconductor structure according to an embodiment of the present invention;

[0007] Figures 2A to 2L as well as Figures 3A to 3NThis is a cross-sectional schematic diagram of each stage of a method for manufacturing a semiconductor structure according to an embodiment of the present invention;

[0008] Figures 4A to 4H This is a top view schematic diagram of various stages of a semiconductor structure manufacturing method according to an embodiment of the present invention;

[0009] Figure 5 This is a cross-sectional schematic diagram of a semiconductor structure according to an embodiment of the present invention. Detailed Implementation

[0010] Reference Figure 1 The semiconductor structure 10 includes a substrate 100, an isolation structure 110, an active region 102, bit lines BL (or first signal lines), word lines WL (or second signal lines), and a contact structure BC. Multiple bit lines BL are disposed on the substrate 100. Each bit line BL extends along a first direction D1, and adjacent bit lines BL are arranged at fixed intervals along a second direction D2. Multiple word lines WL are also disposed within the substrate 100. Each word line WL extends along a second direction D2, and adjacent word lines WL are arranged at fixed intervals along the first direction D1. The word lines WL can be embedded, meaning the top surface of the word line WL can be lower than the top surface of the substrate 100; for example, the word lines WL are embedded within the substrate 100 to achieve a more compact structural design.

[0011] In some embodiments, an isolation structure 110 may be formed in the substrate 100 to define the extent of the active region 102 and to separate adjacent active regions 102 from each other. A plurality of active regions 102 may be formed in the substrate 100, each active region 102 extending generally along a direction at an angle to the first direction D1. This design helps to improve the integration and performance of the component.

[0012] like Figure 1 As shown, each active region 102 spans two word lines WL and crosses one bit line BL. Each active region 102 overlaps with its corresponding bit line BL, and non-overlapping regions are formed on either side of the overlapping region. Storage node contacts (not shown) are disposed in these non-overlapping regions for electrical connection to capacitors (not shown). Each storage node contact is located between two adjacent bit lines BL and between two adjacent word lines WL.

[0013] In some embodiments, each active region 102 has a contact structure BC at the region overlapping with its corresponding bit line BL. When each bit line BL crosses its corresponding word line WL, it can be electrically connected to the doped region of the substrate 100 located between the two word lines WL through the contact structure BC. This design helps to achieve more efficient signal transmission.

[0014] Figures 2A to 2L as well as Figures 3A to 3N yes Figure 1 The diagram shows cross-sectional views of each stage of the manufacturing process of the semiconductor structure 10A. Please refer to... Figure 2A A semiconductor device SD is provided. The semiconductor device SD includes a substrate 100 and a plurality of word lines WL embedded in the substrate 100.

[0015] Substrate 100 is an elemental semiconductor substrate, such as a silicon substrate or a germanium substrate; or a compound semiconductor substrate, such as a silicon carbide substrate or a gallium arsenide substrate. In some embodiments, substrate 100 may be a semiconductor-on-insulator (SOI) substrate. In some embodiments, the top surface of substrate 100 includes an insulating layer 106.

[0016] The substrate 100 includes an active region 102 and an isolation region 104. An isolation structure 110 is filled into the isolation region 104. In some embodiments, the isolation structure 110 is formed of a dielectric material, such as silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), combinations thereof, and / or other suitable materials.

[0017] In some embodiments, an isolation trench is formed in a substrate 100 using an etching process, and then a liner 112 and an isolation structure 110 are formed in the isolation trench.

[0018] In some embodiments, after forming the isolation structure 110, the substrate 100 is patterned to form word line trenches in the active region 102 and the isolation structure 110. Because the etching rates differ in the active region 102 and the isolation structure 110, word line trenches of different depths can be formed in the active region 102 and the isolation structure 110. In some embodiments, the word line trenches in the isolation structure 110 are deeper than the word line trenches in the active region 102.

[0019] A word line WL is formed in the active region 102 and within the word line trench in the isolation structure 110. The word line WL includes a gate dielectric layer 120a and a conductive layer 120c. The gate dielectric layer 120a is formed on the sidewalls and bottom surface of the word line trench in the active region 102. Next, the remaining space in the word line trench is filled with the conductive layer 120c. Optionally, a barrier layer is formed in the word line trench in the active region 102 and within the word line trench in the isolation structure 110 to prevent the diffusion of metal ions from the subsequently formed conductive layer 120c. The conductive layer 120c (and the barrier layer) in the active region 102 and the isolation structure 110 are etched back until a predetermined height is reached.

[0020] In some embodiments, the word line WL further includes a work function layer 125. The work function layer 125 may include, for example, doped or undoped polysilicon, metals (e.g., tantalum, titanium, tungsten, ruthenium, aluminum, etc.), metal alloys, metal nitrides (e.g., titanium nitride, titanium silicon nitride, tantalum nitride, tungsten nitride), metal silicides, etc. After depositing the material used to form the work function layer 125, it is recessed, for example, by an etch-back process, so that the top surface of the work function layer 125 is lower than the top surface of the substrate 100. In some embodiments, a barrier layer may also be included between the conductive layer 120c and the work function layer 125, but the invention is not limited thereto.

[0021] The capping layer 130 fills the remaining space in the word line trench. In some embodiments, the capping layer 130 includes nitrides such as silicon nitride (SiN), silicon carbonitride (SiCN), silicon carbon oxynitride (SiOC), silicon carbonitride oxynitride (SiOCN), combinations thereof, and / or other suitable materials.

[0022] The isolation component TI surrounds the array region where word lines WL are provided and serves to separate the array region from the surrounding region. In some embodiments, the isolation component TI includes a shallow trench isolation structure or other similar structure.

[0023] Next, a dielectric material layer 210 is formed over the substrate 100, extending from above the array region of the substrate 100 where word lines WL are provided to above the isolation member TI. In some embodiments, the dielectric material layer 210 comprises a composite layer of different dielectric materials. For example, the dielectric material layer 210 comprises silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), combinations thereof, and / or other suitable materials.

[0024] Next, a semiconductor material layer 220 is formed over the dielectric material layer 210. In some embodiments, the semiconductor material layer 220 is a doped or undoped semiconductor layer. For example, the semiconductor material layer 220 may be doped with p-type or n-type dopants. The dopants of the semiconductor material layer 220 can be selected according to the actual application requirements. In some embodiments, the semiconductor material layer 220 includes a polysilicon layer.

[0025] The mask layer 230 is located on the semiconductor material layer 220. In some embodiments, the material of the mask layer 230 may include silicon oxide (e.g., silicon oxide formed from tetraethoxysilane (TEOS), silicon nitride, or a combination thereof or other suitable materials.

[0026] A first mask structure 310 is formed over a semiconductor device SD. In this embodiment, the first mask structure 310 is formed on a mask layer 230. In some embodiments, the first mask structure 310 includes, for example, a material of a hard mask. For example, the first mask structure 310 includes a carbide, such as diamond-like carbon, an amorphous carbon film, a highly selective transparent carbon-containing layer, or a combination thereof, or other suitable materials.

[0027] A first etch stop layer 320 is formed on the first mask structure 310. The first etch stop layer 320 has a single-layer or multi-layer structure. For example, the first etch stop layer 320 includes a first layer 324 and a second layer 322. In some embodiments, the first etch stop layer 320 includes silicon oxynitride or other suitable materials, wherein the oxygen content in the first layer 324 is higher than the oxygen content in the second layer 322, and the silicon content in the second layer 322 is higher than the silicon content in the first layer 324.

[0028] A second mask structure 330 is formed over the first mask structure 310. In this embodiment, the second mask structure 330 is formed on the first etch stop layer 320. In some embodiments, the second mask structure 330 includes, for example, a material of a hard mask. For example, the second mask structure 330 includes a carbide, such as diamond-like carbon, an amorphous carbon film, a highly selective transparent carbon-containing layer, or a combination thereof, or other suitable materials.

[0029] A second etch stop layer 340 is formed on the second mask structure 330. The second etch stop layer 340 has a single-layer or multi-layer structure. For example, the second etch stop layer 340 includes a first layer 344 and a second layer 342. In some embodiments, the second etch stop layer 340 includes silicon oxynitride or other suitable materials, wherein the oxygen content in the first layer 344 is higher than the oxygen content in the second layer 342, and the silicon content in the second layer 342 is higher than the silicon content in the first layer 344.

[0030] A first hard mask layer 351 is formed on the second etch stop layer 340. For example, the first hard mask layer 351 includes spin-on carbon (SOC) or spin-on glass (SOG).

[0031] A first anti-reflective layer 361 is formed on the first hard mask layer 351. In some embodiments, the first anti-reflective layer 361 is, for example, a spin-on silicon anti-reflection coating (SOSA).

[0032] A first photoresist pattern layer PR1 is formed on the first antireflective layer 361. For example, a photoresist material is first coated on the first antireflective layer 361, and then a photolithography process and a development process are performed on the aforementioned photoresist material to form the first photoresist pattern layer PR1. The first photoresist pattern layer PR1 includes a first photoresist opening pattern PRH1.

[0033] The first photoresist aperture pattern PRH1 is transferred to the first antireflective layer 361, the first hard mask layer 351, and the second etch stop layer 340. For example, please refer to... Figures 2B to 2E An etching process is performed using the first photoresist pattern layer PR1 as a mask to form a plurality of first openings O1 on the second etch stop layer 340. In some embodiments, the first photoresist opening pattern PRH1 includes, for example, a plurality of circular openings, such as... Figure 4A As shown. Therefore, the first opening O1 on the second etch stop layer 340 is also a circular opening.

[0034] The first opening O1 extends through the second layer 342 of the second etch stop layer 340. In some embodiments, over-etching may cause the first opening O1 to extend into the first layer 344, but the invention is not limited thereto.

[0035] Next, as Figure 2F As shown, the remaining first hard mask layer 351 is removed. Figure 2G As shown, a second hard mask layer 352 is formed on the second etch stop layer 340 and in the first opening O1. For example, the second hard mask layer 352 includes spin-on carbon (SOC) or spin-on glass (SOG).

[0036] A second anti-reflective layer 362 is formed on the second hard mask layer 352. In some embodiments, the second anti-reflective layer 362 is, for example, a spin-on silicon anti-reflection coating (SOSA).

[0037] A second photoresist pattern layer PR2 is formed on the second antireflective layer 362. For example, a photoresist material is first coated on the second antireflective layer 362, and then the photoresist material is subjected to an exposure process and a development process to form the second photoresist pattern layer PR2. The second photoresist pattern layer PR2 includes a second photoresist opening pattern PRH2.

[0038] The second photoresist aperture pattern PRH2 is transferred to the second antireflective layer 362, the second hard mask layer 352, and the second etch stop layer 340. For example, please refer to... Figures 2G to 2KAn etching process is performed using the second photoresist pattern layer PR2 as a mask to form a plurality of second openings O2 on the second etch stop layer 340. In some embodiments, the second photoresist opening pattern PRH2 includes, for example, a plurality of circular openings, such as... Figure 4B As shown. Therefore, the second opening O2 on the second etch stop layer 340 is also a circular opening.

[0039] The second opening O2 extends through the second layer 342 of the second etch stop layer 340. In some embodiments, over-etching may cause the second opening O2 to extend into the first layer 344, but the invention is not limited thereto.

[0040] In this embodiment, the positions of the second opening O2 are staggered with those of the first opening O1. By forming the staggered first opening O1 and second opening O2 in the second etch stop layer 340 through two photolithography processes, the spacing between the openings in the second etch stop layer 340 can be made smaller. For example, the first opening O1 and the second opening O2 constitute an opening array 340H, such as... Figure 4C As shown.

[0041] In this embodiment, the aperture array 340H is formed in the second etch stop layer 340 through two photolithography processes, but the present invention is not limited thereto. In other embodiments, the aperture array 340H is formed through a single photolithography process.

[0042] Next, as Figure 2K As shown, the remaining second hard mask layer 352 is removed. Figure 2L As shown, an etching process is performed to extend the first opening O1 and the second opening O2 to the top surface of the second mask structure 330. In this embodiment, when the first opening O1 and the second opening O2 are extended to the top surface of the second mask structure 330, the second layer 342 in the second etch stop layer 340 is completely removed, leaving only a portion of the first layer 344 on the top surface of the second mask structure 330.

[0043] Please refer to Figures 3A to 3C The first opening O1 and the second opening O2 in the first layer 344 are transferred to the second mask structure 330 and the first etch stop layer 320 through an etching process, so as to form the first opening pattern OP1 in the second mask structure 330 and the first etch stop layer 320. The first opening pattern OP1 is, for example, similar to... Figure 4C The opening array 340H formed by the first opening O1 and the second opening O2 shown has substantially the same vertical projection pattern.

[0044] The first opening pattern OP1 extends through the second layer 322 of the first etch stop layer 320. In some embodiments, over-etching may cause the first opening pattern OP1 to extend into the first layer 324, but the invention is not limited thereto.

[0045] Please refer to Figure 3D A third mask structure 410 is formed on the second mask structure 330 and in the first opening pattern OP1. In some embodiments, the material of the third mask structure 410 includes oxides, such as silicon oxide or other suitable materials. The third mask structure 410 fills the first opening pattern OP1. In some embodiments, the third mask structure 410 has a high etching selectivity to the material underneath it to facilitate the patterning process.

[0046] At least a portion of the second mask structure 330, surrounded by the third mask structure 410, is removed using the third mask structure 410 as a mask. For example, a third photoresist pattern layer PR3 is first formed above the third mask structure 410, wherein the third photoresist pattern layer PR3 is located above the peripheral region of the substrate 100. Then, a portion of the third mask structure 410 is removed using the third photoresist pattern layer PR3 as a mask until the first portion of the second mask structure 330 is exposed, such as... Figure 3E As shown. Then, please refer to... Figure 3F The second mask structure 330 of the first portion is etched using the third mask structure 410 as a mask to form a second opening pattern OP2 in the third mask structure 410. The second opening pattern OP2 is, for example, similar to... Figure 4C The shapes of the vertical projections of the aperture array 340H shown on the semiconductor device SD are substantially complementary.

[0047] In some embodiments, a portion of the first etch stop layer 320 (e.g., a portion of the second layer 322) is located in the second opening pattern OP2.

[0048] In some embodiments, the third photoresist pattern layer PR3 and the second mask structure 330 are removed simultaneously.

[0049] Please refer to Figure 3G The first etch stop layer 320 (partial second layer 322) located in the second etch stop layer OP2 is etched through the second etch stop layer OP2 until the first layer 324 of the first etch stop layer 320 is exposed. Please refer to... Figure 3H The etching process continues through the second opening pattern OP2 to etch the first etch stop layer 320 and the first mask structure 310 located below the third mask structure 410, so as to form the third opening pattern OP3 in the first etch stop layer 320 and the first mask structure 310.

[0050] In some embodiments, while forming the third opening pattern OP3, the remaining portion (i.e., the second portion) of the second mask structure 330 is removed.

[0051] In some embodiments, the shape of the vertical projection of the second opening pattern OP2 onto the semiconductor device SD is substantially the same as the shape of the vertical projection of the third opening pattern OP3 onto the semiconductor device SD; and at least a portion of the shape of the vertical projection of the second opening pattern OP2 (or the third opening pattern OP3) onto the semiconductor device SD is similar to that of the first opening pattern OP1 (see reference). Figures 3A to 3C At least a portion of the shape of the vertical projection onto the semiconductor device SD is substantially complementary in shape.

[0052] Please refer to Figure 3I Optionally, fill layer 420 can be inserted into the third opening pattern OP3. Please also refer to... Figure 3I as well as Figure 4E The third opening pattern OP3 includes a small-gap region OP3a and a large-gap region OP3b. The filling layer 420 deposits faster in the small-gap region OP3a; therefore, the filling layer 420 completely covers the small-gap region OP3a, while not completely covering the large-gap region OP3b. In some embodiments, the filling layer 420 comprises a polymeric material containing carbon chains formed from a reactive gas including CH4. and CH4+. Specifically, an alkane material, such as but not limited to CH4, may be deposited first. CH4 can form reactive gases of CH4. and CH4+ under the action of an electric or magnetic field, and CH4. and CH4+ then form a long-chain filling layer 420. In some embodiments, the filling layer 420 comprises polymeric materials with different carbon chain lengths. Figure 3I as well as Figure 4E In the middle, the filling layer 420 is a full-coverage blanket shape, but in reality, the filling layer 420 has many holes in the area OP3b with large gaps, so the filling layer 420 does not completely cover the area OP3b with large gaps.

[0053] Please refer to Figure 3J as well as Figure 3K The semiconductor device SD is etched using the third opening pattern OP3 to form a fourth opening pattern OP4 in the semiconductor device SD. The fourth opening pattern OP4 extends through the mask layer 230, the semiconductor material layer 220, and the dielectric material layer 210, and extends into the substrate 100. In this embodiment, a portion of the capping layer 130 is also removed during the aforementioned etching process.

[0054] Please refer to Figure 4EIn this embodiment, before etching the semiconductor device SD, a filler layer 420 is first filled into the small gap region OP3a. Therefore, when etching the semiconductor device SD, the etchant is blocked by the filler layer 420 at the small gap region OP3a. On the other hand, since the large gap region OP3b is not completely covered by the filler layer 420, when etching the semiconductor device SD, the etchant can easily etch through the filler layer 420 and etch the semiconductor device SD located underneath it at the large gap region OP3b. Based on this, although the third opening pattern OP3 is essentially a mesh opening, a fourth opening pattern OP4 containing multiple mutually separated contact openings CV can be formed within the semiconductor device SD.

[0055] In this embodiment, the filling layer 420 is used to make the vertical projection shape of the fourth opening pattern OP4 different from the vertical projection shape of the third opening pattern OP3, but the present invention is not limited thereto. In other embodiments, the step of depositing the filling layer 420 can be omitted, so that the vertical projection shape of the fourth opening pattern OP4 is substantially equal to the vertical projection shape of the third opening pattern OP3.

[0056] In addition, in this embodiment, the first mask structure 310 includes a plurality of mutually separated circular island-shaped structures (see reference). Figure 4D The third opening pattern OP3 is essentially a mesh opening, but the invention is not limited thereto. In other embodiments, the circular island structures of the first mask structure 310 are in contact with each other, so that the third opening pattern OP3 substantially includes a plurality of mutually separated openings.

[0057] In some embodiments, after forming a fourth opening pattern OP4 in a semiconductor device SD using an etching process, the semiconductor material layer 220 includes a plurality of first island structures 222 separated from each other, and the dielectric material layer 210 includes a plurality of second island structures 212 separated from each other. The shapes of the first island structures 222 and the second island structures 212 in their vertical projections are substantially equal (e.g., Figure 4D (The circular island structure in the first mask structure 310 shown).

[0058] Please refer to Figure 3L A filler material layer 430 is formed on the mask layer 230 and in the fourth opening pattern OP4. In some embodiments, the filler material layer 430 comprises doped polysilicon, metal, or metal nitride. In one embodiment, the filler material layer 430 may be formed by a deposition process such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, or other suitable methods.

[0059] Compared to a circular opening, the filler material layer 430 can be more easily filled into the contact opening CV. For example, when depositing the filler material layer 430 into a circular opening, the filler material layer 430 may cause closed voids due to the deposition rate on the sidewalls being too fast. In this embodiment, depositing the filler material layer 430 in a non-circular (e.g., star-shaped) opening CV can reduce the probability of the aforementioned closed voids.

[0060] Please refer to Figure 3M Optionally, the filler material layer 430 can be etched back to remove the portion of the filler material layer 430 that extends beyond the mask layer 230. In some embodiments, after the etch-back process is performed, the height of the top surface of the filler material layer 430 is lower than the height of the top surface of the mask layer 230.

[0061] In other embodiments, a planarization process removes the portion of the filler material layer 430 that extends beyond the mask layer 230. In some embodiments, at least a portion of the mask layer 230 is also removed in the aforementioned planarization process, such that the top surface of the filler material layer 430 after planarization is substantially aligned with the top surface of the mask layer 230. In some embodiments, after performing an etch-back process, the filler material layer 430 comprises a plurality of independent structures 432 that are separated from each other, such as... Figure 4F As shown. Please refer to. Figure 3N The mask layer 230 is then removed. For example, the mask layer 230 is removed using an etching process or a planarization process. Next, multiple bit lines BL are formed on the filler material layer 430.

[0062] In some embodiments, the bit line BL includes a multilayer structure, such as a conductive layer 442 and a conductive layer 444. Conductive layers 442 and 444 comprise doped polysilicon, a metal, or a metal nitride, such as tungsten, titanium, titanium nitride, or other suitable materials. Conductive layer 442 comprises titanium nitride, and conductive layer 444 comprises tungsten.

[0063] In some embodiments, a conductive material layer is first formed over the entire surface. Next, a hard mask layer 450 is formed on the conductive material layer. The conductive material layer is etched using the hard mask layer 450 as a mask to form bit lines BL. A fill material layer 430 is etched using the bit lines BL and the hard mask layer 450 as a mask to form multiple contact structures BC, such as... Figure 4G as well as Figure 4H As shown. In some embodiments, the semiconductor material layer 220 beneath the bit line BL is also etched.

[0064] In some embodiments, the shape of at least one of the contact structures BC in its vertical projection onto the semiconductor device includes a concave side CS, and the bit line BL overlaps the concave side CS. Each contact structure BC includes a plurality of concave side CS, and the sidewall SW1 of the contact structure BC is aligned with the sidewall SW2 of the bit line BL. Figure 4H as well as Figure 5 As shown. In some embodiments, the contact structure BC has a cross-sectional shape that is narrower at the top and wider at the bottom. Specifically, the width of the contact structure BC on the side near the bit line BL is smaller than the width of the contact structure BC on the side near the substrate 100.

[0065] In summary, the semiconductor structure of the present invention may include contact structures with small feature sizes, which is beneficial for improving the performance and integration of the device.

Claims

1. A method for manufacturing a semiconductor structure, comprising: A first mask structure is formed above the semiconductor device; A second mask structure is formed above the first mask structure; A first opening pattern is formed in the second mask structure; A third mask structure is formed on the second mask structure and in the first opening pattern; At least a portion of the second mask structure surrounded by the third mask structure is removed using the third mask structure as a mask to form a second opening pattern in the third mask structure; The first mask structure located below the third mask structure is etched by the second opening pattern to form the third opening pattern in the first mask structure; The semiconductor device is etched using the third opening pattern to form a fourth opening pattern in the semiconductor device; A layer of filling material is formed in the fourth opening pattern; Multiple signal lines are formed on the filler material layer; as well as The filler material layer is etched using the multiple signal lines as a mask to form multiple contact structures.

2. The manufacturing method according to claim 1, wherein removing at least a portion of the second mask structure surrounded by the third mask structure using the third mask structure as a mask comprises: A photoresist pattern layer is formed above the third mask structure; The third mask structure, which uses the photoresist pattern layer as a mask to remove a portion of the second mask structure, is removed until the first portion of the second mask structure is exposed; as well as The second mask structure of the first portion is etched using the third mask structure as a mask to form the second opening pattern.

3. The manufacturing method according to claim 2, wherein the second mask structure of the second portion is removed while the third opening pattern is being formed.

4. The manufacturing method according to claim 1, further comprising, before etching the semiconductor device through the third opening pattern: A filling layer is filled into the third opening pattern, wherein the third opening pattern includes a small gap area and a large gap area, wherein the filling layer completely covers the small gap area and the filling layer does not completely cover the large gap area.

5. The manufacturing method according to claim 4, wherein the filler layer comprises a polymer material.

6. The manufacturing method of claim 1, wherein at least a portion of the shape of the vertical projection of the second opening pattern onto the semiconductor device is substantially complementary to at least a portion of the shape of the vertical projection of the first opening pattern onto the semiconductor device.

7. The manufacturing method of claim 1, wherein the shape of the vertical projection of at least one of the plurality of contact structures onto the semiconductor device includes a concave side, and at least one of the plurality of signal lines overlaps the concave side.

8. A semiconductor structure, comprising: Semiconductor devices; Multiple contact structures are located in the semiconductor device, wherein the shape of at least one of the multiple contact structures in the vertical projection onto the semiconductor device includes a concave side. as well as A plurality of first signal lines are located on the plurality of contact structures, and at least one of the plurality of first signal lines overlaps the side of the recess.

9. The semiconductor structure of claim 8, wherein the semiconductor device comprises: Substrate; as well as A plurality of second signal lines are embedded in the substrate, wherein the plurality of first signal lines include bit lines and the plurality of second signal lines include word lines.

10. The semiconductor structure of claim 8, wherein the sidewall of at least one of the plurality of contact structures is aligned with the sidewall of at least one of the plurality of first signal lines.

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