Semiconductor device

Abstract

The present disclosure can provide a semiconductor device including: a substrate; a first stack structure on the substrate and including a plurality of semiconductor patterns stacked in a first direction and spaced apart from each other; a first conductive pattern on a first side of the first stack structure and extending in the first direction; and a plurality of data storage patterns on a second side of the first stack structure, spaced apart from each other in the first direction and extending in a second direction, the second direction intersecting the first direction. Each of the plurality of semiconductor patterns has a width in a third direction greater than a width of each of the plurality of data storage patterns in the third direction, the third direction intersecting each of the first direction and the second direction.

Description

Technical Field

[0001] The exemplary embodiments disclosed herein relate to semiconductor devices. Background Technology

[0002] As electronic products become smaller, more multifunctional, and offer higher performance, the demand for higher-capacity semiconductor devices is increasing. Therefore, there is a growing expectation to increase integration density to provide higher-capacity semiconductor devices. However, the integration density of traditional two-dimensional semiconductor devices is limited because it can be determined primarily by the area occupied by the unit cell. Therefore, a three-dimensional semiconductor device is being proposed that increases memory capacity by vertically stacking multiple cells on a substrate. Summary of the Invention

[0003] Some example embodiments of this disclosure provide semiconductor devices with improved electrical characteristics and / or increased integration density.

[0004] Some exemplary embodiments of this disclosure are not limited to the above description. Those skilled in the art can clearly understand other variations of exemplary embodiments not explicitly described herein from the description of this disclosure.

[0005] According to some example embodiments of this disclosure, a semiconductor device may include: a substrate; a first stacked structure located on the substrate and including a plurality of semiconductor patterns stacked and spaced apart from each other in a first direction; a first conductive pattern located on a first side of the first stacked structure and extending in the first direction; and a plurality of data storage patterns located on a second side of the first stacked structure, spaced apart from each other in the first direction, and extending in a second direction intersecting the first direction. The width of each of the plurality of semiconductor patterns in a third direction is greater than the width of each of the plurality of data storage patterns in the third direction, the third direction intersecting each of the first direction and the second direction.

[0006] According to some example embodiments of this disclosure, a semiconductor device may include: a substrate; a first stacked structure located on the substrate and including a plurality of semiconductor patterns stacked and spaced apart from each other in a first direction; a first conductive pattern located on a first side of the first stacked structure and extending in the first direction; a plurality of data storage patterns located on a second side of the first stacked structure, spaced apart from each other in the first direction and extending in a second direction, the second direction intersecting the first direction; a second stacked structure located on the substrate and spaced apart from the first stacked structure in a third direction, the third direction intersecting each of the first direction and the second direction; and a support pattern located between the first stacked structure and the second stacked structure. The support pattern includes a first region and a second region, the second region extending from the first region in the second direction, and the depth of the first region in the first direction being less than the depth of the second region in the first direction.

[0007] According to some example embodiments of this disclosure, a semiconductor device may include: a substrate; a first stacked structure located on the substrate and including a plurality of semiconductor patterns stacked and spaced apart from each other in a first direction; a first conductive pattern located on a first side of the first stacked structure and extending in the first direction; a plurality of data storage patterns located on a second side of the first stacked structure, spaced apart from each other in the first direction and extending in a second direction, the second direction intersecting the first direction; a second stacked structure located on the substrate and spaced apart from the first stacked structure in a third direction, the third direction intersecting each of the first direction and the second direction; and a support pattern located between the first stacked structure and the second stacked structure. The width of each of the plurality of semiconductor patterns in the third direction is greater than the width of each of the plurality of data storage patterns in the third direction. The width of each of the plurality of semiconductor patterns in the third direction decreases along the second direction toward the second side of the first stacked structure. The support pattern includes a first region and a second region, the second region extending from the first region in the second direction, and the depth of the first region in the first direction is less than the depth of the second region in the first direction.

[0008] According to some example embodiments of this disclosure, a method of manufacturing a semiconductor device may include: alternately stacking a plurality of sacrificial layers and a plurality of semiconductor layers on a substrate along a first direction; forming a plurality of vias that penetrate the plurality of sacrificial layers and the plurality of semiconductor layers to expose the substrate; forming a plurality of support patterns in the plurality of vias; forming a plurality of trenches that penetrate the plurality of sacrificial layers and the plurality of semiconductor layers to expose the substrate; removing the plurality of sacrificial layers; forming a plurality of semiconductor strips by partially removing each of the plurality of semiconductor layers in the first direction; forming a data storage pattern in a first trench among the plurality of trenches; and forming a first conductive pattern in a second trench among the plurality of trenches.

[0009] According to some example embodiments of this disclosure, the plurality of through holes may include a first region and a second region extending from the first region in a second direction intersecting the first direction, and forming the plurality of through holes may include: forming the plurality of through holes such that the width of the first region in a third direction may be less than the width of the second region in the third direction, the third direction intersecting each of the first direction and the second direction.

[0010] According to some example embodiments of this disclosure, the plurality of through holes may include a first region and a second region extending from the first region in a second direction intersecting the first direction, and forming the plurality of through holes may include: forming the plurality of through holes such that the depth of the first region in the first direction may be less than the depth of the second region in the first direction.

[0011] According to some example embodiments of this disclosure, forming the plurality of through holes may include: forming the plurality of through holes such that the depth of the first region in the first direction can increase toward the second region.

[0012] According to some example embodiments of this disclosure, before forming the data storage pattern in the first trench of the plurality of trenches, the method may further include: partially removing each of the plurality of semiconductor strips in a second direction intersecting the first direction to form the data storage pattern.

[0013] According to some example embodiments of this disclosure, a method of manufacturing a semiconductor device may include: stacking a first stacked pattern on a substrate along a first direction by alternately performing a first deposition process for forming a plurality of sacrificial layers and a second deposition process for forming a plurality of semiconductor layers; forming a first mask layer on the first stacked pattern; performing a first etching process on the first stacked pattern to form a plurality of vias; performing a third deposition process to form a plurality of support patterns in the plurality of vias; forming a second mask layer on the plurality of support patterns and the first mask layer; performing a second etching process to form a first trench, a second trench, and a lower pattern in the substrate located between the first trench and the second trench; performing a third etching process to remove the plurality of sacrificial layers; performing a thinning process to form a plurality of semiconductor strips by thinning each of the plurality of semiconductor layers in a first direction; and forming a plurality of first stacked structures and data storage patterns between the plurality of semiconductor strips in the first direction.

[0014] According to some example embodiments of this disclosure, in performing the first etching process, each of the plurality of vias may be formed having a first region and a second region, wherein the depth of the first region in the first direction is less than the depth of the second region in the first direction, and the depth of the first region in the first direction increases toward the second region.

[0015] According to some example embodiments of this disclosure, the integration density of semiconductor devices can be increased by increasing the spacing between horizontally adjacent data storage patterns.

[0016] According to some example embodiments of this disclosure, semiconductor devices with improved electrical characteristics and / or reliability can be provided by increasing the spacing between data storage patterns that are adjacent to each other in the horizontal direction.

[0017] The various beneficial advantages and effects of this disclosure are not limited to those described above, and will be more readily understood in the process of explaining the exemplary embodiments of this disclosure. Attached Figure Description

[0018] The above and other exemplary embodiments and features of this disclosure will become clearer by referring to the accompanying drawings, which describe exemplary embodiments of the present disclosure in detail. Figure 1 This is an equivalent circuit diagram showing a cell array of a semiconductor device according to some example embodiments of the present disclosure; Figure 2 This is a plan view illustrating a semiconductor device according to some example embodiments of the present disclosure; Figure 3 It is along Figure 2 A cross-sectional view taken from line B-B'; Figure 4 It is along Figure 2 A cross-sectional view taken from line C-C'; Figures 5 to 17 This is a view illustrating intermediate steps of a method for manufacturing a semiconductor device according to some exemplary embodiments of the present disclosure; Figure 18 This is a plan view illustrating a semiconductor bar according to some example embodiments of the present disclosure; Figure 19 It is along Figure 16 A cross-sectional view taken from line C-C'. Detailed Implementation

[0019] Semiconductor devices according to some exemplary embodiments of the present disclosure will be described in detail with reference to the following accompanying drawings. The exemplary embodiments disclosed in this specification are exemplary examples. Therefore, the present disclosure is not limited thereto and may be implemented in various other forms. Each exemplary embodiment provided below is not excluded from being combined with one or more features of another exemplary embodiment or other exemplary embodiments consistent with the present disclosure but not provided herein or in this specification. For example, even if a feature described in a particular exemplary example embodiment is not described in another exemplary example embodiment, it may be understood that the feature is related to another exemplary example embodiment unless otherwise stated in the description. It should also be understood that all descriptions of principles, aspects, and exemplary example embodiments are intended to include their structural and functional equivalents. Furthermore, it should be understood that these equivalents include not only currently known equivalents but also equivalents developed in the future, i.e., all devices invented to perform the same function, regardless of their structure. For example, if the present disclosure can be applied to materials forming contacts or pathways, the material may not be limited to the metals exemplified in this specification.

[0020] When an element, component, layer, pattern, structure, region, etc., of a semiconductor device (hereinafter collectively referred to as a "component") is described as "above", "over", "on", "below", "under", "connected to", or "coupled to" another component of the semiconductor device, it may be directly above, above, above, below, under, or connected to, or there may be intermediate components therein. Conversely, when a component of a semiconductor device is described as "directly above", "directly above", "directly above", "directly below", "directly under", "directly connected to", or "directly coupled to" another component of the semiconductor device, there are no intermediate components therein. Furthermore, in this specification, the same reference numerals may refer to the same components.

[0021] Spatial relative terms, such as “above,” “over,” “on,” “above,” “above,” “under,” “below,” “below,” “under,” “top,” “bottom,” etc., are used for ease of explanation when describing the relationship between one component and another, as illustrated in the accompanying drawings. It will be understood that spatial relative terms are intended to include other orientations of the semiconductor device in use or operation, in addition to those depicted in the drawings. For example, if the semiconductor device is flipped in the drawings, a component described as “below” or “under” another component can be oriented as “above” another component, and the “top” or “upper” surface of the component can be the “bottom” or “lower” surface of the component. Thus, depending on the context, the term “below” can include both upward and downward directions, and the term “top” can include both top and bottom. In this way, the semiconductor device can be oriented (rotated 90 degrees or otherwise), and the spatial relative descriptions used in the specification can be interpreted accordingly.

[0022] In this disclosure, although the terms first, second, etc., are used to describe various elements or components, these elements or components are not limited by these terms. It should be understood that these terms are used only to distinguish one element or component from another. It should be understood that the first element or component mentioned below may also be a second element or component within the technical spirit of this disclosure.

[0023] Referring to the following figures, a semiconductor device and a method of manufacturing the same according to some exemplary embodiments of the present disclosure will be described in detail.

[0024] Figure 1 This is an equivalent circuit diagram illustrating a cell array of a semiconductor device according to some example embodiments of the present disclosure. Reference Figure 1 The semiconductor device 100 may include a plurality of memory cells MC, each memory cell MC being configured with a cell transistor TR and a cell capacitor CAP arranged and connected to each other along a first direction D1 and a second direction D2. The plurality of memory cells MC may be arranged in rows and spaced apart from each other along the first direction D1 and a third direction D3 to form a sub-cell array SCA. Here, the second direction D2 may be a direction intersecting (e.g., orthogonal) to the first direction D1. The third direction D3 may be a direction intersecting (e.g., orthogonal) to each of the first direction D1 and the second direction D2.

[0025] Semiconductor device 100 may have a plurality of subcell arrays SCA arranged spaced apart from each other along a third direction D3. A plurality of word lines WL may extend along the third direction D3 and be spaced apart from each other along a first direction D1 and a second direction D2. A plurality of bit lines BL may extend along the first direction D1 and be spaced apart from each other along each of the second direction D2 and the third direction D3.

[0026] Some bit lines in a plurality of bit lines BL can be connected to each other by a bit lines trapping line (BLS) extending along the second direction D2. For example, a bit lines reinforcement line (BLS) can connect bit lines BL that are set along the second direction D2 among a plurality of bit lines BL.

[0027] Multiple unit capacitors CAP can be jointly connected to an upper electrode PLATE extending in a first direction D1 and a third direction D3. For ease of illustration, the upper electrode PLATE is shown extending in the first direction D1, but the upper electrode PLATE positioned along the third direction D3 can form a single body.

[0028] The unit capacitor CAP and the unit transistor TR, which are arranged along the second direction D2, can be arranged in a mirror symmetry with respect to the plane extending along the first direction D1, which is perpendicular to the third direction D3 where the upper electrode PLATE is located.

[0029] The unit transistor TR can be connected to the bit line BL via DC and to the unit capacitor CAP via BC.

[0030] Figure 2 This is a plan view illustrating a semiconductor device according to some example embodiments of the present disclosure. Figure 3 It is along Figure 2 The cross-sectional view taken by line B-B'. Figure 4 It is along Figure 2 The cross-sectional view taken by line C-C'. (Reference) Figures 2 to 4 The semiconductor device 100 according to some example embodiments of the present disclosure may include a substrate 102, a plurality of cell array structures CS1 and CS2, a plurality of first conductive patterns 152, a plurality of support patterns 132 and an upper insulating layer TIL.

[0031] Substrate 102 may comprise a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, a group IV semiconductor may comprise silicon, germanium, or silicon-germanium. Substrate 102 may also comprise impurities. Substrate 102 may be a silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium substrate, or a substrate including an epitaxial layer. However, the exemplary embodiments are not limited thereto.

[0032] The first unit array structure CS1 can be disposed on the substrate 102. For example, the first unit array structure CS1 can be disposed on the substrate 102 along a direction perpendicular to the upper surface of the substrate 102. Here, the direction perpendicular to the upper surface of the substrate 102 can be referred to as the first direction D1. In some example embodiments, the first unit array structure CS1 can refer to... Figure 1 The sub-cell array SCA is shown in the figure.

[0033] The first unit array structure CS1 may include a plurality of first stacked structures SS1 and a plurality of data storage patterns 210. The plurality of first stacked structures SS1 may be disposed on a lower pattern BP formed on a substrate 102. The plurality of first stacked structures SS1 may be disposed spaced apart from each other on a second direction D2 intersecting the first direction D1.

[0034] Multiple data storage patterns 210 can be disposed on a lower pattern BP formed on a substrate 102. The multiple data storage patterns 210 can be disposed spaced apart from each other in a first direction D1. The multiple data storage patterns 210 can extend from a first stacked structure SS1 in a second direction D2. The multiple data storage patterns 210 can be connected to the first stacked structure SS1.

[0035] Multiple data storage patterns 210 can be disposed among multiple first stacked structures SS1 that are adjacent to each other in the second direction D2. In some example embodiments, each of the multiple first stacked structures SS1 can be represented as follows: Figure 1 The unit transistor TR is shown. In some example embodiments, each data storage pattern in the plurality of data storage patterns 210 can be represented as shown in the figure. Figure 1 The unit capacitor CAP is shown.

[0036] The first stacked structure SS1 may include multiple semiconductor patterns SP, multiple gate insulating layers GI, multiple interlayer insulating films ILD, multiple second conductive patterns 154, multiple first spacers S1, multiple second spacers S2, and multiple first insulating pads IL1.

[0037] Multiple semiconductor patterns SP can be disposed spaced apart from the substrate 102. The multiple semiconductor patterns SP can be disposed spaced apart from each other in a first direction D1. Here, the multiple semiconductor patterns SP can overlap each other in the first direction D1. Each semiconductor pattern in the multiple semiconductor patterns SP can extend in a second direction D2. Each semiconductor pattern in the multiple semiconductor patterns SP may include a first edge portion EA1, a second edge portion EA2, and a channel portion CH. In some example embodiments, the thickness of the top semiconductor pattern SP in the multiple semiconductor patterns SP in the first direction D1 may be greater than the thickness of the remaining semiconductor patterns SP in the first direction D1. Among the multiple semiconductor patterns SP, the top semiconductor pattern SP can extend further in the second direction D2 than the remaining semiconductor patterns SP. For example, the top semiconductor pattern SP in the multiple semiconductor patterns SP can overlap with the data storage pattern 210 in the first direction D1.

[0038] The first edge portion EA1 and the second edge portion EA2 may be spaced apart from each other in the second direction D2. A channel portion CH may be disposed between the first edge portion EA1 and the second edge portion EA2. The first edge portion EA1 may contact the first conductive pattern 152. The first edge portion EA1 may be electrically connected to the first conductive pattern 152. Here, the first conductive pattern 152 may refer to... Figure 1 The bit line BL is shown in the figure. The second edge portion EA2 can contact at least one of the plurality of data storage patterns 210. The second edge portion EA2 can be electrically connected to the data storage pattern 210. That is, each of the plurality of semiconductor patterns SP can be connected to the corresponding data storage pattern in the plurality of data storage patterns 210.

[0039] The semiconductor pattern SP may have a first side surface F1 and a second side surface F2 facing each other in a second direction D2. The first side surface F1 may be a side surface of a first edge portion EA1, and the second side surface F2 may be a side surface of a second edge portion EA2. The first side surface F1 of the semiconductor pattern SP may be in contact with the first conductive pattern 152, and the second side surface F2 may be in contact with the data storage pattern 210.

[0040] The semiconductor pattern SP can include at least one of single-crystal semiconductors, polycrystalline semiconductors, oxide semiconductors, and two-dimensional materials. For example, the single-crystal semiconductor can be single-crystal silicon. For example, the polycrystalline semiconductor can be polycrystalline silicon. For example, the oxide semiconductor can be indium gallium zinc oxide (IGZO). For example, the two-dimensional material can be MoS2, WS2, MoSe2, or WSe2. However, the exemplary embodiments are not limited thereto.

[0041] In some example embodiments, each of the first edge portion EA1 and the second edge portion EA2 of the semiconductor pattern SP may include an impurity region in which impurities (e.g., n-type or p-type impurities) are doped. The impurity region may form the source / drain region of the semiconductor pattern SP.

[0042] A second conductive pattern 154 is disposed on a semiconductor pattern SP and may extend in a third direction D3. The second conductive pattern 154 may surround a channel portion CH of the semiconductor pattern SP. That is, the channel portion CH may overlap with the second conductive pattern 154 in the first direction D1. For example, the second conductive pattern 154 may have a structure surrounding the channel portion CH of the semiconductor pattern SP (e.g., a full-ring gate structure). A single second conductive pattern 154 may surround a corresponding channel portion CH of one of the semiconductor patterns SP that are spaced apart from each other in the third direction D3. Here, the third direction D3 may be a direction that intersects with each of the first direction D1 and the second direction D2.

[0043] Each of the plurality of second conductive patterns 154 may surround the channel portion CH of a corresponding semiconductor pattern SP among a plurality of semiconductor patterns SP spaced apart from each other in the first direction D1, and may extend along the third direction D3. The second conductive patterns 154 may be spaced apart from each other in the first direction D1. The second conductive patterns 154 may refer to Figure 1 The word line WL is shown in the figure. The second conductive pattern 154 may contain any one of TiN, MoN, Mo, Ti, and Co. However, the example embodiment is not limited thereto.

[0044] A gate insulating layer GI may be disposed between the second conductive pattern 154 and the semiconductor pattern SP. The gate insulating layer GI may surround at least a portion of the semiconductor pattern SP. For example, the gate insulating layer GI may surround the first edge portion EA1 and the channel portion CH of the semiconductor pattern SP. Multiple gate insulating layers GI may be provided. Each of the multiple gate insulating layers GI may surround at least a portion of the corresponding semiconductor pattern SP.

[0045] The gate insulating layer GI may comprise at least one of silicon oxide, silicon oxynitride, and a high-k material with a dielectric constant higher than that of silicon oxide. The high-k material may include metal oxides or metal oxynitrides. For example, high-k materials that can be used as the gate insulating layer GI may include, but are not limited to, at least one of HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, and Al2O3. However, the exemplary embodiments are not limited thereto. A material having a high dielectric constant (high k) can be defined as a material with a dielectric constant higher than that of silicon oxide.

[0046] An interlayer insulating film (ILD) can be disposed between adjacent second conductive patterns 154 along a first direction D1. The second conductive patterns 154 can be spaced apart from each other by the interlayer insulating film (ILD) in the first direction D1. One side surface of the interlayer insulating film (ILD) can contact a side surface of the first conductive pattern 152. Multiple interlayer insulating films (ILDs) can be provided. The first stacking structure SS1 can be a structure in which multiple second conductive patterns 154 and multiple interlayer insulating films (ILDs) are alternately stacked in the first direction D1. The interlayer insulating film (ILD) can include a single film or a composite film containing insulating material.

[0047] The first spacer S1 may be disposed between interlayer insulating films (ILDs) adjacent to each other along the first direction D1. The first spacer S1 may surround at least a portion of the semiconductor pattern SP. For example, the first spacer S1 may surround a first edge portion EA1 of the semiconductor pattern SP. The first spacer S1 may surround at least a portion of the gate insulating layer GI. One side surface of the first spacer S1 may contact a side surface of the first conductive pattern 152. Multiple first spacers S1 may be provided. The first spacer S1 may comprise a single film or a composite film containing insulating material.

[0048] The second spacer S2 can be disposed between interlayer insulating films (ILDs) adjacent to each other along the first direction D1. The second spacer S2 can surround at least a portion of the semiconductor pattern SP. For example, the second spacer S2 can surround the second edge portion EA2 of the semiconductor pattern SP. Multiple second spacers S2 can be provided. The second spacer S2 can include a single film or a composite film containing insulating material.

[0049] A first insulating pad IL1 may be disposed between second spacers S2 adjacent to each other along the first direction D1. The first insulating pad IL1 may surround at least a portion of the semiconductor pattern SP. For example, the first insulating pad IL1 may cover the upper and lower surfaces of the second edge portion EA2 of the semiconductor pattern SP. The first insulating pad IL1 may be disposed on one side of the second spacers S2. The first insulating pad IL1 may comprise silicon oxide, silicon nitride, or a metal oxide with a dielectric constant higher than that of silicon oxide. The metal oxide may include hafnium oxide, aluminum oxide, zirconium oxide, tantalum oxide, or combinations thereof. However, the exemplary embodiments are not limited thereto. The first insulating pad IL1 may be a single layer or multiple layers.

[0050] A first conductive pattern 152 may be disposed on a substrate 102. The first conductive pattern 152 may fill a second trench STR2 formed on the substrate 102. The first conductive pattern 152 may be disposed on a first side of the first stacked structure SS1. The first conductive pattern 152 may extend in a first direction D1. For example, the first conductive pattern 152 may be disposed on a first side surface F1 of a semiconductor pattern SP. The first conductive pattern 152 may extend along the first direction D1 on the first side surface F1 of the semiconductor pattern SP. Therefore, a single first conductive pattern 152 may contact the first side surface F1 of each of a plurality of semiconductor patterns SPs spaced apart from each other in the first direction D1, and may be electrically connected to the plurality of semiconductor patterns SPs.

[0051] The first conductive pattern 152 may include, but is not limited to, at least one of the following: doped polycrystalline silicon, metals (e.g., Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co), conductive metal nitrides (e.g., TiN, TaN, WN, NbN, TiAlN, TiSiN, TaSiN, RuTiN), conductive metal silicides, or conductive metal oxides (e.g., PtO, RuO2, IrO2, SRO (SrRuO3), BSRO ((Ba,Sr)RuO3), CRO (CaRuO3), LSCo). The first conductive pattern 152 may comprise a single layer or multiple layers of the aforementioned materials. In some example embodiments, the first conductive pattern 152 may comprise a two-dimensional material. For example, the two-dimensional material may comprise graphene, carbon nanotubes, or combinations thereof. However, the example embodiments are not limited thereto.

[0052] The data storage pattern 210 may include a first electrode 212, a capacitor dielectric film 214 disposed on the first electrode 212, and a second electrode 216 disposed on the capacitor dielectric film 214. In some example embodiments, the semiconductor device 100 may be a dynamic random access memory (DRAM), and the data storage pattern 210 may be a capacitor. The first electrode 212 may be spaced apart from the second electrode 216, and the capacitor dielectric film 214 is located between the first electrode 212 and the second electrode 216. In the illustrated example embodiment, the data storage pattern 210 is disclosed as a columnar structure, but the example embodiment is not limited to this example, and the data storage pattern 210 may be configured in various shapes, such as cylindrical or concave.

[0053] Each of the first electrode 212 and the second electrode 216 may comprise a conductive material. For example, each of the first electrode 212 and the second electrode 216 may comprise at least one of the following: doped silicon (Si), doped silicon-germanium (SiGe), metallic materials (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, Pt, Au, Ag, etc.), metal nitrides (e.g., nitrides such as Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, Pt, Au, or Ag), titanium silicon nitride (e.g., TiSiN), titanium aluminum nitride (e.g., TiAlN), and tantalum aluminum nitride (e.g., TaAlN), conductive oxides (e.g., PtO, RuO2, IrO2, SRO (SrRuO3), BSRO ((Ba,Sr)RuO3), CRO (CaRuO3), LSCo), and metal silicides. However, the exemplary embodiments are not limited thereto. Each of the first electrode 212 and the second electrode 216 can be a single membrane made of a single material or a composite membrane comprising two or more materials.

[0054] For example, the capacitor dielectric film 214 may comprise at least one of a metal oxide (e.g., HfO2, ZrO2, Al2O3, La2O3, Ta2O3, and TiO2) and a perovskite-structured dielectric material (such as SrTiO3 (STO), (Ba,Sr)TiO3 (BST), BaTiO3, PZT (lead zirconate titanate), and PLZT (lanthanum lead zirconate titanate)). However, the exemplary embodiments are not limited thereto.

[0055] In some example embodiments, the data storage pattern 210 may be a variable resistance pattern that can be switched between two resistance states by an electrical pulse. In this case, the data storage pattern (DSP) may include a phase change material, perovskite compound, transition metal oxide, magnetic material, ferromagnetic material, or antiferromagnetic material whose crystal state changes according to the amount of current. However, the example embodiments are not limited thereto.

[0056] The upper insulating layer TIL can be disposed on the first stacked structure SS1. The upper insulating layer TIL can be disposed on the top semiconductor pattern SP among a plurality of semiconductor patterns SP. One side of the upper insulating layer TIL can contact the side surface of the first conductive pattern 152. The upper insulating layer TIL can overlap with the first stacked structure SS1 and the data storage pattern 210 in the first direction D1. The upper insulating layer TIL can include a single film or composite film containing insulating material. For example, the upper insulating layer TIL can contain silicon oxide, silicon oxynitride, or silicon nitride. However, the example embodiment is not limited thereto.

[0057] The semiconductor device 100 may also include a first filling film FL1. The first filling film FL1 may be disposed on a substrate 102. The first filling film FL1 may fill a first trench STR1 formed on the substrate 102. A portion of the first filling film FL1 may extend in a second direction D2 and be disposed on a data storage pattern 210. For example, the first filling film FL1 may be disposed between adjacent data storage patterns 210 along the first direction D1. That is, the first filling film FL1 may overlap with the data storage pattern 210 in the first direction D1. Optionally, the first filling film FL1 may overlap with the data storage pattern 210 in the second direction D2. The first filling film FL1 may overlap with an upper insulating layer TIL in the second direction D2. The first filling film FL1 may be in contact with the data storage pattern 210. The first filling film FL1 may include silicon germanium (SiGe). Although the semiconductor device 100 has been described as including the first filling film FL1, the first filling film FL1 may be omitted if the second electrode 216 is a plate electrode. However, the example embodiment is not limited thereto.

[0058] The second unit array structure CS2 may be spaced apart from the first unit array structure CS1 in the third direction D3. The second unit array structure CS2 may be disposed on the substrate 102 in a direction perpendicular to the upper surface of the substrate 102. The second unit array structure CS2 may be disposed on the lower pattern BP formed on the substrate 102. In some example embodiments, the second unit array structure CS2 may refer to... Figure 1 The sub-cell array SCA is shown in the diagram. The second cell array structure CS2 may have the same or similar configuration as the first cell array structure CS1. Therefore, the description of the configuration overlapping with the first cell array structure CS1 is omitted. The second cell array structure CS2 may include multiple second stacked structures SS2. The multiple second stacked structures SS2 may be spaced apart from the multiple first stacked structures SS1 of the first cell array structure CS1 in a third direction D3. The second stacked structures SS2 may have the same or similar configuration as the first stacked structures SS1. Therefore, the description of the configuration of the second stacked structures SS2 overlapping with the first stacked structures SS1 is omitted.

[0059] Support pattern 132 may be disposed on substrate 102. Support pattern 132 may be disposed between the first stacked structure SS1 and the second stacked structure SS2. Support pattern 132 may be made of the same material as the upper insulating layer TIL. For example, support pattern 132 may include silicon oxide, silicon oxynitride, or silicon nitride. However, the example embodiment is not limited thereto.

[0060] In some example embodiments, the data storage pattern 210 connected to the first stack structure SS1 and the data storage pattern 210 connected to the second stack structure SS2 may be spaced apart from each other on the third direction D3. For example, a support pattern 132 may be disposed between the data storage pattern 210 connected to the first stack structure SS1 and the data storage pattern 210 connected to the second stack structure SS2. The data storage pattern 210 connected to the first stack structure SS1 and the data storage pattern 210 connected to the second stack structure SS2 may be spaced apart from each other on the third direction D3 by a desired (and / or alternatively, predetermined) distance or a greater distance.

[0061] In some example embodiments, the width of each semiconductor pattern in the plurality of semiconductor patterns SP in the third direction D3 can be greater than the width of each data storage pattern in the plurality of data storage patterns 210 in the third direction D3. Therefore, the distance in the third direction D3 between the plurality of semiconductor patterns SP of the first stacked structure SS1 and the plurality of semiconductor patterns SP of the second stacked structure SS2 can be less than the distance in the third direction D3 between the plurality of data storage patterns 210 connected to the first stacked structure SS1 and the plurality of data storage patterns 210 connected to the second stacked structure SS2. In some example embodiments, the portion of the first stacked structure SS1 connected to the data storage pattern 210 can be defined as the second side of the first stacked structure SS1. Here, the width of each semiconductor pattern in the plurality of semiconductor patterns SP of the first stacked structure SS1 in the third direction D3 can decrease as it approaches the second side of the first stacked structure SS1 along the second direction D2. However, the semiconductor pattern SP can have a region where its width in the third direction D3 remains constant.

[0062] Figures 5 to 17 This is a diagram illustrating intermediate steps of a method for manufacturing a semiconductor device according to some exemplary embodiments of the present disclosure. For ease of explanation, details may be omitted. Figures 1 to 4 Detailed description of components that are the same as or similar to those described in the embodiments disclosed herein.

[0063] refer to Figure 5 and Figure 6According to some exemplary embodiments of the present disclosure, a method for manufacturing a semiconductor device may involve alternately stacking a plurality of sacrificial layers 110 and a plurality of semiconductor layers 120 on a substrate 102 to form a pre-stacked structure PS. For example, a plurality of sacrificial layers 110 and a plurality of semiconductor layers 120 may be alternately stacked on the substrate 102 along a first direction D1. The sacrificial layer 110 may comprise silicon germanium (SiGe), and the semiconductor layer 120 may comprise silicon (Si). However, the exemplary embodiments are not limited thereto. The semiconductor layer 120 may be disposed on top of the stacked structure. An insulating layer TIL may also be disposed on the semiconductor layer 120 disposed at the topmost position to form the pre-stacked structure PS.

[0064] In some example embodiments, a plurality of sacrificial layers 110, a plurality of semiconductor layers 120, and an upper insulating layer TIL can be formed by chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), or atomic layer deposition (ALD). However, the example embodiments are not limited thereto. In some example embodiments, each of the plurality of sacrificial layers 110 and the plurality of semiconductor layers 120 can be formed in a single-crystal state using a layer in contact with it as a seed layer, or it can be formed in a single-crystal state by a thermal processing process. In some example embodiments, each of the plurality of sacrificial layers 110 and the plurality of semiconductor layers 120 can be formed to have a substantially uniform thickness.

[0065] refer to Figure 7 and Figure 8 After forming the first mask layer 130 on the pre-stacked structure PS, the first mask layer 130 can be used as an etching mask to form a plurality of vias STH that penetrate the pre-stacked structure PS and expose the substrate 102. The first mask layer 130 may have a plurality of openings corresponding to the plurality of vias STH. In some example embodiments, the first mask layer 130 may be made of silicon nitride.

[0066] In some example embodiments, the stacked vias STH can be arranged in a mirror symmetry with respect to an imaginary line extending along a third direction D3 between two adjacent stacked vias STH located along the second direction D2.

[0067] In some example embodiments, each of the plurality of vias STH may include a first region R1 and a second region R2 extending from the first region R1 in a second direction D2. The width of the first region R1 in a third direction D3 may be smaller than the width of the second region R2 in the third direction D3. In this way, because the widths of the first region R1 and the second region R2 in the third direction D3 are different, the depth of the first region R1 in the first direction D1 may be smaller than the depth of the second region R2 in the first direction D1 as a result of etching using the first mask layer 130. In some example embodiments, the depth of the first region R1 in the first direction D1 may increase as it approaches the second region R2.

[0068] refer to Figure 9 and Figure 10 Multiple support patterns 132 can be formed within multiple vias STH. For example, the multiple support patterns 132 can fill multiple vias STH. Therefore, each of the multiple support patterns 132 may include a first region R1 and a second region R2 extending from the first region R1 in a second direction D2. The width of the first region R1 in a third direction D3 may be smaller than the width of the second region R2 in the third direction D3. The depth of the first region R1 in the first direction D1 may be smaller than the depth of the second region R2 in the first direction D1. In some example embodiments, the depth of the first region R1 in the first direction D1 may increase as it approaches the second region R2. The multiple support patterns 132 can be formed by CVD, PECVD, ALD, etc. However, the example embodiments are not limited thereto.

[0069] refer to Figures 11 to 13 After forming the second mask layer 140 on the first mask layer 130, the second mask layer 140 can be used as an etching mask. The second mask layer 140 can be used as an etching mask to form a plurality of trenches STR1 and STR2 exposing the substrate 102 by penetrating the pre-stacked structure PS. The second mask layer 140 may have a plurality of openings corresponding to the plurality of trenches STR1 and STR2. In some example embodiments, the second mask layer 140 may be made of silicon nitride. Here, the first trench STR1 and the second trench STR2 may be formed as at least a portion penetrating the substrate. Therefore, a lower pattern BP can be formed on the substrate 102. The pre-stacked structure PS can be formed on the lower pattern BP.

[0070] Let's refer to each other. Figures 11 to 15Multiple sacrificial layers 110 can be removed via the first trench STR1 and the second trench STR2. For example, the multiple sacrificial layers 110 can be removed via an isotropic etching process with etch selectivity relative to the substrate 102, the multiple semiconductor layers 120, the multiple support patterns 132, and the upper insulating layer TIL. Next, multiple semiconductor strips 120S can be formed by removing portions of the multiple semiconductor layers 120 exposed via the first trench STR1 and the second trench STR2 (e.g., a thinning process for thinning the multiple semiconductor layers 120). For example, the multiple semiconductor strips 120S can be formed by partially removing each of the multiple semiconductor layers 120 in the first direction D1. Here, the semiconductor layer 120 disposed at the top may not be removed. Therefore, the width of each semiconductor strip in the multiple semiconductor strips 120S in the first direction D1 can be formed to have a value smaller than the width of the uppermost semiconductor layer 120 in the first direction D1.

[0071] A plurality of semiconductor strips 120S can be formed by removing portions of the plurality of semiconductor layers 120 using an isotropic etching process that is selective for etching relative to the plurality of support patterns 132 and the upper insulating layer TIL. Therefore, the plurality of semiconductor strips 120S can be spaced apart from each other in the first direction D1. The plurality of semiconductor strips 120S can be supported by the plurality of support patterns 132.

[0072] refer to Figure 16 and Figure 17 Multiple second conductive patterns 154, multiple first spacers S1, and multiple second spacers S2 can be formed to surround at least a portion of the semiconductor strip 120S. Additionally, multiple interlayer insulating films (ILDs) can be formed between adjacent second conductive patterns 154 along the first direction D1.

[0073] Additionally, a gate insulating layer GI, a first insulating pad IL1, and a second insulating pad IL2 can be formed to surround at least a portion of the plurality of semiconductor strips 120S. The second insulating pad IL2 can be disposed on the first insulating pad IL1. The second insulating pad IL2 can comprise silicon oxide, silicon nitride, or silicon oxynitride. However, the example embodiment is not limited thereto. Furthermore, a second filler film FL2 can fill the first trench STR1. Additionally, a first conductive pattern 152 can fill the second trench STR2.

[0074] In some example embodiments, the second filling film FL2 may fill at least a portion of the first trench STR1. For example, as shown, the second filling film FL2 may not fill the central portion of the first trench STR1. The second filling film FL2 may fill at least a portion of the space between a plurality of semiconductor strips 120S spaced apart from each other in the first direction D1. For example, the second filling film FL2 may overlap with the plurality of semiconductor strips 120S in the first direction D1. The second filling film FL2 may comprise silicon oxide, silicon nitride, or silicon oxynitride. However, the example embodiments are not limited thereto. Afterward, portions of the first insulating pad IL1, the second insulating pad IL2, the second filling film FL2, and the second portions of each of the plurality of semiconductor strips 120S are removed, and then a structure is formed as shown... Figures 1 to 4 The first filling film FL1 and the data storage pattern 210 shown are used to form a semiconductor device 100. Here, in order to form the data storage pattern 210, each of the plurality of semiconductor strips 120S can be partially removed in a second direction D2 intersecting the first direction D1.

[0075] Figure 18 This is a plan view illustrating a semiconductor strip according to some example embodiments of the present disclosure. Figure 19 It is along Figure 16 The cross-sectional view taken by line C-C'. (Reference) Figure 18 The semiconductor strip 120S may include a first portion 120S_1P and a second portion 120S_2P. Here, the width of the first portion 120S_1P in the third direction D3 may be greater than the width of the second portion 120S_2P in the third direction D3. In some example embodiments, the width of the first portion 120S_1P in the third direction D3 may decrease as it approaches the second portion 120S_2P. However, at least a portion of the width of the first portion 120S_1P in the third direction D3 may be constant along the second direction D2.

[0076] Let's refer to each other. Figures 1 to 4 The first portion 120S_1P forms a semiconductor pattern SP, and the second portion 120S_2P can be replaced by a data storage pattern 210. Therefore, the width of the semiconductor pattern SP in the third direction D3 can be greater than the width of the data storage pattern 210 in the third direction D3. Thus, a semiconductor device with improved electrical characteristics and / or integration density can be provided by increasing the spacing between adjacent data storage patterns in the third direction D3.

[0077] Let's refer to each other. Figure 18 and Figure 19Two adjacent semiconductor strips 120S among a plurality of semiconductor strips 120S may be spaced apart from each other in the third direction D3. Here, a support pattern 132 may be provided between the semiconductor strips 120S. In some example embodiments, the width of the second portion 120S_2P in the third direction D3 may be smaller than the width of the first portion 120S_1P in the third direction D3. Therefore, the separation distance between adjacent second portions 120S_2P in the third direction D3 may be greater than the separation distance between the first portions 120S_1P. Therefore, the first insulating pad IL1 surrounding each of the adjacent second portions 120S_2P in the third direction D3 may be spaced apart in the third direction D3. Additionally, the second insulating pad IL2 surrounding each of the adjacent second portions 120S_2P in the third direction D3 may be spaced apart from each other in the third direction D3. Therefore, a semiconductor device with improved electrical characteristics and / or integration level can be fabricated.

[0078] Although this disclosure has been described above with reference to limited exemplary embodiments and accompanying drawings, this disclosure is not limited thereto, and those skilled in the art can make various modifications and variations within the equivalent scope of the technical concept and the described claims.

Claims

1. A semiconductor device, the semiconductor device comprising: Substrate; A first stacked structure is located on the substrate and includes a plurality of semiconductor patterns stacked in a first direction and spaced apart from each other; A first conductive pattern is located on a first side of the first stacked structure and extends in the first direction; as well as Multiple data storage patterns are located on a second side of the first stacked structure, spaced apart from each other in the first direction and extending in a second direction, the second direction intersecting the first direction. Wherein, the width of each of the plurality of semiconductor patterns in the third direction is greater than the width of each of the plurality of data storage patterns in the third direction, and the third direction intersects with each of the first direction and the second direction.

2. The semiconductor device according to claim 1, wherein, The width of each of the plurality of semiconductor patterns decreases along the second direction toward the second side of the first stacked structure in the third direction.

3. The semiconductor device according to claim 1, further comprising: A second stacked structure is located on the substrate and is spaced apart from the first stacked structure in the third direction. as well as A support pattern is located between the first stacked structure and the second stacked structure.

4. The semiconductor device according to claim 3, wherein, The support pattern includes a first region and a second region, the second region extending from the first region in the second direction, and The depth of the first region in the first direction is less than the depth of the second region in the first direction.

5. The semiconductor device according to claim 4, wherein, The depth of the first region in the first direction increases toward the second region.

6. The semiconductor device according to claim 4, wherein, The first region overlaps with the plurality of semiconductor patterns in the third direction, and The second region overlaps with the plurality of data storage patterns in the third direction.

7. The semiconductor device according to claim 1, wherein, Each of the plurality of semiconductor patterns is connected to a corresponding data storage pattern among the plurality of data storage patterns.

8. The semiconductor device according to claim 1, further comprising: A filling film is located on the plurality of data storage patterns. Each of the plurality of data storage patterns includes: First electrode; A capacitor dielectric film, the capacitor dielectric film being located on the first electrode; and The second electrode is located on the dielectric film of the capacitor.

9. The semiconductor device according to claim 1, wherein, Each of the plurality of semiconductor patterns includes: A first edge portion, the first edge portion being in contact with the first conductive pattern; A second edge portion, the second edge portion contacting one of the plurality of data storage patterns; and The channel portion is located between the first edge portion and the second edge portion.

10. The semiconductor device according to claim 9, further comprising: A second conductive pattern is located on each of the plurality of semiconductor patterns and extends upward from the third. The channel portion overlaps with the second conductive pattern in the first direction.

11. The semiconductor device according to claim 1, wherein, The thickness of the uppermost semiconductor pattern among the plurality of semiconductor patterns in the first direction is greater than the thickness of the other semiconductor patterns among the plurality of semiconductor patterns in the first direction.

12. A semiconductor device, the semiconductor device comprising: Substrate; A first stacked structure is located on the substrate and includes a plurality of semiconductor patterns stacked in a first direction and spaced apart from each other; A first conductive pattern is located on a first side of the first stacked structure and extends in the first direction; Multiple data storage patterns are located on a second side of the first stacked structure, spaced apart from each other in the first direction and extending in the second direction, the second direction intersecting the first direction; A second stacked structure is located on the substrate and is spaced apart from the first stacked structure in a third direction, the third direction intersecting each of the first direction and the second direction; as well as A support pattern is located between the first stacked structure and the second stacked structure. The support pattern includes a first region and a second region, wherein the second region extends from the first region in the second direction, and The depth of the first region in the first direction is less than the depth of the second region in the first direction.

13. The semiconductor device according to claim 12, wherein, The depth of the first region in the first direction increases toward the second region.

14. The semiconductor device according to claim 12, wherein, The width of each of the plurality of semiconductor patterns in the third direction is greater than the width of each of the plurality of data storage patterns in the third direction.

15. The semiconductor device according to claim 14, wherein, The width of each of the plurality of semiconductor patterns decreases along the second direction toward the second side of the first stacked structure in the third direction.

16. The semiconductor device of claim 12, wherein, The first region overlaps with the plurality of semiconductor patterns in the third direction, and The second region overlaps with the plurality of data storage patterns in the third direction.

17. The semiconductor device according to claim 12, wherein, Each of the plurality of semiconductor patterns is connected to a corresponding data storage pattern among the plurality of data storage patterns.

18. The semiconductor device according to claim 12, wherein, Each of the plurality of semiconductor patterns includes: A first edge portion, the first edge portion contacting the first conductive pattern; A second edge portion, the second edge portion contacting one of the plurality of data storage patterns; and The channel portion is located between the first edge portion and the second edge portion.

19. The semiconductor device of claim 18, further comprising: A second conductive pattern is located on each of the plurality of semiconductor patterns and extends upward from the third. The channel portion overlaps with the second conductive pattern in the first direction.

20. A semiconductor device, the semiconductor device comprising: Substrate; A first stacked structure is located on the substrate and includes a plurality of semiconductor patterns stacked in a first direction and spaced apart from each other; A first conductive pattern is located on a first side of the first stacked structure and extends in the first direction; Multiple data storage patterns are located on a second side of the first stacked structure, spaced apart from each other in the first direction and extending in the second direction, the second direction intersecting the first direction; A second stacked structure is located on the substrate and is spaced apart from the first stacked structure in a third direction, the third direction intersecting each of the first direction and the second direction; as well as A support pattern is located between the first stacked structure and the second stacked structure. in, The width of each of the plurality of semiconductor patterns in the third direction is greater than the width of each of the plurality of data storage patterns in the third direction. The width of each of the plurality of semiconductor patterns decreases in the third direction toward the second side of the first stacked structure. The support pattern includes a first region and a second region, the second region extending from the first region in the second direction, and The depth of the first region in the first direction is less than the depth of the second region in the first direction.

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