Semiconductor device
By employing a multi-row active pattern design in DRAM and utilizing isolation structures of varying depths to increase contact area and support, the limitations of isolation pattern depth and the collapse of active patterns are resolved, thereby improving electrical performance and stability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- FUJIAN JINHUA INTEGRATED CIRCUIT CO LTD
- Filing Date
- 2022-04-01
- Publication Date
- 2026-07-14
Smart Images
Figure CN122395939A_ABST
Abstract
Description
[0001] This application is a divisional application of Chinese Patent CN202210349195.5, filed on April 1, 2022, entitled "Semiconductor Device and Preparation Method Thereof". Technical Field
[0002] This application relates to the field of semiconductor device technology, and specifically to a semiconductor device. Background Technology
[0003] With the trend of miniaturization in various electronic products, the design of dynamic random access memory (DRAM) must also meet the requirements of high integration and high density. For DRAM with recessed gate structure, it has gradually replaced DRAM with only planar gate structure because it can obtain a longer carrier channel length within the same semiconductor substrate.
[0004] Generally, DRAM with a recessed gate structure consists of a large number of memory cells arranged in an array to store data. Each memory cell can be composed of a transistor element and a charge storage device connected in series to receive voltage signals from the word line (WL) and bit line (BL). The word line is located within the substrate and intersects with the active pattern and the isolation pattern. However, in existing structures, due to the limitation of the isolation pattern depth, the contact area between the word line and other structures and the active pattern in the vertical direction is limited in order to ensure the isolation effect, thus limiting the improvement of the device's electrical performance.
[0005] In addition, as the integration density of integrated circuits increases, the density of fine active patterns on the substrate will increase accordingly, and the aspect ratio of active patterns will become larger and larger, making the isolation patterns insufficient to support the active patterns, and the active patterns are prone to collapse. Summary of the Invention
[0006] To address the aforementioned problems, this application provides a semiconductor device that solves the technical problems in the prior art where the limitation of isolation pattern depth restricts the electrical performance of the device and the active pattern in highly integrated circuits is prone to collapse.
[0007] In a first aspect, this application provides a semiconductor device, comprising: Semiconductor substrate; Multiple rows of active patterns are disposed on the upper surface of the substrate; wherein, the multiple rows of active patterns extend along a first direction and are arranged sequentially along a second direction, the second direction being different from the first direction; any two adjacent rows of active patterns are staggered. A first isolation structure is disposed within the upper surface of the substrate and located between any two adjacent active patterns in the same row; The second isolation structure is disposed within the upper surface of the substrate and located between any two adjacent rows of the active patterns; Wherein, the vertical distance from the bottom of the first isolation structure to the upper surface of the substrate is greater than the vertical distance from the bottom of the second isolation structure to the upper surface of the substrate.
[0008] According to an embodiment of this application, optionally, in the above-described semiconductor device, the first isolation structure at any row of active pattern locations is in contact with the adjacent row of active patterns.
[0009] According to an embodiment of this application, optionally, in the above-described semiconductor device, the bottom of the first isolation structure is recessed in a direction extending away from the upper surface of the substrate.
[0010] According to an embodiment of this application, optionally, in the above-described semiconductor device, the bottom of the first isolation structure is a platform shape parallel to the upper surface of the substrate.
[0011] According to an embodiment of this application, optionally, in the above-described semiconductor device, the bottom of the second isolation structure is a protrusion extending in a direction close to the upper surface of the substrate.
[0012] According to an embodiment of this application, optionally, in the above-described semiconductor device, the minimum vertical distance from the bottom of the second isolation structure between any two adjacent first isolation structures to the upper surface of the substrate decreases as the distance between any two adjacent first isolation structures in the first direction increases.
[0013] According to an embodiment of this application, optionally, in the above-described semiconductor device, when the distance between two adjacent first isolation structures in the first direction is greater than a preset threshold, the top of the bottom of the second isolation structure between the two adjacent first isolation structures forms a platform.
[0014] According to an embodiment of this application, optionally, in the above-described semiconductor device, the bottom of the second isolation structure is a platform shape parallel to the upper surface of the substrate.
[0015] According to an embodiment of this application, optionally, in the above-described semiconductor device, the materials of the first isolation structure and the second isolation structure respectively include different insulating materials.
[0016] According to an embodiment of this application, optionally, in the above-described semiconductor device, in a plane parallel to the upper surface of the substrate, the width of the first isolation structure in the second direction is greater than the width of the second isolation structure in the second direction.
[0017] Secondly, this application provides a method for fabricating a semiconductor device, comprising: Provide semiconductor substrates; An active region is formed within the upper surface of the substrate; A first shallow isolation trench and a second shallow isolation trench are formed within the upper surface of the substrate, penetrating the active region to truncate the active region into multiple rows of active patterns extending along a first direction and arranged sequentially along a second direction; wherein the second direction is different from the first direction, and any two adjacent rows of active patterns are staggered; the first shallow isolation trench is located between any two adjacent active patterns in the same row, and the second shallow isolation trench is located between any two adjacent rows of active patterns; the vertical distance from the bottom of the first shallow isolation trench to the upper surface of the substrate is greater than the vertical distance from the bottom of the second shallow isolation trench to the upper surface of the substrate. A first isolation structure and a second isolation structure are formed in the first shallow isolation trench and the second shallow isolation trench, respectively.
[0018] According to an embodiment of this application, optionally, in the above-described method for fabricating a semiconductor device, the first shallow isolation trench at any position of the active pattern in any row is in contact with the active pattern in the adjacent row.
[0019] According to an embodiment of this application, optionally, in the above-described method for fabricating a semiconductor device, the bottom of the first shallow isolation trench is a recessed shape extending in a direction away from the upper surface of the substrate.
[0020] According to an embodiment of this application, optionally, in the above-described method for fabricating a semiconductor device, the bottom of the first shallow isolation trench is in the shape of a platform parallel to the upper surface of the substrate.
[0021] According to an embodiment of this application, optionally, in the above-described method for fabricating a semiconductor device, the bottom of the second shallow isolation trench is a convex shape extending in a direction close to the upper surface of the substrate.
[0022] According to an embodiment of this application, optionally, in the above-described method for fabricating a semiconductor device, the bottom of the second shallow isolation trench is in the shape of a platform parallel to the upper surface of the substrate.
[0023] Compared with the prior art, one or more embodiments of the above solutions may have the following advantages or beneficial effects: This application provides a semiconductor device and its fabrication method. The semiconductor device includes multiple rows of active patterns disposed on the upper surface of a substrate; a first isolation structure disposed on the upper surface of the substrate and located between any two adjacent active patterns in the same row; and a second isolation structure disposed on the upper surface of the substrate and located between any two adjacent rows of active patterns. The vertical distance from the bottom of the first isolation structure to the upper surface of the substrate is greater than the vertical distance from the bottom of the second isolation structure to the upper surface of the substrate. That is, the depth of the first isolation structure is greater than the depth of the second isolation structure, thereby ensuring isolation from the semiconductor substrate while allowing for greater extension space for components such as word lines at the location of the first isolation structure. This further increases the longitudinal contact area between the word lines and other components at the location of the first isolation structure and the active patterns, enhancing the contact effect and improving the electrical performance of the device. Furthermore, the greater depth of the first isolation structure increases the support force of the deeper first isolation structure on the lower part of the surrounding active patterns, while the shallower second isolation structure still maintains support force on the upper part of the surrounding active patterns, significantly reducing the risk of active pattern collapse. Attached Figure Description
[0024] The accompanying drawings are provided to further illustrate the present application and form part of the specification. They are used together with the following detailed description to explain the present application, but do not constitute a limitation thereof. In the drawings: Figure 1 This is a schematic diagram of the front top view of a semiconductor device according to an exemplary embodiment of this application; Figure 2 yes Figure 1 A schematic diagram of the cross-sectional structure along the tangent A-A'; Figure 3 yes Figure 1 A schematic diagram of the cross-sectional structure along the tangent B-B'; Figure 4a and Figure 4b yes Figure 1 Another cross-sectional view of the structure along tangent A-A'; Figure 5 yes Figure 1 Another cross-sectional structural diagram along tangent B-B'; Figure 6a , Figure 6b and Figure 6c yes Figure 1 Another cross-sectional view of the structure along tangent A-A'; Figure 7 This is a schematic diagram of the front top view of another semiconductor device illustrated in an exemplary embodiment of this application; Figure 8a and 8b yes Figure 7 A schematic diagram of the cross-sectional structure along the tangent A-A'; Figure 9 This is a schematic diagram of a semiconductor device fabrication method according to an exemplary embodiment of this application; In the accompanying drawings, the same parts use the same reference numerals, and the drawings are not drawn to scale. The accompanying figure is labeled as follows: 101-Substrate; 102-Active pattern; 1021-Sub-pattern; 103-First isolation structure; 1031-First isolation structure at the location of the active pattern in the odd-numbered rows; 1032-First isolation structure at the location of the active pattern in the even-numbered rows; 103a-First shallow isolation trench; 104-Second isolation structure; 104a-Second shallow isolation trench. Detailed Implementation
[0025] The following detailed description of the embodiments of this application, in conjunction with the accompanying drawings, will provide a thorough understanding of how this application uses technical means to solve technical problems and achieve corresponding technical effects, enabling its implementation. The embodiments of this application and the various features within them can be combined with each other without conflict, and the resulting technical solutions are all within the protection scope of this application. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.
[0026] It should be understood that although the terms "first," "second," "third," etc., may be used to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or part from another element, component, area, layer, or part. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or part discussed below may be referred to as the second element, component, area, layer, or part.
[0027] It should be understood that spatial relation terms such as "above," "located above," "below," "located below," etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as "below other elements" will be oriented "above" other elements or features. Therefore, the exemplary terms "below" and "below" can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.
[0028] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.
[0029] Embodiments of this application are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures). Thus, variations in the shape shown can be anticipated due to, for example, fabrication techniques and / or tolerances. Therefore, embodiments of this application should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, fabrication. For example, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of regions of the device and are not intended to limit the scope of this application.
[0030] To fully understand this application, detailed structures and steps will be presented in the following description to illustrate the technical solutions proposed in this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.
[0031] Example 1 like Figure 1 , Figure 2 and Figure 3As shown, this application provides a semiconductor device, which includes at least a semiconductor substrate 101, an active pattern 102, a first isolation structure 103, and a second isolation structure 104.
[0032] The semiconductor substrate 101 may include at least one of, for example, a single-crystal silicon substrate 101 and a silicon epitaxial layer.
[0033] Multiple rows of active patterns 102 are disposed within the upper surface of the substrate 101. Each row of active patterns 102 includes multiple active patterns 102. The multiple rows of active patterns 102 extend along a first direction (not shown in the figure) and are arranged sequentially along a second direction (not shown in the figure). The second direction is different from the first direction, such as... Figure 1 As shown, the first direction and the second direction can be perpendicular to each other.
[0034] Furthermore, any two adjacent rows of active patterns 102 are staggered. The active patterns 102 are formed by ion implantation to create doped regions (not shown in the figure). The upper surface of the active patterns 102 is flush with the upper surface of the substrate 101.
[0035] The first isolation structure 103 is disposed within the upper surface of the substrate 101 and between any two adjacent active patterns 102 in the same row, that is, any two adjacent active patterns 102 in the same row are isolated by the first isolation structure 103.
[0036] The second isolation structure 104 is disposed within the upper surface of the substrate 101 and located between any two adjacent rows of active patterns 102, that is, any two adjacent rows of active patterns 102 are isolated from each other by the second isolation structure 104.
[0037] In this embodiment, the shape of the contact surface between the first isolation structure 103 and the active pattern 102 in the same row is not limited. In a plane parallel to the upper surface of the substrate 101, the cross-sectional shape of the contact surface between the active pattern 102 and the adjacent first isolation structure 103 can be a straight line, an arc shape that is recessed into the active pattern 102, or a protrusion shape that protrudes into the first isolation structure 103.
[0038] The first isolation structure 103 and the second isolation structure 104 are used to define the shape of the active pattern 102.
[0039] Specifically, the vertical distance H1 from the bottom of the first isolation structure 103 to the upper surface of the substrate 101 is greater than the vertical distance H2 from the bottom of the second isolation structure 104 to the upper surface of the substrate 101. That is, the depth H1 of the first isolation structure 103 is greater than the depth H2 of the second isolation structure 104. This allows for greater extension space for components such as word lines at the location of the first isolation structure 103 while ensuring isolation with the semiconductor substrate 101. This further increases the contact area between the word lines and other components at the location of the first isolation structure 103 and the active pattern 102 in the vertical direction, enhancing the contact effect and improving the electrical performance of the device.
[0040] In this embodiment, although the bottom of the second isolation structure 104 and the bottom of the first isolation structure 103 are located at different heights, they can both achieve the insulation effect.
[0041] In addition, the depth H1 of the first isolation structure 103 is greater than the depth H2 of the second isolation structure 104, which increases the support force of the deeper first isolation structure 103 on the lower part of the active pattern 102 around it, while the shallower second isolation structure 104 can still maintain the support force on the upper part of the active pattern 102 around it, which greatly reduces the risk of collapse of the active pattern 102.
[0042] In some cases, the first isolation structure 103 at the position of each row of active patterns 102 is in contact with the adjacent row of active patterns 102. Maximizing the first isolation structure 103 further increases the contact area between the word lines and other components at the position of the first isolation structure 103 and the active patterns 102 in the vertical direction, enhancing the contact effect and further improving the electrical performance of the device.
[0043] The materials of the first isolation structure 103 and the second isolation structure 104 may include different insulating materials, or they may include the same insulating material.
[0044] In some cases, such as Figure 2 and Figure 3 As shown, the bottom of the first isolation structure 103 is a platform shape parallel to the upper surface of the substrate 101, and the bottom of the second isolation structure 104 is a platform shape parallel to the upper surface of the substrate 101.
[0045] In some cases, such as Figure 4a and Figure 5 As shown, the bottom of the first isolation structure 103 is recessed in a direction extending away from the upper surface of the substrate 101, and the bottom of the second isolation structure 104 is protruding in a direction extending close to the upper surface of the substrate 101.
[0046] When the first isolation structure 103 and the second isolation structure 104 are made of the same material, the bottom of the first isolation structure 103 and the second isolation structure 104 exhibit the following shape: Figure 4b As shown, the bottoms of the first isolation structure 103 and the second isolation structure 104 exhibit an undulating shape.
[0047] In some cases, such as Figure 4a and Figure 5 As shown, in a plane perpendicular to the upper surface of the substrate 101, the cross-sectional shape of the bottom of the first isolation structure 103 and the second isolation structure 104 can be arc-shaped.
[0048] In some cases, such as Figure 6a As shown, in a plane perpendicular to the upper surface of the substrate 101, the cross-sectional shape of the bottom of the first isolation structure 103 and the second isolation structure 104 can also be hill-shaped.
[0049] It can also be understood as, for example Figure 1 As shown, the width W1 of the first isolation structure 103 in the second direction (the arrangement direction of the multiple rows of active patterns 102) is greater than the width W2 of the second isolation structure 104 in the second direction (the arrangement direction of the multiple rows of active patterns 102). Therefore, as the lateral distance (distance along the first direction) from the nearest first isolation structure 103 decreases, the area of the active patterns 102 per unit area (the density of the active patterns) gradually decreases, and the depth H2 (the vertical distance from the bottom to the upper surface of the substrate 101) at each position of the second isolation structure 104 gradually increases (in a downward slope); while as the lateral distance (distance along the first direction) from the nearest second isolation structure 104 decreases, the area of the active patterns 102 per unit area (the density of the active patterns) gradually increases, and the depth H1 (the vertical distance from the bottom to the upper surface of the substrate 101) at each position of the first isolation structure 103 gradually decreases (in an upward slope). Therefore, the final result is a hill-like bottom shape with undulating heights in the isolation structure.
[0050] Furthermore, the minimum vertical distance from the bottom of the second isolation structure 104 between any two adjacent first isolation structures 103 to the upper surface of the substrate 101 decreases as the distance between the two adjacent first isolation structures 103 in the first direction (the extension direction of the active pattern 102) increases. For example... Figure 6bAs shown, in the first direction, the distance between the two first isolation structures 103 on both sides of the second isolation structure 1041 is greater than the distance between the two first isolation structures 103 on both sides of the second isolation structure 1042 (i.e., the width of the second isolation structure 1041 is greater than the width of the second isolation structure 1042). Therefore, correspondingly, the minimum vertical distance H21 from the bottom of the second isolation structure 1041 to the upper surface of the substrate 101 is less than the minimum vertical distance H22 from the bottom of the second isolation structure 1042 to the upper surface of the substrate 101 (H21 < H22). However, the minimum vertical distance H21 from the bottom of the second isolation structure 1041 to the upper surface of the substrate 101 and the minimum vertical distance H22 from the bottom of the second isolation structure 1042 to the upper surface of the substrate 101 are both less than the vertical distance H1 from the bottom of the first isolation structure 103 to the upper surface of the substrate 101 (H21 < H22 < H1).
[0051] Furthermore, when the distance between two adjacent first isolation structures 103 in the first direction is greater than a preset threshold, the top of the bottom of the second isolation structure 104 between the two adjacent first isolation structures 103 forms a platform. Figure 6b As shown, the distance between the two first isolation structures 103 on both sides of the second isolation structure 1041 is relatively large (greater than the aforementioned preset threshold), so correspondingly, the top of the bottom of the second isolation structure 1041 forms a platform.
[0052] Correspondingly, when the materials of the first isolation structure 103 and the second isolation structure 104 are the same, the bottoms of the first isolation structure 103 and the second isolation structure 104 exhibit the following shapes: Figure 6c As shown, the bottom of the first isolation structure 103 and the second isolation structure 104 presents a continuous, undulating hill shape.
[0053] The shapes of the bottoms of the first isolation structure 103 and the second isolation structure 104 are specifically determined by the process parameters used to form the isolation trenches. The trench forming parameters can be designed according to requirements to obtain the corresponding bottom shapes.
[0054] In some cases, such as Figure 1As shown, in a plane parallel to the upper surface of the substrate 101, the width W1 of the first isolation structure 103 in the second direction (the arrangement direction of the multiple rows of active patterns 102) is greater than the width W2 of the second isolation structure 104 in the second direction (the arrangement direction of the multiple rows of active patterns 102). During the formation of the isolation trench, the etching window exposed by the mask at the isolation trench position corresponding to the first isolation structure 103 is larger, while the etching window exposed by the mask at the isolation trench position corresponding to the second isolation structure 104 is smaller. This results in different contact areas between the active region at the isolation trench position corresponding to the first isolation structure 103 and the active region at the isolation trench position corresponding to the second isolation structure 104 and the etching solution, leading to different etching rates. The isolation trench corresponding to the first isolation structure 103 has a large window and a high etching rate, while the isolation trench corresponding to the second isolation structure 104 has a small window and a low etching rate. As a result, the depth of the isolation trench corresponding to the second isolation structure 104 is greater than the depth of the isolation trench corresponding to the second isolation structure 104. Ultimately, the vertical distance from the bottom of the first isolation structure 103 to the upper surface of the substrate 101 is greater than the vertical distance from the bottom of the second isolation structure 104 to the upper surface of the substrate 101.
[0055] This can also be understood as follows: as the lateral distance (distance along the first direction) to the nearest first isolation structure 103 decreases, the area of the active pattern 102 per unit area (the density of the active pattern) gradually decreases, and the area of contact between the isolation trench corresponding to the second isolation structure 104 and the etching solution gradually increases, causing the depth H2 (vertical distance from the bottom to the upper surface of the substrate 101) of the isolation trench corresponding to the second isolation structure 104 to gradually increase (in a downward slope); while as the lateral distance (distance along the first direction) to the nearest second isolation structure 104 decreases, the area of the active pattern 102 per unit area (the density of the active pattern) gradually increases, and the area of contact between the isolation trench corresponding to the first isolation structure 103 and the etching solution gradually decreases, causing the depth H1 (vertical distance from the bottom to the upper surface of the substrate 101) of the isolation trench corresponding to the first isolation structure 103 to gradually decrease (in an upward slope). Therefore, the final result is a hill-like bottom shape with undulating heights in the isolation structure.
[0056] Correspondingly, according to the manufacturing process of the first isolation structure 103 and the second isolation structure 104, in some cases, the larger the lateral dimension of the first isolation structure 103 and the second isolation structure 104, the deeper the total longitudinal depth of the first isolation structure 103 and the second isolation structure 104.
[0057] Correspondingly, in some cases, the lateral dimensions of the first isolation structure 103 at the positions of two adjacent rows of active patterns 102 are different, such as... Figure 7As shown, from left to right, the width L11 of the first isolation structure 1031 at the even-numbered row active pattern 102 position in the first direction (the extension direction of the multi-row active pattern 102) is smaller than the width L12 of the first isolation structure 1032 at the odd-numbered row active pattern 102 position in the first direction (the extension direction of the multi-row active pattern 102). Correspondingly, the bottom shapes of the first isolation structure 1031 at the even-numbered row active pattern 102 position and the first isolation structure 1032 at the odd-numbered row active pattern 102 position are as follows: Figure 8a As shown, the vertical distance H12 from the bottom of the first isolation structure 1032 at the position of the active pattern 102 in the odd-numbered rows to the upper surface of the substrate 101 is greater than the vertical distance H11 from the bottom of the first isolation structure 1031 at the position of the active pattern 102 in the even-numbered rows to the upper surface of the substrate 101. That is, the depth H12 of the first isolation structure 1032 at the position of the active pattern 102 in the odd-numbered rows is greater than the depth H11 of the first isolation structure 1031 at the position of the active pattern 102 in the even-numbered rows.
[0058] In this structure, the supporting force of the first isolation structure 103 on the lower part of the active pattern 102 around it can be further increased, and the contact area between the word lines and other components at the position of the first isolation structure 103 and the active pattern 102 in the longitudinal direction can be further increased, thereby strengthening the contact effect and further improving the electrical performance of the device.
[0059] When the first isolation structure 103 and the second isolation structure 104 are made of the same material, the bottom of the first isolation structure 103 and the second isolation structure 104 exhibit the following shape: Figure 8b As shown, the bottoms of the first isolation structure 103 and the second isolation structure 104 exhibit an undulating shape, and the depth of the recess in the first isolation structure 103 varies at different locations.
[0060] This application provides a semiconductor device in which the depth H1 of the first isolation structure 103 is greater than the depth H2 of the second isolation structure 104. This allows for greater extension space for components such as word lines at the location of the first isolation structure 103 while maintaining isolation from the semiconductor substrate 101. This further increases the contact area between the word lines and other components at the location of the first isolation structure 103 and the active pattern 102 in the vertical direction, enhancing the contact effect and improving the electrical performance of the device. Furthermore, the greater depth H1 of the first isolation structure 103 and the greater depth H2 of the second isolation structure 104 increases the support force of the deeper first isolation structure 103 on the lower part of the surrounding active pattern 102, while the shallower second isolation structure 104 still maintains support force on the upper part of the surrounding active pattern 102, significantly reducing the risk of collapse of the active pattern 102.
[0061] Example 2 Based on Example 1, this example provides a method for fabricating a semiconductor device. Figure 9 This is a schematic diagram of a semiconductor device fabrication method according to an embodiment of the present disclosure.
[0062] like Figure 9 As shown, the method for fabricating the semiconductor device in this embodiment includes the following steps: Step S110: Provide a semiconductor substrate 101.
[0063] The semiconductor substrate 101 may include at least one of, for example, a single-crystal silicon substrate 101 and a silicon epitaxial layer.
[0064] Step S120: An active region is formed within the surface of substrate 101.
[0065] The active region is formed by ion implantation to create a doped region (not shown in the figure), and the upper surface of the active region is flush with the upper surface of the substrate 101.
[0066] Step S130: A first shallow isolation trench (not shown in the figure) and a second shallow isolation trench (not shown in the figure) are formed in the upper surface of the substrate 101, penetrating the active region, so as to cut the active region into multiple rows of active patterns 102 extending along a first direction and arranged sequentially along a second direction; wherein, the second direction is different from the first direction, and any two adjacent rows of active patterns 102 are staggered; the first shallow isolation trench is located between any two adjacent active patterns 102 in the same row, and the second shallow isolation trench is located between any two adjacent rows of active patterns 102; the vertical distance H1 from the bottom of the first shallow isolation trench to the upper surface of the substrate 101 is greater than the vertical distance H2 from the bottom of the second shallow isolation trench to the upper surface of the substrate 101.
[0067] The first and second shallow isolation trenches can be formed using a wet etching process. By adjusting the parameters of the wet etching process, the first and second shallow isolation trenches can be formed simultaneously in a single etching step. For example, because the etch window exposed by the mask is larger at the location of the first shallow isolation trench and smaller at the location of the second shallow isolation trench, the contact area between the active region at the first and second shallow isolation trench locations and the etching solution is different, resulting in different etching rates. The larger window at the first shallow isolation trench location leads to a higher etching rate, while the smaller window at the second shallow isolation trench location leads to a lower etching rate. Consequently, the depth H1 of the first isolation trench is greater than the depth H2 of the second isolation trench; that is, the vertical distance H1 from the bottom of the first shallow isolation trench to the upper surface of the substrate 101 is greater than the vertical distance H2 from the bottom of the second shallow isolation trench to the upper surface of the substrate 101.
[0068] Step S140: As Figures 1 to 3 As shown, a first isolation structure 103 and a second isolation structure 104 are formed in the first shallow isolation trench and the second shallow isolation trench, respectively.
[0069] Insulating material may be filled into the first shallow isolation trench and the second shallow isolation trench to form the first isolation structure 103 and the second isolation structure 104, respectively.
[0070] The first isolation structure 103 is disposed within the upper surface of the substrate 101 and between any two adjacent active patterns 102 in the same row, that is, any two adjacent active patterns 102 in the same row are isolated by the first isolation structure 103.
[0071] The second isolation structure 104 is disposed within the upper surface of the substrate 101 and located between any two adjacent rows of active patterns 102, that is, any two adjacent rows of active patterns 102 are isolated from each other by the second isolation structure 104.
[0072] In this embodiment, the shape of the contact surface between the first isolation structure 103 and the active pattern 102 in the same row is not limited. In a plane parallel to the upper surface of the substrate 101, the contact portion between the active pattern 102 and the adjacent first isolation structure 103 can be straight, concave into the active pattern 102, or protruding into the first isolation structure 103.
[0073] The first isolation structure 103 and the second isolation structure 104 are used to define the shape of the active pattern 102.
[0074] Specifically, the vertical distance H1 from the bottom of the first isolation structure 103 to the upper surface of the substrate 101 is greater than the vertical distance H2 from the bottom of the second isolation structure 104 to the upper surface of the substrate 101. That is, the depth H1 of the first isolation structure 103 is greater than the depth H2 of the second isolation structure 104. This allows for greater extension space for components such as word lines at the location of the first isolation structure 103 while ensuring isolation with the semiconductor substrate 101. This further increases the contact area between the word lines and other components at the location of the first isolation structure 103 and the active pattern 102 in the vertical direction, enhancing the contact effect and improving the electrical performance of the device.
[0075] In this embodiment, although the bottom of the second isolation structure 104 and the bottom of the first isolation structure 103 are located at different heights, they can both achieve the insulation effect.
[0076] In addition, the depth H1 of the first isolation structure 103 is greater than the depth H2 of the second isolation structure 104, which increases the support force of the deeper first isolation structure 103 on the lower part of the active pattern 102 around it, while the shallower second isolation structure 104 can still maintain the support force on the upper part of the active pattern 102 around it, which greatly reduces the risk of collapse of the active pattern 102.
[0077] In some cases, the first isolation structure 103 at the location of each row of active patterns 102 contacts the adjacent row of active patterns 102. Maximizing the first isolation structure 103 further increases the contact area between components such as word lines at the location of the first isolation structure 103 and the active patterns 102 in the vertical direction, strengthening the contact effect and further improving the electrical performance of the device. Additionally, it further increases the support force of the first isolation structure 103 on the surrounding active patterns 102, further reducing the risk of the active patterns 102 collapsing.
[0078] The materials of the first isolation structure 103 and the second isolation structure 104 may include different insulating materials, or they may include the same insulating material.
[0079] In some cases, the bottom of the first isolation structure 103 is a platform parallel to the upper surface of the substrate 101, and the bottom of the second isolation structure 104 is a platform parallel to the upper surface of the substrate 101.
[0080] In some cases, the bottom of the first isolation structure 103 is recessed in a direction extending away from the upper surface of the substrate 101, and the bottom of the second isolation structure 104 is convex in a direction extending close to the upper surface of the substrate 101.
[0081] The shapes of the bottoms of the first isolation structure 103 and the second isolation structure 104 are specifically determined by the process parameters used to form the isolation trenches. The trench forming parameters can be designed according to requirements to obtain the corresponding bottom shapes.
[0082] This application provides a method for fabricating a semiconductor device, including forming a first shallow isolation trench (not shown in the figure) and a second shallow isolation trench (not shown in the figure) penetrating an active region within the upper surface of a substrate 101, thereby truncating the active region into multiple rows of active patterns 102 extending along a first direction and arranged sequentially along a second direction; and forming a first isolation structure 103 and a second isolation structure 104 within the first shallow isolation trench and the second shallow isolation trench, respectively. Specifically, the depth H1 of the first isolation structure 103 is greater than the depth H2 of the second isolation structure 104, thereby ensuring isolation from the semiconductor substrate 101 while allowing for greater extension space for components such as word lines at the location of the first isolation structure 103. This further increases the contact area between the word lines and other components at the location of the first isolation structure 103 and the active patterns 102 in the longitudinal direction, enhancing the contact effect and improving the electrical performance of the device. In addition, the depth H1 of the first isolation structure 103 is greater than the depth H2 of the second isolation structure 104, which increases the support force of the deeper first isolation structure 103 on the lower part of the active pattern 102 around it, while the shallower second isolation structure 104 can still maintain the support force on the upper part of the active pattern 102 around it, which greatly reduces the risk of collapse of the active pattern 102.
[0083] Although the embodiments disclosed in this application are as described above, the content described is merely for the purpose of facilitating understanding of this application and is not intended to limit this application. Any person skilled in the art to which this application pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in this application, but the scope of protection of this application shall still be determined by the scope defined in the appended claims.
Claims
1. A semiconductor device, characterized in that, include: Semiconductor substrate; Multiple rows of active patterns are disposed on the upper surface of the substrate; wherein, the multiple rows of active patterns extend along a first direction and are arranged sequentially along a second direction, the second direction being different from the first direction; any two adjacent rows of active patterns are staggered. The second isolation structure is disposed within the upper surface of the substrate and located between the two adjacent active patterns along the second direction; A first isolation structure, disposed within the upper surface of the substrate, includes: The first part is located between the two adjacent second isolation structures along the first direction; The second part is located between the two most adjacent active patterns along the first direction; Wherein, the vertical distance from the bottom of the first part to the upper surface of the substrate is greater than the vertical distance from the bottom of the second isolation structure to the upper surface of the substrate.
2. The semiconductor device according to claim 1, characterized in that, The bottom of the first isolation structure is recessed in a direction extending away from the upper surface of the substrate.
3. The semiconductor device according to claim 1, characterized in that, The bottom of the second isolation structure is a convex shape extending in a direction close to the upper surface of the substrate.
4. The semiconductor device according to claim 3, characterized in that, The minimum vertical distance from the bottom of the second isolation structure to the upper surface of the substrate between any two adjacent first isolation structures decreases as the distance between the two adjacent first isolation structures in the first direction increases.
5. The semiconductor device according to claim 1, characterized in that, The first isolation structure and the second isolation structure are made of different insulating materials.
6. The semiconductor device according to claim 1, characterized in that, In a plane parallel to the upper surface of the substrate, the width of the first isolation structure in the second direction is greater than the width of the second isolation structure in the second direction.
7. A semiconductor device, characterized in that, include: Semiconductor substrate; Multiple rows of active patterns are disposed on the upper surface of the substrate; wherein the active patterns include a major axis and a minor axis; Any two adjacent active patterns are isolated from each other and staggered. The first isolation structure is located between the short axes of the two most adjacent active patterns in the same row; The second isolation structure is located between the major axes of the two most adjacent active patterns in the two rows; Wherein, the first isolation structure has a maximum vertical distance in a direction perpendicular to the substrate, the second isolation structure has a maximum vertical distance in a direction perpendicular to the substrate, and the maximum vertical distance of the first isolation structure is greater than the maximum vertical distance of the second isolation structure.
8. The semiconductor device according to claim 7, characterized in that, The bottom of the first isolation structure is recessed in a direction extending away from the upper surface of the substrate.
9. The semiconductor device according to claim 7, characterized in that, The bottom of the second isolation structure is a convex shape extending in a direction close to the upper surface of the substrate.
10. The semiconductor device according to claim 9, characterized in that, The minimum vertical distance from the bottom of the second isolation structure to the upper surface of the substrate between any two adjacent first isolation structures decreases as the distance between the two adjacent first isolation structures in the first direction increases.
11. The semiconductor device according to claim 7, characterized in that, In a plane parallel to the upper surface of the substrate, the width of the first isolation structure in the second direction is greater than the width of the second isolation structure in the second direction.
12. A semiconductor device, characterized in that, include: Semiconductor substrate; Multiple rows of active patterns are disposed on the upper surface of the substrate; wherein, the multiple rows of active patterns extend along a first direction and are arranged sequentially along a second direction, the second direction being different from the first direction; any two adjacent rows of active patterns are staggered. The second isolation structure is located between the two most adjacent active patterns along the second direction; The first isolation structure includes: The first part is located between the two adjacent second isolation structures along the first direction; The second part is located between the two most adjacent active patterns along the first direction; Wherein, the first part has a maximum vertical distance in a direction perpendicular to the substrate, the second isolation structure has a maximum vertical distance in a direction perpendicular to the substrate, and the maximum vertical distance of the first part is greater than the maximum vertical distance of the second isolation structure.
13. A semiconductor device, characterized in that, include: Semiconductor substrate; Multiple rows of active patterns are disposed on the upper surface of the substrate; wherein, the multiple rows of active patterns extend along a first direction and are arranged sequentially along a second direction, the second direction being different from the first direction; any two adjacent rows of active patterns are staggered. A first isolation structure is disposed within the upper surface of the substrate and located between any two adjacent active patterns in the same row; The second isolation structure is disposed within the upper surface of the substrate and located between any two adjacent rows of the active patterns; Wherein, the vertical distance from the bottom of the first isolation structure to the upper surface of the substrate is greater than the vertical distance from the bottom of the second isolation structure to the upper surface of the substrate.