A method for manufacturing a three-dimensional dynamic random access memory and a three-dimensional dynamic random access memory
By using two dielectric materials alternately to form dielectric layer groups in 3D DRAM fabrication and employing wet etching technology to construct dual-gate transistor structures, the problems of complexity and high cost in existing 3D DRAM fabrication processes are solved, achieving efficient mass production and compatibility.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- INST OF MICROELECTRONICS CHINESE ACAD OF SCI LTD
- Filing Date
- 2026-04-09
- Publication Date
- 2026-07-14
AI Technical Summary
Existing 3D DRAM manufacturing processes are complex and costly, making mass production difficult on existing manufacturing platforms and resulting in poor compatibility.
Two dielectric materials are used alternately to form dielectric layers. The fabrication process is simplified by wet etching to form spaced trenches and vias, thus constructing a dual-gate transistor structure. Three-dimensional stacking is achieved using conventional processes.
The fabrication process of three-dimensional dynamic random access memory has been simplified, the fabrication difficulty has been reduced, the fabrication efficiency has been improved, compatibility with existing manufacturing platforms has been achieved, and mass production has been supported.
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Figure CN122395941A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor device technology, and in particular to a method for fabricating a three-dimensional dynamic random access memory and the three-dimensional dynamic random access memory itself. Background Technology
[0002] DRAM (Dynamic Random-Access Memory) is a crucial component of semiconductor memory devices, widely used in various electronic devices. With the rapid development of information technology, the demand for DRAM storage density is constantly increasing, and the traditional planar DRAM structure is facing increasingly severe challenges in miniaturization. To improve the integration density of DRAM, a high-density integrated 3D DRAM (Three-Dimensional Dynamic Random-Access Memory) architecture can be achieved by stacking multiple memory cell layers vertically using three-dimensional stacking technology.
[0003] However, the existing 3D DRAM manufacturing process usually requires the introduction of a relatively complex process flow, resulting in numerous process steps, long production cycles, and high manufacturing costs. Moreover, these processes often require specialized equipment or special process conditions, leading to poor compatibility between 3D DRAM manufacturing and the large-scale, highly integrated, and mature manufacturing platforms currently configured by manufacturers. This makes it difficult to directly utilize existing production lines for mass production, further resulting in high difficulty, complex manufacturing processes, and low manufacturing efficiency in 3D DRAM manufacturing. Summary of the Invention
[0004] This application provides a method for fabricating a three-dimensional dynamic random access memory (DRAM) and a DRAM itself. This method can improve the compatibility of the fabrication of the DRAM with existing manufacturing platforms, thereby facilitating the mass production of the DRAM. It can also reduce the fabrication difficulty of the DRAM, simplify the fabrication process, and improve the fabrication efficiency.
[0005] A first aspect of this application provides a method for fabricating a three-dimensional dynamic random access memory, comprising: A substrate and at least two groups of dielectric layers stacked along a first direction are provided, wherein each group of dielectric layers includes a first dielectric layer, a second dielectric layer, a third dielectric layer and a fourth dielectric layer stacked sequentially along the first direction, the fourth dielectric layer being located between the first dielectric layer and the substrate within the corresponding group of dielectric layers, the first direction being perpendicular to the substrate; The dielectric layer group is etched to form a spaced first trench and a second trench, the first trench and the second trench extending into the substrate, adjacent first trenches and second trenches are alternately arranged along a second direction, adjacent first trenches are arranged along a third direction, adjacent second trenches are arranged along the third direction, the second direction and the third direction are both parallel to the substrate, and the second direction and the third direction intersect. Along the circumference of the first trench and the second trench, a portion of the second dielectric layer and a portion of the fourth dielectric layer are removed by a wet etching process to form a first filling space, wherein the second dielectric layer and the fourth dielectric layer located between the first trench and the second trench are completely removed; A gate layer is formed within the first filling space; A fifth dielectric layer is formed in the first trench and the second trench. The fifth dielectric layer includes a first through-hole and a second through-hole that penetrate the substrate. The first through-hole is located in the first trench, and the second through-hole is located in the second trench. Along the circumference of the first through hole and the second through hole, a portion of the first dielectric layer and a portion of the third dielectric layer are removed by a wet etching process to form a second filling space and a third filling space. The first dielectric layer and the third dielectric layer located between the first through hole and the second through hole are completely removed. The second filling space is located in the same layer as the first dielectric layer, and the third filling space is located in the same layer as the third dielectric layer. An interlayer dielectric layer is formed within the second filling space; An active layer is formed within the third filling space; A dual-gate transistor is formed between adjacent first and second vias, a bit line is formed on the side of the dual-gate transistor near the first via, and a capacitor is formed on the side of the dual-gate transistor near the second via. The first dielectric layer and the third dielectric layer each include a first dielectric material, the second dielectric layer and the fourth dielectric layer each include a second dielectric material, the first dielectric layer and the fifth dielectric layer include different dielectric materials, and the second dielectric layer and the fourth dielectric layer have different thicknesses.
[0006] In some embodiments, forming a gate layer within the first filling space includes: An initial gate layer is formed through the first trench and the second trench using an atomic layer deposition process, wherein a portion of the initial gate layer fills the first filling space and a portion of the initial gate layer covers the sidewalls of the first dielectric layer and the third dielectric layer; The initial gate layer is obtained by removing the portion of the initial gate layer covered by the sidewalls of the first dielectric layer and the third dielectric layer using a wet etching process.
[0007] In some embodiments, forming a fifth dielectric layer within the first trench and the second trench includes: A first initial dielectric layer is formed in the first trench and the second trench using an atomic layer deposition process, wherein the first initial dielectric layer fills the interior of the first trench and the second trench; The first initial dielectric layer is etched using a dry etching process to form the first via and the second via within the first initial dielectric layer, thereby obtaining the fifth dielectric layer.
[0008] In some embodiments, forming an interlayer dielectric layer within the second filling space includes: A second initial dielectric layer is formed through the first via and the second via using an atomic layer deposition process. The second initial dielectric layer includes a first dielectric material. A portion of the second initial dielectric layer fills the third filling space, a portion of the second initial dielectric layer covers the sidewall of the gate layer, and a portion of the second initial dielectric layer covers the surface of the gate layer in the first direction. By using a wet etching process, a portion of the second initial dielectric layer is removed through the first and second vias to obtain a sixth dielectric layer, which is located within the second filling space. An interlayer dielectric layer is formed in the second filled space through the first and second vias using an atomic layer deposition process, wherein the interlayer dielectric layer and the second initial dielectric layer comprise different dielectric materials.
[0009] In some embodiments, forming an active layer within the third filling space includes: Along the circumferential direction of the first and second vias, a portion of the gate layer and the sixth dielectric layer are sequentially removed by a wet etching process; A gate insulating layer is formed between the first via and the second via using an atomic layer deposition process, with a portion of the gate insulating layer covering the surface of the gate layer. An initial active layer is formed between the first via and the second via using an atomic layer deposition process, and the initial active layer covers the surface of the gate insulating layer. The initial active layer located on the sidewall of the interlayer dielectric layer is removed by a wet etching process through the first and second vias to obtain the active layer.
[0010] In some embodiments, forming a dual-gate transistor between adjacent first and second vias, forming a bit line on the side of the dual-gate transistor near the first via, and forming a capacitor on the side of the dual-gate transistor near the second via, includes: The gate layer between adjacent interlayer dielectric layers includes a first gate layer and a second gate layer. The first gate layer is located between the second gate layer and the substrate. The active layer is located between the first gate layer and the second gate layer. The first gate layer, the second gate layer and the active layer between adjacent interlayer dielectric layers together form the dual-gate transistor. A first initial conductive layer and a second initial conductive layer are formed through the first via and the second via, respectively, by an atomic layer deposition process. The first initial conductive layer is used to form the bit line. Part of the bit line is located on the side of the interlayer dielectric layer near the first via, and part of the bit line covers the surface of the active layer on the side near the first via. By using a wet etching process, the second initial conductive layer located on the surface of the interlayer dielectric layer near the second via is removed through the second via, thereby obtaining a capacitor plate, which covers the surface of the active layer near the second via. An interplate dielectric layer is formed through the second via using an atomic layer deposition process. Part of the interplate dielectric layer covers the surface of the interplate dielectric layer near the second via, and part of the interplate dielectric layer covers the surface of the capacitor plate. A third initial conductive layer is formed on the side of the inter-plate dielectric layer near the second via through the second via using an atomic layer deposition process. The third initial conductive layer is used to form a common electrode. The capacitor electrode, the inter-plate dielectric layer, and the common electrode together form the capacitor.
[0011] A second aspect of this application provides a three-dimensional dynamic random access memory (DRAM), prepared by any of the three-dimensional DRAM methods described in the first aspect above, wherein the three-dimensional DRAM comprises: Substrate; Multiple memory cell layers and multiple interlayer dielectric layers are stacked alternately along a first direction. Each memory cell layer includes multiple memory cells arranged in an array. Each memory cell includes a dual-gate transistor and a capacitor. Within the memory cell, the capacitor is located on one side of the dual-gate transistor in a second direction. The first direction is perpendicular to the substrate, and the second direction is parallel to the substrate. The dual-gate transistor includes a first gate layer, an active layer, and a second gate layer. The active layer is located between the first gate layer and the second gate layer, and the first gate layer is located between the active layer and the substrate. The capacitor includes a capacitor plate, a common plate, and an inter-plate dielectric layer. The common plate is disposed on the side of the capacitor plate away from the dual-gate transistor, and the inter-plate dielectric layer is located between the common plate and the capacitor plate.
[0012] In some embodiments, the thickness of the first gate layer and the thickness of the second gate layer are equal; The thickness of the interlayer dielectric layer is greater than the thickness of the active layer between the first gate layer and the second gate layer.
[0013] In some embodiments, the three-dimensional dynamic random access memory further includes: Bit lines are disposed on the side of the dual-gate transistor away from the capacitor, and the bit lines cover the surface of the active layer away from the capacitor.
[0014] In some implementations, in the third direction, the bit line corresponds one-to-one with the adjacent capacitor, the third direction is parallel to the substrate, and the second direction intersects the third direction.
[0015] This application provides a method for fabricating a three-dimensional dynamic random access memory (DRAM) and the DRAM itself. By alternating between two dielectric materials to form a dielectric layer group, the fabrication process of the dielectric layer group can be simplified. By setting the thicknesses of the second and fourth dielectric layers within the dielectric layer group to be unequal, the second and fourth dielectric layers can be used as active layers and interlayer dielectric layers, respectively, thereby ensuring the channel quality of the dual-gate transistor and the electrical isolation effect between the three-dimensionally stacked DRAMs. Etching the dielectric layer group to form spaced first and second trenches allows the etching liquid used in subsequent wet etching processes to enter the dielectric layer group, while also enabling isotropic etching along the circumference of the trenches. Since the second and fourth dielectric layers are formed using the same dielectric material, they can be simultaneously etched in a single wet etching process, saving process steps. This also creates two corresponding first filling spaces, facilitating the filling of conductive material within these spaces to form a dual-gate transistor structure with two gates. By forming a fifth dielectric layer within the first and second trenches, the first and second vias can be used as connecting holes for the source and drain electrodes of the dual-gate transistor, facilitating the entry of etching liquid into the dielectric layer group during subsequent wet etching processes. Since the first and third dielectric layers are formed using the same dielectric material, and the fifth dielectric layer is formed using a different dielectric material, the first and third dielectric layers can be simultaneously etched in a single wet etching process while maintaining the integrity of the first and second vias, forming second and third filling spaces of different thicknesses. Furthermore, by forming an interlayer dielectric layer within the second filling space and an active layer within the third filling space, the active layer can be positioned between the two gate layers. This allows the two gate layers and one active layer within a dielectric layer group to collectively constitute a dual-gate transistor structure. Simultaneously, an interlayer dielectric layer of a certain thickness can be formed between adjacent dual-gate transistor structures in the first direction, achieving electrical isolation between different layers of dual-gate transistors and providing support for the entire three-dimensional dynamic random access memory. By forming a bit line on the side of the dual-gate transistor near the first via, the bit line can be electrically connected to the drain of the dual-gate transistor. By controlling the word line connected to the gate of the dual-gate transistor, the transistor can be turned on or off. When the transistor is turned on, data on the bit line can be written to the capacitor, or data stored in the capacitor can be read from the bit line, thus obtaining a 1T1C dynamic random access memory architecture.Therefore, the fabrication process involved in the fabrication method of the three-dimensional dynamic random access memory provided in this application embodiment can be realized by conventional wet etching process, etching process and film growth process, without involving complex film deposition control and film patterning, so it can be compatible with existing three-dimensional stacked structure production lines, and further realize the mass production of three-dimensional dynamic random access memory, thereby reducing the fabrication difficulty of three-dimensional dynamic random access memory, simplifying the fabrication process and improving the fabrication efficiency. Attached Figure Description
[0016] To more clearly illustrate the technical solution of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0017] Figure 1 A schematic flowchart illustrating a method for fabricating a three-dimensional dynamic random access memory provided in this application embodiment; Figure 2 A schematic cross-sectional view of the substrate and dielectric layer group provided for a method of fabricating a three-dimensional dynamic random access memory according to an embodiment of this application; Figure 3 A schematic top view of the substrate and dielectric layer group provided for a method of fabricating a three-dimensional dynamic random access memory according to an embodiment of this application; Figure 4 A schematic cross-sectional view of the first trench and the second trench provided for a method of fabricating a three-dimensional dynamic random access memory according to an embodiment of this application; Figure 5 A schematic cross-sectional view of the first filling space provided in a method for fabricating a three-dimensional dynamic random access memory according to an embodiment of this application; Figure 6 A schematic cross-sectional view of the initial gate layer provided for a method of fabricating a three-dimensional dynamic random access memory according to an embodiment of this application; Figure 7 A schematic cross-sectional view of the gate layer provided in a method for fabricating a three-dimensional dynamic random access memory according to an embodiment of this application; Figure 8 A schematic cross-sectional view of the first initial dielectric layer provided for a method of fabricating a three-dimensional dynamic random access memory according to an embodiment of this application; Figure 9 A schematic top view of the fifth dielectric layer provided in a method for fabricating a three-dimensional dynamic random access memory according to an embodiment of this application; Figure 10A schematic cross-sectional view of the fifth dielectric layer at the B-B1 position provided in the fabrication method of a three-dimensional dynamic random access memory according to an embodiment of this application; Figure 11 A schematic cross-sectional view of the second and third filling spaces provided in the fabrication method of a three-dimensional dynamic random access memory according to an embodiment of this application; Figure 12 A schematic cross-sectional view of the second initial dielectric layer provided in a method for fabricating a three-dimensional dynamic random access memory according to an embodiment of this application; Figure 13 A schematic cross-sectional view of the sixth dielectric layer provided in a method for fabricating a three-dimensional dynamic random access memory according to an embodiment of this application; Figure 14 A schematic cross-sectional view of the interlayer dielectric layer provided for a method of fabricating a three-dimensional dynamic random access memory according to an embodiment of this application; Figure 15 A schematic cross-sectional view of the structure after removing part of the gate layer and the sixth dielectric layer, provided for a method of fabricating a three-dimensional dynamic random access memory according to an embodiment of this application; Figure 16 A schematic cross-sectional view of the gate insulating layer provided in a method for fabricating a three-dimensional dynamic random access memory according to an embodiment of this application; Figure 17 A schematic cross-sectional view of the active layer provided in a method for fabricating a three-dimensional dynamic random access memory according to an embodiment of this application; Figure 18 A schematic cross-sectional view of a three-dimensional dynamic random access memory provided for a method of fabricating a three-dimensional dynamic random access memory according to an embodiment of this application; Figure 19 This is a schematic structural diagram of a three-dimensional dynamic random access memory provided in an embodiment of this application. Detailed Implementation
[0018] To better understand the technical solutions provided in the embodiments of this specification, the technical solutions of the embodiments of this specification will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the embodiments of this specification and the specific features in the embodiments are detailed descriptions of the technical solutions of the embodiments of this specification, rather than limitations on the technical solutions of this specification. In the absence of conflict, the embodiments of this specification and the technical features in the embodiments can be combined with each other.
[0019] In this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, without necessarily requiring or implying any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. The term "two or more" includes two or more cases.
[0020] Figure 1 This is a schematic flowchart illustrating a method for fabricating a three-dimensional dynamic random access memory (DRAM) according to an embodiment of this application. Figure 2 A schematic cross-sectional view of the substrate and dielectric layer group provided for a method of fabricating a three-dimensional dynamic random access memory according to an embodiment of this application. Figure 3 This is a schematic top view of the substrate and dielectric layer assembly provided for a method of fabricating a three-dimensional dynamic random access memory (DRAM) according to an embodiment of this application. Figures 1 to 3 As shown, a first aspect of this application provides a method for fabricating a three-dimensional dynamic random access memory, comprising: Step S1: Provide a substrate P and at least two dielectric layer groups N stacked along a first direction F1, wherein each dielectric layer group N includes a first dielectric layer L1, a second dielectric layer L2, a third dielectric layer L3 and a fourth dielectric layer L4 stacked sequentially along the first direction F1, the fourth dielectric layer L4 being located between the first dielectric layer L1 and the substrate P within the corresponding dielectric layer group N, and the first direction F1 being perpendicular to the substrate P; wherein the first dielectric layer L1 and the third dielectric layer L3 both include a first dielectric material, the second dielectric layer L2 and the fourth dielectric layer L4 both include a second dielectric material, the first dielectric layer L1 and the fifth dielectric layer L5 include different dielectric materials, and the second dielectric layer L2 and the fourth dielectric layer L4 have different thicknesses.
[0021] For example, the first dielectric material and the second dielectric material may include nitrides and oxides, such as silicon nitride, silicon oxide, etc.
[0022] For example, the thickness of the first dielectric layer and the third dielectric layer can be equal, for example, 40 nm, the thickness of the second dielectric layer is about 30 nm to 40 nm, and the thickness of the fourth dielectric layer can be 50 nm.
[0023] Figure 4This is a schematic cross-sectional view of the first and second trenches provided for a method of fabricating a three-dimensional dynamic random access memory according to an embodiment of this application. Figure 4 As shown, the fabrication method of the three-dimensional dynamic random access memory provided in this application embodiment further includes, after step S1: step S2, etching the dielectric layer group N to form a first trench T1 and a second trench T2 spaced apart. The first trench T1 and the second trench T2 penetrate to the substrate P. Adjacent first trenches T1 and second trenches T2 are alternately arranged along the second direction F2. Adjacent first trenches T1 are arranged along the third direction F3. Adjacent second trenches T2 are arranged along the third direction F3. The second direction F2 and the third direction F3 are both parallel to the substrate P, and the second direction F2 and the third direction F3 intersect.
[0024] For example, the first trench and the second trench can be obtained by etching the dielectric layer group using a dry etching process.
[0025] For example, in the second direction, the dimensions of the first trench and the second trench can be different. The dimension of the first trench in the second direction can be 120 nm, the dimension of the second trench in the second direction can be 300 nm, and the dimension of the dielectric layer group between the first trench and the second trench in the second direction can be 500 nm.
[0026] Figure 5 This is a schematic cross-sectional view of the first filling space provided in a method for fabricating a three-dimensional dynamic random access memory according to an embodiment of this application. Figure 5 As shown, the fabrication method of the three-dimensional dynamic random access memory provided in this application embodiment further includes, after step S2: step S3, removing a portion of the second dielectric layer L2 and a portion of the fourth dielectric layer L4 along the circumferential direction of the first trench T1 and the second trench T2 using a wet etching process to form a first filling space Z1, wherein the second dielectric layer L2 and the fourth dielectric layer L4 located between the first trench T1 and the second trench T2 are completely removed. Figure 5 As shown, the area outlined by the dashed line is the first filling space Z1 obtained after completing step S3.
[0027] It should be noted that, because wet etching is isotropic, when Figure 4 When the device structure shown is immersed in the etching solution, the etching solution will etch along the circumferential direction of the first trench and the second trench. Therefore, the second dielectric layer and the fourth dielectric layer located between the first trench and the second trench will be etched from both sides at the same time until they are completely etched to form the gate region.
[0028] The method for fabricating a three-dimensional dynamic random access memory provided in this application embodiment further includes, after step S3: step S4, forming a gate layer in the first filling space.
[0029] Figure 6 This is a schematic cross-sectional view of the initial gate layer provided for a method of fabricating a three-dimensional dynamic random access memory according to an embodiment of this application. Figure 7 This is a schematic cross-sectional view of the gate layer provided in a method for fabricating a three-dimensional dynamic random access memory (DRAM) according to an embodiment of this application. Figure 6 and Figure 7 As shown, in some feasible embodiments, step S4: forming a gate layer within the first filling space includes: Step S41: An initial gate layer G0 is formed by an atomic layer deposition process through a first trench T1 and a second trench T2, wherein a portion of the initial gate layer G0 fills the first filling space Z1 and a portion of the initial gate layer G0 covers the sidewalls of the first dielectric layer L1 and the third dielectric layer L3.
[0030] For example, the material of the initial gate layer may include conductive materials such as tungsten and titanium nitride.
[0031] Step S42: Remove the portion of the initial gate layer G0 covered by the sidewalls of the first dielectric layer L1 and the third dielectric layer L3 by wet etching process to obtain the gate layer G.
[0032] It should be noted that since the initial gate layer is prepared by atomic layer deposition, spaces are naturally formed in the first and second trenches during the preparation process. Therefore, the excess initial gate layer can be removed by wet etching process using an etching solution, avoiding electrical connections between the gate layers. This can improve the control capability of the gate in the dual-gate transistor and further improve the electrical isolation effect between the dual-gate transistors.
[0033] The method for fabricating a three-dimensional dynamic random access memory provided in this application embodiment further includes, after step S4: step S5, forming a fifth dielectric layer in the first trench and the second trench. The fifth dielectric layer includes a first through-hole and a second through-hole that penetrate to the substrate. The first through-hole is located in the first trench, and the second through-hole is located in the second trench.
[0034] Figure 8 This is a schematic cross-sectional view of the first initial dielectric layer provided for a method of fabricating a three-dimensional dynamic random access memory according to an embodiment of this application. Figure 9 This is a schematic top view of the fifth dielectric layer provided in a method for fabricating a three-dimensional dynamic random access memory according to an embodiment of this application. Figure 10 This is a schematic cross-sectional view of the fifth dielectric layer at the B-B1 position, provided for a method of fabricating a three-dimensional dynamic random access memory according to an embodiment of this application. Figures 8 to 10 As shown, in some feasible embodiments, step S5: forming a fifth dielectric layer in the first trench and the second trench includes: Step S51: A first initial dielectric layer L50 is formed in the first trench T1 and the second trench T2 by atomic layer deposition process, wherein the first initial dielectric layer L50 fills the interior of the first trench T1 and the second trench T2.
[0035] Step S52: The first initial dielectric layer L50 is etched by a dry etching process to form a first through hole H1 and a second through hole H2 in the first initial dielectric layer L50, thereby obtaining the fifth dielectric layer L5.
[0036] It should be noted that, Figure 8 It can also be used to express about Figure 9 A schematic cross-sectional view of the A-A1 position. Figure 10 A white space exists around the fifth dielectric layer L5 within the first trench T1 and the second trench T2, indicating that the first trench T1 and the second trench T2 at location B-B1 are hollow structures, i.e., the cross-sections of the first through hole H1 and the second through hole H2. Figure 10 The fifth dielectric layer L5 in the first trench T1 and the second trench T2 is the fifth dielectric layer L5 on the third direction F3 that can be observed through the first through hole H1 and the second through hole H2.
[0037] Figure 11 This is a schematic cross-sectional view of the second and third filling spaces provided in a method for fabricating a three-dimensional dynamic random access memory according to an embodiment of this application. Figure 11 As shown, the fabrication method of the three-dimensional dynamic random access memory provided in this application embodiment further includes, after step S5: step S6, removing part of the first dielectric layer L1 and part of the third dielectric layer L3 along the circumferential direction of the first through hole H1 and the second through hole H2 by a wet etching process to form a second filling space Z2 and a third filling space Z3, wherein the first dielectric layer L1 and the third dielectric layer L3 located between the first through hole H1 and the second through hole H2 are completely removed, the second filling space Z2 is located in the same layer as the first dielectric layer L1, and the third filling space Z3 is located in the same layer as the third dielectric layer L3.
[0038] The method for fabricating a three-dimensional dynamic random access memory provided in this application embodiment further includes, after step S6: step S7, forming an interlayer dielectric layer in the second filling space.
[0039] Figure 12 This is a schematic cross-sectional view of the second initial dielectric layer provided in a method for fabricating a three-dimensional dynamic random access memory according to an embodiment of this application. Figure 13 This is a schematic cross-sectional view of the sixth dielectric layer provided in a method for fabricating a three-dimensional dynamic random access memory according to an embodiment of this application. Figure 14This is a schematic cross-sectional view of the interlayer dielectric layer provided in a method for fabricating a three-dimensional dynamic random access memory (DRAM) according to an embodiment of this application. Figures 12 to 14 As shown, in some feasible embodiments, step S7: forming an interlayer dielectric layer within the second filling space includes: Step S71: A second initial dielectric layer L60 is formed through a first via H1 and a second via H2 by an atomic layer deposition process. The second initial dielectric layer L60 includes a first dielectric material. A portion of the second initial dielectric layer L60 fills the third filling space Z3. A portion of the second initial dielectric layer L60 covers the sidewall of the gate layer G. A portion of the second initial dielectric layer L60 covers the surface of the gate layer G in the first direction F1.
[0040] Step S72: Using a wet etching process, a portion of the second initial dielectric layer L60 is removed through the first via H1 and the second via H2 to obtain the sixth dielectric layer L6, which is located within the second filling space Z2.
[0041] It should be noted that by using a sixth dielectric layer to occupies the active layer, the interlayer dielectric layer can be prevented from growing within the active region during the formation of the interlayer dielectric layer using atomic layer deposition. This eliminates the need for cleaning the active region before subsequent active layer fabrication, simplifying the fabrication process, reducing its difficulty, and improving its efficiency. It also ensures the quality of the subsequent active layer fabrication, further enhancing the reliability of the three-dimensional dynamic random access memory.
[0042] Step S73: Using atomic layer deposition, an interlayer dielectric layer I is formed in the second filling space Z2 through the first through-hole H1 and the second through-hole H2, wherein the interlayer dielectric layer I and the second initial dielectric layer L60 comprise different dielectric materials.
[0043] It should be noted that since the sixth dielectric layer is only used to occupy the active region, it needs to be removed in subsequent processes. Therefore, using different dielectric materials to form the sixth dielectric layer and the interlayer dielectric layer can ensure the integrity of the interlayer dielectric layer during the removal of the sixth dielectric layer, thereby ensuring the support and electrical isolation effects of the interlayer dielectric layer and further improving the reliability of the three-dimensional dynamic random access memory.
[0044] The method for fabricating a three-dimensional dynamic random access memory provided in this application embodiment further includes, after step S7: step S8, forming an active layer in the third filling space.
[0045] Figure 15 This is a schematic cross-sectional view of the structure after removing part of the gate layer and the sixth dielectric layer, provided for a method of fabricating a three-dimensional dynamic random access memory according to an embodiment of this application. Figure 16This is a schematic cross-sectional view of the gate insulating layer provided in the fabrication method of a three-dimensional dynamic random access memory according to an embodiment of this application. Figure 17 This is a schematic cross-sectional view of the active layer provided in a method for fabricating a three-dimensional dynamic random access memory (DRAM) according to an embodiment of this application. Figures 15 to 17 As shown, in some feasible implementations, step S8: forming an active layer within the third filling space includes: Step S81: Along the circumferential direction of the first via H1 and the second via H2, a portion of the gate layer G and the sixth dielectric layer L6 are removed sequentially by a wet etching process.
[0046] It should be noted that since multiple wet etching processes have been performed before step S81, other etching liquid may remain on the sidewalls of the gate layer inside the first and second vias, causing corrosion to the gate layer. Therefore, removing part of the gate layer before forming the active layer can improve the reliability of the gate layer, extend the device's lifespan, and further improve the gate's control over the active layer, thereby improving the reliability of the three-dimensional dynamic random access memory. Removing the sixth dielectric layer exposes the active region, facilitating the subsequent formation of the active layer.
[0047] Step S82: Using an atomic layer deposition process, a gate insulating layer GI is formed between the first via H1 and the second via H2, with a portion of the gate insulating layer GI covering the surface of the gate layer G.
[0048] Step S83: An initial active layer is formed between the first via H1 and the second via H2 through an atomic layer deposition process, and the initial active layer covers the surface of the gate insulating layer GI.
[0049] Step S84: Using a wet etching process, the initial active layer located on the sidewall of the interlayer dielectric layer I is removed through the first via H1 and the second via H2 to obtain the active layer S.
[0050] It should be noted that removing the active layer material enveloped by the sidewalls of the interlayer dielectric layer through wet etching can avoid mutual interference between the dual-gate transistors, and further improve the reliability of the three-dimensional dynamic random access memory.
[0051] The method for fabricating a three-dimensional dynamic random access memory provided in this application embodiment further includes, after step S8: step S9, forming a dual-gate transistor between adjacent first and second vias, forming a bit line on the side of the dual-gate transistor near the first via, and forming a capacitor on the side of the dual-gate transistor near the second via.
[0052] Figure 18This is a schematic cross-sectional view of a three-dimensional dynamic random access memory (DRAM) provided by a method for fabricating a DRAM according to an embodiment of this application. In some feasible implementations, step S9: forming a dual-gate transistor between adjacent first and second vias, forming a bit line on the side of the dual-gate transistor near the first via, and forming a capacitor on the side of the dual-gate transistor near the second via, includes: Step S91: The gate layer G between adjacent interlayer dielectric layers I includes a first gate layer G1 and a second gate layer G2. The first gate layer G1 is located between the second gate layer G2 and the substrate P. The active layer S is located between the first gate layer G1 and the second gate layer G2. The first gate layer G1, the second gate layer G2 and the active layer S between adjacent interlayer dielectric layers I together form a dual-gate transistor.
[0053] Step S92: Using atomic layer deposition, a first initial conductive layer and a second initial conductive layer are formed through the first via H1 and the second via H2, respectively. The first initial conductive layer is used to form bit lines BL. Part of the bit lines BL are located on the side of the interlayer dielectric layer I near the first via H1, and part of the bit lines BL cover the surface of the active layer S near the first via H1.
[0054] Step S93: Using a wet etching process, the second initial conductive layer located on the surface of the interlayer dielectric layer I near the second via H2 is removed through the second via H2 to obtain capacitor plate C1. Capacitor plate C1 covers the surface of the active layer S near the second via H2.
[0055] Step S94: Using atomic layer deposition, an interplate dielectric layer C0 is formed through the second via H2. Part of the interplate dielectric layer C0 covers the surface of the interplate dielectric layer I near the second via H2, and part of the interplate dielectric layer C0 covers the surface of the capacitor plate C1.
[0056] Step S95: Through atomic layer deposition, a third initial conductive layer is formed on the side of the inter-plate dielectric layer C0 near the second through hole H2 through the second through hole H2. The third initial conductive layer is used to form the common electrode C2. The capacitor electrode C1, the inter-plate dielectric layer C0 and the common electrode C2 together form a capacitor.
[0057] The method for fabricating a three-dimensional dynamic random access memory (DRAM) provided in this application simplifies the fabrication process by alternately forming dielectric layer groups using two dielectric materials. By setting unequal thicknesses for the second and fourth dielectric layers within the dielectric layer group, the second and fourth dielectric layers can be used as active layers and interlayer dielectric layers, respectively, thus ensuring the channel quality of the dual-gate transistor and the electrical isolation between the three-dimensionally stacked DRAMs. Etching the dielectric layer group to form spaced first and second trenches allows the etching liquid used in subsequent wet etching processes to enter the dielectric layer group, while also enabling isotropic etching along the circumference of the trenches. Since the second and fourth dielectric layers are formed using the same dielectric material, they can be simultaneously etched in a single wet etching process, saving process steps and creating two corresponding first filling spaces. These spaces can then be filled with conductive material to form a dual-gate transistor structure with two gates. By forming a fifth dielectric layer within the first and second trenches, the first and second vias can be used as connecting holes for the source and drain electrodes of the dual-gate transistor, facilitating the entry of etching liquid into the dielectric layer group during subsequent wet etching processes. Since the first and third dielectric layers are formed using the same dielectric material, and the fifth dielectric layer is formed using a different dielectric material, the first and third dielectric layers can be simultaneously etched in a single wet etching process while maintaining the integrity of the first and second vias, forming second and third filling spaces of different thicknesses. Furthermore, by forming an interlayer dielectric layer within the second filling space and an active layer within the third filling space, the active layer can be positioned between the two gate layers. This allows the two gate layers and one active layer within a dielectric layer group to collectively constitute a dual-gate transistor structure. Simultaneously, an interlayer dielectric layer of a certain thickness can be formed between adjacent dual-gate transistor structures in the first direction, achieving electrical isolation between different layers of dual-gate transistors and providing support for the entire three-dimensional dynamic random access memory. By forming a bit line on the side of the dual-gate transistor near the first via, the bit line can be electrically connected to the drain of the dual-gate transistor. By controlling the word line connected to the gate of the dual-gate transistor, the transistor can be turned on or off. When the transistor is turned on, data on the bit line can be written to the capacitor, or data stored in the capacitor can be read from the bit line, thus obtaining a 1T1C dynamic random access memory architecture.Therefore, the fabrication process involved in the fabrication method of the three-dimensional dynamic random access memory provided in this application embodiment can be realized by conventional wet etching process, etching process and film growth process, without involving complex film deposition control and film patterning, so it can be compatible with existing three-dimensional stacked structure production lines, and further realize the mass production of three-dimensional dynamic random access memory, thereby reducing the fabrication difficulty of three-dimensional dynamic random access memory, simplifying the fabrication process and improving the fabrication efficiency.
[0058] Figure 19 This is a schematic structural diagram of a three-dimensional dynamic random access memory provided in an embodiment of this application. Figure 19 As shown, a second aspect of this application provides a three-dimensional dynamic random access memory (DRAM), fabricated using any of the three-dimensional DRAM methods described in the first aspect. The three-dimensional DRAM includes: a substrate P; a plurality of memory cell layers and a plurality of interlayer dielectric layers alternately stacked along a first direction F1. Each memory cell layer includes a plurality of memory cells arranged in an array. Each memory cell includes a dual-gate transistor T and a capacitor C. Within the memory cell, the capacitor C is located on one side of the dual-gate transistor T along a second direction F2. Wherein, the first direction F1 is perpendicular to the substrate P, and the second direction F2 is parallel to the substrate P; wherein, the dual-gate transistor T includes a first gate layer G1, an active layer S, and a second gate layer G2, the active layer S is located between the first gate layer G1 and the second gate layer G2, the first gate layer G1 is located between the active layer S and the substrate P, and the capacitor C includes a capacitor plate C1, a common plate C2, and an inter-plate dielectric layer C0, the common plate C2 is disposed on the side of the capacitor plate C1 away from the dual-gate transistor T, and the inter-plate dielectric layer C0 is located between the common plate C2 and the capacitor plate C1. It should be noted that... Figure 19 The area outlined by the white dashed "- -" is the area where the dual-gate transistor T is located; the area outlined by the white dashed "· ——·——" is the area where the capacitor C is located; the area outlined by the black dashed "- -" is the area where the memory cell layer is located; and the area outlined by the black dashed "·——·——" is the area where the interlayer dielectric layer is located.
[0059] The three-dimensional dynamic random access memory (DRAM) provided in this application simplifies the fabrication process by alternating dielectric layers formed with two different dielectric materials. By setting unequal thicknesses for the second and fourth dielectric layers within the dielectric layer group, the second and fourth dielectric layers can be used as active layers and interlayer dielectric layers, respectively, thus ensuring the channel quality of the dual-gate transistor and the electrical isolation between the three-dimensionally stacked DRAMs. Etching the dielectric layer group to form spaced first and second trenches allows the etching liquid used in subsequent wet etching processes to enter the dielectric layer group, while also enabling isotropic etching along the circumference of the trenches. Since the second and fourth dielectric layers are formed using the same dielectric material, they can be simultaneously etched in a single wet etching process, saving process steps and creating two corresponding first filling spaces. These spaces can then be filled with conductive material to form a dual-gate transistor structure with two gates. By forming a fifth dielectric layer within the first and second trenches, the first and second vias can be used as connecting holes for the source and drain electrodes of the dual-gate transistor, facilitating the entry of etching liquid into the dielectric layer group during subsequent wet etching processes. Since the first and third dielectric layers are formed using the same dielectric material, and the fifth dielectric layer is formed using a different dielectric material, the first and third dielectric layers can be simultaneously etched in a single wet etching process while maintaining the integrity of the first and second vias, forming second and third filling spaces of different thicknesses. Furthermore, by forming an interlayer dielectric layer within the second filling space and an active layer within the third filling space, the active layer can be positioned between the two gate layers. This allows the two gate layers and one active layer within a dielectric layer group to collectively constitute a dual-gate transistor structure. Simultaneously, an interlayer dielectric layer of a certain thickness can be formed between adjacent dual-gate transistor structures in the first direction, achieving electrical isolation between different layers of dual-gate transistors and providing support for the entire three-dimensional dynamic random access memory. By forming a bit line on the side of the dual-gate transistor near the first via, the bit line can be electrically connected to the drain of the dual-gate transistor. By controlling the word line connected to the gate of the dual-gate transistor, the transistor can be turned on or off. When the transistor is turned on, data on the bit line can be written to the capacitor, or data stored in the capacitor can be read from the bit line, thus obtaining a 1T1C dynamic random access memory architecture.Therefore, the fabrication process involved in the fabrication method of the three-dimensional dynamic random access memory provided in this application embodiment can be realized by conventional wet etching process, etching process and film growth process, without involving complex film deposition control and film patterning, so it can be compatible with existing three-dimensional stacked structure production lines, and further realize the mass production of three-dimensional dynamic random access memory, thereby reducing the fabrication difficulty of three-dimensional dynamic random access memory, simplifying the fabrication process and improving the fabrication efficiency.
[0060] like Figure 19 As shown, in some feasible embodiments, the thickness of the first gate layer G1 and the second gate layer G2 are equal; the thickness of the interlayer dielectric layer is greater than the thickness of the active layer S between the first gate layer G1 and the second gate layer G2.
[0061] The three-dimensional dynamic random access memory provided in this application reduces the control difficulty of dual-gate transistors by setting the thickness of the first gate layer and the second gate layer to be equal, and facilitates the on / off control of the active layer through the coordinated control of the first gate layer and the second gate layer. By setting the thickness of the interlayer dielectric layer to be greater than the thickness of the active layer between the first gate layer and the second gate layer, the support effect and electrical isolation effect of the interlayer dielectric layer can be further improved, the control effect of each dual-gate transistor can be improved, the stability of each memory cell layer can be improved, and the reliability of the three-dimensional dynamic random access memory can be further improved.
[0062] like Figure 19 As shown, in some feasible implementations, the three-dimensional dynamic random access memory further includes: a bit line BL disposed on the side of the dual-gate transistor T away from the capacitor C, and the bit line BL covers the surface of the active layer S away from the capacitor C.
[0063] The three-dimensional dynamic random access memory provided in this application embodiment forms a bit line on the side of the dual-gate transistor near the first via, allowing the bit line to be electrically connected to the drain of the dual-gate transistor. By controlling the word line connected to the gate of the dual-gate transistor, the transistor can be turned on or off. When the transistor is turned on, data on the bit line can be written to the capacitor, or data stored in the capacitor can be read from the bit line, thereby obtaining a 1T1C architecture dynamic random access memory.
[0064] In some feasible implementations, in the third direction, the bit line corresponds one-to-one with the adjacent capacitor, the third direction is parallel to the substrate, and the second direction intersects with the third direction.
[0065] The three-dimensional dynamic random access memory (DRAM) provided in this application establishes a direct spatial correspondence between each bit line and its adjacent capacitors. This allows the transistors and capacitors in each memory cell to form a regular, repeating array arrangement, thus maintaining a uniform layout during atomic layer deposition and wet etching stages and reducing process deviations caused by misalignment. Simultaneously, it shortens the interconnection path between the bit line and the corresponding memory cell, reducing parasitic resistance and capacitance, thereby optimizing the signal integrity and speed of read and write operations and further improving the reliability of the three-dimensional DRAM.
[0066] The above embodiments are merely exemplary embodiments of this application and are not intended to limit this application. The scope of protection of this application is defined by the claims. Those skilled in the art can make various modifications or equivalent substitutions to this application within its substance and scope of protection, and such modifications or equivalent substitutions should also be considered to fall within the scope of protection of this application.
[0067] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit it. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.
[0068] Although preferred embodiments have been described in this specification, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this specification.
[0069] Obviously, those skilled in the art can make various modifications and variations to this specification without departing from its spirit and scope. Therefore, if such modifications and variations fall within the scope of the claims and their equivalents, this specification is also intended to include such modifications and variations.
Claims
1. A method for fabricating a three-dimensional dynamic random access memory, characterized in that, include: A substrate and at least two groups of dielectric layers stacked along a first direction are provided, wherein each group of dielectric layers includes a first dielectric layer, a second dielectric layer, a third dielectric layer and a fourth dielectric layer stacked sequentially along the first direction, the fourth dielectric layer being located between the first dielectric layer and the substrate within the corresponding group of dielectric layers, the first direction being perpendicular to the substrate; The dielectric layer group is etched to form a spaced first trench and a second trench, the first trench and the second trench extending into the substrate, adjacent first trenches and second trenches are alternately arranged along a second direction, adjacent first trenches are arranged along a third direction, adjacent second trenches are arranged along the third direction, the second direction and the third direction are both parallel to the substrate, and the second direction and the third direction intersect. Along the circumference of the first trench and the second trench, a portion of the second dielectric layer and a portion of the fourth dielectric layer are removed by a wet etching process to form a first filling space, wherein the second dielectric layer and the fourth dielectric layer located between the first trench and the second trench are completely removed; A gate layer is formed within the first filling space; A fifth dielectric layer is formed in the first trench and the second trench. The fifth dielectric layer includes a first through-hole and a second through-hole that penetrate the substrate. The first through-hole is located in the first trench, and the second through-hole is located in the second trench. Along the circumference of the first through hole and the second through hole, a portion of the first dielectric layer and a portion of the third dielectric layer are removed by a wet etching process to form a second filling space and a third filling space. The first dielectric layer and the third dielectric layer located between the first through hole and the second through hole are completely removed. The second filling space is located in the same layer as the first dielectric layer, and the third filling space is located in the same layer as the third dielectric layer. An interlayer dielectric layer is formed within the second filling space; An active layer is formed within the third filling space; A dual-gate transistor is formed between adjacent first and second vias, a bit line is formed on the side of the dual-gate transistor near the first via, and a capacitor is formed on the side of the dual-gate transistor near the second via. The first dielectric layer and the third dielectric layer each include a first dielectric material, the second dielectric layer and the fourth dielectric layer each include a second dielectric material, the first dielectric layer and the fifth dielectric layer include different dielectric materials, and the second dielectric layer and the fourth dielectric layer have different thicknesses.
2. The method for fabricating a three-dimensional dynamic random access memory according to claim 1, characterized in that, The formation of a gate layer within the first filling space includes: An initial gate layer is formed through the first trench and the second trench using an atomic layer deposition process, wherein a portion of the initial gate layer fills the first filling space and a portion of the initial gate layer covers the sidewalls of the first dielectric layer and the third dielectric layer; The initial gate layer is obtained by removing the portion of the initial gate layer covered by the sidewalls of the first dielectric layer and the third dielectric layer using a wet etching process.
3. The method for fabricating a three-dimensional dynamic random access memory according to claim 1, characterized in that, The formation of a fifth dielectric layer within the first trench and the second trench includes: A first initial dielectric layer is formed in the first trench and the second trench using an atomic layer deposition process, wherein the first initial dielectric layer fills the interior of the first trench and the second trench; The first initial dielectric layer is etched using a dry etching process to form the first via and the second via within the first initial dielectric layer, thereby obtaining the fifth dielectric layer.
4. The method for fabricating a three-dimensional dynamic random access memory according to claim 1, characterized in that, The formation of an interlayer dielectric layer within the second filling space includes: A second initial dielectric layer is formed through the first via and the second via using an atomic layer deposition process. The second initial dielectric layer includes a first dielectric material. A portion of the second initial dielectric layer fills the third filling space, a portion of the second initial dielectric layer covers the sidewall of the gate layer, and a portion of the second initial dielectric layer covers the surface of the gate layer in the first direction. By using a wet etching process, a portion of the second initial dielectric layer is removed through the first and second vias to obtain a sixth dielectric layer, which is located within the second filling space. An interlayer dielectric layer is formed in the second filled space through the first and second vias using an atomic layer deposition process, wherein the interlayer dielectric layer and the second initial dielectric layer comprise different dielectric materials.
5. The method for fabricating a three-dimensional dynamic random access memory according to claim 4, characterized in that, The formation of an active layer within the third filling space includes: Along the circumferential direction of the first and second vias, a portion of the gate layer and the sixth dielectric layer are sequentially removed by a wet etching process; A gate insulating layer is formed between the first via and the second via using an atomic layer deposition process, with a portion of the gate insulating layer covering the surface of the gate layer. An initial active layer is formed between the first via and the second via using an atomic layer deposition process, and the initial active layer covers the surface of the gate insulating layer. The initial active layer located on the sidewall of the interlayer dielectric layer is removed by a wet etching process through the first and second vias to obtain the active layer.
6. The method for fabricating a three-dimensional dynamic random access memory according to claim 5, characterized in that, The method of forming a dual-gate transistor between adjacent first and second vias, forming a bit line on the side of the dual-gate transistor near the first via, and forming a capacitor on the side of the dual-gate transistor near the second via includes: The gate layer between adjacent interlayer dielectric layers includes a first gate layer and a second gate layer. The first gate layer is located between the second gate layer and the substrate. The active layer is located between the first gate layer and the second gate layer. The first gate layer, the second gate layer and the active layer between adjacent interlayer dielectric layers together form the dual-gate transistor. A first initial conductive layer and a second initial conductive layer are formed through the first via and the second via, respectively, by an atomic layer deposition process. The first initial conductive layer is used to form the bit line. Part of the bit line is located on the side of the interlayer dielectric layer near the first via, and part of the bit line covers the surface of the active layer on the side near the first via. By using a wet etching process, the second initial conductive layer located on the surface of the interlayer dielectric layer near the second via is removed through the second via, thereby obtaining a capacitor plate, which covers the surface of the active layer near the second via. An interplate dielectric layer is formed through the second via using an atomic layer deposition process. Part of the interplate dielectric layer covers the surface of the interplate dielectric layer near the second via, and part of the interplate dielectric layer covers the surface of the capacitor plate. A third initial conductive layer is formed on the side of the inter-plate dielectric layer near the second via through the second via using an atomic layer deposition process. The third initial conductive layer is used to form a common electrode. The capacitor electrode, the inter-plate dielectric layer, and the common electrode together form the capacitor.
7. A three-dimensional dynamic random access memory, characterized in that, The three-dimensional dynamic random access memory (DRAM) is prepared by any one of claims 1 to 6, wherein the DRAM comprises: Substrate; Multiple memory cell layers and multiple interlayer dielectric layers are stacked alternately along a first direction. Each memory cell layer includes multiple memory cells arranged in an array. Each memory cell includes a dual-gate transistor and a capacitor. Within the memory cell, the capacitor is located on one side of the dual-gate transistor in a second direction. The first direction is perpendicular to the substrate, and the second direction is parallel to the substrate. The dual-gate transistor includes a first gate layer, an active layer, and a second gate layer. The active layer is located between the first gate layer and the second gate layer, and the first gate layer is located between the active layer and the substrate. The capacitor includes a capacitor plate, a common plate, and an inter-plate dielectric layer. The common plate is disposed on the side of the capacitor plate away from the dual-gate transistor, and the inter-plate dielectric layer is located between the common plate and the capacitor plate.
8. The three-dimensional dynamic random access memory according to claim 7, characterized in that, The thickness of the first gate layer is equal to that of the second gate layer; The thickness of the interlayer dielectric layer is greater than the thickness of the active layer between the first gate layer and the second gate layer.
9. The three-dimensional dynamic random access memory according to claim 7, characterized in that, Also includes: Bit lines are disposed on the side of the dual-gate transistor away from the capacitor, and the bit lines cover the surface of the active layer away from the capacitor.
10. The three-dimensional dynamic random access memory according to claim 9, characterized in that, In the third direction, the bit line corresponds one-to-one with the adjacent capacitor, the third direction is parallel to the substrate, and the second direction intersects the third direction.