Non-volatile memory and method of manufacturing the same

Abstract

This invention discloses a non-volatile memory and its manufacturing method. The non-volatile memory includes: a substrate; an oxide semiconductor layer on the substrate; a tunneling dielectric layer on the oxide semiconductor layer; a gate stack on the tunneling dielectric layer; an erase gate on the tunneling dielectric layer; a second inter-gate dielectric layer between the gate stack and the erase gate; and source and drain regions on the substrate and located on opposite sides of the oxide semiconductor layer. The gate stack includes: a floating gate on the tunneling dielectric layer; a first inter-gate dielectric layer on the floating gate; and a control gate on the first inter-gate dielectric layer.

Description

Technical Field

[0001] This invention relates to a non-volatile memory, and more particularly to a non-volatile memory and a method for manufacturing the same. Background Technology

[0002] With the widespread adoption of consumer electronics such as smartphones, memory cards, and USB flash drives, and the maturity of manufacturing technologies, the application of non-volatile memory, such as flash RAM, read-only memory (ROM), erasable programmable read-only memory (EPROM), and electrically erasable programmable read-only memory (EEPROM), has grown significantly.

[0003] However, as the demand for various electronic products increases, there are also higher requirements for the read and write speeds of non-volatile memory, and it is also expected that the leakage current of non-volatile memory can be reduced. Summary of the Invention

[0004] This invention provides a non-volatile memory and a method for forming the same, to improve the read and write speeds of the non-volatile memory while reducing its leakage current.

[0005] This invention proposes a non-volatile memory, comprising: a substrate; an oxide semiconductor layer on the substrate; a tunneling dielectric layer on the oxide semiconductor layer; and a gate stack on the tunneling dielectric layer, wherein the gate stack includes: a floating gate on the tunneling dielectric layer, a first inter-gate dielectric layer on the floating gate, and a control gate on the first inter-gate dielectric layer; an erase gate on the tunneling dielectric layer; a second inter-gate dielectric layer between the gate stack and the erase gate; and a source region and a drain region on the substrate and located on opposite sides of the oxide semiconductor layer.

[0006] According to one embodiment of the present invention, the oxide semiconductor layer includes In-Sn-Ga-Zn-O, In-Ga-Zn-O, In-Sn-Zn-O, In-Al-Zn-O, Sn-Ga-Zn-O, Al-Ga-Zn-O, Sn-Al-Zn-O, In-Zn-O, Sn-Zn-O, Al-Zn-O, Zn-Mg-O, Sn-Mg-O, In-Mg-O, In-O, Sn-O, or Zn-O.

[0007] According to one embodiment of the present invention, the oxide semiconductor layer comprises a material represented by the chemical formula InMO3(ZnO)m, wherein M is one or more selected from Ga, Al, Mn and Co, and m>0.

[0008] According to one embodiment of the present invention, the thickness of the oxide semiconductor layer is 2 nm to 200 nm.

[0009] According to one embodiment of the present invention, the oxide semiconductor layer is a channel layer of a non-volatile memory.

[0010] According to one embodiment of the present invention, it further includes: a first spacer wall located on the sidewall of the gate stack; and a second spacer wall located on the sidewall of the erased gate.

[0011] According to one embodiment of the present invention, the top surface of the control gate and the top surface of the erase gate are coplanar.

[0012] This invention proposes a method for manufacturing a non-volatile memory, comprising: providing a semiconductor substrate; providing a substrate; forming an oxide semiconductor layer on the substrate; forming a tunneling dielectric layer on the oxide semiconductor layer; forming a gate stack on the tunneling dielectric layer, wherein the gate stack includes: a floating gate located on the tunneling dielectric layer, a first inter-gate dielectric layer located on the floating gate, and a control gate located on the first inter-gate dielectric layer; forming an erase gate located on the tunneling dielectric layer; forming a second inter-gate dielectric layer between the gate stack and the erase gate; and forming a source region and a drain region located on the substrate and on opposite sides of the oxide semiconductor layer.

[0013] According to one embodiment of the present invention, the step of forming an oxide semiconductor layer on a substrate includes: depositing an oxide semiconductor material on the substrate; and patterning the oxide semiconductor material to define the oxide semiconductor layer.

[0014] According to one embodiment of the present invention, the step of depositing oxide semiconductor material on a substrate includes physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD).

[0015] According to one embodiment of the present invention, the oxide semiconductor layer includes In-Sn-Ga-Zn-O, In-Ga-Zn-O, In-Sn-Zn-O, In-Al-Zn-O, Sn-Ga-Zn-O, Al-Ga-Zn-O, Sn-Al-Zn-O, In-Zn-O, Sn-Zn-O, Al-Zn-O, Zn-Mg-O, Sn-Mg-O, In-Mg-O, In-O, Sn-O, or Zn-O.

[0016] According to one embodiment of the present invention, the oxide semiconductor layer comprises InMO3(ZnO). m The material is represented by M, which is selected from one or more of Ga, Al, Mn and Co, and m>0.

[0017] According to one embodiment of the present invention, the thickness of the oxide semiconductor layer is 2 nm to 200 nm.

[0018] According to one embodiment of the present invention, the oxide semiconductor layer is a channel layer of a non-volatile memory.

[0019] According to one embodiment of the present invention, it further includes: forming a first spacer wall on the sidewall of the gate stack; and forming a second spacer wall on the sidewall of the erased gate.

[0020] According to one embodiment of the present invention, the top surface of the control gate and the top surface of the erase gate are coplanar.

[0021] Based on the above, in the non-volatile memory and its manufacturing method of the present invention, an oxide semiconductor layer is used as the channel layer. Based on the characteristics of the oxide semiconductor layer material itself, the electrons in the non-volatile memory can have a high mobility, thus increasing the read and write speed of the non-volatile memory. Furthermore, using an oxide semiconductor layer as the channel layer of the non-volatile memory can also reduce the non-volatile memory and improve the device efficiency.

[0022] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0023] Figures 1 to 10 This is a cross-sectional flow diagram of a method for manufacturing a non-volatile memory according to an embodiment of the present invention.

[0024] Symbol Explanation

[0025] 10: Non-volatile memory

[0026] 100: Base

[0027] 110: Oxide semiconductor layer

[0028] 122: Tunneling dielectric layer

[0029] 124: Electronic Access Layer

[0030] 126: Dielectric layer / First inter-gate dielectric layer

[0031] 128: First polycrystalline silicon layer

[0032] 130: First oxide layer

[0033] 132: Second intergate dielectric layer

[0034] 140: Second polycrystalline silicon layer

[0035] 150: Second oxide layer

[0036] 160: Conductive layer

[0037] 170: Contact plug

[0038] CG: Control Gate

[0039] EG: Gate erase

[0040] FG: Floating Gate

[0041] G: Gate Stack

[0042] S1: First partition wall

[0043] S2: Second partition wall

[0044] S / D: Source and Drain Regions Detailed Implementation

[0045] The following examples are described in detail with reference to the accompanying drawings, but the examples provided are not intended to limit the scope of the invention.

[0046] For ease of understanding, the same components will be indicated by the same symbols in the following descriptions, and will not be repeated in the following paragraphs.

[0047] Furthermore, the accompanying drawings are for illustrative purposes only and are not drawn to their original dimensions. In fact, for clarity of explanation, the dimensions of various features may be increased or decreased as appropriate.

[0048] Furthermore, for ease of description, the terms "above," "below," and similar spatial relative terms are used herein to describe the relative relationship between one component and another as shown in the accompanying drawings, and are not intended to limit the invention. Therefore, it should be understood that "above" and "below" are used interchangeably, and when a component is located "above" another component, the component may be placed directly on the other component, or there may be an intermediate component. On the other hand, when a component is said to be placed "directly" on another component, there is no intermediate component between them.

[0049] The terminology used herein is for illustrative purposes only and is not intended to limit the invention. In this context, the singular form includes the plural form unless the context otherwise requires.

[0050] Please see Figure 1 First, a substrate 100 is provided, and then an oxide semiconductor layer 110 is formed on the substrate 100.

[0051] In some embodiments, the substrate 100 may include materials such as silicon and glass, but is not limited thereto; any substrate 100 used to manufacture the non-volatile memory 10 may be used.

[0052] In some embodiments, the oxide semiconductor layer 110 may include metal oxides, such as quaternary metal oxides In-Sn-Ga-Zn-O; ternary metal oxides In-Ga-Zn-O, In-Sn-Zn-O, In-Al-Zn-O, Sn-Ga-Zn-O, Al-Ga-Zn-O, Sn-Al-Zn-O; binary metal oxides In-Zn-O, Sn-Zn-O, Al-Zn-O, Zn-Mg-O, Sn-Mg-O, In-Mg-O; and monometallic metal oxides In-O, Sn-O, Zn-O, etc.

[0053] Additionally, the oxide semiconductor layer 110 may include InMO3 (ZnO). m The material is represented by M, which is one or more metallic elements selected from Ga, Al, Mn and Co. For example, M can be Ga alone, or a combination of two metallic elements such as Ga and Al, Ga and Mn, or Ga and Co, and m>0.

[0054] Furthermore, in InMO3(ZnO) m Among the materials represented by (m>0), materials where M is Ga are often called IGZO (Indium Gallium Zinc Oxide).

[0055] In some embodiments, various suitable deposition methods can be used to form oxide semiconductor materials on the substrate 100, such as physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD), but are not limited thereto; any method that can be used to form oxide semiconductor materials can be used in this invention. Then, patterning is performed using methods such as photolithography or etching to define the desired cell area and shape on the oxide semiconductor layer 110.

[0056] The cell size and shape defined in the oxide semiconductor layer 110 must be able to accommodate the main components of the non-volatile memory 10 such as the floating gate FG, control gate CG, and erase gate EG that are subsequently formed, but the requirements for component density must also be taken into account, and it cannot be expanded indefinitely.

[0057] Furthermore, the thickness of the oxide semiconductor layer 110 varies depending on factors such as the material used for the oxide semiconductor layer 110 and the size of the non-volatile memory 10 to be formed. Generally, the thickness of the oxide semiconductor layer 110 can be approximately 2 nm to 200 nm, preferably 2 nm to 5 nm. However, this thickness range is a result of matching the current size of the non-volatile memory 10. As the size of the non-volatile memory 10 changes in the future, the thickness of the oxide semiconductor layer 110 will also need to be changed accordingly.

[0058] The oxide semiconductor layer 110 can be used as such Figure 10 The channel layer of the non-volatile memory 10 shown, based on the characteristics of the oxide semiconductor layer 110 material itself, allows electrons in the non-volatile memory 10 to have a high mobility, thus increasing the read and write speed of the non-volatile memory 10; furthermore, using the oxide semiconductor layer 110 as the channel layer of the non-volatile memory 10 can also reduce leakage current and improve device efficiency.

[0059] Next, please refer to Figure 2 A tunneling dielectric layer 122 is formed on the oxide semiconductor layer 110.

[0060] In some embodiments, the tunneling dielectric layer 122 may include an oxide layer, but is not limited thereto.

[0061] Next, please refer to the following: Figure 2 as well as Figure 3A gate stack G is formed on the tunneling dielectric layer 122, wherein the gate stack G includes a floating gate FG located on the tunneling dielectric layer 122, a first inter-gate dielectric layer 126 located on the floating gate FG, and a control gate CG located on the first inter-gate dielectric layer 126.

[0062] In some embodiments, the step of forming a gate stack G on the tunneling dielectric layer 122 may include: sequentially forming an electron access layer 124, a dielectric layer 126, and a first polysilicon layer 128 on the tunneling dielectric layer 122, such as... Figure 2 As shown; next, using photolithography and etching, the first polysilicon layer 128, dielectric layer 126, and electron access layer 124 are patterned to sequentially form the control gate CG, the first inter-gate dielectric layer 126, and the floating gate FG on the tunneling dielectric layer 122, thus completing the definition of the gate stack G, as shown. Figure 3 As shown.

[0063] In some embodiments, the electronic access layer 124 may include any electronic access material suitable for the non-volatile memory 10, such as silicon nitride (Si3N4) or polycrystalline silicon, but is not limited thereto, for use as the floating gate FG of the non-volatile memory 10.

[0064] The dielectric layer 126 may include any material suitable for the space between the floating gate FG and the control gate CG of the non-volatile memory 10, so as to give the non-volatile memory 10 lower leakage current and better data retention capability, thereby improving the reliability of the non-volatile memory 10. In some embodiments, the dielectric layer 126 may include an oxide layer, a nitride layer, or a material combining multiple oxide and nitride layers, such as an oxide-nitride-oxide (ONO) layer or an oxide-nitride-oxide-nitride (ONON) layer.

[0065] After the cell of the gate stack G is defined, the first polysilicon layer 128 forms the control gate CG of the non-volatile memory 10.

[0066] Next, as Figure 4 As shown, a first oxide layer 130 can be formed on the top and side surfaces of the gate stack G by deposition or tempering.

[0067] Then, a second polysilicon layer 140 is deposited on the tunneling dielectric layer 122 and the gate stack G.

[0068] In some embodiments, the second polysilicon layer 140 can completely cover the gate stack G, meaning the thickness of the deposited second polysilicon layer 140 can exceed the thickness of the gate stack G. Then, the excess second polysilicon layer 140 in the vertical direction is removed using a planarization method such as chemical mechanical polishing (CMP). Because there is a certain degree of etch selectivity between the polysilicon and the oxide layer, the removal of the second polysilicon layer 140 can be stopped at a horizontal position, coplanar with the top surface of the first oxide layer 130. That is, at this point, the top surface of the first oxide layer 130 and the top surface of the second polysilicon layer 140 are coplanar. Figure 5 As shown.

[0069] Next, the second polysilicon layer 140 is patterned using photolithography and etching to define the size of the erase gate EG of the non-volatile memory 10 on the tunnel dielectric layer 122, such as... Figure 6 As shown.

[0070] Next, a second oxide layer 150 can be formed on the top and sidewalls of the erased gate EG by means of direct deposition or thermal oxidation.

[0071] If a second oxide layer 150 is formed on the top and sidewalls of the erase gate EG using thermal oxidation, since the erase gate EG is formed by patterning the second polysilicon layer 140 and its material is polysilicon, the polysilicon exposed to oxygen in an oxygen-filled and high-temperature environment will oxidize to silicon oxide. Therefore, from Figure 6 The erase gate EG shown will have its outer portion exposed to oxygen undergo thermal oxidation, causing the polysilicon erase gate EG to shrink inwards. Figure 7 The erase gate EG is shown, while Figure 6 A second oxide layer 150 is formed on the top and sidewalls exposed by the erased gate EG. The degree of inward retraction of the erased gate EG is not as... Figure 7 As is so obvious, this exaggerated depiction is intended to provide a clearer description and illustration.

[0072] Next, as Figure 8 As shown, various etching methods can be used to remove the exposed tunneling dielectric layer 122, the first oxide layer 130 on the top surface of the gate stack G, and the second oxide layer 150 on the top surface of the erase gate EG, so as to expose the top surface of the substrate 100, the top surface of the control gate CG, and the top surface of the erase gate EG.

[0073] The first oxide layer 130 remaining after this etching process is formed as a first spacer wall S1 on the sidewall of the gate stack G and a second inter-gate dielectric layer 132 between the gate stack G and the erased gate EG; and the second oxide layer 150 remaining after this etching process is formed as a second spacer wall S2 on the sidewall of the erased gate EG.

[0074] In some embodiments, dry etching can be used to remove the exposed tunneling dielectric layer 122, the first oxide layer 130 on the top surface of the gate stack G, and the second oxide layer 150 on the top surface of the erase gate EG, so as to expose the top surface of the substrate 100, the top surface of the control gate CG, and the top surface of the erase gate EG. The first oxide layer 130 remaining after this etching process is formed as a first spacer S1 on the sidewall of the gate stack G and a second inter-gate dielectric layer 132 between the gate stack G and the erase gate EG. The second oxide layer 150 remaining after this etching process is formed as a second spacer S2 on the sidewall of the erase gate EG.

[0075] In some embodiments, wet etching can be used to remove the exposed tunneling dielectric layer 122, the first oxide layer 130 on the top surface of the gate stack G, and the second oxide layer 150 on the top surface of the erase gate EG, exposing the top surface of the substrate 100, the top surface of the control gate CG, and the top surface of the erase gate EG. The first oxide layer 130 remaining after this etching process is formed as a first spacer S1 on the sidewall of the gate stack G and a second inter-gate dielectric layer 132 between the gate stack G and the erase gate EG. The second oxide layer 150 remaining after this etching process is formed as a second spacer S2 on the sidewall of the erase gate EG. Especially when the tunneling dielectric layer 122 is an oxide, since the tunneling dielectric layer 122, the first oxide layer 130, and the second oxide layer 150 to be removed are all oxides, they have a relatively high etch selectivity relative to the oxide semiconductor layer 110. Therefore, damage to the oxide semiconductor layer 110, which serves as the channel layer, can be avoided in this wet etching process.

[0076] In some embodiments, the top surface of the control gate CG and the top surface of the erase gate EG may be coplanar, such as... Figure 8 As shown.

[0077] Next, as Figure 9 As shown, a conductive layer 160 may be formed on the substrate 100. This conductive layer 160 may include conductive materials such as titanium nitride (TiN) to reduce the resistance between the contact plug 170 subsequently formed on the substrate 100 and the substrate 100.

[0078] Then, as Figure 10As shown, source and drain regions S / D are formed on opposite sides of the oxide semiconductor layer 110 on the substrate 100, and a plurality of contact plugs 170 are formed on the top surface of the conductive layer 160, the top surface of the control gate CG and the top surface of the erase gate EG to facilitate device control, and insulating materials such as silicon oxide (not shown) are also included between these plurality of contact plugs 170.

[0079] In the non-volatile memory 10 of this embodiment, the oxide semiconductor layer 110 can serve as such as Figure 10 The channel layer of the non-volatile memory 10 shown, based on the characteristics of the oxide semiconductor layer 110 material itself, allows electrons in the non-volatile memory 10 to have a high mobility, thus increasing the read and write speed of the non-volatile memory 10; furthermore, using the oxide semiconductor layer 110 as the channel layer of the non-volatile memory 10 can also reduce leakage current and improve device efficiency.

[0080] In summary, in the non-volatile memory and its manufacturing method of the present invention, an oxide semiconductor layer is used as the channel layer. Based on the characteristics of the oxide semiconductor layer material itself, the electrons in the non-volatile memory can have a high mobility, thus increasing the read and write speed of the non-volatile memory. Furthermore, using an oxide semiconductor layer as the channel layer of the non-volatile memory can also reduce the non-volatile memory and improve the device efficiency.

[0081] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be defined by the appended claims.

Claims

1. A non-volatile memory, comprising: Base; An oxide semiconductor layer is located on the substrate; A tunneling dielectric layer is located on the oxide semiconductor layer; A gate stack is located on the tunneling dielectric layer, wherein the gate stack comprises: A floating gate is located on the tunneling dielectric layer. The first inter-gate dielectric layer is located on the floating gate, and The control gate is located on the first inter-gate dielectric layer; The gate is erased and located on the tunneling dielectric layer; A second inter-gate dielectric layer is disposed between the gate stack and the erase gate; and The source region and the drain region are located on the substrate and on opposite sides of the oxide semiconductor layer.

2. The non-volatile memory of claim 1, wherein the oxide semiconductor layer comprises In-Sn-Ga-Zn-O, In-Ga-Zn-O, In-Sn-Zn-O, In-Al-Zn-O, Sn-Ga-Zn-O, Al-Ga-Zn-O, Sn-Al-Zn-O, In-Zn-O, Sn-Zn-O, Al-Zn-O, Zn-Mg-O, Sn-Mg-O, In-Mg-O, In-O, Sn-O, or Zn-O.

3. The non-volatile memory of claim 1, wherein the oxide semiconductor layer comprises a material represented by the chemical formula InMO3(ZnO)m, wherein M is one or more selected from Ga, Al, Mn and Co, and m>0.

4. The non-volatile memory of claim 1, wherein the thickness of the oxide semiconductor layer is 2 nm to 200 nm.

5. The non-volatile memory of claim 1, wherein the oxide semiconductor layer is the channel layer of the non-volatile memory.

6. The non-volatile memory of claim 1, further comprising: A first spacer wall is located on the sidewall of the gate stack; and The second spacer is located on the sidewall of the erase gate.

7. The non-volatile memory of claim 1, wherein the top surface of the control gate and the top surface of the erase gate are coplanar.

8. A method for manufacturing a non-volatile memory, comprising: Provide a base; On the substrate where the oxide semiconductor layer is formed; A tunneling dielectric layer is formed on the oxide semiconductor layer; A gate stack is formed on the tunneling dielectric layer, wherein the gate stack comprises: A floating gate is located on the tunneling dielectric layer. The first inter-gate dielectric layer is located on the floating gate, and The control gate is located on the first inter-gate dielectric layer; An erase gate is formed on the tunneling dielectric layer; A second inter-gate dielectric layer is formed between the gate stack and the erase gate; and Source and drain regions are formed on the substrate and on opposite sides of the oxide semiconductor layer.

9. The method of manufacturing a non-volatile memory as claimed in claim 8, wherein the step of forming the oxide semiconductor layer on the substrate comprises: Depositing oxide semiconductor material on the substrate; and The oxide semiconductor material is patterned to define the oxide semiconductor layer.

10. The method for manufacturing a non-volatile memory as claimed in claim 8, wherein the step of depositing the oxide semiconductor material on the substrate includes physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD).

11. The method of manufacturing a non-volatile memory as claimed in claim 8, wherein the oxide semiconductor layer comprises In-Sn-Ga-Zn-O, In-Ga-Zn-O, In-Sn-Zn-O, In-Al-Zn-O, Sn-Ga-Zn-O, Al-Ga-Zn-O, Sn-Al-Zn-O, In-Zn-O, Sn-Zn-O, Al-Zn-O, Zn-Mg-O, Sn-Mg-O, In-Mg-O, In-O, Sn-O, or Zn-O.

12. The method of manufacturing a non-volatile memory as claimed in claim 8, wherein the oxide semiconductor layer comprises a material represented by the chemical formula InMO3(ZnO)m, wherein M is one or more selected from Ga, Al, Mn and Co, and m>0.

13. The method for manufacturing a non-volatile memory as claimed in claim 8, wherein the thickness of the oxide semiconductor layer is 2 nm to 200 nm.

14. The method for manufacturing a non-volatile memory as claimed in claim 8, wherein the oxide semiconductor layer is the channel layer of the non-volatile memory.

15. The method for manufacturing a non-volatile memory as described in claim 8, further comprising: A first spacer wall is formed on the sidewall of the gate stack; and A second spacer wall is formed on the sidewall of the erase gate.

16. The method of manufacturing a non-volatile memory as claimed in claim 8, wherein the top surface of the control gate and the top surface of the erase gate are coplanar.

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