Semiconductor device and electronic system including the same

Abstract

A semiconductor device and an electronic system are provided. The semiconductor device includes a first conductive pattern, a second conductive pattern spaced apart from the first conductive pattern in a first direction, a dielectric pattern between the first conductive pattern and the second conductive pattern, a first molding pattern at a same level as a level of the first conductive pattern, a second molding pattern at a same level as a level of the second conductive pattern and spaced apart from the first molding pattern in the first direction, a memory trench structure penetrating the first conductive pattern and the second conductive pattern, a first connection contact electrically connected to the first conductive pattern, and a first connection contact dielectric layer surrounding the first connection contact. The dielectric pattern is between the first molding pattern and the second molding pattern. The first connection contact and the first connection contact dielectric layer are between the second conductive pattern and the second molding pattern.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2025-0005050, filed on January 13, 2025, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Some example embodiments relate to a semiconductor device and / or an electronic system including the semiconductor device, and more specifically, to a semiconductor device including a molded pattern and / or an electronic system including the semiconductor device. Background Technology

[0004] Semiconductor devices have attracted attention as fundamental components in the electronics industry due to their characteristics such as compactness, versatility, and / or low manufacturing cost. Semiconductor devices can include one or more of the following: semiconductor memory devices for storing logic data, semiconductor logic devices for processing logic data, and hybrid semiconductor devices that have both memory and logic elements.

[0005] Recently, the high speed and / or low power consumption requirements of electronic products necessitate that semiconductor devices embedded in these products possess high operating speeds and / or low operating voltages. However, the increased integration of semiconductor devices may lead to a decrease in their electrical characteristics and production yield.

[0006] Therefore, many studies have been conducted to improve the electrical characteristics and production yield of semiconductor devices. Summary of the Invention

[0007] Some example embodiments provide a semiconductor device with increased reliability and improved electrical characteristics, as well as an electronic system including the semiconductor device.

[0008] According to some example embodiments, a semiconductor device may include: a first conductive pattern; a second conductive pattern spaced apart from the first conductive pattern in a first direction; a dielectric pattern between the first and second conductive patterns; a first molded pattern at the same level as the first conductive pattern; a second molded pattern at the same level as the second conductive pattern and spaced apart from the first molded pattern in the first direction; a memory channel structure penetrating the first and second conductive patterns; a first connection contact electrically connected to the first conductive pattern; and a first connection contact dielectric layer surrounding the first connection contact. The dielectric pattern may be between the first and second molded patterns. The first connection contact and the first connection contact dielectric layer may be between the second conductive pattern and the second molded pattern.

[0009] Alternatively or additionally, according to some example embodiments, a semiconductor device may include: a first-side separation structure; a second-side separation structure spaced apart from the first-side separation structure in a first direction; a first conductive pattern, a second conductive pattern, and a molded pattern between the first-side separation structure and the second-side separation structure; a dielectric structure between the first-side separation structure and the second-side separation structure, the dielectric structure penetrating the molded pattern; a memory channel structure penetrating the first conductive pattern; and a first connection contact electrically connected to the first conductive pattern. The first conductive pattern may be between the first-side separation structure and the dielectric structure. The second conductive pattern may be between the second-side separation structure and the dielectric structure. The first conductive pattern and the second conductive pattern may be spaced apart from each other in the first direction. The molded pattern may contact the first conductive pattern and the second conductive pattern. The molded pattern may include: a first portion between the dielectric structure and the first conductive pattern; a second portion between the dielectric structure and the second conductive pattern; and a third portion connecting the first portion and the second portion to each other.

[0010] Alternatively or additionally, according to some example embodiments, an electronic system may include: a motherboard; a semiconductor device on the motherboard; and a controller on the motherboard and electrically connected to the semiconductor device. The semiconductor device may include: a first side separation structure; a second side separation structure spaced apart from the first side separation structure in a first direction; a first conductive pattern, a second conductive pattern, a third conductive pattern, a fourth conductive pattern, a first molded pattern, and a second molded pattern between the first and second side separation structures; a dielectric pattern between the first and third conductive patterns, between the second and fourth conductive patterns, and between the first and second molded patterns; a dielectric structure between the first and second side separation structures, the dielectric structure penetrating the first and second molded structures; a memory channel structure penetrating the first conductive pattern; a first connection contact electrically connected to the first conductive pattern; a first connection contact dielectric layer surrounding the first connection contact; and a second connection contact electrically connected to the third conductive pattern.

[0011] A second connecting contact dielectric layer surrounds the second connecting contact. A first molded pattern may contact a first conductive pattern and a second conductive pattern. A second molded pattern may contact a third conductive pattern and a fourth conductive pattern. A first connecting contact may contact the first conductive pattern and the first molded pattern. The first connecting contact dielectric layer may contact the third conductive pattern and the second molded pattern.

[0012] Alternatively or additionally, according to some example embodiments, a method of manufacturing a semiconductor device is provided, the method comprising: manufacturing peripheral circuitry on and in a substrate; forming a plurality of source layers and a plurality of dummy layers on the peripheral circuitry; forming a plurality of dielectric patterns and a plurality of sacrificial patterns on the plurality of source layers and the plurality of dummy layers; forming a plurality of vias through the plurality of dielectric patterns and the plurality of sacrificial patterns; filling the plurality of vias with sacrificial layers; forming a photoresist layer on the uppermost dielectric pattern of the plurality of dielectric patterns, the photoresist layer defining openings on at least some of the plurality of filled vias; removing at least some of the sacrificial layers; and expanding at least some of the vias from which the sacrificial layers were removed.

[0013] In some example embodiments, expanding at least some of the holes involves isotropically etching the holes.

[0014] In some example embodiments, expansion includes expansion using a wet etching process. Attached Figure Description

[0015] Figure 1A A simplified block diagram illustrating an electronic system including a semiconductor device according to some example embodiments is shown.

[0016] Figure 1B A simplified perspective view is shown illustrating an electronic system including a semiconductor device according to some example embodiments.

[0017] Figure 1C and Figure 1D A simplified cross-sectional view illustrating a semiconductor package according to some example embodiments is shown.

[0018] Figure 2A A plan view illustrating a semiconductor device according to some example embodiments is shown.

[0019] Figure 2B It shows along Figure 2A The cross-sectional view taken by line A1-A1'.

[0020] Figure 2C It shows along Figure 2A The cross-sectional view taken from line A2-A2'.

[0021] Figure 2D It shows along Figure 2A The cross-sectional view taken from line A3-A3'.

[0022] Figure 2E The demonstration shows Figure 2A A magnified view of part Q1.

[0023] Figure 2F The demonstration shows Figure 2BA magnified view of part Q2.

[0024] Figure 2G The demonstration shows Figure 2C A magnified view of part Q3.

[0025] Figure 3A , Figure 3B , Figure 3C , Figure 4A , Figure 4B , Figure 5A , Figure 5B , Figure 6A , Figure 6B , Figure 6C , Figure 7A , Figure 7B , Figure 7C , Figure 8A and Figure 8B Demonstrates manufacturing Figures 2A to 2G A diagram illustrating a method for using a semiconductor device.

[0026] Figure 9 A plan view illustrating a semiconductor device according to some example embodiments is shown.

[0027] Figure 10 and Figure 11 Demonstrates manufacturing Figure 9 A diagram illustrating a method for using a semiconductor device.

[0028] Figure 12 A plan view illustrating a semiconductor device according to some example embodiments is shown.

[0029] Figure 13 Demonstrates manufacturing Figure 12 A plan view of the method for creating a semiconductor device.

[0030] Figure 14 An enlarged plan view illustrating a semiconductor device according to some example embodiments is shown.

[0031] Figure 15 , Figure 16 and Figure 17 Demonstrates manufacturing Figure 14 A plan view of the method for creating a semiconductor device.

[0032] Figure 18A and Figure 18B A cross-sectional view illustrating a semiconductor device according to some example embodiments is shown. Detailed Implementation

[0033] Referring to the accompanying drawings, a semiconductor device and an electronic system including the semiconductor device according to some example embodiments will now be described in detail.

[0034] Figure 1A A simplified block diagram illustrating an electronic system including a semiconductor device according to some example embodiments is shown.

[0035] Reference Figure 1A According to some example embodiments, the electronic system 1000 may include a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100. The electronic system 1000 may be a storage device, may include a storage device, or may be included in a storage device that includes one or more semiconductor devices 1100, and / or, the electronic system 1000 may be an electronic device, may include an electronic device, or may be included in an electronic device that includes a storage device. For example, the electronic system 1000 may be, may include, a solid-state drive (SSD) device, a universal serial bus (USB), a computing system, a medical device, or a communication device, or may be included in, a solid-state drive (SSD) device, a universal serial bus (USB), a computing system, a medical device, or a communication device, each of which includes one or more semiconductor devices 1100.

[0036] Semiconductor device 1100 may be or may include a non-volatile memory device, such as a NAND flash memory device. Semiconductor device 1100 may include a first structure 1100F and a second structure 1100S on the first structure 1100F. In some example embodiments, the first structure 1100F may be disposed on one side of the second structure 1100S. The first structure 1100F may be or may include a peripheral circuit structure, including a decoder circuit 1110, a page buffer 1120, and logic circuitry 1130. The second structure 1100S may be or may include a memory cell structure, including a bit line BL, a common source line CSL, a word line WL, a first gate upper line UL1 and a second gate upper line UL2, a first gate lower line LL1 and a second gate lower line LL2, and a memory cell string CSTR between the bit line BL and the common source line CSL. In some example embodiments, semiconductor device 1100 may have a cell-on-periphery (COP) structure; however, the example embodiments are not limited thereto.

[0037] In the second structure 1100S, each of the memory cell strings CSTRs may include lower transistors LT1 and LT2 adjacent to the common source line CSL, upper transistors UT1 and UT2 adjacent to the bit line BL, and a memory cell transistor MCT disposed between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. The number of lower transistors LT1 and LT2 and / or the number of upper transistors UT1 and UT2 may vary depending on the exemplary embodiment, and may be the same or different.

[0038] In some example embodiments, the upper transistors UT1 and UT2 may include string select transistors, and the lower transistors LT1 and LT2 may include ground select transistors. The lower gate lines LL1 and LL2 may be the gate electrodes of the lower transistors LT1 and LT2, respectively. The word line WL may be the gate electrode of the memory cell transistor MCT, and the upper gate lines UL1 and UL2 may be the gate electrodes of the upper transistors UT1 and UT2, respectively.

[0039] The common source line CSL, the first lower gate line LL1, the second lower gate line LL2, the word line WL, and the first upper gate line UL1 and the second upper gate line UL2 can be electrically connected to the decoder circuit 1110 via a first connection line 1115 extending from the first structure 1100F to the second structure 1100S. The bit line BL can be electrically connected to the page buffer 1120 via a second connection line 1125 extending from the first structure 1100F to the second structure 1100S.

[0040] In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 can perform control operations on at least one of the multiple memory cell transistors (MCTs) to select a memory cell transistor. The logic circuit 1130 can control the decoder circuit 1110 and the page buffer 1120. The semiconductor device 1100 can communicate with the controller 1200 via input / output pads 1101 electrically connected to the logic circuit 1130. The input / output pads 1101 can be electrically connected to the logic circuit 1130 via input / output connection lines 1135 extending from the first structure 1100F to the second structure 1100S.

[0041] The controller 1200 may include a processor 1210, a NAND controller 1220, and a host interface (I / F) 1230. In some example embodiments, the electronic system 1000 may include a plurality of semiconductor devices 1100, and in this case, the controller 1200 may control the plurality of semiconductor devices 1100.

[0042] Processor 1210 can control some or all (e.g., all) operations of electronic system 1000, including controller 1200. Processor 1210 can operate based on firmware (such as acquired firmware, dynamically determined firmware, or alternatively predetermined firmware) and can control NAND controller 1220 to access semiconductor device 1100. NAND controller 1220 may include NAND interface 1221 for processing communication with semiconductor device 1100. NAND interface 1221 can be used to transmit control commands for controlling semiconductor device 1100, data intended to be written to memory cell transistors (MCTs) of semiconductor device 1100, and / or data intended to be read from memory cell transistors (MCTs) of semiconductor device 1100. Host interface 1230 can provide electronic system 1000 with communication with an external host. When a control command is received from an external host via host interface 1230, processor 1210 can control semiconductor device 1100 in response to the control command.

[0043] Figure 1B A simplified perspective view is shown illustrating an electronic system including a semiconductor device according to some example embodiments.

[0044] Reference Figure 1B An electronic system 2000 according to some example embodiments may include a motherboard 2001, a controller 2002 mounted on the motherboard 2001, at least one semiconductor package 2003, and dynamic random access memory (DRAM) 2004. The semiconductor package 2003 and DRAM 2004 may be connected to the controller 2002 via wiring patterns 2005 formed on the motherboard 2001.

[0045] The motherboard 2001 may include a connector 2006, which includes a plurality of pins for connection to an external host. The number and / or arrangement of the plurality of pins on the connector 2006 may vary based on the communication interface between the electronic system 2000 and the external host. In some example embodiments, the electronic system 2000 may communicate with the external host through one or more interfaces, such as one or more of Universal Serial Bus (USB), High-Speed ​​Peripheral Component Interconnect (PIC-Express), Serial Advanced Technology Attachment (SATA), and / or M-PHY (UFS) for Universal Flash Memory. In some example embodiments, the electronic system 2000 may operate using power supplied from the external host via the connector 2006. The electronic system 2000 may also include a power management integrated circuit (PMIC) through which power supplied from the external host is distributed to the controller 2002 and the semiconductor package 2003.

[0046] The controller 2002 can write data to the semiconductor package 2003, read data from the semiconductor package 2003, and / or increase the operating speed of the electronic system 2000.

[0047] DRAM 2004 may be or may include a buffer memory that reduces the speed difference between an external host and the semiconductor package 2003, which serves as data storage space. The DRAM 2004 included in the electronic system 2000 can operate as a high-speed buffer memory and can provide space for temporary data storage under the control of the semiconductor package 2003. When the electronic system 2000 includes DRAM 2004, the controller 2002 may include not only a NAND controller for controlling the semiconductor package 2003 but also a DRAM controller for controlling the DRAM 2004; the example embodiments are not limited thereto.

[0048] Semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may be or may include a semiconductor package having a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a package substrate 2100, semiconductor chips 2200 on the package substrate 2100, an adhesion layer 2300 disposed on the bottom surface of the semiconductor chip 2200, a connection structure 2400 electrically connecting the semiconductor chip 2200 to the package substrate 2100, and a molding layer 2500 on the package substrate 2100 and covering the semiconductor chip 2200 and the connection structure 2400.

[0049] The package substrate 2100 may be or may include an integrated circuit board, which includes pads 2130 on the package. Each of the semiconductor chips 2200 may include one or more input / output pads 2210. The input / output pads 2210 may correspond to... Figure 1A The input / output pads 1101. Each of the semiconductor chips 2200 may include a gate stack structure 3210 and a memory channel structure 3220. Each of the semiconductor chips 2200 may include a semiconductor device, which will be discussed below.

[0050] In some example embodiments, the connection structure 2400 may be or may include bonding wires that electrically connect the input / output pads 2210 to the on-package pads 2130. Therefore, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other via wire bonding and may be electrically connected to the on-package pads 2130 of the package substrate 2100. In some example embodiments, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, instead of or in addition to the connection structure 2400 or bonding wires, the semiconductor chips 2200 may be electrically connected to each other using through-silicon vias (TSVs).

[0051] In some example embodiments, the controller 2002 and the semiconductor chip 2200 may be included in a single package. In some example embodiments, the controller 2002 and the semiconductor chip 2200 may be mounted on a separate insert substrate other than the motherboard 2001, and may be connected to each other via interconnects disposed in the insert substrate.

[0052] Figure 1C and Figure 1D A simplified cross-sectional view illustrating a semiconductor package according to some example embodiments is shown. Figure 1C and Figure 1D Each depicted Figure 1B The example of semiconductor package 2003 shown in the figure conceptually demonstrates along... Figure 1B The cross-section of the semiconductor package 2003 shown is taken along line I-I'.

[0053] Reference Figure 1C The printed circuit board can be used as the package substrate 2100 of the semiconductor package 2003. The package substrate 2100 may include a package substrate body 2120 and package pads disposed on the top surface of the package substrate body 2120 (see See). Figure 1B The upper pad 2130 (2130) is disposed on or exposed on the bottom surface of the package substrate body 2120, and an internal line 2135 is located in the package substrate body 2120 and electrically connects the upper pad 2130 to the lower pad 2125. The number and / or arrangement of the internal lines 2135 are not limited to the features described in the figures. The upper pad 2130 may be electrically connected to a connection structure (see Figure 2130). Figure 1B (2400). The lower pad 2125 can be connected via conductive connector 2800 to, for example, Figure 1B Wiring pattern 2005 on the motherboard 2001 of the electronic system 2000 shown.

[0054] Each of the semiconductor chips 2200 may include a semiconductor substrate 3010, and may also include a first structure 3100 and a second structure 3200 sequentially stacked on the semiconductor substrate 3010. For different semiconductor chips 2200, the thickness and / or material composition of the first structure 3100 may be the same, or at least one of the thicknesses and / or material compositions of at least one of the semiconductor chips 2200 may be different from the other semiconductor chips 2200. The first structure 3100 may include a peripheral circuit region including peripheral wiring lines 3110. The second structure 3200 may include a common source line 3205, a gate stack structure 3210 on the common source line 3205, a memory channel structure 3220 penetrating the gate stack structure 3210, a bit line 3240 electrically connected to the memory channel structure 3220, and a corresponding word line electrically connected to the gate stack structure 3210 (see [link to relevant documentation]). Figure 1A Gate contact plug 3235 of WL).

[0055] Each of the semiconductor chips 2200 may include peripheral wiring 3110 electrically connected to the first structure 3100 and extending into the second structure 3200 via wiring 3245. The number and / or arrangement of the peripheral wiring 3110 are not limited to the features described in the figures. The via wiring 3245 may be disposed outside the gate stack structure 3210. In some example embodiments, the via wiring 3245 may penetrate the gate stack structure 3210. Each of the semiconductor chips 2200 may also include input / output pads (see...). Figure 1B (of 2210).

[0056] Reference Figure 1D In the semiconductor package 2003A, each of the semiconductor chips 2200b may include a semiconductor substrate 4010, a first structure 4100 on the semiconductor substrate 4010, and a second structure 4200 disposed on the first structure 4100 and bonded thereto to the wafer.

[0057] The first structure 4100 may include a peripheral circuit region, which includes a peripheral wiring line 4110 and a first junction structure 4150. The second structure 4200 may include a common source line 4205, a gate stack structure 4210 between the common source line 4205 and the first structure 4100, a memory channel structure 4220 penetrating the gate stack structure 4210, a bit line 4240 electrically connected to the memory channel structure 4220, and a corresponding word line electrically connected to the gate stack structure 4210 (see [link to relevant documentation]). Figure 1AThe gate contact plug 4235 and the second bonding structure 4250 of the WL) are provided. For example, the second bonding structure 4250 can be electrically connected to the corresponding memory channel structure 4220 via a bit line 4240 of the memory channel structure 4220. The first bonding structure 4150 of the first structure 4100 can be bonded to the second bonding structure 4250 of the second structure 4200. The first bonding structure 4150 and the second bonding structure 4250 can have their bonding portions formed of, for example, copper (Cu). Each or at least one of the semiconductor chips 2200b may also include input / output pads (see Figure 1B (of 2210).

[0058] Figure 1C Semiconductor chip 2200 and / or Figure 1D The semiconductor chip 2200b can be connected via a connection structure similar in shape to a bonding wire (see...). Figure 1B The 2400 chips are electrically connected to each other. In some example embodiments, the semiconductor chips (such as, ) in a semiconductor package are electrically connected to each other. Figure 1C Semiconductor chip 2200 and Figure 1D The semiconductor chip 2200b can be electrically connected via a connection structure including a through electrode (TSV).

[0059] Figure 2A A plan view illustrating a semiconductor device according to some example embodiments is shown. Figure 2B It shows along Figure 2A The cross-sectional view taken by line A1-A1'. Figure 2C It shows along Figure 2A The cross-sectional view taken from line A2-A2'. Figure 2D It shows along Figure 2A The cross-sectional view taken from line A3-A3'. Figure 2E The demonstration shows Figure 2A A magnified view of part Q1. Figure 2F The demonstration shows Figure 2B A magnified view of part Q2. Figure 2G The demonstration shows Figure 2C A magnified view of part Q3.

[0060] Reference Figure 2A , Figure 2B , Figure 2C and Figure 2D The semiconductor device may include a peripheral circuit structure PST and a memory cell structure on the peripheral circuit structure PST. In some example embodiments, the semiconductor device may have a peripheral-on-cell or peripheral-on-top-cell (COP) structure; however, the example embodiments are not limited thereto. The memory cell structure may include a source structure SST and a gate stack structure GST on the source structure SST.

[0061] The peripheral circuit structure PST may include a substrate 100. Substrate 100 may be or may include one or more of a semiconductor substrate, a dielectric substrate, or a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate may be or may include, for example, a silicon substrate and / or a germanium substrate. Substrate 100 may have a plate shape extending along a plane defined in a first direction D1 and a second direction D2. The first direction D1 and the second direction D2 may intersect each other. For example, the first direction D1 and the second direction D2 may be horizontal directions orthogonal to each other.

[0062] The peripheral circuit structure PST may include a peripheral circuit dielectric layer 120 on the substrate 100. The peripheral circuit dielectric layer 120 may include a dielectric material. In some example embodiments, the peripheral circuit dielectric layer 120 may be or may include a multi-dielectric layer comprising multiple dielectric layers.

[0063] Substrate 100 may have device isolation layer 103 therein. Device isolation layer 103 may include a dielectric material. Peripheral circuit structure PST may also include transistor 110, such as, but not limited to, planar transistors. Transistor 110 may be disposed between substrate 100 and peripheral circuit dielectric layer 120. Transistor 110 may include source / drain regions, gate dielectric layer, and gate electrode. Gate electrode may extend in a direction such as a second direction D2 and / or in a direction such as a first direction D1; the exemplary embodiment is not limited thereto.

[0064] The peripheral circuit structure PST may further include peripheral contacts 105 and peripheral conductive lines 107. Peripheral contacts 105 may be connected to transistor 110. Peripheral conductive lines 107 may be connected to peripheral contacts 105. Peripheral contacts 105 and peripheral conductive lines 107 may include conductive materials. The number and / or arrangement of peripheral contacts 105 and / or peripheral conductive lines 107 are not limited to the features described in the figures.

[0065] The memory cell structure may include a source structure SST, a gate stack structure GST, a memory channel structure CH, a first cover dielectric layer 131, a second cover dielectric layer 132, a first side separation structure SDS1, a second side separation structure SDS2, a central separation structure CDS, a dielectric structure IS, a first connection contact structure CS1, a second connection contact structure CS2, a bit line contact BC, a bit line BL, a dummy structure DH, a conductive line contact SC, and a conductive line CL.

[0066] The source structure SST may include a cell region CR and an extension region ER. The cell region CR and the extension region ER can be distinguished from a planar view defined by a first direction D1 and a second direction D2.

[0067] The source structure SST may include several source layers and dummy layers, such as the first source layer SL1 on the peripheral circuit structure PST, the second source layer SL2 on the first source layer SL1, the first dummy layer DL1, the second dummy layer DL2 and the third dummy layer DL3 on the first source layer SL1, and the third source layer SL3 on the second source layer SL2 and the third dummy layer DL3.

[0068] The first source layer SL1, the second source layer SL2, and the third source layer SL3 may comprise conductive materials, such as the same or different conductive materials. For example, at least one of the first source layer SL1, the second source layer SL2, and the third source layer SL3 may comprise polysilicon, such as doped polysilicon. The second source layer SL2 may be disposed on the cell region CR. The second source layer SL2 may be a common source line.

[0069] The first dummy layer DL1, the second dummy layer DL2, and the third dummy layer DL3 may be sequentially disposed on the first source layer SL1 along a third direction D3. The first dummy layer DL1, the second dummy layer DL2, and the third dummy layer DL3 may be disposed on the extension region ER. The first dummy layer DL1, the second dummy layer DL2, and the third dummy layer DL3 may be located at the same level as the second source layer SL2. The first dummy layer DL1, the second dummy layer DL2, and the third dummy layer DL3 may include a dielectric material. In some example embodiments, the first dummy layer DL1 and the third dummy layer DL3 may include the same dielectric material, and the second dummy layer DL2 may include a dielectric material different from the dielectric materials of the first dummy layer DL1 and the third dummy layer DL3, for example, it may include a dielectric material with a different dielectric constant and / or a different etch rate. For example, the second dummy layer DL2 may include a nitride, while the first dummy layer DL1 and the third dummy layer DL3 may include oxides.

[0070] The gate stack structure (GST) can be disposed on the source structure (SST). In some example embodiments, the number of gate stack structures (GST) can be two or more.

[0071] The gate stack structure GST may include dielectric patterns IP and conductive patterns CP alternately stacked along a third direction D3. The third direction D3 may intersect with the first direction D1 and the second direction D2. For example, the third direction D3 may be a vertical direction perpendicular to the first direction D1 and the second direction D2.

[0072] The gate stack structure GST may also include a molded pattern MP. The molded patterns MP may overlap each other on the third direction D3. The molded patterns MP may be spaced apart from each other on the third direction D3. The molded patterns MP and the dielectric pattern IP may be stacked alternately along the third direction D3. The molded pattern MP may be located at the same level as the conductive pattern CP. As used herein, the term "level" may refer to the distance from the top surface of the substrate 100 on the third direction D3. The molded pattern MP may be in contact with the conductive pattern CP.

[0073] The dielectric pattern IP may include a dielectric material. For example, the dielectric pattern IP may include an oxide. The conductive pattern CP may include a conductive material. For example, the conductive pattern CP may include tungsten. The molded pattern MP may include a dielectric material different from the dielectric material of the dielectric pattern IP; for example, it may include a dielectric material with a different dielectric constant and / or a different etch rate. For example, the molded pattern MP may include a nitride.

[0074] The memory channel structure CH can extend on the third source layer D3 to penetrate the conductive pattern CP and dielectric pattern IP of the gate stack structure GST. The memory channel structure CH can penetrate the third source layer SL3 and the second source layer SL2. Each of the memory channel structures CH may include a dielectric capping layer 189, a channel layer 187 surrounding the dielectric capping layer 189, and a memory layer 183 surrounding the channel layer 187. The memory channel structure CH can be disposed on the cell region CR.

[0075] The dielectric capping layer 189 may include a dielectric material. For example, the dielectric capping layer 189 may include an oxide. The channel layer 187 may include a conductive material. For example, the channel layer 187 may include polysilicon, such as doped polysilicon. The channel layer 187 may be electrically connected to the second source layer SL2. The second source layer SL2 may penetrate the memory layer 183 to connect to the channel layer 187.

[0076] Memory layer 183 can store data. In some example embodiments, memory layer 183 may include a tunnel dielectric layer surrounding channel layer 187, a data storage layer surrounding the tunnel dielectric layer, and a barrier layer surrounding the data storage layer. The tunnel dielectric layer and the barrier layer may include, for example, oxides (such as silicon oxide) and may or may not include nitrides. The data storage layer may include, for example, nitrides (such as silicon nitride) and may or may not include oxides.

[0077] Each of the memory channel structures CH may further include bit line pads 185 disposed on the channel layer 187. The bit line pads 185 may include conductive materials. For example, the bit line pads 185 may include polysilicon (such as doped polysilicon) and / or metal.

[0078] The dummy structure DH can extend along the third direction D3 to penetrate the conductive pattern CP and dielectric pattern IP of the gate stack structure GST. The dummy structure DH can be disposed on the extension region ER. The dummy structure DH can include a dielectric material. In some example embodiments, the dummy structure DH can have a structure similar to that of the memory channel structure CH.

[0079] A first overlay dielectric layer 131 may be disposed on the gate stack structure GST and the memory channel structure CH. The first overlay dielectric layer 131 may include a dielectric material. A second overlay dielectric layer 132 may be disposed on the first overlay dielectric layer 131. The second overlay dielectric layer 132 may include a dielectric material.

[0080] The first-side separation structure SDS1, the second-side separation structure SDS2, the central separation structure CDS, and the dielectric structure IS can penetrate the gate stack structure GST along the third-side direction D3. The first-side separation structure SDS1, the second-side separation structure SDS2, the central separation structure CDS, and the dielectric structure IS can pass through the conductive pattern CP and the dielectric pattern IP along the third-side direction D3. The dielectric structure IS can penetrate the molded pattern MP along the third-side direction D3.

[0081] The first side separation structure SDS1, the second side separation structure SDS2, the central separation structure CDS, and the dielectric structure IS may extend in the second direction D2. The dielectric material may be included in the first side separation structure SDS1, the second side separation structure SDS2, the central separation structure CDS, and the dielectric structure IS. In some example embodiments, the dielectric structure IS may include the same dielectric material as the dielectric material of the dielectric pattern IP. For example, the dielectric structure IS and the dielectric pattern IP may include oxides. Alternatively or additionally, in some example embodiments, the dielectric structure IS may include a dielectric material different from the dielectric material of the dielectric pattern IP and the molded pattern MP. For example, the dielectric structure IS may include a material that has etch selectivity (e.g., slower etch rate and / or faster etch rate) relative to the materials included in the dielectric pattern IP and the molded pattern MP.

[0082] The first side separation structure SDS1 and the second side separation structure SDS2 may be spaced apart from each other in the first direction D1. The first side separation structure SDS1 and the second side separation structure SDS2 may be configured to have a central separation structure CDS, a dielectric structure IS, a conductive pattern CP, a dielectric pattern IP, and a molded pattern MP between them.

[0083] In some example embodiments, the region between the first side separation structure SDS1 and the central separation structure CDS can be defined as the first block of the semiconductor device, and the region between the central separation structure CDS and the second side separation structure SDS2 can be defined as the second block of the semiconductor device.

[0084] In some example embodiments, the region between the first-side separation structure SDS1 and the second-side separation structure SDS2 can be defined as a block of the semiconductor device.

[0085] In some example embodiments, the semiconductor device may include a first side separation structure, a second side separation structure, and a third side separation structure arranged sequentially along a first direction D1. The semiconductor device may include a first central separation structure between the first and second side separation structures, a second central separation structure between the second and third side separation structures, a first dielectric structure between the first and second side separation structures, and a second dielectric structure between the second and third side separation structures. The region between the first and third side separation structures may be positioned as a block of the semiconductor device.

[0086] In some example embodiments, the semiconductor device may include a first side separation structure, a second side separation structure, a third side separation structure, and a fourth side separation structure arranged sequentially along a first direction D1. The semiconductor device may include a first central separation structure between the first and second side separation structures, a second central separation structure between the second and third side separation structures, a third central separation structure between the third and fourth side separation structures, a first dielectric structure between the first and second side separation structures, a second dielectric structure between the second and third side separation structures, and a third dielectric structure between the third and fourth side separation structures. The region between the first and fourth side separation structures may be defined as a block of the semiconductor device. A bit line contact BC may be connected to a memory channel structure CH. The bit line contact BC may penetrate a first overlay dielectric layer 131. A bit line BL may be disposed on the bit line contact BC. The bit line BL may be disposed in a second overlay dielectric layer 132.

[0087] The conductive line contact SC can be connected to the first connecting contact structure CS1 and the second connecting contact structure CS2. The conductive line contact SC can penetrate the first covering dielectric layer 131. The conductive line CL can be disposed on the conductive line contact SC. The conductive line CL can be disposed in the second covering dielectric layer 132. Conductive material can be included in the bit line contact BC, bit line BL, conductive line contact SC, and conductive line CL.

[0088] The conductive pattern CP may include a first conductive pattern CP1, a second conductive pattern CP2, a third conductive pattern CP3, and a fourth conductive pattern CP4. The first conductive pattern CP1 and the second conductive pattern CP2 may overlap each other in the third direction D3. The first conductive pattern CP1 and the second conductive pattern CP2 may be spaced apart from each other in the third direction D3. The second conductive pattern CP2 may be located at a level higher than the level of the first conductive pattern CP1. The third conductive pattern CP3 and the fourth conductive pattern CP4 may overlap each other in the third direction D3. The third conductive pattern CP3 and the fourth conductive pattern CP4 may be spaced apart from each other in the third direction D3. The fourth conductive pattern CP4 may be located at a level higher than the level of the third conductive pattern CP3. The first conductive pattern CP1 and the third conductive pattern CP3 may be located at the same level. The second conductive pattern CP2 and the fourth conductive pattern CP4 may be located at the same level.

[0089] The memory channel structure CH can penetrate the first conductive pattern CP1 and the second conductive pattern CP2 in the third direction D3, or it can penetrate the third conductive pattern CP3 and the fourth conductive pattern CP4 in the third direction D3.

[0090] The molded pattern MP may include a first molded pattern MP1 and a second molded pattern MP2. The second molded pattern MP2 may be located at a higher level than the first molded pattern MP1. The first molded pattern MP1 may be located at the same level as the first conductive pattern CP1 and the third conductive pattern CP3. The second molded pattern MP2 may be located at the same level as the second conductive pattern CP2 and the fourth conductive pattern CP4. The first molded pattern MP1 may be in contact with the first conductive pattern CP1 and the third conductive pattern CP3. The second molded pattern MP2 may be in contact with the second conductive pattern CP2 and the fourth conductive pattern CP4.

[0091] The dielectric pattern IP can be positioned between the first conductive pattern CP1 and the second conductive pattern CP2. The dielectric pattern IP can be positioned between the third conductive pattern CP3 and the fourth conductive pattern CP4. The dielectric pattern IP can be positioned between the first molded pattern MP1 and the second molded pattern MP2.

[0092] The first conductive pattern CP1 and the second conductive pattern CP2 can be disposed between the first side separation structure SDS1 and the dielectric structure IS. The third conductive pattern CP3 and the fourth conductive pattern CP4 can be disposed between the second side separation structure SDS2 and the dielectric structure IS.

[0093] The first conductive pattern CP1 and the third conductive pattern CP3 may be spaced apart from each other in the first direction D1. The second conductive pattern CP2 and the fourth conductive pattern CP4 may be spaced apart from each other in the first direction D1. The central separation structure CDS and the dielectric structure IS may be disposed between the first conductive pattern CP1 and the third conductive pattern CP3, and between the second conductive pattern CP2 and the fourth conductive pattern CP4.

[0094] The memory channel structure CH can penetrate the first conductive pattern CP1 and the second conductive pattern CP2 in the third direction D3, or it can penetrate the third conductive pattern CP3 and the fourth conductive pattern CP4 in the third direction D3.

[0095] The first connection contact structure CS1 may include a first connection contact CC1 and a first connection contact dielectric layer CI1. The first connection contact dielectric layer CI1 may surround the first connection contact CC1. The first connection contact CC1 may include a conductive material. The first connection contact dielectric layer CI1 may include a dielectric material.

[0096] Each of the first conductive pattern CP1 and the third conductive pattern CP3 can be electrically connected to the first connecting contact structure CS1. Each of the first conductive pattern CP1 and the third conductive pattern CP3 can be electrically connected to the first connecting contact CC1. The first connecting contact structure CS1 can be electrically connected to the first conductive pattern CP1, the third conductive pattern CP3, and a conductive pattern CP located at a lower level than the first conductive pattern CP1 and the third conductive pattern CP3. The first connecting contact CC1 can be electrically connected to the first conductive pattern CP1, the third conductive pattern CP3, and a conductive pattern CP located at a lower level than the first conductive pattern CP1 and the third conductive pattern CP3.

[0097] The first connecting contact structure CS1 can contact at least a portion of the molded pattern MP and at least a portion of the conductive pattern CP. The first connecting contact dielectric layer CI1 can contact at least a portion of the molded pattern MP and at least a portion of the conductive pattern CP. The first connecting contact CC1 can contact the molded pattern MP and the conductive pattern CP.

[0098] A first connecting contact structure CS1 can be disposed between the molded pattern MP and the conductive pattern CP. For example, the first connecting contact structure CS1 electrically connected to the first conductive pattern CP1 can be disposed between the second molded pattern MP2 and the second conductive pattern CP2. A first connecting contact dielectric layer CI1 can be disposed between the molded pattern MP and the conductive pattern CP. For example, the first connecting contact dielectric layer CI1 electrically connected to the first connecting contact structure CS1 can be disposed between the second molded pattern MP2 and the second conductive pattern CP2. A first connecting contact CC1 can be disposed between the molded pattern MP and the conductive pattern CP. For example, the first connecting contact CC1 electrically connected to the first connecting contact structure CS1 can be disposed between the second molded pattern MP2 and the second conductive pattern CP2.

[0099] The second connection contact structure CS2 may include a second connection contact CC2 and a second connection contact dielectric layer CI2. The second connection contact dielectric layer CI2 may surround the second connection contact CC2. The second connection contact CC2 may include a conductive material. The second connection contact dielectric layer CI2 may include a dielectric material.

[0100] Each of the second conductive pattern CP2 and the fourth conductive pattern CP4 can be electrically connected to the second connecting contact structure CS2. Each of the second conductive pattern CP2 and the fourth conductive pattern CP4 can be electrically connected to the second connecting contact CC2. The second connecting contact structure CS2 can be correspondingly connected to the conductive pattern CP located at a level higher than the first conductive pattern CP1 and the third conductive pattern CP3. The second connecting contact CC2 can be correspondingly connected to the conductive pattern CP located at a level higher than the first conductive pattern CP1 and the third conductive pattern CP3.

[0101] When in such Figure 2A When viewed in the plan view shown, the second connecting contact structure CS2 can be surrounded by a conductive pattern CP. When in... Figure 2A When viewed in the plan view shown, the second connecting contact dielectric layer CI2 can be surrounded by the conductive pattern CP. The second connecting contact CC2 can contact the conductive pattern CP. When in... Figure 2A When viewed in a plan view, the central separation structure CDS and the dielectric structure IS can have a ribbed profile; the example embodiment is not limited thereto.

[0102] The length of the second connecting contact CC2 on the third direction D3 can be less than the length of the first connecting contact CC1 on the third direction D3.

[0103] Reference Figure 2E , Figure 2F and Figure 2GThe conductive pattern CP may have a first sidewall CP_S1 that contacts the central separation structure CDS, a second sidewall CP_S2 that contacts the dielectric structure IS, and a third sidewall CP_S3 that contacts the molded pattern MP.

[0104] The dielectric structure IS may have a first sidewall IS_S1 that contacts the second sidewall CP_S2 of the conductive pattern CP and a second sidewall IS_S2 that contacts the molded pattern MP.

[0105] The molded pattern MP may have a first sidewall MP_S1 and a second sidewall MP_S2. The first sidewall MP_S1 and the second sidewall MP_S2 of the molded pattern MP may contact a third sidewall CP_S3 of a conductive pattern CP that is different from each other. The molded pattern MP may have a third sidewall MP_S3 and a fourth sidewall MP_S4. Each of the third sidewall MP_S3 and the fourth sidewall MP_S4 of the molded pattern MP may contact a second sidewall IS_S2 of the dielectric structure IS.

[0106] The first connecting contact structure CS1 may have a first sidewall CS1_S1 and a second sidewall CS1_S2. The first sidewall CS1_S1 of the first connecting contact structure CS1 may be in contact with at least one conductive pattern CP. The second sidewall CS1_S2 of the first connecting contact structure CS1 may be in contact with at least one molded pattern MP. The first sidewall CS1_S1 and the second sidewall CS1_S2 of the first connecting contact structure CS1 may be the first sidewall and the second sidewall of the first connecting contact dielectric layer CI 1.

[0107] The second conductive pattern CP2 may have a surface CP2_O1 that contacts the first sidewall CS1_S1 of the first connection contact structure CS1 electrically connected to the first conductive pattern CP1. The second molded pattern MP2 may have a surface MP2_O1 that contacts the second sidewall CS1_S2 of the first connection contact structure CS1 electrically connected to the first conductive pattern CP1.

[0108] The bottom surface CS1_L of the first connecting contact structure CS1 may include the bottom surface CC1_L of the first connecting contact CC1 and the bottom surface CI1_L of the first connecting contact dielectric layer CI1. The bottom surface CS1_L of the first connecting contact structure CS1 may be in contact with the conductive pattern CP and the molded pattern MP.

[0109] The first conductive pattern CP1 may have a first surface CP1_O1 that contacts a first sidewall CS1_S1 of a first connection contact structure CS1 electrically connected to the first conductive pattern CP1. The first conductive pattern CP1 may have a second surface CP1_O2 that contacts a bottom surface CS1_L of the first connection contact structure CS1 electrically connected to the first conductive pattern CP1.

[0110] The first molded pattern MP1 may have a first surface MP1_O1 that contacts the second sidewall CS1_S2 of the first connection contact structure CS1 electrically connected to the first conductive pattern CP1. The first molded pattern MP1 may have a second surface MP1_O2 that contacts the bottom surface CS1_L of the first connection contact structure CS1 electrically connected to the first conductive pattern CP1.

[0111] The first surface MP1_O1 of the first molded pattern MP1 can contact the second sidewall CS1_S2 of the first connecting contact dielectric layer CI1 of the first connecting contact structure CS1 electrically connected to the first conductive pattern CP1.

[0112] The second surface MP1_O2 of the first molded pattern MP1 can contact the bottom surface CC1_L of the first connecting contact CC1 of the first connecting contact structure CS1 electrically connected to the first conductive pattern CP1 and the bottom surface CI1_L of the first connecting contact dielectric layer CI1.

[0113] The first surface CP1_O1 of the first conductive pattern CP1 can contact the first sidewall CS1_S1 of the first connecting contact dielectric layer CI1 of the first connecting contact structure CS1 electrically connected to the first conductive pattern CP1.

[0114] The second surface CP1_O2 of the first conductive pattern CP1 can contact the bottom surface CC1_L of the first connecting contact CC1 of the first connecting contact structure CS1 electrically connected to the first conductive pattern CP1 and the bottom surface CI1_L of the first connecting contact dielectric layer CI1.

[0115] The first surface MP1_O1 of the first molded pattern MP1 can connect the second surface MP1_O2 of the first molded pattern MP1 to the top surface of the first molded pattern MP1. The first surface CP1_O1 of the first conductive pattern CP1 can connect the second surface CP1_O2 of the first conductive pattern CP1 to the top surface of the first conductive pattern CP1. The second surface MP1_O2 of the first molded pattern MP1 can be coplanar with the second surface CP1_O2 of the first conductive pattern CP1.

[0116] The third conductive pattern CP3 may include a first overlapping portion CP3_OV on the third-direction D3 that overlaps with the first connecting contact CC1 of the first connecting contact structure CS1 electrically connected to the third conductive pattern CP3. The first molded pattern MP1 may include a second overlapping portion MP1_OV on the third-direction D3 that overlaps with the first connecting contact CC1 of the first connecting contact structure CS1 electrically connected to the third conductive pattern CP3. The first overlapping portion CP3_OV and the second overlapping portion MP1_OV may be in contact with each other.

[0117] The first conductive pattern CP1 may include an overlapping portion on the third direction D3 that overlaps or at least partially overlaps with the first connecting contact CC1 of the first connecting contact structure CS1 electrically connected to the first conductive pattern CP1.

[0118] The molded pattern MP includes a first portion 22, a second portion 23, and a third portion 21. Each of the first portion 22 and the second portion 23 can be disposed between a dielectric structure IS and a conductive pattern CP. For example, the first portion 22 of the second molded pattern MP2 can be disposed between the second conductive pattern CP2 and the dielectric structure IS, and the second portion 23 of the second molded pattern MP2 can be disposed between a fourth conductive pattern CP4 and the dielectric structure IS. The third portion 21 can connect the first portion 22 and the second portion 23 to each other. The dielectric structure IS can be disposed between the first portion 22 and the second portion 23.

[0119] In some example embodiments, the first connection contact CC1, which is electrically connected to the first connection contact structure CS1 of the first conductive pattern CP1, can contact the first portion 22 of the first molded pattern MP1.

[0120] The first portion 22 of the second molded pattern MP2 may have a sidewall that contacts the second conductive pattern CP2. The second portion 23 of the second molded pattern MP2 may have a sidewall that contacts the fourth conductive pattern CP4. The distance L1 between the sidewalls of the first portion 22 and the second portion 23 of the second molded pattern MP2 in the first direction D1 may decrease as the distance from the memory channel structure CH or the central separation structure CDS decreases.

[0121] The central separation structure CDS may include a base 11 and a protrusion 12. The base 11 may extend in a third direction D3. The protrusion 12 may protrude in a first direction D1 or in a direction opposite to that of the base 11.

[0122] The protrusion 12 may have a sidewall 12_S that contacts the first sidewall CP_S1 of the conductive pattern CP, a top surface 12_U that contacts the bottom surface of the dielectric pattern IP, and a bottom surface 12_L that contacts the top surface of the dielectric pattern IP. The base 11 may have a sidewall 11_S that contacts the sidewall IP_S of the dielectric pattern IP. The sidewall 11_S of the base 11 may be disposed between protrusions 12 that are adjacent to each other along the third direction D3. The sidewall 11_S of the base 11 may connect the top surface 12_U and the bottom surface 12_L of the protrusions 12 that are adjacent to each other in the third direction D3.

[0123] Similar to the central separation structure CDS, each of the first side separation structure SDS1 and the second side separation structure SDS2 may include a base and a protrusion.

[0124] The first sidewall IS_S1 and the second sidewall IS_S2 of the dielectric structure IS can be flat. The lengths of the first sidewall IS_S1 and the second sidewall IS_S2 of the dielectric structure IS in the third direction D3 can be greater than the lengths of the sidewall 11_S of the base 11 in the third direction D3 and the lengths of the sidewall 12_S of each of the protrusions 12 in the third direction D3.

[0125] The maximum width W1 of the central separation structure CDS in the first direction D1 can be greater than the maximum width W2 of the dielectric structure IS in the first direction D1. The maximum width W1 of the central separation structure CDS in the first direction D1 can be, or can correspond to, the width between the sidewalls 12_S of the protrusion portion 12 in the first direction D1. The maximum width of each of the first side separation structure SDS1 and the second side separation structure SDS2 in the first direction D1 can be greater than the maximum width W2 of the dielectric structure IS in the first direction D1.

[0126] The dielectric structure IS may include a first dielectric portion 31 in contact with the molded pattern MP, a second dielectric portion 32 in contact with the conductive pattern CP, and a third dielectric portion 33 in contact with the central separation structure CDS. The dielectric structure IS may have a third sidewall IS_S3 in contact with the central separation structure CDS. The maximum width of the third dielectric portion 33 in the first direction D1 may be smaller than the maximum width of the first dielectric portion 31 in the first direction D1 and the maximum width W2 of the second dielectric portion 32 in the first direction D1.

[0127] In a semiconductor device according to some example embodiments, a molded pattern MP can support (e.g., can physically support) a dielectric pattern IP. Therefore, the dielectric pattern IP can be stably supported, and the stability of the semiconductor device can be improved.

[0128] Because the dielectric pattern IP can be supported more stably, the number of dummy structures DH can be reduced. Reducing the number of dummy structures DH can prevent or reduce interference between the dummy structures DH and the first connection contact structure CS1, and the first connection contact structure CS1 can be formed large enough to have a relatively large length.

[0129] Figure 3A , Figure 3B , Figure 3C , Figure 4A , Figure 4B , Figure 5A , Figure 5B , Figure 6A , Figure 6B , Figure 6C , Figure 7A , Figure 7B , Figure 7C , Figure 8A and Figure 8B Demonstrates manufacturing Figures 2A to 2G A schematic diagram of a method for using a semiconductor device, as depicted in the diagram.

[0130] Reference Figure 3A , Figure 3B and Figure 3C A device isolation layer 103 and a transistor 110 may be formed on the substrate 100. A peripheral circuit dielectric layer 120 may be formed on the substrate 100. Peripheral contacts 105 and peripheral conductive lines 107 may be formed in the peripheral circuit dielectric layer 120.

[0131] A first source layer SL1, a first dummy layer DL1, a second dummy layer DL2, a third dummy layer DL3, and a third source layer SL3 can be sequentially formed on the peripheral circuit dielectric layer 120.

[0132] Dielectric pattern IP and sacrificial pattern SP can be alternately formed on the third source layer SL3. The sacrificial pattern SP can include a dielectric material that has etch selectivity relative to the material included in the dielectric pattern IP. For example, the sacrificial pattern SP can include a nitride, and the dielectric pattern IP can include an oxide.

[0133] It can form a memory channel structure CH, a dummy structure DH, a first sacrificial pillar 201, a second sacrificial pillar 202, a third sacrificial pillar 203 and a fourth sacrificial pillar 204.

[0134] The formation of the memory channel structure CH, the dummy structure DH, the first sacrificial pillar 201, the second sacrificial pillar 202, the third sacrificial pillar 203, and the fourth sacrificial pillar 204 may include forming channel vias, dummy vias, a first via, a second via, a third via, and a fourth via; forming the first sacrificial pillar 201 in the first via; forming the second sacrificial pillar 202 in the second via; forming the third sacrificial pillar 203 in the third via; forming the fourth sacrificial pillar 204 in the fourth via; forming the dummy structure DH in the dummy via; and forming the memory channel structure CH in the channel via. In some example embodiments, the formation of vias may be based on or may include an etching process, such as, but not limited to, wet etching and / or dry etching processes. In some example embodiments, the formation of pillars may be based on or may include a filling process, such as a deposition process such as one or more of chemical vapor deposition (CVD) and physical vapor deposition (PVD); the example embodiments are not limited thereto. The first sacrificial pillar 201, the second sacrificial pillar 202, the third sacrificial pillar 203, and the fourth sacrificial pillar 204 may have etch selectivity relative to the dielectric pattern IP and the sacrificial pattern SP. For example, the first sacrificial pillar 201, the second sacrificial pillar 202, the third sacrificial pillar 203, and the fourth sacrificial pillar 204 may comprise metal or silicon.

[0135] In some example embodiments, the via, dummy via, first via, second via, third via, and fourth via can be formed simultaneously with each other. In some example embodiments, forming a memory channel structure CH in a via may include forming a channel sacrificial pillar in the via, removing the channel sacrificial pillar to open the via, and forming the memory channel structure CH in the opened via. In this case, the channel sacrificial pillar can be formed simultaneously with the first sacrificial pillar 201, the second sacrificial pillar 202, the third sacrificial pillar 203, and the fourth sacrificial pillar 204. In some example embodiments, forming a dummy structure DH may include forming a dummy sacrificial pillar in a dummy via, removing the dummy sacrificial pillar to open the dummy via, and forming the dummy structure DH in the opened dummy via. In this case, the dummy sacrificial pillar can be formed simultaneously with the first sacrificial pillar 201, the second sacrificial pillar 202, the third sacrificial pillar 203, and the fourth sacrificial pillar 204.

[0136] The memory channel structure CH, the dummy structure DH, the first sacrificial pillar 201, the second sacrificial pillar 202, the third sacrificial pillar 203, and the fourth sacrificial pillar 204 can penetrate the dielectric pattern IP and the sacrificial pattern SP on the third-direction D3.

[0137] Contact sacrificial pillar 206 can be formed. The formation of contact sacrificial pillar 206 may include forming a contact hole and forming contact sacrificial pillar 206 in the contact hole.

[0138] Each of the contact sacrificial pillars 206 can contact at least one sacrificial pattern SP.

[0139] The first sacrificial pillar 201 can be arranged to be spaced apart from each other in the second direction D2. The second sacrificial pillar 202 can be arranged to be spaced apart from each other in the second direction D2. The third sacrificial pillar 203 can be arranged to be spaced apart from each other in the second direction D2. The fourth sacrificial pillar 204 can be arranged to be spaced apart from each other in the second direction D2. The third sacrificial pillar 203 and the fourth sacrificial pillar 204 can be arranged along the second direction D2.

[0140] Reference Figure 4A and Figure 4B A photoresist layer PR can be formed to cover the first sacrificial pillar 201, the second sacrificial pillar 202, and the third sacrificial pillar 203, the memory channel structure CH, the dummy structure DH, and the contact sacrificial pillar 206. The photoresist layer PR may include an opening OP exposing the fourth sacrificial pillar 204. The opening OP can be formed by exposing and developing the photoresist layer PR. The opening OP can be formed using a photolithography process. The photoresist layer PR may include a photoresist material.

[0141] Reference Figure 5A and Figure 5B The fourth sacrificial pillar 204 can be removed through the opening OP of the photoresist layer PR. The fourth sacrificial pillar 204 can be removed to open the fourth hole.

[0142] An expansion process can be performed to expand the fourth via. The expansion of the fourth via can connect the fourth vias to each other and form a dielectric trench IT. The expansion of the fourth via can be based on an isotropic etching process, such as a wet etching process; however, the example embodiments are not limited thereto.

[0143] In some example embodiments, when removing the fourth sacrificial post 204 and expanding the fourth hole, the third sacrificial post 203, which is closest to the fourth sacrificial post 204, may be removed. The third hole, opened due to the removal of the third sacrificial post 203, can connect to the expanded fourth hole, thereby defining the third hole as part of the dielectric trench IT.

[0144] A dielectric structure IS can be formed in a dielectric trench IT. The dielectric structure IS can penetrate the dielectric pattern IP and the sacrificial pattern SP on the third-direction D3.

[0145] Reference Figures 6A to 6C The first sacrificial post 201, the second sacrificial post 202, and the third sacrificial post 203 can be removed. The removal of the first sacrificial post 201, the second sacrificial post 202, and the third sacrificial post 203 can open the first hole, the second hole, and the third hole.

[0146] An expansion process can be performed on the first, second, and third vias. The first via can be expanded and connected to each other to form a first trench TR1. The expansion process can be based on an isotropic etching process, such as a wet etching process; however, the example embodiment is not limited thereto. The second via can be expanded and connected to each other to form a second trench TR2. The third via can be expanded and connected to each other to form a third trench TR3. The third trench TR3 can be connected to a dielectric structure IS. The first trench TR1, the second trench TR2, and the third trench TR3 can penetrate the dielectric pattern IP and the sacrificial pattern SP on a third-direction D3. The third trench TR3 and the dielectric structure IS can be disposed between the first trench TR1 and the second trench TR2.

[0147] Reference Figures 7A to 7C The sacrificial pattern SP can be selectively etched through the first trench TR1, the second trench TR2, and the third trench TR3. For example, phosphoric acid can be provided through the first trench TR1, the second trench TR2, and the third trench TR3.

[0148] A sacrificial pattern SP can be etched to form a molded pattern MP. The unetched residue of the sacrificial pattern SP can be defined as the molded pattern MP. The sacrificial pattern SP may include a portion in contact with the dielectric structure IS, and this portion of the sacrificial pattern SP can be retained during the etching process.

[0149] At least a portion of the contact sacrificial column 206 may come into contact with the molded pattern MP.

[0150] Reference Figure 8A and Figure 8B A conductive pattern CP can be formed. Forming the conductive pattern CP may include depositing conductive material through a first trench TR1, a second trench TR2, and a third trench TR3. In some example embodiments, the deposition of the conductive material may form conductive connectors connecting the conductive pattern CP in the first trench TR1, the second trench TR2, and the third trench TR3. An etching process may be performed to remove the conductive connectors through the first trench TR1, the second trench TR2, and the third trench TR3. Removal of the conductive connectors may remove portions of the conductive pattern CP adjacent to the first trench TR1, the second trench TR2, and the third trench TR3.

[0151] On cell region CR, the first dummy layer DL1, the second dummy layer DL2, and the third dummy layer DL3 can be removed. The memory layer 183 exposed due to the removal of the first dummy layer DL1, the second dummy layer DL2, and the third dummy layer DL3 can be partially removed. A second source layer SL2 can then be formed.

[0152] A first-side separation structure SDS1, a second-side separation structure SDS2, and a central separation structure CDS can be formed. The first-side separation structure SDS1 can fill the first trench TR1. The second-side separation structure SDS2 can fill the second trench TR2. The central separation structure CDS can fill the third trench TR3. The portions of the conductive pattern CP adjacent to the first trench TR1, the second trench TR2, and the third trench TR3 can be removed to form empty spaces, and a protruding portion of the central separation structure CDS can be formed within these empty spaces (see...). Figure 2F 12).

[0153] Return to reference Figure 2A , Figure 2B , Figure 2C and Figure 2D The contact sacrificial post 206 can be removed. A first connecting contact structure CS1 and a second connecting contact structure CS2 can be formed in the empty space obtained by removing the contact sacrificial post 206.

[0154] A first covering dielectric layer 131 can be formed. Bit line contacts BC and conductive line contacts SC can be formed.

[0155] A second covering dielectric layer 132 can be formed. Bit lines BL and conductive lines CL can be formed.

[0156] In a method for manufacturing a semiconductor device according to some example embodiments, after etching the sacrificial pattern SP, a molded pattern MP can support the dielectric pattern IP. Therefore, improved stability can be achieved in the manufacturing of the semiconductor device.

[0157] Alternatively or additionally, in the method of manufacturing a semiconductor device according to some example embodiments, the molded pattern MP may support the dielectric pattern IP to reduce the number of dummy structures DH. Therefore, the size of the contact sacrificial pillar 206 can be increased relatively without interfering with the dummy structures DH.

[0158] Figure 9 A plan view illustrating a semiconductor device according to some example embodiments is shown. In addition to the following description, according to Figure 9 Semiconductor devices can be similar to those based on Figures 2A to 2G Semiconductor devices.

[0159] Reference Figure 9 The maximum width W1a of the dielectric structure Isa in the first direction D1 can be greater than the maximum width W2a of the central separation structure CDS in the first direction D1.

[0160] Figure 10 and Figure 11 Demonstrates manufacturing Figure 9A schematic diagram of a method for using a semiconductor device is depicted. In addition to the following description, according to... Figure 10 and Figure 11 The method for manufacturing semiconductor devices will be similar to that based on Figure 3A , Figure 3B , Figure 3C , Figure 4A , Figure 4B , Figure 5A , Figure 5B , Figure 6A , Figure 6B , Figure 6C , Figure 7A , Figure 7B , Figure 7C , Figure 8A and Figure 8B Manufacturing in Figures 2A to 2G The method for semiconductor devices described in the text.

[0161] Reference Figure 10 This can form the first sacrificial pillar 201, the second sacrificial pillar 202, the third sacrificial pillar 203, and the fourth sacrificial pillar 204a.

[0162] The interval L2a between adjacent fourth sacrificial pillars 204a in the second direction D2 can be greater than the interval between adjacent first sacrificial pillars 201 in the second direction D2, the interval between adjacent second sacrificial pillars 202 in the second direction D2, and the interval between adjacent third sacrificial pillars 203 in the second direction D2.

[0163] The interval L2a between adjacent fourth sacrificial pillars 204a in the second direction D2 can be smaller than the interval L1a between the third sacrificial pillar 203 and the fourth sacrificial pillar 204a in the second direction D2.

[0164] Reference Figure 11 The fourth sacrificial pillar 204a can be removed. An expansion process can be performed on the fourth hole, which becomes open due to the removal of the fourth sacrificial pillar 204a. The degree of expansion of the fourth hole can be greater than that in the expansion processes of the first to third holes (see...). Figure 6A , Figure 6B and Figure 6C The expansion degree of the first to third holes. Therefore, the maximum width of the dielectric trench ITa in the first direction D1 can be greater than that of the first trench, the second trench, and the third trench (see Figure 6A , Figure 6B and Figure 6C The maximum width of TR1, TR2 and TR3 in the first direction D1.

[0165] A dielectric structure ISa can be formed in a dielectric trench ITa.

[0166] Figure 12A plan view illustrating a semiconductor device according to some example embodiments is shown. In addition to the following description, according to Figure 12 Semiconductor devices can be similar to those based on Figures 2A to 2G Semiconductor devices.

[0167] Reference Figure 12 The first side separation structure SDS1b, the second side separation structure SDS2b, the central separation structure CDSb, and the dielectric structure ISb may include sidewalls extending in the second direction D2. The first side separation structure SDS1b, the second side separation structure SDS2b, the central separation structure CDSb, and the dielectric structure ISb may have flat sidewalls extending in the second direction D2.

[0168] Figure 13 Demonstrates manufacturing Figure 12 A plan view of the method for using a semiconductor device depicted in the diagram. In addition to the following description, according to... Figure 13 The method for manufacturing semiconductor devices will be similar to that based on Figure 3A , Figure 3B , Figure 3C , Figure 4A , Figure 4B , Figure 5A , Figure 5B , Figure 6A , Figure 6B , Figure 6C , Figure 7A , Figure 7B , Figure 7C , Figure 8A and Figure 8B Manufacturing in Figures 2A to 2G The method for semiconductor devices described in the text.

[0169] Reference Figure 13 A dielectric trench ITb can be formed, including sidewalls extending in the second direction D2. A dielectric structure ISb can be formed in the dielectric trench ITb.

[0170] Return to reference Figure 12 A first trench TR1b, a second trench TR2b, and a third trench TR3b can be formed, each of which includes a sidewall extending in the second direction D2. A sacrificial pattern SP can be etched (see...). Figure 7A , Figure 7B and Figure 7C It can form a first-side separation structure SDS1b, a second-side separation structure SDS2b, and a central separation structure CDSb.

[0171] Figure 14An enlarged plan view illustrating a semiconductor device according to some example embodiments is shown. In addition to the following description, according to Figure 12 Semiconductor devices can be similar to those based on Figures 2A to 2G Semiconductor devices.

[0172] Reference Figure 14 The dielectric structure ISc may include a base 410 and a protrusion 420 protruding from the base 410. The base 410 may include a first dielectric portion 411, a second dielectric portion 412, a third dielectric portion 413, and a fourth dielectric portion 414. The first dielectric portion 411, the second dielectric portion 412, and the third dielectric portion 413 may be disposed between conductive patterns CPC. The first dielectric portion 411, the second dielectric portion 412, and the third dielectric portion 413 may be spaced apart from the molded pattern MP. The protrusion 420 may protrude from the first dielectric portion 411, the second dielectric portion 412, and the third dielectric portion 413.

[0173] The fourth dielectric portion 414 can contact the molded pattern MP. The protrusion 420 can contact the conductive pattern CPC. The protrusion 420 can contact the molded pattern MP.

[0174] The second dielectric portion 412 may be disposed between the first dielectric portion 411 and the third dielectric portion 413. The maximum width of the second dielectric portion 412 in the first direction D1 may be smaller than the maximum width of the first dielectric portion 411 in the first direction D1 and the maximum width of the third dielectric portion 413 in the first direction D1.

[0175] Figure 15 , Figure 16 and Figure 17 Demonstrates manufacturing Figure 14 A plan view of the method for using a semiconductor device depicted in the diagram. In addition to the following description, according to... Figure 15 , Figure 16 and Figure 17 The manufacturing method of semiconductor devices will be similar to that based on Figure 3A , Figure 3B , Figure 3C , Figure 4A , Figure 4B , Figure 5A , Figure 5B , Figure 6A , Figure 6B , Figure 6C , Figure 7A , Figure 7B , Figure 7C , Figure 8A and Figure 8B Manufacturing in Figures 2A to 2G The method for semiconductor devices described in the text.

[0176] Reference Figure 15 This can form a first sacrificial pillar 201, a second sacrificial pillar 202, a third sacrificial pillar 203, and a sacrificial structure 301c. The formation of the sacrificial structure 301c may include forming the first sacrificial pillar 201, the second sacrificial pillar 202, the third sacrificial pillar 203, and a fourth sacrificial pillar (see [reference]). Figure 3A 204), the fourth sacrificial pillar 204 is removed, a dielectric trench ITc is formed by expanding the fourth hole from which the fourth sacrificial pillar 204 has been removed, and a sacrificial structure 301c is formed in the dielectric trench ITc.

[0177] Reference Figure 16 The first sacrificial post 201, the second sacrificial post 202, and the third sacrificial post 203 can be removed. The first, second, and third holes can be expanded to form a first groove TR1, a second groove TR2, and a third groove TR3. The third groove TR3 can be connected to the sacrificial structure 301c. A molded pattern MP can be formed.

[0178] Reference Figure 17 The sacrificial structure 301c can be removed. Removing the sacrificial structure 301c can open the dielectric trench ITc.

[0179] Return to reference Figure 14 A conductive pattern CPc can be formed through the third trench TR3 and the dielectric trench ITc. Similar to... Figure 8A and Figure 8B As discussed herein, an etching process can be performed to remove the conductive connector, and the removal action can be performed on the portion of the conductive pattern CPC adjacent to the third trench TR3 and the dielectric trench ITc.

[0180] A dielectric structure ISc can be formed to fill the third trench TR3 and the dielectric trench ITc. The protrusion 420 of the dielectric structure ISc can fill the empty space obtained by removing the portion of the conductive pattern CPc adjacent to the third trench TR3 and the dielectric trench ITc.

[0181] Figure 18A and Figure 18B A cross-sectional view illustrating a semiconductor device according to some example embodiments is shown. In addition to the following description, according to... Figure 18A and Figure 18B Semiconductor devices can be similar to those based on Figures 2A to 2G Semiconductor devices.

[0182] Reference Figure 18A and Figure 18B The semiconductor device may include a peripheral circuit structure PSTd. The peripheral circuit structure PSTd may include a substrate 100, a peripheral circuit dielectric layer 120, a transistor 110, a device isolation layer 103, peripheral contacts 105, and peripheral conductive lines 107.

[0183] The peripheral circuit structure PSTd may further include a first interlayer dielectric layer 511 on the peripheral circuit dielectric layer 120 and a second interlayer dielectric layer 512 on the first interlayer dielectric layer 511. The first interlayer dielectric layer 511 and the second interlayer dielectric layer 512 may include dielectric materials.

[0184] The peripheral circuit structure PSTd may further include a first conductive contact 521 located on the peripheral conductive line 107, a first conductive pad 522 connected to the first conductive contact 521, a second conductive contact 523 connected to the first conductive pad 522, and a second conductive pad 524 connected to the second conductive contact 523. Conductive material may be included in the first conductive contact 521, the first conductive pad 522, the second conductive contact 523, and the second conductive pad 524.

[0185] The third interlayer dielectric layer 513 may be disposed on the second interlayer dielectric layer 512. The fourth interlayer dielectric layer 514 may be disposed on the third interlayer dielectric layer 513. The fifth interlayer dielectric layer 515 may be disposed on the fourth interlayer dielectric layer 514. The sixth interlayer dielectric layer 516 may be disposed on the fifth interlayer dielectric layer 515. The third interlayer dielectric layer 513, the fourth interlayer dielectric layer 514, the fifth interlayer dielectric layer 515, and the sixth interlayer dielectric layer 516 may include dielectric materials.

[0186] The third conductive pad 525 may be disposed in the third interlayer dielectric layer 513. At least one of the third conductive pads 525 may be bonded to the second conductive pad 524 by, for example, a wafer bonding process. The third interlayer dielectric layer 513 may be bonded to the second interlayer dielectric layer 512 by, for example, a wafer bonding process.

[0187] A third conductive contact 526 may be provided and connected to the third conductive pad 525. The third conductive contact 526 may be connected to the bit line BLd or the conductive line CLd. The third conductive pad 525 and the third conductive contact 526 may include conductive material.

[0188] The sixth interlayer dielectric layer 516 may have a gate stack structure GSTd comprising a dielectric pattern IPd, a conductive pattern CPd, and a molded pattern MPd. The sixth interlayer dielectric layer 516 may also have a memory channel structure CHd, a first connection contact structure CS1d, and a second connection contact structure CS2d. The memory channel structure CHd may include a bit line pad 185d on the sixth interlayer dielectric layer 516, a dielectric capping layer 189d on the bit line pad 185d, a channel layer 187d on the dielectric capping layer 189d, and a memory layer 183d on the channel layer 187d.

[0189] Bit line contact BCd can be disposed in the sixth interlayer dielectric layer 516 to connect bit line pad 185d and bit line BLd to each other. Conductive line contact SCd can be disposed in the sixth interlayer dielectric layer 516 to connect conductive line CLd to the first connection contact structure CS1d or the second connection contact structure CS2d.

[0190] The sixth interlayer dielectric layer 516 may have a first side separation structure SDS1d, a second side separation structure SDS2d, a central separation structure CDSd, and a dielectric structure ISd disposed thereon.

[0191] The source structure SSTd may be disposed on the channel layer 187d of the first-side discrete structure SDS1d, the second-side discrete structure SDS2d, the central discrete structure CDSd, and the memory channel structure CHd. The source structure SSTd may include, for example, polysilicon. A cover dielectric layer 517 may be disposed on the source structure SSTd and the dielectric structure ISd.

[0192] A semiconductor device according to some example embodiments may include a molded pattern to stably support a dielectric pattern and improve the stability of the semiconductor device.

[0193] Although the inventive concept has been described in conjunction with some exemplary embodiments shown in the accompanying drawings, those skilled in the art will understand that changes in form and detail may be made without departing from the spirit and essential characteristics of the inventive concept. Therefore, the embodiments disclosed above should be considered illustrative rather than restrictive. Furthermore, the exemplary embodiments discussed above may be combined with each other if desired; in particular, the exemplary embodiments are not necessarily mutually exclusive.

Claims

1. A semiconductor device, comprising: First conductive pattern; The second conductive pattern is spaced apart from the first conductive pattern in a first direction; A dielectric pattern located between the first conductive pattern and the second conductive pattern; A first molded pattern is located at the same level as the first conductive pattern; The second molded pattern is at the same level as the second conductive pattern and is spaced apart from the first molded pattern in the first direction; A memory channel structure that penetrates the first conductive pattern and the second conductive pattern; A first connecting contact is electrically connected to the first conductive pattern; as well as A first connecting contact dielectric layer surrounds the first connecting contact. Wherein, the dielectric pattern is located between the first molding pattern and the second molding pattern, and The first connecting contact and the first connecting contact dielectric layer are located between the second conductive pattern and the second molded pattern.

2. The semiconductor device according to claim 1, wherein, The first connecting contact contacts the first conductive pattern and the first molded pattern, and The first connecting contact dielectric layer contacts the first conductive pattern and the first molded pattern.

3. The semiconductor device according to claim 2, in, The first conductive pattern includes: The first surface, which contacts the bottom surface of the first connecting contact, and The second surface contacts the first sidewall of the first connecting contact dielectric layer, and The first molded pattern includes, The first surface, which contacts the bottom surface of the first connecting contact, and The second surface contacts the second sidewall of the first connecting contact dielectric layer.

4. The semiconductor device according to claim 3, wherein, The second conductive pattern contacts the first sidewall of the first connecting contact dielectric layer, and The second molded pattern contacts the second sidewall of the first connecting contact dielectric layer.

5. The semiconductor device according to claim 1, wherein, The first conductive pattern includes a first overlapping portion that at least partially overlaps with the first connecting contact. The first molded pattern includes a second overlapping portion that at least partially overlaps with the first connecting contact, and The first overlapping portion and the second overlapping portion are in contact with each other.

6. The semiconductor device according to claim 1, further comprising: A dielectric structure that penetrates both the first and second molded patterns. The second molded pattern includes the portion between the dielectric structure and the second conductive pattern.

7. The semiconductor device according to claim 6, wherein, The second conductive pattern includes: Contact the first sidewall of the dielectric structure; The second sidewall of the second molded pattern is in contact with the second sidewall; and The surface of the first connecting contact dielectric layer comes into contact with it.

8. The semiconductor device according to claim 1, further comprising: The second connecting contact is electrically connected to the second conductive pattern; as well as A second connecting contact dielectric layer surrounds the second connecting contact. Wherein, the length of the second connecting contact in the first direction is less than the length of the first connecting contact in the first direction.

9. A semiconductor device, comprising: First-side separation structure; The second side separation structure is spaced apart from the first side separation structure in a first direction; A first conductive pattern, a second conductive pattern, and a molded pattern are located between the first side separation structure and the second side separation structure; A dielectric structure located between the first side separation structure and the second side separation structure, the dielectric structure penetrating the molded pattern; A memory channel structure that penetrates the first conductive pattern; as well as The first connecting contact is electrically connected to the first conductive pattern. The first conductive pattern is located between the first side separation structure and the dielectric structure. The second conductive pattern is located between the second side separation structure and the dielectric structure. The first conductive pattern and the second conductive pattern are spaced apart from each other in the first direction. The molded pattern contacts both the first conductive pattern and the second conductive pattern. The molded pattern includes: The first part is located between the dielectric structure and the first conductive pattern. The second part, which lies between the dielectric structure and the second conductive pattern, and The third part connects the first part and the second part to each other.

10. The semiconductor device according to claim 9, wherein, The dielectric structure is located between the first portion and the second portion.

11. The semiconductor device according to claim 9, wherein, The first connecting contact contacts the first portion and the first conductive pattern.

12. The semiconductor device according to claim 9, further comprising: A third conductive pattern is spaced apart from the first conductive pattern in a second direction, and the second direction intersects the first direction. A fourth conductive pattern, which is spaced apart from the second conductive pattern in the second direction; A dielectric pattern, which lies between the first conductive pattern and the third conductive pattern, and between the second conductive pattern and the fourth conductive pattern. The dielectric structure includes sidewalls that are in contact with the first sidewall of the first conductive pattern, the first sidewall of the third conductive pattern, and the first sidewall of the dielectric pattern. The first side separation structure includes: base, and A protrusion extending from the base. The base includes a sidewall that contacts a second sidewall of the dielectric pattern, and The protrusion includes: The sidewall, which contacts the second sidewall of the first conductive pattern, and The top surface contacts the bottom surface of the dielectric pattern.

13. The semiconductor device according to claim 12, wherein, The length of the sidewall of the dielectric structure in the second direction is greater than the length of the sidewall of the base in the second direction, and is also greater than the length of the sidewall of the protrusion in the second direction.

14. The semiconductor device of claim 9, further comprising: A central separation structure is located between the first side separation structure and the second side separation structure, and is connected to the dielectric structure. The central separation structure is located between the first conductive pattern and the second conductive pattern.

15. The semiconductor device according to claim 14, wherein, The maximum width of the central separation structure in the first direction is greater than the maximum width of the dielectric structure in the first direction.

16. The semiconductor device according to claim 14, wherein, The dielectric structure includes: The first dielectric portion contacts the molded pattern; The second dielectric portion contacts the first conductive pattern and the second conductive pattern; and The third dielectric portion contacts the central separation structure. Wherein, the maximum width of the third dielectric portion in the first direction is less than the maximum width of the first dielectric portion in the first direction.

17. The semiconductor device according to claim 14, wherein, The maximum width of the dielectric structure in the first direction is greater than the maximum width of the central separation structure in the first direction.

18. The semiconductor device according to claim 9, wherein, The dielectric structure includes: base; and Multiple protrusions protruding from the base, The base includes: The first dielectric portion contacts the molded pattern, and The second dielectric portion is spaced apart from the molded pattern, and The plurality of protrusions protrude from the second dielectric portion.

19. An electronic system comprising: Motherboard; A semiconductor device on the motherboard; as well as The controller is located on the motherboard and is electrically connected to the semiconductor device. The semiconductor device includes: First-side separation structure, The second side separation structure is spaced apart from the first side separation structure in a first direction. A first conductive pattern, a second conductive pattern, a third conductive pattern, a fourth conductive pattern, a first molded pattern, and a second molded pattern are located between the first side separation structure and the second side separation structure. A dielectric pattern, which lies between the first conductive pattern and the third conductive pattern, between the second conductive pattern and the fourth conductive pattern, and between the first molded pattern and the second molded pattern. A dielectric structure is located between the first side separation structure and the second side separation structure, the dielectric structure penetrating the first molding structure and the second molding structure. The memory channel structure penetrates the first conductive pattern. The first connecting contact is electrically connected to the first conductive pattern. A first connecting contact dielectric layer surrounds the first connecting contact. The second connecting contact is electrically connected to the third conductive pattern, and A second connecting contact dielectric layer surrounds the second connecting contact. The first molded pattern contacts both the first conductive pattern and the second conductive pattern. The second molded pattern contacts the third conductive pattern and the fourth conductive pattern. Wherein, the first connecting contact contacts the first conductive pattern and the first molded pattern, and The first connecting contact dielectric layer contacts the third conductive pattern and the second molded pattern.

20. The electronic system according to claim 19, wherein, The second molded pattern includes: The first portion is located between the dielectric structure and the first conductive pattern; The second portion is located between the dielectric structure and the second conductive pattern; and The third part connects the first and second parts to each other. The first part includes a sidewall that contacts the first conductive pattern. The second portion includes a sidewall that contacts the second conductive pattern, and The distance between the sidewall of the first part and the sidewall of the second part in the first direction decreases as the distance from the memory channel structure decreases.

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