Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and its formation method are disclosed. The structure includes: a substrate comprising a memory region and a capacitor region; a floating gate structure, a control gate structure, and a source line structure located on the memory region, wherein the control gate structure is located on the floating gate structure and exposes a portion of the surface of the floating gate structure, the floating gate structure exposes a portion of the surface of the memory region, and the source line structure is located on the exposed memory region by the floating gate structure; a word line gate structure located on the sidewall of the floating gate structure; a first electrode plate located on the capacitor region, the first electrode plate being formed during the formation of the control gate structure; and a dielectric layer and a second electrode plate sequentially stacked on the first electrode plate, the dielectric layer and the second electrode plate being formed during the formation of the word line gate structure. The capacitor structure and the memory structure of the memory region can be integrated on a single chip, facilitating circuit design and saving chip area.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] A PIP capacitor (Poly-Insulator-Poly Capacitor) is a type of capacitor with a polysilicon-insulator-polysilicon structure. Its working principle is based on the polarization induced by an electric field in the insulating medium, thereby storing charge between two layers of polysilicon. It has advantages such as excellent performance, high capacitance density, small voltage coefficient, and low parasitic effects, and is widely used in CMOS technology.

[0003] The manufacturing process and structural performance of PIP capacitors need further optimization. Summary of the Invention

[0004] The technical problem solved by this invention is to provide a semiconductor structure and its formation method to optimize the formation process and structural performance of PIP capacitors.

[0005] To address the aforementioned technical problems, the present invention provides a semiconductor structure comprising: a substrate including a storage region and a capacitor region; a floating gate structure, a control gate structure, and a source line structure located on the storage region, wherein the control gate structure is located on the floating gate structure, the control gate structure exposes a portion of the surface of the floating gate structure, the floating gate structure exposes a portion of the surface of the storage region, and the source line structure is located on the storage region exposed by the floating gate structure; a word line gate structure located on the sidewall of the floating gate structure; a first electrode plate located on the capacitor region, the first electrode plate being formed during the formation of the control gate structure; and a dielectric layer and a second electrode plate sequentially stacked on the first electrode plate, the dielectric layer and the second electrode plate being formed during the formation of the word line gate structure.

[0006] Optionally, it further includes: a first isolation structure located within the storage area, wherein adjacent floating gate structures are isolated from each other by the first isolation structure, and the first isolation structure protrudes from the surface of the storage area; and a second isolation structure located on the capacitor area, wherein the second isolation structure is located between the first electrode plate and the capacitor area.

[0007] Optionally, the height of the first isolation structure is lower than the top surface of the floating gate structure.

[0008] Optionally, it further includes: a second sidewall located between the source line structure and the control gate structure, the second sidewall being located on the floating gate structure, and the top of the second sidewall being higher than the top of the control gate structure; a first sidewall located on top of the control gate structure, and the second sidewall being located between the first sidewall and the source line structure.

[0009] Optionally, the top of the source line structure is lower than the top of the second sidewall, and the structure further includes a protective layer located on top of the source line structure, the top of which is flush with the top of the second sidewall.

[0010] Optionally, it also includes a fourth sidewall located between the source line structure and the floating grid structure, the fourth sidewall also being located on the sidewall of the second sidewall.

[0011] Optionally, it also includes: a first doped region located within a portion of the memory region exposed by the floating gate structure; the source line structure is electrically connected to the first doped region.

[0012] Optionally, it also includes a third sidewall located on the sidewalls of the floating grid structure and the control grid structure, the third sidewall being located between the floating grid structure and the control grid structure and the word line grid structure.

[0013] Optionally, the control gate structure includes: a control gate dielectric layer and a control gate layer located on the control gate dielectric layer, wherein the first electrode plate is formed during the formation of the control gate layer.

[0014] Optionally, the word line gate structure includes: a word line gate dielectric layer and a word line gate layer located on the word line gate dielectric layer, wherein the dielectric layer is formed during the formation of the word line gate dielectric layer, and the second electrode plate is formed during the formation of the word line gate layer.

[0015] Accordingly, the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a memory region and a capacitor region; forming an initial floating gate structure on the memory region; forming a control gate structure material layer on the memory region, the control gate structure material layer being located on the side of the initial floating gate structure away from the memory region; forming a first electrode plate on the capacitor region, the first electrode plate being formed during the formation of the control gate structure material layer; forming a floating gate structure, a control gate structure, and a source line structure on the memory region, the control gate structure being located on the floating gate structure, the control gate structure and the floating gate structure being formed based on the initial floating gate structure and the control gate structure material layer, the control gate structure exposing a portion of the surface of the floating gate structure, the floating gate structure exposing a portion of the surface of the memory region, and the source line structure being located on the memory region exposed by the floating gate structure; forming a word line gate structure on the sidewalls of the floating gate structure and the control gate structure; and sequentially forming a dielectric layer and a second electrode plate on the first electrode plate, the dielectric layer and the second electrode plate being formed during the formation of the word line gate structure.

[0016] Optionally, before forming a control gate structure material layer on the storage region and forming a first electrode plate on the capacitor region, the method further includes: forming a first isolation structure located within the storage region, wherein adjacent initial floating gate structures are isolated from each other by the first isolation structure, and the first isolation structure protrudes from the surface of the storage region.

[0017] Optionally, the method for forming the initial floating gate structure and the first isolation structure includes: forming a floating gate structure material layer on the storage region and the capacitor region; forming a first hard mask material layer on the floating gate structure material layer; removing a portion of the first hard mask material layer, a portion of the floating gate structure material layer, and a portion of the storage region, forming a first groove in the storage region that penetrates the first hard mask material layer and the floating gate structure material layer and extends into the storage region; forming an initial isolation structure in the first groove; removing a portion of the initial isolation structure to form the first isolation structure; and removing the first hard mask material layer.

[0018] Optionally, while removing part of the first hard mask material layer, part of the floating gate structure material layer, and part of the storage area, the method also includes: removing the first hard mask material layer, the floating gate structure material layer, and part of the capacitor area; forming an initial isolation structure in the groove; and forming a second isolation structure on the capacitor area, wherein the second isolation structure is located between the first electrode plate and the capacitor area.

[0019] Optionally, the top surface of the first isolation structure is lower than the top surface of the initial floating gate structure.

[0020] Optionally, the method for forming the floating gate structure, control gate structure, and source line structure in the storage region includes: forming a second hard mask material layer on the control gate structure material layer and on the first electrode plate; removing a portion of the second hard mask material layer on the storage region, forming a second groove within the second hard mask material layer, the second groove exposing a portion of the surface of the control gate structure material layer; forming a first sidewall on the sidewall of the second groove; etching the control gate structure material layer exposed by the second groove using the first sidewall as a mask until the surface of the initial floating gate structure is exposed, forming an initial control gate structure; forming a third groove at the bottom of the second groove; forming a second sidewall on the sidewall of the third groove, the second sidewall being located on the sidewall of the initial control gate structure and the sidewall of the first sidewall; etching the initial floating gate structure using the second sidewall as a mask until the surface of the storage region is exposed, forming a fourth groove within the initial floating gate structure; and forming a source line structure within the second groove, the third groove, and the fourth groove.

[0021] Optionally, before forming the source line structure in the fourth groove, the method further includes: performing ion implantation on the storage region at the bottom of the fourth groove to form a first doped region in the storage region; the source line structure is electrically connected to the first doped region.

[0022] Optionally, the top surface of the source line structure is lower than the top surface of the first sidewall, and the top surface of the source line structure is higher than the top surface of the initial control gate structure; the method of forming the source line structure includes: forming an initial source line structure in the second groove, the third groove and the fourth groove, wherein the top surface of the initial source line structure is flush with the top surface of the first sidewall; removing part of the initial source line structure to form the source line structure.

[0023] Optionally, after forming the source line structure, the method further includes: forming a protective layer on top of the source line structure, wherein the top surface of the protective layer is flush with the top surface of the first sidewall.

[0024] Optionally, the method for forming the floating gate structure and the control gate structure in the storage area further includes: removing a second hard mask material layer on the storage area and the capacitor area; after removing the second hard mask material layer, using the first sidewall as a mask, etching the initial control gate structure and the initial floating gate structure until the surface of the storage area is exposed, forming the floating gate structure and the control gate structure located on the floating gate structure.

[0025] Optionally, the method for forming the word line gate structure, dielectric layer, and second electrode plate includes: forming a word line gate structure material layer on the memory region and the capacitor region, the word line gate structure material layer including a word line gate dielectric material layer and a word line gate material layer located on the word line gate dielectric material layer; etching back the word line gate structure material layer on the memory region to form a word line gate structure on the sidewalls of the floating gate structure and the control gate structure.

[0026] Optionally, the method for forming the dielectric layer and the second electrode plate further includes: patterning the word line gate structure material layer on the capacitor region, forming the word line gate dielectric material layer as a dielectric layer, and forming the word line gate material layer as the second electrode plate.

[0027] Optionally, before forming the word line gate structure material layer on the memory region and the capacitor region, the method further includes: forming a third sidewall on the sidewalls of the floating gate structure and the control gate structure, the third sidewall being located between the floating gate structure and the control gate structure and the word line gate structure.

[0028] Compared with the prior art, the technical solution of the present invention has the following beneficial effects: In the semiconductor structure of the present invention, the first electrode plate is formed during the formation of the control gate structure, and the dielectric layer and the second electrode plate are formed during the formation of the word line gate structure. Thus, the capacitor structure composed of the first electrode plate, the dielectric layer and the second electrode plate can be integrated with the formation process of the memory device in the memory area. That is, the capacitor structure can be formed using the process of forming the memory device in the memory area. The capacitor structure and the memory structure in the memory area can be integrated on a single chip, which facilitates circuit design and saves chip area.

[0029] Furthermore, the capacitor structure formed by the first electrode plate, the dielectric structure, and the second electrode plate has a dielectric layer and a second isolation structure between it and the capacitor region. The capacitor structure has a large gap with the substrate, so that the capacitor structure and the substrate are less likely to generate large parasitic capacitance, thereby improving the performance of the capacitor structure.

[0030] Furthermore, the top surface of the first isolation structure is lower than the top surface of the floating gate structure, so that the control gate structure formed above the floating gate structure and the first isolation structure is also located on part of the sidewall of the floating gate structure. The control gate structure can surround the floating gate structure, increase the coupling area between the control gate structure and the floating gate structure, and improve the coupling efficiency.

[0031] The method of the present invention integrates the formation process of the capacitor structure in the capacitor region with the formation process of the memory device in the storage region. That is, the capacitor structure can be formed using the process of forming the memory device in the storage region without additional process steps, without increasing the number of photomasks, and the process of forming the capacitor structure is simple and easy to mass produce. Attached Figure Description

[0032] Figures 1 to 18 This is a schematic diagram of the semiconductor structure formation process in an embodiment of the present invention. Detailed Implementation

[0033] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0034] Figures 1 to 18 This is a schematic diagram of the semiconductor structure formation process in an embodiment of the present invention.

[0035] Please refer to Figure 1 and Figure 2 , Figure 1 yes Figure 2 Top view, Figure 2 yes Figure 1 A cross-sectional structural schematic diagram along the section line AA1 shows a substrate 200, which includes a storage region I and a capacitor region II.

[0036] The storage area I is used to form a storage device, and the capacitor area II is used to form a capacitor structure.

[0037] In this embodiment, the substrate 200 is made of silicon.

[0038] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0039] In this embodiment, the cross-section line AA1 is parallel to the first direction X, and the first direction X is parallel to the surface of the substrate 200.

[0040] Next, an initial floating gate structure is formed on the memory area I. For the process of forming the initial floating gate structure, please refer to [link / reference needed]. Figures 3 to 8 .

[0041] Please refer to Figure 3 and Figure 4 , Figure 3 yes Figure 4 Top view, Figure 4 yes Figure 3 A cross-sectional structural schematic diagram along the section line AA1 shows that a floating gate structure material layer is formed on the storage region I and the capacitor region II; a first hard mask material layer 203 is formed on the floating gate structure material layer.

[0042] The floating gate structure material layer includes: a floating gate dielectric material layer 201 and a floating gate material layer 202 located on the floating gate dielectric material layer 201.

[0043] In this embodiment, the floating gate dielectric material layer 201 is made of silicon oxide, and the process for forming the floating gate dielectric material layer 201 includes a furnace tube process or a deposition process; the floating gate material layer 202 is made of polysilicon, and the process for forming the floating gate material layer 202 includes a furnace tube process or a deposition process.

[0044] The material of the first hard mask material layer 203 includes a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbonate, silicon oxynitride, aluminum oxide, aluminum nitride, silicon oxycarbonate, and silicon oxycarbonate.

[0045] In this embodiment, the material of the first hard mask material layer 203 includes silicon nitride.

[0046] Please refer to Figure 5 and Figure 6 , Figure 5 yes Figure 6 Top view, Figure 6 yes Figure 5 A cross-sectional view along section line AA1 shows the following: a portion of the first hard mask material layer 203, a portion of the floating gate structure material layer, and a portion of the storage area I are removed. A first groove is formed in the storage area I, penetrating the first hard mask material layer 203 and the floating gate structure material layer and extending into the storage area I. An isolation material layer is formed in the first groove and on the first hard mask material layer 203. The isolation material layer is planarized until the surface of the first hard mask material layer 203 is exposed, so that the isolation material layer forms an initial isolation structure 206 in the first groove.

[0047] In this embodiment, while removing part of the first hard mask material layer 203, part of the floating gate structure material layer and part of the storage region I, the first hard mask material layer 203, the floating gate structure material layer and part of the substrate 200 on the capacitor region II are also removed.

[0048] In this embodiment, the thickness of the capacitor region II is less than the thickness of the storage region I.

[0049] In this embodiment, the material of the isolation material layer is different from the material of the first hard mask material layer 203. This is so that the planarization of the isolation material layer can be stopped at the surface of the first hard mask material layer 203.

[0050] In this embodiment, the material of the insulating material layer includes silicon oxide.

[0051] In this embodiment, the isolation material layer is also formed on the capacitor region II. When the isolation material layer is planarized, the isolation material layer of the capacitor region II is also planarized, and the initial isolation structure 206 is still located on the capacitor region II.

[0052] Removing a portion of the first hard mask material layer 203, a portion of the floating gate structure material layer, and a portion of the storage area I, and forming a first groove in the storage area I that penetrates the first hard mask material layer 203 and the floating gate structure material layer and extends into the storage area I, includes: forming a patterned mask layer on the first hard mask material layer 203; etching the first hard mask material layer 203, the floating gate structure material layer, and the storage area I using the patterned mask layer as a mask, forming the first groove within the first hard mask material layer 203, the floating gate structure material layer, and the storage area I, and forming the floating gate structure material layer into an initial floating gate structure.

[0053] In this embodiment, the process of etching the first hard mask material layer 203, the floating gate structure material layer and the storage area I includes a dry etching process.

[0054] In this embodiment, the initial floating gate structure includes: an initial floating gate dielectric layer 204 and an initial floating gate layer 205 located on the initial floating gate dielectric layer 204. The initial floating gate dielectric layer 204 is located between the initial floating gate layer 205 and the memory region I. The initial floating gate dielectric layer 204 is formed by etching the floating gate dielectric material layer 201, and the floating gate dielectric material layer 201 is formed by etching the floating gate material layer 202.

[0055] Please refer to Figure 7 and Figure 8 , Figure 8 yes Figure 7 Top view, Figure 7 yes Figure 8 A cross-sectional view along the AA1 direction shows the removal of part of the initial isolation structure 206 to form a first isolation structure 207; after forming the first isolation structure 207, the first hard mask material layer 203 is removed.

[0056] In this embodiment, the initial isolation structure 206 is also located on the capacitor region II. Removing part of the initial isolation structure 206 includes removing part of the initial isolation structure 206 of the storage region I and the capacitor region II, forming a first isolation structure 207 in the storage region I, and forming a second isolation structure 208 on the capacitor region II.

[0057] In this embodiment, the thickness of the second isolation structure 208 located on the capacitor region II is less than the thickness of the initial isolation structure 206.

[0058] In this embodiment, the initial floating gate structures that are adjacent in the first direction X are isolated from each other by the first isolation structure 207, which protrudes from the surface of the storage area I and is lower than the top surface of the initial floating gate structure.

[0059] In other embodiments, the first isolation structure is flush with the top surface of the initial floating gate structure.

[0060] In this embodiment, the process of removing part of the initial isolation structure 206 includes a back etching process or an atomic layer etching process; the process of removing the first hard mask material layer 203 includes a wet etching process or a dry etching process.

[0061] Please refer to Figure 9 , Figure 9 In order to be in Figure 8 Based on the structural schematic diagram, after removing the first hard mask material layer 203, ion implantation is performed on the exposed initial floating gate layer 205.

[0062] The implanted ions for ion implantation of the exposed initial floating gate layer 205 include N-type ions or P-type ions. When the device structure formed by the storage region I is N-type, that is, the channel type is N-type, the implanted ions are N-type ions; when the device structure formed by the storage region I is P-type, that is, the channel type is P-type, the implanted ions are P-type ions.

[0063] The N-type ions include one or more combinations of phosphorus ions, arsenic ions, and antimony ions; the P-type ions include one or more combinations of boron ions, borofluorine ions, and indium ions.

[0064] In this embodiment, the implanted ions for ion implantation of the exposed initial floating gate layer 205 include N-type ions, which include phosphorus ions.

[0065] Ion implantation of the exposed initial floating gate layer 205 can increase the conductivity of the subsequently formed floating gate, which is beneficial for uniform charge distribution and helps to improve programming speed.

[0066] In other embodiments, ion implantation can be performed without first implanting the initial floating gate layer.

[0067] Next, a floating gate structure, a control gate structure, and a source line structure are formed on the memory region I. The control gate structure is located on the floating gate structure, exposing a portion of the surface of the floating gate structure. The floating gate structure also exposes a portion of the surface of memory region I. The source line structure is located on the memory region I exposed by the floating gate structure. The formation process of the floating gate structure, control gate structure, and source line structure is described in [reference needed]. Figures 10 to 15 .

[0068] Please refer to Figures 10 to 12 , Figure 10 yes Figure 11 and Figure 12 Top view, Figure 11 yes Figure 10 A schematic diagram of the cross-sectional structure along section line AA1. Figure 12 yes Figure 10 A cross-sectional view along section line BB1 ​​shows that a control gate structure material layer is formed on the storage region I, and the control gate structure material layer is located on the side of the initial floating gate structure away from the storage region I; a first electrode plate 213 is formed on the capacitor region II, and the first electrode plate 213 is formed synchronously with the control gate structure material layer; a second hard mask material layer 211 is formed on the control gate structure material layer and the first electrode plate 213.

[0069] In this embodiment, the control gate structure material layer includes: a control gate dielectric material layer 209 and a control gate material layer 210 located on the control gate dielectric material layer 209.

[0070] In this embodiment, the material of the control gate dielectric material layer 209 includes silicon oxide, and the process for forming the control gate dielectric material layer 209 includes a furnace tube process or a deposition process; the material of the control gate material layer 210 includes polysilicon, and the process for forming the control gate material layer 210 includes a furnace tube process or a deposition process.

[0071] The first electrode plate 213 is formed synchronously with the control gate structure material layer. Specifically, the first electrode plate 213 is formed synchronously with the control gate material layer 210. The material of the first electrode plate 213 is the same as the material of the control gate material layer 210, and the thickness of the first electrode plate 213 is the same as the thickness of the control gate material layer 210.

[0072] In this embodiment, when forming the control gate dielectric material layer 209, the method further includes forming a dielectric layer 212 on the second isolation structure 208 on the capacitor region II, wherein the material of the dielectric layer 212 is the same as the material of the control gate dielectric material layer 209, and the thickness of the dielectric layer 212 is the same as the thickness of the control gate dielectric material layer 209.

[0073] The material of the second hard mask material layer 211 includes a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbonate, silicon oxynitride, aluminum oxide, aluminum nitride, silicon oxycarbonate, and silicon oxycarbonate.

[0074] In this embodiment, the material of the second hard mask material layer 211 includes silicon nitride.

[0075] In this embodiment, the second isolation structure 208 is located between the first electrode plate 213 and the capacitor region II, and the dielectric layer 212 is located between the first electrode plate 213 and the second isolation structure 208.

[0076] In this embodiment, the cross-section line BB1 ​​is parallel to the second direction Y, which is parallel to the surface of the substrate 200 and perpendicular to the first direction X.

[0077] Please continue to refer to this. Figures 10 to 12 Before forming the second hard mask material layer 211, the method further includes: ion implantation of the control gate material layer 210.

[0078] The implanted ions for ion implantation into the control gate material layer 210 include N-type ions or P-type ions. When the device structure formed by the storage region I is N-type, that is, the channel type is N-type, the implanted ions are P-type ions; when the device structure formed by the storage region I is P-type, that is, the channel type is P-type, the implanted ions are N-type ions.

[0079] The N-type ions include one or more combinations of phosphorus ions, arsenic ions, and antimony ions; the P-type ions include one or more combinations of boron ions, borofluorine ions, and indium ions.

[0080] In this embodiment, the implanted ions for ion implantation into the control gate material layer 210 include P-type ions, and the P-type ions include boron ions.

[0081] Control gate structures typically require a high work function to optimize threshold voltage and reliability. Ion implantation of the control gate material layer 210 can improve the work function of the subsequently formed control gate structure, which helps to reduce programming / control voltage and improve the stability of the memory window.

[0082] In other embodiments, ion implantation can be avoided in the control gate material layer.

[0083] Please refer to Figure 13 , Figure 13 In order to be in Figure 12 Based on the structural diagram, a portion of the second hard mask material layer 211 on storage region I is removed, and a second groove is formed within the second hard mask material layer 211, exposing a portion of the surface of the control gate structure material layer; a first sidewall 214 is formed on the sidewall of the second groove; the control gate structure material layer exposed by the second groove is etched using the first sidewall 214 as a mask until the surface of the initial floating gate structure is exposed, forming the initial control gate structure, and a third groove is formed at the bottom of the second groove; a second sidewall 215 is formed on the sidewall of the third groove, the second sidewall 215 being located on the sidewall of the initial control gate structure and the sidewall of the first sidewall 214; the initial floating gate structure is etched using the second sidewall 215 as a mask until the surface of storage region I is exposed, forming a fourth groove within the initial floating gate structure; a source line structure 221 is formed within the second groove, the third groove, and the fourth groove.

[0084] In this embodiment, removing a portion of the second hard mask material layer 211 on the storage region I and forming a second groove within the second hard mask material layer 211 includes: forming a patterned mask layer on the second hard mask material layer 211 on the storage region I and the capacitor region II, the patterned mask layer exposing a portion of the surface of the second hard mask material layer 211 on the storage region I; etching the second mask material layer 211 using the patterned mask layer as a mask to form a second groove within the second mask material layer 211 that exposes a portion of the surface of the control gate structure material layer.

[0085] The process of etching the second mask material layer 211 includes a dry etching process.

[0086] In this embodiment, the method for forming the first sidewall 214 includes: forming a sidewall material layer on the surface and bottom surface of the first groove sidewall and the surface of the second hard mask material layer 211; etching back the sidewall material layer until the surface of the second hard mask material layer 211 and the surface of the control gate structure material layer are exposed, thereby forming a first sidewall 214 on the first groove sidewall, wherein the first sidewall 214 is located on the side of the control gate structure material layer away from the substrate 200.

[0087] The process for forming the sidewall material layer includes furnace tube process or deposition process.

[0088] The material of the first sidewall 214 includes a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide, and silicon carbide.

[0089] In this embodiment, the material of the first sidewall 214 includes silicon oxide.

[0090] Forming a second sidewall 215 on the third groove sidewall includes: forming a sidewall material layer on the surface and bottom surface of the third groove sidewall, the surface and top surface of the first sidewall sidewall, and the surface of the second hard mask material layer 211; etching back the sidewall material layer until the surface of the initial floating gate structure and the surface of the second hard mask material layer 211 are exposed, thereby forming a second sidewall 215 on the third groove sidewall.

[0091] The process for forming the sidewall material layer includes furnace tube process or deposition process.

[0092] The material of the second sidewall 215 includes a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide, and silicon carbide.

[0093] In this embodiment, the material of the second sidewall 215 includes silicon oxide.

[0094] In this embodiment, the material of the second sidewall 215 is the same as the material of the first sidewall 214.

[0095] In other embodiments, the material of the second sidewall may be different from the material of the first sidewall.

[0096] In this embodiment, the projection of the fourth groove on the substrate 200 is located within the projection range of the third groove on the substrate, and the projection of the third groove on the substrate 200 is located within the projection range of the second groove on the substrate.

[0097] In this embodiment, the first sidewall 214 exposes the top of the third recess, and the second sidewall 215 exposes the top of the fourth recess. The top of the first sidewall 214 is flush with the top of the second sidewall 215.

[0098] In this embodiment, the etching process of the control gate structure material layer includes a dry etching process. Etching the control gate structure material layer until the initial floating gate structure surface is exposed to form the initial control gate structure specifically includes etching the control gate material layer 210 and the control gate dielectric material layer 209. The initial control gate structure includes an initial control gate dielectric layer 218 and an initial control gate layer 219. The initial control gate dielectric layer 218 is located between the initial floating gate structure and the initial control gate layer 219. The initial control gate dielectric layer 218 is formed by etching the control gate dielectric material layer 209, and the initial control gate layer 219 is formed by etching the control gate material layer 210.

[0099] Please continue to refer to this. Figure 13 Ion implantation is performed on the storage region I at the bottom of the fourth groove to form a first doped region 217 within the storage region I at the bottom of the fourth groove.

[0100] The implanted ions for ion implantation in the storage region I at the bottom of the fourth groove include N-type ions or P-type ions. When the device structure formed by the storage region I is N-type, that is, the channel type is N-type, the implanted ions are P-type ions; when the device structure formed by the storage region I is P-type, that is, the channel type is P-type, the implanted ions are N-type ions.

[0101] The N-type ions include one or more combinations of phosphorus ions, arsenic ions, and antimony ions; the P-type ions include one or more combinations of boron ions, borofluorine ions, and indium ions.

[0102] In this embodiment, the implanted ions for ion implantation into the storage area I at the bottom of the fourth groove include P-type ions, and the P-type ions include boron ions.

[0103] Please continue to refer to this. Figure 13 After the first doped region 217 is formed, a fourth sidewall 220 is formed on the sidewall of the fourth groove and the sidewall of the second sidewall 215.

[0104] The fourth sidewall 220 is used for the electrically isolated source line structure 221 and the initial floating gate structure, and the fourth sidewall 220 and the second sidewall 215 are used for the electrically isolated source line structure and the initial control gate structure.

[0105] The method for forming the fourth sidewall 220 includes: forming a sidewall material layer on the fourth groove sidewall, the second sidewall 215 sidewall, and the second hard mask material layer 211; etching back the sidewall material layer until the surface of the storage area I and the surface of the second hard mask material layer 211 are exposed, thereby forming the fourth sidewall 220 on the fourth groove sidewall and the second sidewall 215 sidewall.

[0106] The process for forming the sidewall material layer includes furnace tube process or deposition process.

[0107] The material of the fourth sidewall 220 includes a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide, and silicon carbide.

[0108] In this embodiment, the material of the fourth sidewall 220 includes silicon oxide.

[0109] In this embodiment, the material of the fourth sidewall 220 is the same as the material of the first sidewall 214 and the second sidewall 215.

[0110] In other embodiments, the material of the fourth sidewall may be different from the materials of the first and second sidewalls.

[0111] Please continue to refer to this. Figure 13 An initial source line structure is formed within the fourth groove, the third groove, and the second groove. A portion of the initial source line structure is removed, and a source line structure 221 is formed within the fourth groove, the third groove, and the second groove. The top surface of the source line structure 221 is lower than the top surface of the first sidewall 214, and the top surface of the source line structure 221 is higher than the top surface of the initial control gate structure. The fourth sidewall 220 is located between the source line structure 221 and the initial floating gate structure, and the fourth sidewall 220 and the second sidewall 215 are located between the source line structure 221 and the initial control gate structure. A protective layer 216 is formed on top of the source line structure 221, and the top surface of the protective layer 216 is flush with the top surface of the first sidewall 214.

[0112] In this embodiment, the source line structure 221 is electrically connected to the first doped region 217.

[0113] In this embodiment, the top surface of the initial source line structure is flush with the top surface of the first sidewall 214. The method for forming the initial source line structure includes: forming a source line structure material layer in the second groove, the third groove, the fourth groove, and the surface of the second hard mask material layer 211; planarizing the source line structure material layer until the surface of the protective layer 216, the surface of the second sidewall 215, the surface of the first sidewall 214, and the surface of the second hard mask material layer 211 are exposed, and forming the initial source line structure in the second groove, the third groove, and the fourth groove.

[0114] In this embodiment, the source line structure 221 includes: a source dielectric layer located on the surface of storage region I and a source electrode layer located on the source dielectric layer. The source line structure material layer includes: a source dielectric layer located on the surface of storage region I and a source electrode material layer located on the source dielectric layer.

[0115] In this embodiment, the material of the source dielectric layer includes silicon oxide, and the process for forming the source dielectric layer is an oxidation process; the material of the source electrode layer is polycrystalline silicon, and the process for forming the source electrode material layer includes a furnace tube process or a deposition process.

[0116] The process for removing part of the initial source line structure includes a back etching process.

[0117] In this embodiment, the material of the protective layer 216 is the same as the material of the first sidewall 214 and the second sidewall 215.

[0118] In other embodiments, the material of the protective layer may be different from the materials of the first sidewall and the second sidewall.

[0119] In this embodiment, the top surface of the protective layer 216 is flush with the top surface of the first sidewall 214 and the top surface of the second sidewall 215.

[0120] In other embodiments, the top surface of the protective layer may not be flush with the top surface of the first sidewall and the top surface of the second sidewall.

[0121] In other embodiments, the top surface of the source line structure is flush with the top surface of the first sidewall, so that the protective layer is not formed, or the protective layer is located on the source line structure, the first sidewall, and the second sidewall.

[0122] Please refer to Figure 14 After forming the source line structure 221, the second hard mask material layer 211 on the storage region I and the capacitor region II is removed; the second hard mask material layer 211 exposes the surface of the initial control gate structure of the first sidewall 214.

[0123] The process for removing the second hard mask material layer 211 includes a wet etching process or a dry etching process.

[0124] Please refer to Figure 15 After removing the second hard mask material layer 211, the initial control gate structure and the initial floating gate structure exposed by the second hard mask material layer 211 are etched using the first sidewall 214 as a mask until the surface of the storage area I is exposed, forming the floating gate structure and the control gate structure located on the floating gate structure.

[0125] The control gate structure is formed by etching the initial control gate structure, which is formed by etching the control gate structure material layer; the floating gate structure is formed by etching the initial floating gate structure, which is formed by etching the floating gate structure material layer.

[0126] In this embodiment, the floating gate structure includes a floating gate dielectric layer 222 and a floating gate layer 223. The floating gate dielectric layer 222 is located between the floating gate layer 223 and the memory region I. The floating gate layer 223 is formed after etching the initial floating gate layer 205, and the floating gate dielectric layer 222 is formed after etching the initial floating gate dielectric layer 204.

[0127] In this embodiment, the control gate structure includes a control gate dielectric layer 224 and a control gate layer 225. The control gate dielectric layer 224 is located between the control gate layer 225 and the floating gate structure. The control gate layer 225 is formed by etching the initial control gate layer 219, and the control gate dielectric layer 224 is formed by etching the initial control gate dielectric layer 218.

[0128] Using the first sidewall 214 as a mask, the initial control gate structure and the initial floating gate structure exposed by the second hard mask material layer 211 are etched. Specifically, the initial control gate structure and the initial floating gate structure are also etched using the second sidewall 215 and the protective layer 216 as masks. During the etching of the initial control gate structure and the initial floating gate structure in memory region I, the process also includes forming a mask located in capacitor region II to protect the first electrode plate 213 in capacitor region II from damage caused by the etching process.

[0129] The process of etching the initial control gate structure and the initial floating gate structure exposed by the second hard mask material layer 211 using the first sidewall 214 as a mask includes a dry etching process.

[0130] In this embodiment, the top surface of the first isolation structure 207 is lower than the top surface of the floating gate structure, so that the control gate structure formed above the floating gate structure and the first isolation structure 207 is also located on part of the sidewall of the floating gate structure. The control gate structure can surround the floating gate structure, increase the coupling area between the control gate structure and the floating gate structure, and improve the coupling efficiency.

[0131] Please refer to Figure 16 A third sidewall 226 is formed on the sidewalls of the floating grid structure and the control grid structure.

[0132] In this embodiment, the third sidewall 226 is also located on the sidewall of the first sidewall 214, and the third sidewall 226 is located on the side of the floating grid structure and the control grid structure away from the source line structure 221.

[0133] The method for forming the third sidewall 226 includes: forming a sidewall material layer on the sidewall of the floating gate structure, the sidewall of the control gate structure, the sidewall and top of the first sidewall 214, the top of the second sidewall 215, the top of the protective layer 216 and the surface of the storage area I, and the surface of the first electrode plate 213 of the capacitor area II; etching back the sidewall material layer until the surface of the storage area I, the top surface of the first sidewall 214, the top surface of the second sidewall 215 and the top surface of the protective layer 216 are exposed, thereby forming the third sidewall 226 on the sidewalls of the floating gate structure and the control gate structure.

[0134] During the re-etching of the sidewall material layer, the entire sidewall material layer located in capacitor region II is removed.

[0135] The process for forming the sidewall material layer includes furnace tube process or deposition process.

[0136] The material of the third sidewall 226 includes a dielectric material, which includes one or more combinations of silicon oxide, silicon nitride, silicon carbide, silicon carbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide, and silicon carbide.

[0137] In this embodiment, the material of the third sidewall 226 includes silicon oxide.

[0138] Next, a word line grid structure is formed on the sidewalls of the floating grid structure and the control grid structure, and a dielectric layer and a second electrode plate are formed on the first electrode plate. Please refer to [reference needed] for the formation process of the word line grid structure. Figure 17 and Figure 18 .

[0139] Please refer to Figure 17 A word line gate material layer is formed on the sidewall of the floating gate structure, the sidewall of the control gate structure, the sidewall and top of the first sidewall 214, the top of the second sidewall 215, the top of the protective layer 216 and the surface of the storage area I, and the surface of the first electrode plate 213 of the capacitor area II.

[0140] The word line gate material layer includes: a word line gate dielectric material layer 227 and a word line gate material layer 228 located on the word line gate dielectric material layer 227.

[0141] The word line gate dielectric material layer 227 is made of silicon oxide, and the process for forming the word line gate dielectric material layer 227 includes an oxidation process, a furnace tube process, or a deposition process; the word line gate material layer 228 is made of polysilicon, and the process for forming the word line gate material layer 228 includes a furnace tube process or a deposition process.

[0142] In this embodiment, the process of forming the word line gate dielectric material layer 227 includes an oxidation process, and the word line gate dielectric material layer 227 is located only on the surface of the memory area I.

[0143] In this embodiment, the word line gate material layer is also formed on the first electrode plate 213 of the capacitor region II.

[0144] Please refer to Figure 18 The word line gate material layer on the memory region I is etched back until the surface of the memory region I, the top surface of the first sidewall 214, the top surface of the second sidewall 215, and the top surface of the protective layer 216 are exposed, forming a word line gate structure on the sidewalls of the floating gate structure and the control gate structure.

[0145] The word line gate structure includes: a word line gate dielectric layer 229 and a word line gate layer 230 located on the word line gate dielectric layer 229. The third sidewall 226 is located between the word line gate structure and the floating gate structure and the control gate structure, and the third sidewall 226 electrically isolates the word line gate structure from the floating gate structure and the control gate structure.

[0146] In this embodiment, the word line gate dielectric layer 229 is located on the surface of memory area I.

[0147] In other embodiments, the word line grid dielectric layer is also located on the surface of a third sidewall.

[0148] Please continue to refer to this. Figure 18 During the process of etching the word line gate material layer on the memory region I, the method further includes: patterning the word line gate structure material layer on the capacitor region II, forming the word line gate dielectric material layer 227 into a dielectric layer 231, and forming the word line gate material layer 228 into a second electrode plate 232.

[0149] The second electrode plate 232, the dielectric layer 231 and the first electrode plate 213 constitute a capacitor structure.

[0150] In this embodiment, the capacitor structure formed by the first electrode plate 213, the dielectric layer, and the second electrode plate 232 has a dielectric layer 212 and a second isolation structure 208 between it and the capacitor region II. The capacitor structure has a large gap with the substrate 200, so that the capacitor structure and the substrate 200 are less likely to generate large parasitic capacitance, thereby improving the performance of the capacitor structure.

[0151] In this embodiment, the second electrode plate 232 and the dielectric layer 231 expose the surface of the first electrode plate 213 so as to form an electrical connection structure in the future, so that the first electrode plate 213 is electrically connected to the external circuit.

[0152] In other embodiments, the word line gate structure material layer on the capacitor region can be formed as a dielectric layer without patterning, and the word line gate material layer can be formed as a second electrode plate.

[0153] It should be noted that the material of the patterned mask layer mentioned in the article is photoresist, which is removed after the etching process is completed.

[0154] Thus, the semiconductor structure formed, the process of forming the capacitor structure in capacitor region II can be integrated with the process of forming the memory device in memory region I. That is, the capacitor structure can be formed using the process of forming the memory device in memory region, without additional process steps, without increasing the number of photomasks, the process of forming the capacitor structure is simple and easy to mass produce.

[0155] Accordingly, embodiments of the present invention also provide a semiconductor structure, please refer to [the relevant documentation]. Figure 18 ,include: Substrate 200, the substrate 200 including storage region I and capacitor region II; A floating gate structure, a control gate structure, and a source line structure 221 are located on storage area I. The control gate structure is located on the floating gate structure and exposes a portion of the surface of the floating gate structure. The floating gate structure exposes a portion of the surface of storage area I. The source line structure 221 is located on the storage area I exposed by the floating gate structure. The character line grid structure located on the side wall of the floating grid structure; The first electrode plate 213 is located on the capacitor region II and is formed during the formation of the control gate structure; A dielectric layer 231 and a second electrode plate 232 are stacked sequentially on a first electrode plate 213, and the dielectric layer 231 and the second electrode plate 232 are formed during the formation of a word grid structure.

[0156] The semiconductor structure is such that the first electrode plate 213 is formed during the formation of the control gate structure, and the dielectric layer 231 and the second electrode plate 232 are formed during the formation of the word line gate structure. Thus, the capacitor structure composed of the first electrode plate 213, the dielectric layer 231, and the second electrode plate 232 can be integrated with the formation process of the memory device of the memory region I. That is, the capacitor structure can be formed using the process of forming the memory device of the memory region. The capacitor structure and the memory structure of the memory region I can be integrated on a single chip, which facilitates circuit design and saves chip area.

[0157] In this embodiment, it further includes: a first isolation structure located within the storage region I, wherein adjacent floating gate structures are isolated from each other by the first isolation structure, and the first isolation structure protrudes from the surface of the storage region I; and a second isolation structure 208 located on the capacitor region II, wherein the second isolation structure 208 is located between the first electrode plate 213 and the capacitor region II.

[0158] In this embodiment, the height of the first isolation structure is lower than the top surface of the floating gate structure.

[0159] In this embodiment, it further includes: a second sidewall 215 located between the source line structure 221 and the control gate structure, the second sidewall 215 being located on the floating gate structure, and the top of the second sidewall 215 being higher than the top of the control gate structure; a first sidewall 214 located at the top of the control gate structure, and the second sidewall 215 being located between the first sidewall 214 and the source line structure 221.

[0160] In this embodiment, it further includes a fourth sidewall 220 located between the source line structure 221 and the floating grid structure, and the fourth sidewall 220 is also located on the side wall of the second sidewall 215.

[0161] In this embodiment, the top of the source line structure 221 is lower than the top of the second side wall 215, and it also includes a protective layer 216 located on the top of the source line structure 221, the top of the protective layer 216 being flush with the top of the second side wall 215.

[0162] In this embodiment, it further includes: a first doped region 217 located within the portion of the memory region I exposed by the floating gate structure; the source line structure 221 is electrically connected to the first doped region 217.

[0163] In this embodiment, it further includes a third sidewall 226 located on the sidewalls of the floating grid structure and the control grid structure, the third sidewall 226 being located between the floating grid structure and the control grid structure and the word line grid structure.

[0164] In this embodiment, the control gate structure includes a control gate dielectric layer 224 and a control gate layer 225 located on the control gate dielectric layer 224, and the first electrode plate 213 is formed during the formation of the control gate layer 225.

[0165] In this embodiment, the word line gate structure includes: a word line gate dielectric layer 229 and a word line gate layer 230 located on the word line gate dielectric layer 229. The dielectric layer 231 is formed during the formation of the word line gate dielectric layer 229, and the second electrode plate 232 is formed during the formation of the word line gate layer 230.

[0166] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: Substrate, the substrate including a storage region and a capacitor region; A floating gate structure, a control gate structure, and a source line structure are located on a storage area. The control gate structure is located on the floating gate structure and exposes a portion of the surface of the floating gate structure. The floating gate structure exposes a portion of the surface of the storage area, and the source line structure is located on the storage area exposed by the floating gate structure. The character line grid structure located on the side wall of the floating grid structure; A first electrode plate located on the capacitor region is formed during the formation of the control gate structure; A dielectric layer and a second electrode plate are stacked sequentially on a first electrode plate, and the dielectric layer and the second electrode plate are formed during the formation of a word line grid structure.

2. The semiconductor structure as described in claim 1, characterized in that, Also includes: A first isolation structure is located within the storage area, and adjacent floating gate structures are isolated from each other by the first isolation structure, the first isolation structure protruding from the surface of the storage area; A second isolation structure is located on the capacitor region, between the first electrode plate and the capacitor region.

3. The semiconductor structure as described in claim 2, characterized in that, The height of the first isolation structure is lower than the top surface of the floating gate structure.

4. The semiconductor structure as described in claim 1, characterized in that, Also includes: A second sidewall is located between the source line structure and the control gate structure, the second sidewall is located on the floating gate structure, and the top of the second sidewall is higher than the top of the control gate structure; A first sidewall is located on top of the control grid structure, and a second sidewall is located between the first sidewall and the source line structure.

5. The semiconductor structure as described in claim 4, characterized in that, The top of the source line structure is lower than the top of the second side wall, and it also includes a protective layer located on top of the source line structure, the top of which is flush with the top of the second side wall.

6. The semiconductor structure as described in claim 4, characterized in that, Also includes: A fourth sidewall is located between the source line structure and the floating grid structure, and the fourth sidewall is also located on the side wall of the second sidewall.

7. The semiconductor structure as described in claim 1, characterized in that, Also includes: The first doped region is located within the portion of the memory region exposed by the floating gate structure; The source line structure is electrically connected to the first doped region.

8. The semiconductor structure as described in claim 1, characterized in that, Also includes: A third sidewall is located on the sidewalls of the floating grid structure and the control grid structure, between the floating grid structure and the control grid structure and the word line grid structure.

9. The semiconductor structure as described in claim 1, characterized in that, The control gate structure includes a control gate dielectric layer and a control gate layer located on the control gate dielectric layer, wherein the first electrode plate is formed during the formation of the control gate layer.

10. The semiconductor structure as claimed in claim 1, characterized in that, The word line gate structure includes: a word line gate dielectric layer and a word line gate layer located on the word line gate dielectric layer. The dielectric layer is formed during the formation of the word line gate dielectric layer, and the second electrode plate is formed during the formation of the word line gate layer.

11. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a storage region and a capacitor region; An initial floating gate structure is formed on the storage area; A control gate structure material layer is formed on the memory region, and the control gate structure material layer is located on the side of the initial floating gate structure away from the memory region; A first electrode plate is formed on the capacitor region, and the first electrode plate is formed during the formation of the control gate structure material layer; A floating gate structure, a control gate structure, and a source line structure are formed on the memory region. The control gate structure is located on the floating gate structure. The control gate structure and the floating gate structure are formed based on the material layers of the initial floating gate structure and the control gate structure. The control gate structure exposes a portion of the surface of the floating gate structure. The floating gate structure exposes a portion of the surface of the memory region. The source line structure is located on the memory region exposed by the floating gate structure. A word line grid structure is formed on the sidewalls of the floating grid structure and the control grid structure; A dielectric layer and a second electrode plate are sequentially formed on the first electrode plate, and the dielectric layer and the second electrode plate are formed during the formation of the word line grid structure.

12. The method for forming a semiconductor structure as described in claim 11, characterized in that, Before forming a control gate structure material layer on the storage region and forming a first electrode plate on the capacitor region, the method further includes: forming a first isolation structure located within the storage region, wherein adjacent initial floating gate structures are isolated from each other by the first isolation structure, and the first isolation structure protrudes from the surface of the storage region.

13. The method for forming a semiconductor structure as described in claim 12, characterized in that, The method for forming the initial floating gate structure and the first isolation structure includes: forming a floating gate structure material layer on the storage region and the capacitor region; forming a first hard mask material layer on the floating gate structure material layer; removing a portion of the first hard mask material layer, a portion of the floating gate structure material layer, and a portion of the storage region, forming a first groove in the storage region that penetrates the first hard mask material layer and the floating gate structure material layer and extends into the storage region; forming an initial isolation structure in the first groove; removing a portion of the initial isolation structure to form the first isolation structure; and removing the first hard mask material layer.

14. The method for forming a semiconductor structure as described in claim 13, characterized in that, While removing part of the first hard mask material layer, part of the floating gate structure material layer, and part of the storage area, the process also includes: removing the first hard mask material layer, the floating gate structure material layer, and part of the capacitor area; forming an initial isolation structure in the groove; and forming a second isolation structure on the capacitor area, wherein the second isolation structure is located between the first electrode plate and the capacitor area.

15. The method for forming a semiconductor structure as described in claim 12, characterized in that, The top surface of the first isolation structure is lower than the top surface of the initial floating gate structure.

16. The method for forming a semiconductor structure as described in claim 11, characterized in that, A method for forming a floating gate structure, a control gate structure, and a source line structure in the storage region includes: forming a second hard mask material layer on the control gate structure material layer and a first electrode plate; removing a portion of the second hard mask material layer on the storage region, forming a second groove within the second hard mask material layer, the second groove exposing a portion of the surface of the control gate structure material layer; forming a first sidewall on the sidewall of the second groove; etching the control gate structure material layer exposed by the second groove using the first sidewall as a mask until the surface of the initial floating gate structure is exposed, forming an initial control gate structure; forming a third groove at the bottom of the second groove; forming a second sidewall on the sidewall of the third groove, the second sidewall being located on the sidewall of the initial control gate structure and the sidewall of the first sidewall; etching the initial floating gate structure using the second sidewall as a mask until the surface of the storage region is exposed, forming a fourth groove within the initial floating gate structure; and forming a source line structure within the second groove, the third groove, and the fourth groove.

17. The method for forming a semiconductor structure as described in claim 16, characterized in that, Before forming the source line structure in the fourth groove, the method further includes: performing ion implantation on the storage region at the bottom of the fourth groove to form a first doped region in the storage region; the source line structure is electrically connected to the first doped region.

18. The method for forming a semiconductor structure as described in claim 16, characterized in that, The top surface of the source line structure is lower than the top surface of the first sidewall, and the top surface of the source line structure is higher than the top surface of the initial control gate structure; The method for forming the source line structure includes: forming an initial source line structure in the second groove, the third groove and the fourth groove, wherein the top surface of the initial source line structure is flush with the top surface of the first sidewall. Remove part of the initial source line structure to form the source line structure.

19. The method for forming a semiconductor structure as described in claim 16, characterized in that, After forming the source line structure, the method further includes: forming a protective layer on top of the source line structure, wherein the top surface of the protective layer is flush with the top surface of the first sidewall.

20. The method for forming a semiconductor structure as described in claim 16, characterized in that, The method for forming the floating gate structure and the control gate structure in the storage area further includes: removing a second hard mask material layer on the storage area and the capacitor area; after removing the second hard mask material layer, using the first sidewall as a mask, etching the initial control gate structure and the initial floating gate structure until the surface of the storage area is exposed, forming the floating gate structure and the control gate structure located on the floating gate structure.

21. The method for forming a semiconductor structure as described in claim 11, characterized in that, The method for forming the word line gate structure, dielectric layer, and second electrode plate includes: forming a word line gate structure material layer on the memory region and the capacitor region, the word line gate structure material layer including a word line gate dielectric material layer and a word line gate material layer located on the word line gate dielectric material layer; etching back the word line gate structure material layer on the memory region to form a word line gate structure on the sidewalls of the floating gate structure and the control gate structure.

22. The method for forming a semiconductor structure as described in claim 21, characterized in that, The method for forming the dielectric layer and the second electrode plate further includes: patterning the word line gate structure material layer on the capacitor region, forming the word line gate dielectric material layer as a dielectric layer, and forming the word line gate material layer as a second electrode plate.

23. The method for forming a semiconductor structure as described in claim 21, characterized in that, Before forming a word line gate structure material layer on the memory region and the capacitor region, the method further includes: forming a third sidewall on the sidewalls of the floating gate structure and the control gate structure, the third sidewall being located between the floating gate structure and the control gate structure and the word line gate structure.

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