Method of manufacturing a flash memory device

Abstract

The application provides a preparation method of a flash memory device. After an opening is formed in a hard mask layer of a peripheral logic region, a first thickness of a polysilicon material layer of the peripheral logic region is etched, then main etching is performed in two stages to etch a second thickness of the polysilicon material layer and form a trench, then auxiliary etching is performed to etch a third thickness of the polysilicon material layer and modify the profile of the trench, and finally over-etching is performed to etch a remaining thickness of the polysilicon material layer and form a gate. Through the main etching, the auxiliary etching and the over-etching, the polysilicon material layer of a storage region can be integrally etched and removed, meanwhile, the gate profile of the peripheral logic circuit region and the trench profile / shape between the gates can meet the process requirements, the process flow is simplified, and the device performance is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and specifically to a method for preparing a flash memory device. Background Technology

[0002] In the manufacturing process of flash memory devices, floating gates (FG) and control gates (CG) are usually formed in the storage area first, and then the gate structure is formed in the peripheral logic circuit area.

[0003] Traditional flash memory device fabrication typically involves two processes: 1) MCEL-ET: removing the storage area and depositing polysilicon, and 2) GPL-ET: etching polysilicon in the peripheral logic circuit area to form the control gate. Current improved flash memory device fabrication processes integrate these two processes into one.

[0004] However, the difficulty of this integrated process lies in the fact that the polysilicon material layer of the memory region is deposited on the word line polysilicon, resulting in poor overall uniformity of the polysilicon material layer. At the same time, the overall height of the memory region is higher than that of the peripheral logic circuit region. On the basis of completely etching the polysilicon material layer of the memory region, the gate of the peripheral logic circuit region and the trench contour between the gates need to meet the requirements. Summary of the Invention

[0005] This application provides a method for fabricating a flash memory device, which can solve the problem of the inability to balance the overall uniformity of the polysilicon material layer on the word line polysilicon of the storage region and the gate morphology and trench contour between the gates in the peripheral logic circuit region.

[0006] This application provides a method for fabricating a flash memory device, including: A substrate is provided, the substrate comprising: a memory region, a lead-out region, and a peripheral logic region, wherein memory cells are formed on the substrate of the memory region, and the top of the memory cells is covered with a polysilicon material layer; stacked ONO film, control gate material layer, dielectric layer, and polysilicon material layer are formed on the substrate of the lead-out region; and a pad oxide layer, polysilicon material layer, and hard mask layer are formed on the substrate of the peripheral logic region. A photoresist layer is coated on the polysilicon material layer of the storage area, the lead-out area, and the hard mask layer of the peripheral lead-out area; The gate pattern is defined on the photoresist layer through photolithography, forming a patterned photoresist layer; Using a patterned photoresist layer as a mask, the hard mask layer of the peripheral logic region is etched down to the surface of the polysilicon material layer to form an opening; Remove the patterned photoresist layer; The hard mask layer, with a portion of its thickness between the openings of the peripheral logic region, is etched away, and the polysilicon material layer of a first thickness is etched according to the openings. The main etching is performed in two stages to remove the second thickness of the polysilicon material layer of the peripheral logic region to form trenches in the polysilicon material layer. The gases involved in the etching include at least SF6 and CH2F2. The radio frequency power of the first stage is greater than that of the second stage. A secondary etching process is performed to etch the polysilicon material layer of the third thickness of the peripheral logic region and modify the contour of the trench. In the secondary etching process, the gases involved in the etching include at least HBr, He and O2. Over-etching is performed to etch the remaining thickness of the polysilicon material layer of the peripheral logic region down to the surface of the pad oxide layer to form a gate, wherein the gases involved in the over-etching process include at least: HBr, N2 and O2; Remove the remaining thickness of the hard mask layer at the top of the gate.

[0007] Optionally, in the method for fabricating the flash memory device, in the first stage of the main etching, the radio frequency power is not less than 600W and the bias voltage is not less than 250V; In the second stage of the main etching, the radio frequency power is not less than 600W and the bias voltage is not less than 250V.

[0008] Optionally, in the method for fabricating the flash memory device, during the main etching process, the flow rate ratio of SF6 and CH2F2 is 1:1.2; and the total flow rate of all gases involved in the etching does not exceed 150 sccm.

[0009] Optionally, in the method for fabricating the flash memory device, during the auxiliary etching process, the flow rate of HBr is not less than 150 sccm, the proportion of He in the total gas participating in etching is greater than 10% and not more than 25%, and the proportion of O2 in the total gas participating in etching is not more than 5%, so that the etching selectivity ratio of the polycrystalline silicon material layer to the dielectric layer is 8:1.

[0010] Optionally, in the method for fabricating the flash memory device, during the over-etching process, the pressure in the process chamber is not less than 50 mT; the bias voltage is not less than 200 V; the flow ratio of HBr and N2 is 1:1; and the proportion of O2 in the total gas participating in the etching does not exceed 3%, so as to increase the etching selectivity between the polysilicon material layer and the dielectric layer.

[0011] Optionally, in the method for fabricating the flash memory device, a first-thickness polycrystalline silicon material layer is removed from the upper surface of the dielectric layer of the storage region and the lead-out region during the main etching process.

[0012] Optionally, in the method for fabricating the flash memory device, a second-thickness polycrystalline silicon material layer is removed from the upper surface of the dielectric layer of the storage region and the lead-out region during the auxiliary etching process.

[0013] Optionally, in the method for fabricating the flash memory device, during the etching process, the remaining thickness of the polycrystalline silicon material layer on the upper surface of the dielectric layer of the storage region and the lead-out region is removed.

[0014] The technical solution of this application has at least the following advantages: This application provides a method for fabricating a flash memory device. After forming an opening in the hard mask layer of the peripheral logic region, a polysilicon material layer of a first thickness in the peripheral logic region is etched. Then, a two-stage main etching process is performed to etch a second-thickness polysilicon material layer, forming trenches. Next, an auxiliary etching process is performed to etch a third-thickness polysilicon material layer and refine the trench contours. Finally, over-etching is performed to etch the remaining thickness of the polysilicon material layer, forming the gate. This application, through main etching, auxiliary etching, and over-etching, can integrally etch and remove the polysilicon material layer of the memory region, while ensuring that the gate morphology of the peripheral logic circuit region meets process requirements, and that the trench contours / morphology between gates also meet process requirements. This achieves a balance between the overall uniformity of the polysilicon material layer on the word line polysilicon of the memory region and the absence of defects in the gate morphology and trench contours between gates in the peripheral logic circuit region. It also simplifies the process flow and improves device performance. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0016] Figure 1 This is a flowchart of a method for fabricating a flash memory device according to an embodiment of the present invention; Figures 2-6 This is a schematic diagram of the semiconductor structure in each process step of fabricating a flash memory device according to an embodiment of the present invention; The reference numerals in the attached figures are explained as follows: 10-Substrate, 11-Shallow trench isolation structure, 20-Pad oxide layer, 30-Floating gate material layer, 40-ONO film layer, 50-Control gate material layer, 60-Dielectric layer, 70-Word line polysilicon, 80-Polysilicon material layer, 81-Trench, 82-Gate, 90-Hard mask layer, 91-Opening. Detailed Implementation

[0017] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0018] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0019] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0020] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0021] This application provides a method for fabricating a flash memory device, referring to... Figure 1 , Figure 1 This is a flowchart of a method for fabricating a flash memory device according to an embodiment of the present invention. The method for fabricating the flash memory device includes: First, perform step S1: Refer to Figure 2 , Figure 2 This is a schematic diagram of a semiconductor structure after an opening is formed in the hard mask layer according to an embodiment of this application. A substrate 10 is provided, which includes a memory region, an exit region, and a peripheral logic region. A memory cell is formed on the substrate 10 of the memory region, and the top of the memory cell is covered with a polysilicon material layer 80. Stacked ONO film layer 40, control gate material layer 50, dielectric layer 60, and polysilicon material layer 80 are formed on the substrate 10 of the exit region. A pad oxide layer 20, polysilicon material layer 80, and hard mask layer 90 are formed on the substrate 10 of the peripheral logic region.

[0022] In this embodiment, the memory cell is isolated by a shallow trench isolation structure 11. The memory cell typically includes: a pad oxide layer 20, a floating gate material layer 30, an ONO film layer 41, a control gate material layer 50, and a dielectric layer 60 on top of the control gate material layer 50. The memory cell may also include: a word line polysilicon layer 70, which is located in the stacked floating gate material layer 30, ONO film layer 41, control gate material layer 50, and dielectric layer 60.

[0023] It is worth noting that this application does not impose any restrictions on the specific film structure of the storage cell, and it can be a conventional storage cell structure in traditional flash memory devices.

[0024] In this embodiment, the ONO dielectric layer includes: a stacked top silicon oxide layer, a silicon nitride layer, and a bottom silicon oxide layer.

[0025] Furthermore, the dielectric layer 60 can be made of silicon oxide.

[0026] Then, step S2 is performed: a photoresist layer (not shown) is coated on the polysilicon material layer 70 of the storage area and the lead-out area and the hard mask layer 90 of the peripheral lead-out area.

[0027] Next, step S3 is performed: a gate pattern is defined on the photoresist layer through photolithography to form a patterned photoresist layer.

[0028] Further, step S4 is performed: using a patterned photoresist layer as a mask, the hard mask layer 90 of the peripheral logic area is etched to the surface of the polysilicon material layer 80 to form an opening 91.

[0029] Next, step S5 is performed: the patterned photoresist layer is removed.

[0030] Further, proceed to step S6: Refer to Figure 3 , Figure 3 This is a schematic diagram of the semiconductor structure after etching the polysilicon material layer of the first thickness according to an embodiment of this application. The hard mask layer 90 with a portion of the thickness of the top of the polysilicon material layer 80 between the openings 91 of the peripheral logic region is etched away, and the polysilicon material layer 80 of the first thickness is etched according to the openings 91.

[0031] Next, proceed to step S7: (Refer to...) Figure 4 , Figure 4This is a schematic diagram of the semiconductor structure after etching the second thickness of the polysilicon material layer according to an embodiment of this application. The main etching is performed in two stages to etch away the second thickness of the polysilicon material layer 80 of the peripheral logic region to form trenches 81 in the polysilicon material layer 80. The gases involved in the etching include at least SF6 and CH2F2. The radio frequency power of the first stage is greater than that of the second stage.

[0032] In the first stage of the main etching, the radio frequency power is not less than 600W and the bias voltage is not less than 250V; in the second stage of the main etching, the radio frequency power is not less than 600W and the bias voltage is not less than 250V.

[0033] This application divides the main etching process into two stages and gradually reduces the bias voltage, which can reduce damage to the polysilicon material layer while improving the selective etching ratio of the polysilicon material layer and the dielectric layer.

[0034] Preferably, during the main etching process, the flow rate ratio of SF6 and CH2F2 is 1:1.2; and the total flow rate of all gases involved in the etching does not exceed 150 sccm.

[0035] During the main etching process, a polysilicon material layer 80 of the first thickness on the upper surface of the dielectric layer of the storage area and the lead-out area is removed.

[0036] Further, proceed to step S8: (Refer to...) Figure 5 , Figure 5 This is a schematic diagram of the semiconductor structure after etching the polysilicon material layer of the third thickness according to an embodiment of this application. Auxiliary etching is performed to etch the polysilicon material layer 80 of the third thickness of the peripheral logic region and modify the contour of the trench 81. In the auxiliary etching process, the gases involved in the etching include at least: HBr, He and O2.

[0037] Preferably, during the auxiliary etching process, the flow rate of HBr is not less than 150 sccm, the proportion of He in the total gas participating in the etching is greater than 10% and not more than 25%, and the proportion of O2 in the total gas participating in the etching is not more than 5%, so that the etching selectivity ratio of the polycrystalline silicon material layer to the dielectric layer is 8:1, that is, the etching amount of the polycrystalline silicon material layer is 8 times that of the dielectric layer.

[0038] During the auxiliary etching process, a second-thickness polysilicon material layer 80 is removed from the upper surface of the dielectric layer of the storage region and the lead-out region.

[0039] Next, proceed to step S9: (Refer to...) Figure 6 , Figure 6This is a schematic diagram of the semiconductor structure after etching the remaining thickness of the polysilicon material layer according to an embodiment of this application. Over-etching is performed to etch the remaining thickness of the polysilicon material layer 80 of the peripheral logic region to the surface of the pad oxide layer 20 to form the gate 82. In the over-etching process, the gases involved in the etching include at least HBr, N2 and O2.

[0040] Preferably, the ratio of the first thickness, the second thickness, and the third thickness of the removed polycrystalline silicon material layer is 7:2:1.

[0041] Preferably, during the over-etching process, the pressure in the process chamber is not less than 50 mT; the bias voltage is not less than 200 V; the flow ratio of HBr and N2 is 1:1; and the proportion of O2 in the total gas participating in the etching does not exceed 3%, so as to increase the etching selectivity ratio between the polycrystalline silicon material layer 80 and the dielectric layer 60.

[0042] During the etching process, the remaining thickness of the polysilicon material layer 80 on the upper surface of the dielectric layer of the storage area and the lead-out area is removed.

[0043] Finally, step S10 is performed: the remaining thickness of the hard mask layer 90 at the top of the gate 82 is removed.

[0044] In this application, after forming an opening in the hard mask layer of the peripheral logic region, a polysilicon material layer of a first thickness in the peripheral logic region is etched. Then, a two-stage main etching process is performed to etch a second-thickness polysilicon material layer, forming trenches. Next, an auxiliary etching process is performed to etch a third-thickness polysilicon material layer and refine the trench contours. Finally, over-etching is performed to etch the remaining thickness of the polysilicon material layer, forming the gate. This application, through main etching, auxiliary etching, and over-etching, can integrally etch and remove the polysilicon material layer of the memory region, while ensuring that the gate morphology of the peripheral logic circuit region and the trench contours / morphology between gates meet process requirements. This achieves a balance between the overall uniformity of the polysilicon material layer on the word line polysilicon of the memory region and the absence of defects in the gate morphology and trench contours between gates in the peripheral logic circuit region. It also simplifies the process flow and improves device performance.

[0045] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.

Claims

1. A method for fabricating a flash memory device, characterized in that, include: A substrate is provided, the substrate comprising: a memory region, a lead-out region, and a peripheral logic region, wherein memory cells are formed on the substrate of the memory region, and the top of the memory cells is covered with a polysilicon material layer; stacked ONO film, control gate material layer, dielectric layer, and polysilicon material layer are formed on the substrate of the lead-out region; and a pad oxide layer, polysilicon material layer, and hard mask layer are formed on the substrate of the peripheral logic region. A photoresist layer is coated on the polysilicon material layer of the storage area, the lead-out area, and the hard mask layer of the peripheral lead-out area; The gate pattern is defined on the photoresist layer through photolithography, forming a patterned photoresist layer; Using a patterned photoresist layer as a mask, the hard mask layer of the peripheral logic region is etched down to the surface of the polysilicon material layer to form an opening; Remove the patterned photoresist layer; The hard mask layer, with a portion of its thickness between the openings of the peripheral logic region, is etched away, and the polysilicon material layer of a first thickness is etched according to the openings. The main etching is performed in two stages to remove the second thickness of the polysilicon material layer of the peripheral logic region to form trenches in the polysilicon material layer. The gases involved in the etching include at least SF6 and CH2F2. The radio frequency power of the first stage is greater than that of the second stage. A secondary etching process is performed to etch the polysilicon material layer of the third thickness of the peripheral logic region and modify the contour of the trench. In the secondary etching process, the gases involved in the etching include at least HBr, He and O2. Over-etching is performed to etch the remaining thickness of the polysilicon material layer of the peripheral logic region down to the surface of the pad oxide layer to form a gate, wherein the gases involved in the over-etching process include at least: HBr, N2 and O2; Remove the remaining thickness of the hard mask layer at the top of the gate.

2. The method for fabricating a flash memory device according to claim 1, characterized in that, In the first stage of the main etching, the radio frequency power is not less than 600W and the bias voltage is not less than 250V. In the second stage of the main etching, the radio frequency power is not less than 600W and the bias voltage is not less than 250V.

3. The method for fabricating a flash memory device according to claim 1, characterized in that, During the main etching process, the flow rate ratio of SF6 and CH2F2 is 1:1.2; the total flow rate of all gases involved in the etching does not exceed 150 sccm.

4. The method for fabricating a flash memory device according to claim 1, characterized in that, During the auxiliary etching process, the flow rate of HBr is not less than 150 sccm, the proportion of He in the total gas participating in the etching is greater than 10% and not more than 25%, and the proportion of O2 in the total gas participating in the etching is not more than 5%, so that the etching selectivity ratio of the polycrystalline silicon material layer to the dielectric layer is 8:

1.

5. The method for fabricating a flash memory device according to claim 1, characterized in that, During the etching process, the pressure in the process chamber is not less than 50 mT; the bias voltage is not less than 200 V; the flow ratio of HBr and N2 is 1:1; and the proportion of O2 in the total gas participating in the etching does not exceed 3%, so as to increase the etching selectivity between the polycrystalline silicon material layer and the dielectric layer.

6. The method for fabricating a flash memory device according to claim 1, characterized in that, While performing the main etching, the first thickness of the polycrystalline silicon material layer on the upper surface of the dielectric layer of the storage area and the lead-out area is removed.

7. The method for fabricating a flash memory device according to claim 1, characterized in that, While performing auxiliary etching, a second-thickness polycrystalline silicon material layer is removed from the upper surface of the dielectric layer in the storage region and the lead-out region.

8. The method for fabricating a flash memory device according to claim 1, characterized in that, During the etching process, the remaining thickness of the polycrystalline silicon material layer on the upper surface of the dielectric layer in the storage and lead-out areas is removed.

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