Sonos structure device and forming method thereof

Abstract

The present disclosure provides a SONOS structure device and a forming method thereof, wherein the SONOS structure device comprises: a substrate; a stacked gate structure located on the substrate; the stacked gate structure comprises: a first silicon oxynitride blocking layer located on the substrate; a tunneling oxide layer located on the first silicon oxynitride blocking layer; a silicon nitride layer located on the tunneling oxide layer; a second silicon oxynitride blocking layer located on the silicon nitride layer; a blocking oxide layer located on the second silicon oxynitride blocking layer; and a gate layer located on the blocking oxide layer; wherein the thickness of the first silicon oxynitride blocking layer is less than the thickness of the tunneling oxide layer, and the thickness of the second silicon oxynitride blocking layer is less than the thickness of the blocking oxide layer. By using the above technical solution, the interface state can be improved and the leakage current can be reduced.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing technology, and in particular to a SONOS structure device and a method for forming the same. Background Technology

[0002] In semiconductor manufacturing processes, SONOS (silicon-oxide-nitride-oxide-silicon) flash memory devices have become the mainstream type of non-volatile memory due to their excellent scaling characteristics, radiation resistance, and low operating voltage.

[0003] However, as device dimensions continue to shrink, the thickness of the tunneling oxide layer continues to decrease, leading to increased leakage current and severely impacting device reliability and performance. Simultaneously, the high interface state density between the oxide layer and substrate in traditional SONOS structures makes it prone to introducing defects during programming / erasing cycles, generating stress-induced leakage current and further degrading durability and data retention characteristics.

[0004] Therefore, how to provide technical solutions to improve the interface state and reduce leakage current has become an urgent technical problem to be solved. Summary of the Invention

[0005] In view of this, the present disclosure provides a SONOS structure device and a method for forming the same, which can improve interface states and reduce leakage current.

[0006] This disclosure provides a SONOS structure device, including: a substrate; a stacked gate structure located on the substrate; the stacked gate structure includes: a first silicon oxynitride barrier layer located on the substrate; a tunneling oxide layer located on the first silicon oxynitride barrier layer; a silicon nitride layer located on the tunneling oxide layer; a second silicon oxynitride barrier layer located on the silicon nitride layer; a barrier oxide layer located on the second silicon oxynitride barrier layer; and a gate layer located on the barrier oxide layer; wherein the thickness of the first silicon oxynitride barrier layer is less than the thickness of the tunneling oxide layer, and the thickness of the second silicon oxynitride barrier layer is less than the thickness of the barrier oxide layer.

[0007] Optionally, the nitrogen content on the side of the first silicon oxynitride barrier layer closest to the substrate is greater than the nitrogen content on the side closest to the tunneling oxide layer; and / or, the nitrogen content on the side of the second silicon oxynitride barrier layer closest to the silicon nitride layer is greater than the nitrogen content on the side closest to the barrier oxide layer.

[0008] Optionally, the SONOS structure device further includes: a source region and a drain region located in the substrate and spaced apart, and the stacked gate structure is present on the substrate between the source region and the drain region; and sidewalls located on the substrate between the source region and the drain region and on both sides of the stacked gate structure.

[0009] Optionally, the SONOS structure device satisfies one or more of the following: the substrate is monocrystalline silicon; the gate layer is polycrystalline silicon; the thickness of the tunneling oxide layer is 1 nanometer to 5 nanometers; the thickness of the silicon nitride layer is 4 nanometers to 7 nanometers; the thickness of the barrier oxide layer is 3 nanometers to 10 nanometers; and the thickness of the gate layer is 100 nanometers to 200 nanometers.

[0010] Optionally, the SONOS structure device satisfies one or more of the following: the thickness of the first silicon oxynitride barrier layer is 1 to 20 angstroms; the thickness of the second silicon oxynitride barrier layer is 1 to 15 angstroms; and the thickness of the first silicon oxynitride barrier layer is greater than the thickness of the second silicon oxynitride barrier layer.

[0011] Optionally, the stacked gate structure further includes: a third silicon oxynitride barrier layer located on the tunneling oxide layer, and / or a fourth silicon oxynitride barrier layer located on the barrier oxide layer.

[0012] This disclosure also provides a method for forming a SONOS structure device, comprising: providing a substrate; forming a stacked gate structure on the substrate; the step of forming the stacked gate structure includes: forming a first silicon oxynitride barrier layer on the substrate; forming a tunneling oxide layer on the first silicon oxynitride barrier layer; forming a silicon nitride layer on the tunneling oxide layer; forming a second silicon oxynitride barrier layer on the silicon nitride layer; forming a barrier oxide layer on the second silicon oxynitride barrier layer; and forming a gate layer on the barrier oxide layer; wherein the thickness of the first silicon oxynitride barrier layer is less than the thickness of the tunneling oxide layer, and the thickness of the second silicon oxynitride barrier layer is less than the thickness of the barrier oxide layer.

[0013] Optionally, under the same process conditions, the thickness of the second silicon oxynitride barrier layer is less than the thickness of the first silicon oxynitride barrier layer.

[0014] Optionally, the method further includes: forming sidewalls on the substrates on both sides of the stacked gate structure; forming source regions and drain regions spaced apart in the substrates, wherein the stacked gate structure is formed on the substrates between the source regions and the drain regions.

[0015] Optionally, the method further includes: forming a third silicon oxynitride barrier layer on the tunneling oxide layer before forming the silicon nitride layer, the third silicon oxynitride barrier layer being located between the tunneling oxide layer and the silicon nitride layer; and forming a fourth silicon oxynitride barrier layer on the barrier oxide layer before forming the gate layer, the fourth silicon oxynitride barrier layer being located between the barrier oxide layer and the gate layer.

[0016] Compared with the prior art, the technical solution of the present disclosure has the following advantages: The SONOS structure device and its formation method provided in this disclosure include: a substrate; a stacked gate structure located on the substrate; the stacked gate structure includes: a first silicon oxynitride barrier layer located on the substrate; a tunneling oxide layer located on the first silicon oxynitride barrier layer; a silicon nitride layer located on the tunneling oxide layer; a second silicon oxynitride barrier layer located on the silicon nitride layer; a barrier oxide layer located on the second silicon oxynitride barrier layer; and a gate layer located on the barrier oxide layer; wherein the thickness of the first silicon oxynitride barrier layer is less than the thickness of the tunneling oxide layer, and the thickness of the second silicon oxynitride barrier layer is less than the thickness of the barrier oxide layer. By placing a first silicon oxynitride (Soxy) barrier layer with a thickness smaller than that of the tunneling oxide layer between the substrate and the tunneling oxide layer, the nitrogen atoms in the first Soxy barrier layer can passivate the silicon dangling bonds on the substrate surface, significantly reducing the interface state density at the substrate / tunneling oxide interface, thereby reducing leakage current assisted by interface traps. Furthermore, since the thickness of the first Soxy barrier layer is smaller than that of the tunneling oxide layer, it does not significantly increase the equivalent thickness of charge tunneling during programming / erasing, thus improving interface quality without adversely affecting the write / erase efficiency of the device. Finally, the second Soxy barrier layer can optimize the interface between silicon nitride and the barrier oxide layer. The surface quality is improved to suppress the back diffusion of charge from the silicon nitride layer to the barrier oxide layer and reduce stress-induced defects in the barrier oxide layer, thereby further reducing leakage current along the charge loss path. The thicknesses of the first and second silicon nitride barrier layers are both smaller than those of their adjacent main oxide layers (tunneling oxide layer and barrier oxide layer). These two silicon nitride barrier layers function only as ultra-thin interface modification layers and do not alter the original electric field distribution and charge tunneling / blocking mechanism of the entire stacked gate structure. This effectively suppresses interface states and leakage current while maintaining the excellent programming / erasing performance and data retention characteristics of the SONOS device. Therefore, the SONOS structure device can improve interface states and reduce leakage current. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments disclosed in this specification, the drawings used in the description of the embodiments disclosed in this specification or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this specification. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figures 1 to 4 This is a cross-sectional structural schematic diagram of some steps in a method for forming a SONOS structure device according to an embodiment of this disclosure; Figure 5This is a cross-sectional structural schematic diagram of another SONOS structure device in an embodiment of this disclosure; Figure 6 This is a schematic flowchart of a method for forming a SONOS structure device according to an embodiment of this disclosure; Figure 7 This is a flowchart illustrating a method for forming a stacked gate structure of a SONOS structure device according to an embodiment of this disclosure; Figure 8 This is a schematic flowchart of a partial method for forming a SONOS structure device according to an embodiment of this disclosure; Figure 9 This is a flowchart illustrating another method for forming a SONOS structure device in this embodiment. Detailed Implementation

[0019] The technical solutions described herein will be described in detail below with reference to specific embodiments and accompanying drawings. The embodiments described herein are specific implementations of this disclosure and are used to illustrate the concept of this disclosure. These descriptions are illustrative and exemplary and should not be construed as limiting the implementation methods or the scope of protection of this disclosure. In addition to the embodiments described herein, those skilled in the art can employ other obvious technical solutions based on the content disclosed in the claims and specification of this application. These technical solutions include those that make any obvious substitutions and modifications to the embodiments described herein.

[0020] It should be noted that the accompanying drawings in this embodiment are schematic diagrams used to illustrate the concept of this disclosure, and to schematically show the shape and interrelationship of each part. It should be understood that, in order to clearly show the structure of each component of this disclosure, the drawings are not drawn to the same scale, and the same reference numerals are used to indicate the same parts in the drawings.

[0021] As described in the background art, in semiconductor manufacturing processes, SONOS (silicon-oxide-nitride-oxide-silicon) flash memory devices have become the mainstream type of non-volatile memory due to their excellent scaling characteristics, radiation resistance, and low operating voltage.

[0022] However, as device dimensions continue to shrink, the thickness of the tunneling oxide layer continues to decrease, leading to increased leakage current and severely impacting device reliability and performance. Simultaneously, the high interface state density between the oxide layer and substrate in traditional SONOS structures makes it prone to introducing defects during programming / erasing cycles, generating stress-induced leakage current and further degrading durability and data retention characteristics.

[0023] Therefore, how to provide technical solutions to improve the interface state and reduce leakage current has become an urgent technical problem to be solved.

[0024] The SONOS structure device and its formation method provided in this disclosure include: a substrate; a stacked gate structure located on the substrate; the stacked gate structure includes: a first silicon oxynitride barrier layer located on the substrate; a tunneling oxide layer located on the first silicon oxynitride barrier layer; a silicon nitride layer located on the tunneling oxide layer; a second silicon oxynitride barrier layer located on the silicon nitride layer; a barrier oxide layer located on the second silicon oxynitride barrier layer; and a gate layer located on the barrier oxide layer; wherein the thickness of the first silicon oxynitride barrier layer is less than the thickness of the tunneling oxide layer, and the thickness of the second silicon oxynitride barrier layer is less than the thickness of the barrier oxide layer. By placing a first silicon oxynitride (Soxy) barrier layer with a thickness smaller than that of the tunneling oxide layer between the substrate and the tunneling oxide layer, the nitrogen atoms in the first Soxy barrier layer can passivate the silicon dangling bonds on the substrate surface, significantly reducing the interface state density at the substrate / tunneling oxide interface, thereby reducing leakage current assisted by interface traps. Furthermore, since the thickness of the first Soxy barrier layer is smaller than that of the tunneling oxide layer, it does not significantly increase the equivalent thickness of charge tunneling during programming / erasing, thus improving interface quality without adversely affecting the write / erase efficiency of the device. Finally, the second Soxy barrier layer can optimize the interface between silicon nitride and the barrier oxide layer. The surface quality is improved to suppress the back diffusion of charge from the silicon nitride layer to the barrier oxide layer and reduce stress-induced defects in the barrier oxide layer, thereby further reducing leakage current along the charge loss path. The thicknesses of the first and second silicon nitride barrier layers are both smaller than those of their adjacent main oxide layers (tunneling oxide layer and barrier oxide layer). These two silicon nitride barrier layers function only as ultra-thin interface modification layers and do not alter the original electric field distribution and charge tunneling / blocking mechanism of the entire stacked gate structure. This effectively suppresses interface states and leakage current while maintaining the excellent programming / erasing performance and data retention characteristics of the SONOS device. Therefore, the SONOS structure device can improve interface states and reduce leakage current.

[0025] To make the above-described objects, features and advantages of this disclosure more apparent and understandable, the disclosure is illustrated below with reference to the accompanying drawings.

[0026] See Figure 6 , Figure 6 This is a schematic flowchart illustrating a method for forming a SONOS structure device according to an embodiment of this disclosure. The method can perform the following steps S210 to S220.

[0027] In step S210, a substrate is provided.

[0028] In step S220, a stacked gate structure is formed on the substrate.

[0029] The following combination Figures 1 to 5 The above methods will be explained.

[0030] See Figure 1 Substrate 100 is provided.

[0031] The substrate 100 is used to provide a process platform for the formation of the SONOS structure.

[0032] The substrate 100 is made of single-crystal silicon. In other embodiments, the substrate 100 may also be made of one or more of germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride. The substrate 100 may also be other types of substrates, such as a silicon-on-insulator substrate or a germanium-on-insulator substrate. In other embodiments, an epitaxial layer with the same crystal structure as the substrate may also be formed on the surface of the substrate 100.

[0033] A stacked gate structure is formed on the substrate 100.

[0034] See Figure 7 , Figure 7 This is a schematic flowchart illustrating a method for forming a stacked gate structure of a SONOS structure device according to an embodiment of this disclosure. The method for forming the stacked gate structure can be performed by executing the following steps S221 to S226.

[0035] In step S221, a first silicon oxynitride barrier layer is formed on the substrate.

[0036] In step S222, a tunneling oxide layer is formed on the first silicon oxynitride barrier layer.

[0037] In step S223, a silicon nitride layer is formed on the tunneling oxide layer.

[0038] In step S224, a second silicon oxynitride barrier layer is formed on the silicon nitride layer.

[0039] In step S225, a barrier oxide layer is formed on the second silicon oxynitride barrier layer.

[0040] In step S226, a gate layer is formed on the barrier oxide layer.

[0041] See also Figure 1 An initial stacked gate structure is formed on the substrate 100.

[0042] The step of forming an initial stacked gate structure on the substrate 100 includes: forming a first silicon oxynitride barrier material layer 111a on the substrate 100; forming a tunneling oxide material layer 120a on the first silicon oxynitride barrier material layer 111a; forming a silicon nitride material layer 130a on the tunneling oxide material layer 120a; forming a second silicon oxynitride barrier material layer 112a on the silicon nitride layer 130a; forming a barrier oxide material layer 140a on the second silicon oxynitride barrier material layer 112a; and forming a gate material layer 150a on the barrier oxide layer 140a.

[0043] The material of the first silicon oxynitride barrier layer 111a is silicon oxynitride.

[0044] The method for forming the first silicon oxynitride barrier material layer 111a includes one or more combinations of low-pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, high-temperature chemical vapor deposition, high-temperature thermal nitriding, rapid thermal nitriding / oxidation, physical vapor deposition, and atomic layer deposition.

[0045] In this embodiment, the first silicon oxynitride barrier material layer 111a can be formed using a low-pressure chemical vapor deposition method.

[0046] Specifically, nitrous oxide (N2O) is introduced into the substrate 100 at a temperature of 700°C to 900°C for a duration of 1 to 5 minutes. The nitrous oxide reacts with the silicon in the substrate 100 to form silicon oxynitride, thus obtaining the first silicon oxynitride barrier material layer 111a.

[0047] In some embodiments, in a low-pressure reaction chamber, silicon source and oxygen / nitrogen source gas are heated to cause a chemical reaction on the surface of the substrate 100 to form a thin film, thereby obtaining the first silicon oxynitride barrier material layer 111a.

[0048] In plasma-enhanced chemical vapor deposition (PECVD), plasma energy is used to promote gas decomposition and reaction, enabling film formation at relatively low temperatures. The temperature is around 300°C, and the gases introduced include SiH4, N2O, and NH3. This low-temperature process (sometimes as low as room temperature) allows for controllable film composition.

[0049] In high-temperature chemical vapor deposition (HTCVD) processes, the thermochemical vapor deposition reaction is carried out at high temperatures, and special silicon sources such as trisilylamine (TSA) can be used. When the temperature is less than or equal to 600℃, gases such as TSA, NH3, and O2 are introduced to avoid the formation of byproducts such as ammonium chloride, thereby improving film purity.

[0050] In high-temperature thermal nitriding, a silicon substrate or silicon oxide layer is treated in a high-temperature nitrogen-containing atmosphere (such as N2 or NH3) to introduce nitrogen atoms and form a SiON layer. The temperature ranges from 760°C to 1050°C, and the introduced gases, including N2 and NH3, directly act on the substrate. Its characteristics include high nitriding temperature and long treatment time, and it is often combined with Rapid Thermal Processing (RTP) to achieve a controllable high-temperature process.

[0051] In the rapid thermal nitriding / oxidation process, an extremely thin silicon oxynitride layer is rapidly formed in an oxygen- and nitrogen-containing atmosphere using rapid thermal treatment technology. The introduced gases include O2 and N2O, which can very quickly generate ultra-thin (2nm to 3nm) dielectrics with excellent performance.

[0052] In physical vapor deposition, silicon targets are bombarded with high-energy particles under vacuum conditions, causing silicon atoms to deposit and react with introduced reactive gases (N2, O2) to form a silicon oxynitride film.

[0053] In atomic layer deposition (ALD) technology, a precursor pulse alternating reaction is introduced, and only one atomic layer is deposited in each cycle, which has extremely high precision in thickness and composition control.

[0054] The thickness of the first silicon oxynitride barrier material layer 111a is 1 to 30 angstroms.

[0055] In this embodiment, the thickness of the first silicon oxynitride barrier material layer 111a is 1 to 20 angstroms.

[0056] In some embodiments, the nitrogen content on the side of the first silicon oxynitride barrier material layer 111a closest to the substrate 100 is greater than the nitrogen content on the side furthest from the substrate 100.

[0057] The methods for forming the tunneling oxide material layer 120a include one or more combinations of low-pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, high-density plasma chemical vapor deposition, dry oxygen oxidation, wet oxygen oxidation, rapid thermal oxidation, in-situ steam oxidation, and plasma oxidation.

[0058] Specifically, the tunneling oxide layer 120a is formed using a DCS and N2O gas reaction method at a temperature of 700°C to 900°C. In semiconductor manufacturing processes, DCS is an important silicon source precursor gas, dichlorosilane. The quality of the tunneling oxide layer 120a is optimized by improving the flow rate ratio of DCS and N2O. Generally, the DCS to N2O ratio is 1:2. If too much DCS is used, HCl may remain in the film or damage the substrate, affecting the film's electrical properties. A higher N2O content ensures the quality of the tunneling oxide layer 120a, but too much will reduce the reaction rate. The reaction time is controlled to achieve a thickness of 1 nanometer to 5 nanometers for the tunneling oxide layer 120a.

[0059] The thickness of the first silicon oxynitride barrier material layer 111a is less than the thickness of the tunneling oxide material layer 120a.

[0060] The method for forming the silicon nitride material layer 130a includes one or more combinations of low-pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, high-density plasma chemical vapor deposition, atomic layer deposition, rapid thermal nitriding, and magnetron sputtering.

[0061] Specifically, the silicon nitride material layer 130a is formed by low-pressure chemical vapor deposition using dichlorosilane (DCS) and ammonia (NH3) as reactant gases at a temperature of 600°C to 800°C. In semiconductor manufacturing processes, DCS reacts with NH3 to generate silicon nitride. By optimizing the flow ratio of DCS to NH3, the composition and quality of the silicon nitride material layer 130a can be controlled. Generally, the flow ratio of DCS to NH3 is controlled within the range of 1:5 to 1:10. If the DCS ratio is too high, the silicon content in the resulting silicon nitride film will be too high (silicon-rich silicon nitride), which may lead to abnormal charge trap density or increased leakage current. If the NH3 ratio is too high, although it can improve the insulation performance of the film, the deposition rate will decrease significantly, and excess hydrogen may be introduced, affecting the film density. By controlling the reaction time and deposition pressure, the thickness of the silicon nitride material layer 130a is made from 3 nm to 15 nm to obtain suitable charge storage capacity and trap density. In this embodiment, the thickness of the silicon nitride material layer 130a is 4 nanometers to 7 nanometers.

[0062] The material of the second silicon oxynitride barrier layer 112a is silicon oxynitride.

[0063] The method for forming the second silicon oxynitride barrier material layer 112a includes one or more combinations of low-pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, high-temperature chemical vapor deposition, high-temperature thermal nitriding, rapid thermal nitriding / oxidation, physical vapor deposition, and atomic layer deposition.

[0064] In this embodiment, the second silicon oxynitride barrier material layer 112a can be formed using a low-pressure chemical vapor deposition method.

[0065] Specifically, nitrous oxide (N2O) is introduced into the silicon nitride material layer 130a at a temperature of 700°C to 900°C for a duration of 1 to 5 minutes. The nitrous oxide reacts with the silicon nitride in the silicon nitride material layer 130a to form silicon oxynitride, resulting in the second silicon oxynitride barrier material layer 112a.

[0066] It should be noted that, under the same process conditions, the thickness of the second silicon oxynitride barrier material layer 112a is less than the thickness of the first silicon oxynitride barrier material layer 111a.

[0067] The method for forming the barrier oxide material layer 140a includes one or more combinations of low-pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, high-density plasma chemical vapor deposition, dry oxygen oxidation, rapid thermal oxidation, and in-situ steam oxidation.

[0068] Specifically, the barrier oxide layer 140a is formed by low-pressure chemical vapor deposition using dichlorosilane (DCS) and nitrous oxide (N2O) as reactant gases at a temperature of 650°C to 800°C. Similar to the tunneling oxide layer 120a, the density and insulation properties of the barrier oxide layer can be controlled by optimizing the flow ratio of DCS to N2O. Typically, the flow ratio of DCS to N2O is controlled within the range of 1:2 to 1:10; if the DCS ratio is too high, it may lead to chlorine residue or a decrease in film uniformity; if the N2O ratio is high, it helps to obtain silicon dioxide close to the stoichiometry, improving the film breakdown strength, but the deposition rate will decrease accordingly. By controlling the reaction time and pressure, the thickness of the barrier oxide layer 140a is made from 3 nm to 20 nm (preferably from 3 nm to 10 nm) to obtain sufficient charge blocking capability and prevent the charge stored in the silicon nitride layer from leaking upward to the gate.

[0069] The method for forming the gate material layer 150a includes one or more combinations of low-pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, high-density plasma chemical vapor deposition, physical vapor deposition, and atomic layer deposition.

[0070] Specifically, the gate material layer 150a is formed by low-pressure chemical vapor deposition using silane (SiH4) as the silicon source gas at a temperature of 500°C to 700°C. By optimizing the silane flow rate and deposition pressure, the grain size, doping uniformity, and resistivity of the polycrystalline silicon layer can be controlled. In-situ doping or ion implantation doping (such as phosphorus or boron) is typically performed after deposition to reduce the gate resistance. The deposition time is controlled to achieve a thickness of 50 nm to 200 nm for the gate material layer 150a, thus obtaining sufficient conductivity and a suitable etching process window. Alternatively, dichlorosilane (DCS) can be used instead of silane for deposition at higher temperatures (600°C-700°C) to improve film uniformity and step coverage; or a metal layer (such as tungsten or titanium nitride) can be used to form a metal gate through physical vapor deposition or atomic layer deposition.

[0071] In this embodiment, the gate material layer 150a is polycrystalline silicon.

[0072] See Figure 2 This forms a stacked gate structure.

[0073] The stacked gate structure is obtained by removing part of the initial stacked gate structure.

[0074] Specifically, portions of the gate material layer 150a, the barrier oxide layer 140a, the second silicon oxynitride barrier material layer 112a, the silicon nitride material layer 130a, the tunneling oxide layer 120a, and the first silicon oxynitride barrier material layer 111a are removed sequentially until the surface of the substrate 100 is exposed, thereby obtaining the stacked gate structure. The stacked gate structure includes: the gate layer 150, the barrier oxide layer 140, the second silicon oxynitride barrier layer 112a, the silicon nitride layer 130, the tunneling oxide layer 120a, and the first silicon oxynitride barrier layer 111a.

[0075] Dry etching can be used to sequentially remove portions of the gate material layer 150a, the barrier oxide material layer 140a, the second silicon oxynitride barrier material layer 112a, the silicon nitride material layer 130a, the tunneling oxide material layer 120a, and the first silicon oxynitride barrier material layer 111a.

[0076] During the etching process, a suitable etching gas system is selected for different material layers: For the gate material layer 150a (polysilicon), etching is performed using a chlorine- or bromine-containing gas (such as Cl2, HBr) in conjunction with O2. For the barrier oxide layer 140a, the tunneling oxide layer 120a (silicon dioxide), and the first and second silicon oxynitride barrier layers (SiON), fluorine-based gases (such as CF4, CHF3, C4F6, etc.) are used in combination with O2 and Ar for etching. The silicon nitride material layer 130a (Si3N4) is etched using a fluorine-based gas (such as CF4, CHF3, SF6) or a chlorine-based gas (such as Cl2).

[0077] In some embodiments, the stopping time of each layer etching is precisely controlled by endpoint detection technology (such as optical emission spectroscopy or interference endpoint detection) to ensure that etching terminates in time when the surface of the substrate 100 is exposed, thereby avoiding excessive damage to the substrate 100.

[0078] After removing the photoresist mask, a cleaning step may be performed to remove etching residues and polymers.

[0079] In this embodiment, the thickness of the tunneling oxide layer 120 is 1 nanometer to 5 nanometers; the thickness of the first silicon oxynitride barrier layer 111 is 1 angstrom to 20 angstroms. A first silicon oxynitride barrier layer 111 with a thickness smaller than that of the tunneling oxide layer 120 is disposed between the substrate 100 and the tunneling oxide layer 120. The nitrogen atoms in the first silicon oxynitride barrier layer 111 can passivate the silicon dangling bonds on the surface of the substrate 100, significantly reducing the interface state density at the substrate / tunneling oxide interface, thereby reducing the leakage current assisted by interface traps. The thickness of the first silicon oxynitride barrier layer 111 is smaller than that of the tunneling oxide layer 120, and it does not significantly increase the equivalent thickness of charge tunneling during programming / erasing, thereby improving the interface quality without adversely affecting the write / erase efficiency of the device.

[0080] The second silicon oxynitride barrier layer 112 is located between the silicon nitride layer 130 and the barrier oxide layer 140. The second silicon oxynitride barrier layer 112 can optimize the interface quality between the silicon nitride layer 130 and the barrier oxide layer 140, suppress the reverse diffusion of charge in the silicon nitride layer 130 to the barrier oxide layer 140, and reduce stress-induced defects in the barrier oxide layer 140, thereby further reducing leakage current on the charge loss path.

[0081] In this embodiment, the thickness of the tunneling oxide layer 120 is 1 nm to 5 nm; the thickness of the silicon nitride layer 130 is 4 nm to 7 nm; the thickness of the barrier oxide layer 140 is 3 nm to 10 nm; the thickness of the first silicon nitride barrier layer 111 is 1 angstrom to 20 angstroms; the thickness of the second silicon nitride barrier layer 112 is 1 angstrom to 15 angstroms; and the thickness of the gate layer 150 is 100 nm to 200 nm. The thicknesses of the first and second silicon nitride barrier layers are both smaller than those of the adjacent main oxide layers (tunneling oxide layer and barrier oxide layer). The two silicon nitride barrier layers only function as ultra-thin interface modification layers and do not change the original electric field distribution and charge tunneling / blocking mechanism of the entire stacked gate structure. Thus, while effectively suppressing interface states and leakage current, the excellent programming / erasing performance and data retention characteristics of the SONOS device are maintained.

[0082] Under the same process conditions, the thickness of the first silicon oxynitride barrier layer 111 is greater than the thickness of the second silicon oxynitride barrier layer 112. Specifically, at a temperature of 700°C to 800°C, the reaction rate of N2O with monocrystalline silicon is greater than the reaction rate of N2O with silicon nitride.

[0083] See Figure 8 , Figure 8 This is a schematic flowchart of a partial method for forming a SONOS structure device according to an embodiment of this disclosure. The method can perform the following steps S231 to S232.

[0084] In step S231, sidewalls are formed on the substrates on both sides of the stacked gate structure.

[0085] In step S232, a source region and a drain region are formed in the substrate at intervals, wherein the stacked gate structure is formed on the substrate between the source region and the drain region.

[0086] The following combination Figures 3 to 4 The above methods will be explained.

[0087] See Figure 3 This forms a 160mm sidewall.

[0088] After the stacked gate structure is formed, one or more sidewall material layers are conformally deposited on the surface of the substrate 100, the top of the stacked gate structure and the sidewalls using a chemical vapor deposition method.

[0089] In this embodiment, the sidewall material layer is selected from one or a combination of silicon nitride, silicon dioxide, and silicon oxynitride. Preferably, silicon nitride is used as the sidewall material because it has high density and good etching selectivity, which can effectively protect the sidewalls of the stacked gate structure in subsequent processes.

[0090] The sidewall material layer can be formed using low-pressure chemical vapor deposition or plasma-enhanced chemical vapor deposition.

[0091] Specifically, the deposition temperature is 300°C to 800°C, and the deposition pressure is 0.1 Torr to 10 Torr. Taking silicon nitride as an example, dichlorosilane (DCS) and ammonia (NH3) are used as reactant gases, with a DCS to NH3 flow ratio of 1:5 to 1:10, and a deposition thickness of 20 nanometers to 100 nanometers, forming a sidewall material layer covering the entire device surface.

[0092] An anisotropic dry etch-back process is performed on the sidewall material layer. The etching gas can be a fluorine-based gas (such as CF4, CHF3, SF6) or a chlorine-based gas (such as Cl2), and O2 and Ar are used to adjust the etching rate and selectivity. During the etching process, the sidewall material layer on the horizontal surface (such as the exposed area of ​​the substrate 100, above the gate layer 150 on top of the stacked gate structure) is completely removed, while due to the characteristics of anisotropic etching, the sidewall material located on the sidewalls of the stacked gate structure is retained, forming a layer such as... Figure 3 The side wall shown is 160.

[0093] In some embodiments, the etching endpoint is monitored by time mode or optical emission spectrum to ensure that etching stops on the surface of the substrate 100 and to avoid excessive damage to the substrate 100.

[0094] The sidewall 160 covers the entire sidewall of the stacked gate structure, extending from the upper surface edge of the gate layer 150 to the lower surface edge of the first silicon oxynitride barrier layer 111, and the bottom of the sidewall 160 contacts the substrate 100. During subsequent source / drain ion implantation, the sidewall 160 prevents implanted impurities from entering the channel region beneath the stacked gate structure, thereby ensuring self-alignment between the source / drain region and the channel.

[0095] See Figure 4 This forms a source-drain structure 170.

[0096] The source-drain structure 170 includes a source region and a drain region.

[0097] Specifically, using the sidewall 160 as an implantation mask, doped ions are implanted into the substrate 100 to form source and drain regions spaced apart.

[0098] In this embodiment, the appropriate dopant ions are selected according to the conductivity type (NMOS or PMOS) of the SONOS structure device. For NMOS devices, the implanted dopant ions are phosphorus (P) or arsenic (As); for PMOS devices, the implanted dopant ions are boron (B) or boron difluoride (BF2).

[0099] During the implantation process, the stacked gate structure and its sidewalls 160 on both sides effectively block doped ions from entering the channel region, so that the source region and the drain region are automatically aligned with the outer edge of the sidewalls 160.

[0100] Specifically, the source region is located in the substrate 100 outside the sidewall 160 on one side of the stacked gate structure, and the drain region is located in the substrate 100 outside the sidewall 160 on the opposite side; the stacked gate structure is located on the substrate 100 between the source region and the drain region, and the sidewall 160 is located on opposite sides of the stacked gate structure and on the substrate 100 between the source region and the drain region.

[0101] In some embodiments, before forming the source / drain structure 170, a lightly doped drain implantation may be performed to form a lightly doped drain region to improve the channel electric field distribution. When forming the lightly doped drain region, a low-dose implantation is performed using the stacked gate structure as a mask, followed by the formation of the sidewalls 160, and then a heavily doped source / drain implantation.

[0102] See Figure 9 , Figure 9 This is a schematic flowchart of another method for forming a SONOS structure device according to an embodiment of this disclosure. The method can perform the following steps S241 to S242.

[0103] In step S241, before forming the silicon nitride layer, a third silicon oxynitride barrier layer is formed on the tunneling oxide layer, the third silicon oxynitride barrier layer being located between the tunneling oxide layer and the silicon nitride layer.

[0104] In step S242, before forming the gate layer, a fourth silicon oxynitride barrier layer is formed on the barrier oxide layer, the fourth silicon oxynitride barrier layer being located between the barrier oxide layer and the gate layer.

[0105] See Figure 5 This is to explain the above method. Figure 5 This is a cross-sectional schematic diagram of another SONOS structure device in an embodiment of this disclosure.

[0106] Figure 5 Another SONOS structure device is shown, which is in Figure 4 Based on the structure shown, it further includes a third silicon oxynitride barrier layer 113 located between the tunneling oxide layer 120 and the silicon nitride layer 130, and a fourth silicon oxynitride barrier layer 114 located between the barrier oxide layer 140 and the gate layer 150.

[0107] The third silicon oxynitride barrier layer 113 is formed.

[0108] After the tunneling oxide layer 120 is formed and before the silicon nitride layer 130 is deposited, a third silicon oxynitride barrier layer 113 is formed on the upper surface of the tunneling oxide layer 120. The third silicon oxynitride barrier layer 113 is located between the tunneling oxide layer 120 and the subsequently formed silicon nitride layer 130, and is used to optimize the interface quality between the tunneling oxide layer 120 and the silicon nitride layer 130, suppress interface states and charge traps, and reduce charge recombination and leakage at the interface.

[0109] The method for forming the third silicon oxynitride barrier layer 113 includes one or more of the following: plasma-enhanced chemical vapor deposition, low-pressure chemical vapor deposition, rapid thermal nitriding, atomic layer deposition, or in-situ vapor oxidation combined with nitriding. In this embodiment, low-pressure chemical vapor deposition or rapid thermal nitriding is preferred. Specific related processes can be found in the above description of the first silicon oxynitride barrier layer 111 and the second silicon oxynitride barrier layer 112, and will not be repeated here.

[0110] A fourth silicon oxynitride barrier layer 114 is formed.

[0111] After the formation of the barrier oxide layer 140 and before the deposition of the gate layer 150, a fourth silicon oxynitride barrier layer 114 is formed on the upper surface of the barrier oxide layer 140. The fourth silicon oxynitride barrier layer 114 is located between the barrier oxide layer 140 and the subsequently formed gate layer 150, and is used to optimize the interface quality between the barrier oxide layer 140 and the gate layer 150, suppress interface traps and charge leakage caused by gate injection, and improve the breakdown characteristics and reliability of the device.

[0112] The method for forming the fourth silicon oxynitride barrier layer 114 is similar to that for the third silicon oxynitride barrier layer 113, and can employ one or more of low-pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, rapid thermal nitriding, or atomic layer deposition. In this embodiment, low-pressure chemical vapor deposition or in-situ vapor oxidation followed by nitriding annealing is preferred. Specific related processes can be found in the above description of the first silicon oxynitride barrier layer 111 and the second silicon oxynitride barrier layer 112, and will not be repeated here.

[0113] After sequentially forming the first silicon oxynitride barrier layer 111, the tunnel oxide layer 120, the third silicon oxynitride barrier layer 113, the silicon nitride layer 130, the second silicon oxynitride barrier layer 112, the barrier oxide layer 140, the fourth silicon oxynitride barrier layer 114, and the gate layer 150, the etching, sidewall formation, and source / drain region implantation steps are followed to complete the process as described above. Figure 5 The SONOS structure device is shown.

[0114] Accordingly, this disclosure also provides a SONOS structure device.

[0115] See Figure 4 , Figure 4 This is a cross-sectional structural diagram of a SONOS structure device according to an embodiment of this disclosure.

[0116] The SONOS structure device includes: substrate 100.

[0117] The substrate 100 is used to provide a process platform for the formation of the SONOS structure.

[0118] The substrate 100 is made of single-crystal silicon. In other embodiments, the substrate 100 may also be made of one or more of germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride. The substrate 100 may also be other types of substrates, such as a silicon-on-insulator substrate or a germanium-on-insulator substrate. In other embodiments, an epitaxial layer with the same crystal structure as the substrate may also be formed on the surface of the substrate 100.

[0119] The SONOS structural device includes a stacked gate structure.

[0120] The stacked gate structure is located on the substrate 100.

[0121] The stacked gate structure includes: a first silicon oxynitride barrier layer 111 on the substrate 100; a tunneling oxide layer 120 on the first silicon oxynitride barrier layer 111; a silicon nitride layer 130 on the tunneling oxide layer 120; a second silicon oxynitride barrier layer 112 on the silicon nitride layer 130; a barrier oxide layer 140 on the second silicon oxynitride barrier layer 112; and a gate layer 150 on the barrier oxide layer 140.

[0122] The first silicon oxynitride barrier layer 111 is made of silicon oxynitride.

[0123] In some embodiments, the nitrogen content of the side of the first silicon oxynitride barrier layer 111 closest to the substrate 100 is greater than the nitrogen content of the side furthest from the substrate 100. The nitrogen content of the side of the second silicon oxynitride barrier layer 112 closest to the silicon nitride layer 130 is greater than the nitrogen content of the side closest to the barrier oxide layer 140.

[0124] Specifically, the nitrogen content of the side of the first silicon oxynitride barrier layer 111 closest to the substrate 100 is greater than the nitrogen content of the side closest to the tunneling oxide layer 120. By making the nitrogen content of the first silicon oxynitride barrier layer 111 closer to the substrate 100 higher than the nitrogen content of the side farther from the substrate 100, and the nitrogen content of the second silicon oxynitride barrier layer 112 closer to the silicon nitride layer 130 higher than the nitrogen content of the side farther from the silicon nitride layer 130, the high-nitrogen bottom layer can effectively passivate the silicon dangling bonds on the surface of the substrate 100 (the surface of the silicon nitride layer 130), significantly reducing the interface state density and thus suppressing leakage current caused by interface defects. The low-nitrogen top layer has a composition closer to silicon dioxide, which is beneficial for forming a high-quality, uniform, and thickness-controllable tunneling oxide layer 120 on it, avoiding the impact of excessive nitrogen content on the growth quality of the oxide layer. This structure, without increasing the equivalent oxide layer thickness, balances interface passivation and process compatibility, effectively improving the reliability and electrical performance of SONOS devices.

[0125] The gate layer 150 is polycrystalline silicon.

[0126] In this embodiment, the thickness of the tunneling oxide layer 120 is 1 nanometer to 5 nanometers; the thickness of the first silicon oxynitride barrier layer 111 is 1 angstrom to 20 angstroms. A first silicon oxynitride barrier layer 111 with a thickness smaller than that of the tunneling oxide layer 120 is disposed between the substrate 100 and the tunneling oxide layer 120. The nitrogen atoms in the first silicon oxynitride barrier layer 111 can passivate the silicon dangling bonds on the surface of the substrate 100, significantly reducing the interface state density at the substrate / tunneling oxide interface, thereby reducing the leakage current assisted by interface traps. The thickness of the first silicon oxynitride barrier layer 111 is smaller than that of the tunneling oxide layer 120, and it does not significantly increase the equivalent thickness of charge tunneling during programming / erasing, thereby improving the interface quality without adversely affecting the write / erase efficiency of the device.

[0127] The material of the second silicon oxynitride barrier layer 112 is silicon oxynitride.

[0128] It should be noted that, under the same process conditions, the thickness of the second silicon oxynitride barrier layer 112 is less than the thickness of the first silicon oxynitride barrier layer 111.

[0129] The second silicon oxynitride barrier layer 112 is located between the silicon nitride layer 130 and the barrier oxide layer 140. The second silicon oxynitride barrier layer 112 can optimize the interface quality between the silicon nitride layer 130 and the barrier oxide layer 140, suppress the reverse diffusion of charge in the silicon nitride layer 130 to the barrier oxide layer 140, and reduce stress-induced defects in the barrier oxide layer 140, thereby further reducing leakage current on the charge loss path.

[0130] In this embodiment, the thickness of the tunneling oxide layer 120 is 1 nm to 5 nm; the thickness of the silicon nitride layer 130 is 4 nm to 7 nm; the thickness of the barrier oxide layer 140 is 3 nm to 10 nm; the thickness of the first silicon nitride barrier layer 111 is 1 angstrom to 20 angstroms; the thickness of the second silicon nitride barrier layer 112 is 1 angstrom to 15 angstroms; and the thickness of the gate layer 150 is 100 nm to 200 nm. The thickness of the first silicon nitride barrier layer 111 is less than the thickness of the tunneling oxide layer 120, and the thickness of the second silicon nitride barrier layer 112 is less than the thickness of the barrier oxide layer 140. The two silicon nitride barrier layers function only as ultra-thin interface modification layers without changing the original electric field distribution and charge tunneling / blocking mechanism of the entire stacked gate structure. This effectively suppresses interface states and leakage current while maintaining the excellent programming / erasing performance and data retention characteristics of the SONOS device.

[0131] The SONOS structure device also includes: sidewall 160 and source / drain structure 170.

[0132] The sidewall 160 is made of one or a combination of silicon nitride, silicon dioxide, and silicon oxynitride. Preferably, silicon nitride is used as the sidewall material because it has high density and good etching selectivity, which can effectively protect the sidewalls of the stacked gate structure.

[0133] The sidewall 160 covers the entire sidewall of the stacked gate structure, extending from the upper surface edge of the gate layer 150 to the lower surface edge of the first silicon oxynitride barrier layer 111, and the bottom of the sidewall 160 contacts the substrate 100. During subsequent source / drain ion implantation, the sidewall 160 prevents implanted impurities from entering the channel region beneath the stacked gate structure, thereby ensuring self-alignment between the source / drain region and the channel.

[0134] The source-drain structure 170 includes a source region and a drain region.

[0135] The source region and the drain region are located in the substrate 100 and are spaced apart, and the stacked gate structure is present on the substrate 100 between the source region and the drain region.

[0136] In this embodiment, the appropriate dopant ions are selected according to the conductivity type (NMOS or PMOS) of the SONOS structure device. For NMOS devices, the implanted dopant ions are phosphorus (P) or arsenic (As); for PMOS devices, the implanted dopant ions are boron (B) or boron difluoride (BF2).

[0137] The stacked gate structure and its sidewalls 160 on both sides can effectively block doped ions from entering the channel region, so that the source region and drain region are automatically aligned with the outer edge of the sidewalls 160.

[0138] Specifically, the source region is located in the substrate 100 outside the sidewall 160 on one side of the stacked gate structure, and the drain region is located in the substrate 100 outside the sidewall 160 on the opposite side; the stacked gate structure is located on the substrate 100 between the source region and the drain region, and the sidewall 160 is located on opposite sides of the stacked gate structure and on the substrate 100 between the source region and the drain region.

[0139] See Figure 5 , Figure 5 This is a cross-sectional schematic diagram of another SONOS structure device in an embodiment of this disclosure.

[0140] Figure 5 Another SONOS structure device is shown, which is in Figure 4 Based on the structure shown, the stacked gate structure further includes a third silicon oxynitride barrier layer 113 located between the tunneling oxide layer 120 and the silicon nitride layer 130, and a fourth silicon oxynitride barrier layer 114 located between the barrier oxide layer 140 and the gate layer 150.

[0141] The third silicon oxynitride barrier layer 113 is located on the tunneling oxide layer 120.

[0142] The fourth silicon oxynitride barrier layer 114 is located on the barrier oxide layer 140.

[0143] The third silicon oxynitride barrier layer 113 is located between the tunneling oxide layer 120 and the silicon nitride layer 130, and is used to optimize the interface quality between the tunneling oxide layer 120 and the silicon nitride layer 130, suppress interface states and charge traps, and reduce charge recombination and leakage at the interface.

[0144] The fourth silicon oxynitride barrier layer 114 is located between the barrier oxide layer 140 and the subsequently formed gate layer 150. It is used to optimize the interface quality between the barrier oxide layer 140 and the gate layer 150, suppress interface traps and charge leakage caused by gate injection, and improve the breakdown characteristics and reliability of the device.

[0145] The SONOS structure device further includes: sidewalls 160 and source / drain structures 170. The sidewalls 160 and source / drain structures 170 are as described above and will not be repeated here.

[0146] It should be noted that the illustrated embodiment shows only one layer of stacked gate structure in a specific order. However, any variations in the formation order, relative position, or overall structure such as flipping or rotating of the layers (including the first silicon oxynitride barrier layer, the second silicon oxynitride barrier layer, the third silicon oxynitride barrier layer, the fourth silicon oxynitride barrier layer, the tunnel oxide layer, the silicon nitride layer, the barrier oxide layer, and the gate layer) that can achieve the functions of improving interface states and reducing leakage current should be considered within the scope of this disclosure.

[0147] In some embodiments, the SONOS structure device includes one or more of a first silicon oxynitride barrier layer, a second silicon oxynitride barrier layer, a third silicon oxynitride barrier layer, and a fourth silicon oxynitride barrier layer.

[0148] The foregoing describes several embodiments of the SONOS structure device and its formation method. The various optional methods described in each embodiment can be combined and cross-referenced without conflict, thereby extending to a variety of possible embodiments. These can all be considered as embodiments disclosed in this publication.

[0149] It should be particularly noted that, in this specification and accompanying drawings, in order to clearly describe the core structure and formation method of the SONOS structure device provided in this disclosure, descriptions of relative positions, thickness relationships, and spatial arrangements such as "located on...", "located below...", "stacked", "parallel to the substrate surface", "perpendicular to the stacking direction", "thickness greater than / less than", and "spaced" are all based on theoretical design conditions and ideal process conditions. Those skilled in the art should understand that, in actual semiconductor manufacturing and assembly processes, due to factors such as process fluctuations (e.g., deposition rate, etching load effect), processing tolerances, material deformation, thermal expansion effects, and measurement errors, the actual thickness, interface morphology, relative position, and size ratio of each material layer (including the first silicon oxynitride barrier layer, tunneling oxide layer, silicon nitride layer, barrier oxide layer, gate layer, etc.) may have acceptable minor deviations from the theoretical design. For example, "located on..." should be understood as "substantially located on...", allowing for non-ideal contact due to interface roughness or tilt; "thickness less than" should be understood as "thickness significantly less than", allowing for thicknesses within a certain tolerance range; "parallel to the substrate surface" should be understood as "generally parallel to the substrate surface", allowing for minor tilting due to wafer warpage or process inhomogeneity. These deviations, as long as they do not substantially affect the core technical effects of interface passivation, leakage current suppression, and improved data retention reliability upon which this disclosure relies, should be considered within the scope of protection of this disclosure. Process deviations known in the semiconductor manufacturing industry and variations in size, thickness, and position allowed by industry standards are all covered by this description.

[0150] It should be noted that the illustrated embodiments only show some embodiments of the SONOS structure device and its formation method. Those skilled in the art should understand that other embodiments obtained by mirroring, flipping, rotating, or adapting the position, relative connection relationship, or orientation of each structure in the SONOS structure device based on the structure shown in the figures, or by adaptively adjusting its shape and size, should all be considered within the scope of this disclosure.

[0151] It should be understood that the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article indicates that the preceding and following related objects have an "or" relationship.

[0152] In the embodiments of this application, "multiple" refers to two or more.

[0153] The descriptions of "first," "second," etc., appearing in the embodiments of this application are for illustrative purposes and to distinguish the objects being described. They have no order and do not indicate any special limitation on the number of objects in the embodiments of this application. They cannot constitute any limitation on the embodiments of this application.

[0154] While the embodiments disclosed herein are as described above, this disclosure is not limited thereto. Any person skilled in the art can make various alterations and modifications without departing from the spirit and scope of this disclosure; therefore, the scope of protection of this disclosure should be determined by the scope defined in the claims.

Claims

1. A SONOS structure device, characterized in that, include: Substrate; A stacked gate structure is located on the substrate; The stacked gate structure includes: A first silicon oxynitride barrier layer is located on the substrate; A tunneling oxide layer located on the first silicon oxynitride barrier layer; A silicon nitride layer located on the tunneling oxide layer; A second silicon oxynitride barrier layer is located on the silicon nitride layer; Barrier oxide layer located on the second silicon oxynitride barrier layer; Gate layer located on the barrier oxide layer; Wherein, the thickness of the first silicon oxynitride barrier layer is less than the thickness of the tunneling oxide layer, and the thickness of the second silicon oxynitride barrier layer is less than the thickness of the barrier oxide layer.

2. The SONOS structure device according to claim 1, characterized in that, The nitrogen content on the side of the first silicon oxynitride barrier layer closest to the substrate is greater than the nitrogen content on the side closest to the tunneling oxide layer; And / or, the nitrogen content on the side of the second silicon oxynitride barrier layer closest to the silicon nitride layer is greater than the nitrogen content on the side closest to the barrier oxide layer.

3. The SONOS structure device according to claim 1, characterized in that, Also includes: The source region and the drain region are located in the substrate and are spaced apart, and the stacked gate structure is present on the substrate between the source region and the drain region; Sidewalls are located on the substrate between the source region and the drain region, and on both sides of the stacked gate structure.

4. The SONOS structure device according to claim 1, characterized in that, Meet one or more of the following: The substrate is monocrystalline silicon; The gate layer is polycrystalline silicon; The thickness of the tunneling oxide layer is 1 nanometer to 5 nanometers; The thickness of the silicon nitride layer is 4 nanometers to 7 nanometers; The thickness of the barrier oxide layer is 3 nanometers to 10 nanometers; The thickness of the gate layer is 100 nanometers to 200 nanometers.

5. The SONOS structure device according to claim 1, characterized in that, Meet one or more of the following: The thickness of the first silicon oxynitride barrier layer is 1 to 20 angstroms; The thickness of the second silicon oxynitride barrier layer is 1 to 15 angstroms; The thickness of the first silicon oxynitride barrier layer is greater than the thickness of the second silicon oxynitride barrier layer.

6. The SONOS structure device according to claim 1, characterized in that, The stacked gate structure further includes: a third silicon oxynitride barrier layer located on the tunneling oxide layer, and / or a fourth silicon oxynitride barrier layer located on the barrier oxide layer.

7. A method for forming a SONOS structure device, characterized in that, include: Provide substrate; A stacked gate structure is formed on the substrate; The steps for forming the stacked gate structure include: A first silicon oxynitride barrier layer is formed on the substrate; A tunneling oxide layer is formed on the first silicon oxynitride barrier layer; A silicon nitride layer is formed on the tunneling oxide layer; A second silicon oxynitride barrier layer is formed on the silicon nitride layer; A barrier oxide layer is formed on the second silicon oxynitride barrier layer; A gate layer is formed on the barrier oxide layer; Wherein, the thickness of the first silicon oxynitride barrier layer is less than the thickness of the tunneling oxide layer, and the thickness of the second silicon oxynitride barrier layer is less than the thickness of the barrier oxide layer.

8. The forming method according to claim 7, characterized in that, Under the same process conditions, the thickness of the second silicon oxynitride barrier layer is less than the thickness of the first silicon oxynitride barrier layer.

9. The forming method according to claim 7, characterized in that, Also includes: Sidewalls are formed on the substrates on both sides of the stacked gate structure; Source regions and drain regions are formed in the substrate at intervals, wherein the stacked gate structure is formed on the substrate between the source regions and the drain regions.

10. The forming method according to claim 7, characterized in that, Also includes: Before forming the silicon nitride layer, a third silicon oxynitride barrier layer is formed on the tunneling oxide layer, the third silicon oxynitride barrier layer being located between the tunneling oxide layer and the silicon nitride layer; Before forming the gate layer, a fourth silicon oxynitride barrier layer is formed on the barrier oxide layer, the fourth silicon oxynitride barrier layer being located between the barrier oxide layer and the gate layer.

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