Memory, method of manufacturing memory, and operating method

Abstract

Embodiments of the present disclosure disclose a memory, a manufacturing method and an operating method of the memory. The memory comprises a memory cell, the memory cell comprising a first electrode layer, a first storage layer, a second electrode layer, a second storage layer and a third electrode layer stacked in sequence, wherein a material of the second storage layer is different from a material of the first storage layer; the first storage layer and the second storage layer are both configured to store any one of a first logical data and a second logical data, wherein the second logical data is different from the first logical data.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a memory, a method for manufacturing the memory, and a method for operating the memory. Background Technology

[0002] Resistive Random Access Memory (RRAM) features simple structure, small feature size, and fast programming / erasing speed, making it a promising technology. Selector Only Memory (SOM) offers excellent selectability, simplified integrated structure, and high programming / erasing efficiency, making it a promising technology for applications.

[0003] However, both resistive random access memory and selector-only memory are limited by the read window, making it difficult to achieve multi-value storage and limiting the improvement of storage density. Summary of the Invention

[0004] According to a first aspect of the present disclosure, a memory is provided, comprising: a memory unit, the memory unit comprising a first electrode layer, a first memory layer, a second electrode layer, a second memory layer and a third electrode layer stacked sequentially, wherein the material of the second memory layer is different from the material of the first memory layer; the first memory layer and the second memory layer are both configured to store either first logical data or second logical data, wherein the second logical data is different from the first logical data.

[0005] In some embodiments, the thickness of the first storage layer and the thickness of the second storage layer are the same.

[0006] In some embodiments, the orthographic projections of the first storage layer and the second storage layer overlap.

[0007] In some embodiments, the second electrode layer includes a first barrier layer, a sub-electrode layer, and a second barrier layer stacked sequentially, wherein the first barrier layer is located between the first storage layer and the sub-electrode layer, and the second barrier layer is located between the sub-electrode layer and the second storage layer.

[0008] In some embodiments, the materials of the first barrier layer and the second barrier layer comprise metal nitrides; the material of the sub-electrode layer comprises carbon.

[0009] In some embodiments, the first storage layer is one of a bidirectional threshold switching layer and a resistive switching layer, and the second storage layer is the other of the bidirectional threshold switching layer and the resistive switching layer.

[0010] In some embodiments, the resistive switching layer is made of at least one of germanium selenide arsenide, germanium telluride arsenide, germanium selenide telluride selenide, germanium selenide, selenium arsenide, germanium telluride, silicon telluride, hafnium oxide, titanium oxide, tantalum oxide, silicon oxide, nickel oxide, tin oxide, and aluminum oxide; the bidirectional threshold switching layer is made of at least one of zinc telluride, germanium telluride, niobium oxide, silicon arsenide telluride, vanadium oxide, iron oxide, neodymium nickel oxide, samarium nickel oxide, lanthanum cobalt oxide, gadolinium cobalt oxide, aluminum telluride, boron telluride, germanium selenide, germanium sulfide, and antimony telluride.

[0011] In some embodiments, the memory includes a write driving circuit coupled to the memory cell; the write driving circuit is configured to: apply a first write pulse to the memory cell, such that the first memory layer stores the first logical data and the second memory layer stores the second logical data; apply a second write pulse to the memory cell, such that the first memory layer stores the first logical data and the second memory layer stores the first logical data, wherein the second write pulse and the first write pulse have the same pulse direction, and the pulse amplitude and pulse duration of the second write pulse and the first write pulse are different; apply a third write pulse to the memory cell, such that the first memory layer stores the second logical data and the second memory layer stores the first logical data; apply a fourth write pulse to the memory cell, such that the first memory layer stores the second logical data and the second memory layer stores the second logical data, wherein the fourth write pulse and the third write pulse have the same pulse direction, the fourth write pulse and the first write pulse have opposite pulse directions, and the pulse amplitude and pulse duration of the fourth write pulse and the third write pulse are different.

[0012] In some embodiments, the pulse amplitudes of the first write pulse and the third write pulse range from 20 μA to 30 μA, and the pulse durations of the first write pulse and the third write pulse range from 5 nanoseconds to 100 nanoseconds; the pulse amplitudes of the second write pulse and the fourth write pulse range from 50 μA to 100 μA, and the pulse durations of the second write pulse and the fourth write pulse range from 20 nanoseconds to 1000 nanoseconds, and the pulse durations of the second write pulse and the fourth write pulse are greater than the pulse durations of the first write pulse and the third write pulse.

[0013] According to a second aspect of the present disclosure, a method for operating a memory is provided for operating the memory described in any embodiment of the first aspect, comprising: applying a first write pulse to a memory cell of the memory, such that a first storage layer of the memory cell stores first logical data and a second storage layer of the memory cell stores second logical data, wherein the material of the second storage layer is different from the material of the first storage layer, and the second logical data is different from the first logical data; applying a second write pulse to the memory cell, such that the first storage layer stores the first logical data and the second storage layer stores the first logical data, wherein the pulse direction of the second write pulse and the first write pulse are the same, and the pulse amplitude and pulse duration of the second write pulse and the first write pulse are different; applying a third write pulse to the memory cell, such that the first storage layer stores the second logical data and the second storage layer stores the first logical data; applying a fourth write pulse to the memory cell, such that the first storage layer stores the second logical data and the second storage layer stores the second logical data, wherein the pulse direction of the fourth write pulse and the third write pulse are the same, the pulse direction of the fourth write pulse and the first write pulse are opposite, and the pulse amplitude and pulse duration of the fourth write pulse and the third write pulse are different.

[0014] In this embodiment, by setting a first storage layer between the first electrode layer and the second electrode layer, and a second storage layer between the second electrode layer and the third electrode layer, and by using different materials for the first and second storage layers, both layers can store either first or second logical data. This achieves several advantages: first, it enables multi-value storage of the storage cells, which improves storage density; second, by combining the storage characteristics of the different materials in the first and second storage layers, the read window between different storage states can be increased, improving data read reliability and reducing read interference; third, the combination of the first and second storage layers with different materials effectively reduces leakage current in the storage cells, allowing for three-dimensional integration of the memory and improving integration density. Attached Figure Description

[0015] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the various drawings denote the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings depict only some embodiments disclosed in this application and should not be construed as limiting the scope of this application.

[0016] Figure 1 This is a schematic diagram of two types of storage units provided in an exemplary embodiment of this disclosure; Figure 2 This is a schematic diagram of a memory provided in an embodiment of this disclosure; Figure 3 This is a schematic diagram of a storage unit provided in the first embodiment of this disclosure; Figure 4 This is a schematic diagram of a storage unit provided in the second embodiment of this disclosure; Figure 5 This is a schematic diagram of applying a write pulse according to the first embodiment of this disclosure; Figure 6 This is a schematic diagram of applying a write pulse provided in the second embodiment of this disclosure; Figure 7 This is a flowchart of a method for manufacturing a memory according to an embodiment of this disclosure; Figure 8 This is a flowchart of a memory operation method provided in an embodiment of this disclosure; Figure 9 This is a schematic diagram of the read windows of different memories provided in the embodiments of this disclosure; Figure 10 This is a current distribution diagram of different memories under different voltages provided in the embodiments of this disclosure. Detailed Implementation

[0017] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0018] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0019] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0020] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0021] Spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0022] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0023] To fully understand this disclosure, detailed steps and structures will be set forth in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0024] Figure 1 This is a schematic diagram of two types of storage units provided in an exemplary embodiment of this disclosure. Wherein, Figure 1 Figure (A) shows a schematic diagram of the storage cells of a resistive random access memory. Figure 1 Figure (B) shows a schematic diagram of the storage cells of the selector-only memory.

[0025] Reference Figure 1 As shown in Figure (A), the storage cell of the resistive random access memory (RRAM) includes a first electrode layer 102, a resistive switching layer 104, and a second electrode layer 106 stacked sequentially. By applying corresponding voltage pulses to the first electrode layer 102 and the second electrode layer 106, the resistance state of the resistive switching layer 104 can be changed (e.g., switched to a low resistance state or a high resistance state), thereby realizing the storage of logic data "1" or "0". That is, the storage cell of the RRAM stores only one bit of logic data. The logic data mentioned in this article can also be referred to as binary data.

[0026] Reference Figure 1 As shown in Figure (B), the storage cell of the selector-only memory includes a first electrode layer 102, a bidirectional threshold switching layer 108, and a second electrode layer 106 stacked sequentially. By applying corresponding voltage pulses to the first electrode layer 102 and the second electrode layer 106, the threshold voltage state of the bidirectional threshold switching layer 108 can be changed (e.g., switched to a low threshold voltage or a high threshold voltage), thereby realizing the storage of logic data "1" or "0", that is, the storage cell of the selector-only memory stores only one bit of logic data.

[0027] It can be seen that, on the one hand, both resistive random access memory and selector-only memory are limited by the read window and can only store one bit of logical data, making it difficult to achieve multi-value storage (e.g., storing two or more bits of data), which limits the improvement of storage density; on the other hand, both resistive random access memory and selector-only memory have leakage problems in their storage cells, which makes three-dimensional integration more difficult, thus limiting the improvement of integration.

[0028] Based on one or more of the above-mentioned technical problems, this disclosure provides a memory.

[0029] Figure 2 This is a schematic diagram of a memory provided in an embodiment of this disclosure. Figure 3 This is a schematic diagram of a storage unit provided in the first embodiment of this disclosure. Figure 4 This is a schematic diagram of a storage unit provided in the second embodiment of this disclosure.

[0030] Reference Figure 2 and Figure 3 As shown, the memory 200 includes a memory cell array 202, which includes a plurality of memory cells 300, which can be arranged in an array. As an example, the plurality of memory cells 300 can be arranged in an array along a first direction and a second direction, wherein the first direction and the second direction intersect, and the angle between the first direction and the second direction can be an acute angle, a right angle, or an obtuse angle. Both the first direction and the second direction are perpendicular to the stacking direction. In this example, the stacking direction can refer to the direction in which multiple film layers in the memory cell 300 are stacked. In practical applications, both the first direction and the second direction are parallel to the horizontal plane, and the stacking direction is perpendicular to the horizontal plane. It should be noted that... Figure 2 and Figure 3 The present disclosure is not limited to the case where the storage cell array 202 includes only one storage cell 300.

[0031] Reference Figure 3 As shown, the storage cell 300 includes a first electrode layer 302, a first storage layer 304, a second electrode layer 306, a second storage layer 308, and a third electrode layer 310 stacked sequentially. Specifically, the first storage layer 304 is located between the first electrode layer 302 and the second electrode layer 306, and the second storage layer 308 is located between the second electrode layer 306 and the third electrode layer 310. The material of the second storage layer 308 is different from the material of the first storage layer 304.

[0032] The materials of the first electrode layer 302, the second electrode layer 306, and the third electrode layer 310 may include amorphous carbon, such as α-phase carbon. All three electrode layers are used to conduct electrical signals. It should be noted that the materials of any two of the first electrode layer 302, the second electrode layer 306, and the third electrode layer 310 may be the same or different, and this disclosure does not impose any special restrictions in this regard.

[0033] One of the first storage layer 304 and the second storage layer 308 may be made of an omonic threshold switching (OTS) material, and the other of the first storage layer 304 and the second storage layer 308 may be made of a storage memory (SM) material with resistive switching or phase-change characteristics. That is, the materials of the first storage layer 304 and the second storage layer 308 are different. The OTS material may include zinc telluride (Zn). a Te b Germanium telluride (Ge) a Te b), niobium oxide (Nb) a O b ), silicon arsenide tellurium (Si a As b Te c The materials include at least one of the following: vanadium oxide, iron oxide, neodymium nickel oxide, samarium nickel oxide, lanthanum cobalt oxide, gadolinium cobalt oxide, aluminum telluride, boron telluride, germanium selenide, germanium sulfide, and antimony telluride, where a, b, and c are all positive numbers. SM materials may include germanium selenide arsenic, germanium telluride arsenic, germanium selenide telluride selenium, germanium selenide, selenium arsenide, germanium telluride, silicon telluride, and hafnium oxide (HfO). x Titanium oxide (TiO) x ), tantalum oxide (TaO) x ), silicon dioxide (SiO) x Nickel oxide (NiO) x ), Tin oxide (SnO) x ) and aluminum oxide (AlO x At least one of the following, where x is a positive number.

[0034] In some embodiments, the second electrode layer 306 includes a first barrier layer, a sub-electrode layer and a second barrier layer stacked sequentially, wherein the first barrier layer is located between the first storage layer 304 and the sub-electrode layer, and the second barrier layer is located between the sub-electrode layer and the second storage layer 308.

[0035] In some embodiments, the materials of the first barrier layer and the second barrier layer include metal nitrides; the material of the sub-electrode layer includes carbon.

[0036] The first and second barrier layers can effectively block element diffusion between the storage layer and the sub-electrode layer, improve interface properties, reduce defects at the interface, and enhance the adhesion between the sub-electrode layer and the storage layer. For example, the first barrier layer can block element diffusion between the first storage layer 304 and the sub-electrode layer, and improve the adhesion between them; the second barrier layer can block element diffusion between the sub-electrode layer and the second storage layer 308, and improve the adhesion between them.

[0037] In some embodiments, the thickness of the first storage layer 304 is the same as the thickness of the second storage layer 308. By setting the thickness of the first storage layer 304 and the second storage layer 308 to be the same, process control, stress matching, and performance balance can be facilitated. In practical applications, the thickness of the first storage layer 304 and the second storage layer 308 can be reasonably set according to device design requirements, and this disclosure does not impose any special limitations in this regard.

[0038] In some embodiments, the orthographic projections of the first storage layer 304 and the second storage layer 308 overlap. By setting the orthographic projections of the first storage layer 304 and the second storage layer 308 to overlap, the area occupied by the storage cells on the plane can be reduced, thereby enabling the miniaturization of the memory.

[0039] In the first embodiment of this disclosure, reference is made to Figure 3 As shown, the material of the first storage layer 304 can be an OTS material, so the first storage layer 304 can be a bidirectional threshold switching layer; the material of the second storage layer 308 can be an SM material with resistive switching properties, so the second storage layer 308 can be a resistive switching layer.

[0040] In the second embodiment of this disclosure, reference is made to Figure 4 As shown, the material of the first storage layer 404 can be an SM material with resistive switching properties, so the first storage layer 404 can be a resistive switching layer; the material of the second storage layer 408 can be an OTS material, so the second storage layer 408 can be a bidirectional threshold switching layer.

[0041] This disclosure does not restrict the choice of materials for the first and second storage layers, only requiring that the materials of the first and second storage layers be different to achieve different storage characteristics. For ease of understanding, the following explanation will use a bidirectional threshold switching layer as the first storage layer and a resistive switching layer as the example.

[0042] Reference Figure 3 As shown, both the first storage layer 304 and the second storage layer 308 are configured to store either the first logical data or the second logical data, wherein the second logical data is different from the first logical data. One of the first logical data and the second logical data can be logical data "1", and the other can be logical data "0". For example, the first logical data can be logical data "1", and the second logical data can be logical data "0". Another example is that the first logical data can be logical data "0", and the second logical data can be logical data "1". For ease of understanding, the following explanation will use the example of the first logical data being "1" and the second logical data being "0".

[0043] It should be noted that by performing a write (also known as programming) operation on the storage unit 300, the first storage layer 304 can store the first logical data or the second logical data, and the second storage layer 308 can store the first logical data or the second logical data. That is, the two storage layers of the storage unit 300 can each store one bit of logical data, so that the storage unit 300 as a whole can store two bits of logical data, thereby realizing the multi-value storage of the storage unit 300. The logical data stored in the first storage layer 304 and the second storage layer 308 can be the same or different.

[0044] As a first example, by performing a write (also known as programming) operation on the storage unit 300, the first storage layer 304 can store logical data "0", and the second storage layer 308 can store logical data "0", that is, the two bits of logical data stored in the storage unit 300 are "00", and the storage unit 300 can be in the first storage state.

[0045] As a second example, by performing a write operation on the storage unit 300, the first storage layer 304 can store logical data "0", and the second storage layer 308 can store logical data "1". That is, the two logical data stored in the storage unit 300 are "01", and the storage unit 300 can be in the second storage state.

[0046] As a third example, by performing a write operation on the storage unit 300, the first storage layer 304 can store logical data "1", and the second storage layer 308 can store logical data "0", that is, the two logical data stored in the storage unit 300 is "10", and the storage unit 300 can be in a third storage state.

[0047] As a fourth example, by performing a write operation on storage unit 300, the first storage layer 304 can store logical data "1", and the second storage layer 308 can store logical data "1", that is, the two logical data stored in storage unit 300 is "11", and storage unit 300 can be in the fourth storage state.

[0048] As can be seen from the first to fourth examples above, by performing a write operation on storage unit 300, storage unit 300 can be programmed to any of the first to fourth storage states. The storage states of any two storage units among the multiple storage units 300 can be the same or different. For example, if the first storage unit among the multiple storage units 300 stores logical data "00" and the second storage unit among the multiple storage units stores logical data "11", then the storage states of the first and second storage units are different. As another example, if the first and second storage units both store logical data "10", then the storage states of the first and second storage units are the same.

[0049] It should be noted that the first to fourth storage states mentioned above are only for distinguishing four different states of storage units, and are not intended to describe a specific order or sequence.

[0050] Table 1 shows the threshold voltages for programming memory cell 300 to different memory states. Referring to Table 1, when the logic data stored in storage cell 300 is "11", the threshold voltage of the first storage layer 304 is 1.5V, the threshold voltage of the second storage layer 308 is 3V, and the threshold voltage of storage cell 300 is 4.5V; when the logic data stored in storage cell 300 is "10", the threshold voltage of the first storage layer 304 is 2.3V, the threshold voltage of the second storage layer 308 is 3V, and the threshold voltage of storage cell 300 is 4.5V; when the logic data stored in storage cell 300 is "01", the threshold voltage of the first storage layer 304 is 1.5V, the threshold voltage of the second storage layer 308 is 4.5V, and the threshold voltage of storage cell 300 is 6.0V; when the logic data stored in storage cell 300 is "00", the threshold voltage of the first storage layer 304 is 2.3V, the threshold voltage of the second storage layer 308 is 4.5V, and the threshold voltage of storage cell 300 is 6.8V. The data in Table 1 are for illustrative purposes only and are not intended to limit the threshold voltage of the first storage layer, the threshold voltage of the second storage layer, or the threshold voltage of the storage cell in this application. All storage cell configurations that conform to the inventive concept of this application are within the scope of protection of this application.

[0051] Table 1 Threshold voltages of memory cells in different storage states

[0052] In this embodiment, by setting a first storage layer between the first electrode layer and the second electrode layer, and a second storage layer between the second electrode layer and the third electrode layer, and by using different materials for the first and second storage layers, both layers can store either first or second logical data. This achieves several advantages: first, it enables multi-value storage of the storage cells, which improves storage density; second, by combining the storage characteristics of the different materials in the first and second storage layers, the read window between different storage states can be increased, improving data read reliability and reducing read interference; third, the combination of the first and second storage layers with different materials effectively reduces leakage current in the storage cells, allowing for three-dimensional integration of the memory and improving integration density.

[0053] In some embodiments, the memory 200 further includes a first conductive line (not shown) and a second conductive line (not shown), wherein the first conductive line and the second conductive line are both parallel to the horizontal plane and intersect each other, and the memory cell 300 is located between the first conductive line and the second conductive line.

[0054] One of the first conductive line and the second conductive line can be a bit line, and the other can be a word line. For example, the first conductive line is a bit line, the second conductive line is a word line, the first electrode layer 302 is located between the bit line and the first memory layer 304, and the third electrode layer 310 is located between the second memory layer 308 and the word line. That is, the bit line, the first electrode layer 202, the first memory layer 204, the second electrode layer 206, the second memory layer 208, the third electrode layer 210, and the word line are arranged sequentially along the stacking direction. Of course, in other embodiments, the positions of the word line and the bit line can be interchanged, and this disclosure does not impose any special restrictions on this.

[0055] The number of first conductive lines and second conductive lines can be one or more. As an example, the memory 200 includes multiple first conductive lines and multiple second conductive lines. The multiple first conductive lines can be arranged at intervals along a first direction, and each first conductive line extends along a second direction and is coupled to multiple memory cells 300 arranged at intervals along the second direction. The multiple second conductive lines can also be arranged at intervals along the second direction, and each second conductive line extends along the first direction and is coupled to multiple memory cells 300 arranged at intervals along the first direction. By selecting a target first conductive line among the multiple first conductive lines and a target second conductive line among the multiple second conductive lines, a target memory cell among the multiple memory cells 300 can be selected, thereby performing write, read, or erase operations on the target memory cell. Here, the target memory cell is the memory cell among the multiple memory cells 300 coupled to the target first conductive line and the target second conductive line.

[0056] The materials of the first and second conductive lines may include conductive materials, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon, doped silicon, or any combination thereof. The first and second conductive lines may have the same conductive material or different conductive materials, and this disclosure does not impose any particular limitation in this regard.

[0057] It should be noted that the first plane on which the first conductive line is set and the second plane on which the second conductive line is set are parallel, and the first plane and the second plane do not overlap. The storage cell 300 is located between the first plane and the second plane, and the storage cell 300 is perpendicular to both the first plane and the second plane.

[0058] To more clearly convey this disclosure, the operation method of the memory 200 provided in the embodiments of this disclosure will be described in detail below. Before describing the operation method of the memory 200, the storage characteristics of the resistive switching layer and the bidirectional threshold switching layer will be described by way of example.

[0059] The resistive switching layer can reversibly switch between a high-resistance state and a low-resistance state under the influence of an electric field or current. Since the two resistive states have a significant difference in resistance, they can correspond to logic data "0" and "1" respectively, thereby realizing information storage. The change of the resistive switching layer's resistive state mainly depends on the formation and breakage of conductive filaments.

[0060] Specifically, in the initial state, the resistive switching layer typically exhibits a high-resistivity state, corresponding to logic data "0". By applying a forward write pulse or forward bias voltage with a certain amplitude and width to the resistive switching layer, metal ions, oxygen vacancies, or other defects within the resistive switching layer can migrate and accumulate under the influence of an external electric field. This forms conductive pathways (i.e., conductive filaments) connecting the upper and lower electrodes within the resistive switching layer. These conductive filaments provide low-resistivity pathways for charge carriers, causing the resistive switching layer to transition from a high-resistivity state to a low-resistivity state, thus completing the writing of logic data "1". This process is commonly referred to as a set operation. Conversely, by applying a reverse write pulse or reverse bias voltage with a certain amplitude and width to the resistive switching layer, the conductive filaments will melt, break, or oxidize under the influence of an electric field or Joule heating. This destroys the conductive pathways in the resistive switching layer, preventing the formation of effective conductive channels, and thus causing the resistive switching layer to return to a high-resistivity state, thereby completing the writing of logic data "0". This process is commonly referred to as a reset operation. Furthermore, when the applied external electric field is removed, the resistive switching layer can maintain its current resistive state for a long time, and can maintain the data state without continuous power supply, which can meet the requirements of non-volatile storage.

[0061] A bidirectional threshold switching layer can achieve reversible transitions between a high-resistance state (off state) and a low-resistance state (on state) under the influence of an electric field. Its state transitions mainly rely on the threshold switching effect caused by electric field-induced carrier injection and recombination. Because it exhibits a high-resistance state below the threshold voltage and a low-resistance state above the threshold voltage, and automatically recovers to the high-resistance state after the voltage is removed, it can be applied to memory cells. By applying voltage pulses of different amplitudes to the switching layer, the storage of logic data "0" and "1" can be achieved.

[0062] Specifically, in the initial state or before the threshold voltage is reached, the active material (such as chalcogenides) in the bidirectional threshold transition layer is in a highly disordered or defect-bound state. Charge carriers are trapped in deep-level traps and cannot migrate freely, thus exhibiting a high-resistivity state, corresponding to logic data "0". In this state, the device can effectively suppress creeping current. When it is necessary to access the target memory cell or write logic data "1", a voltage pulse with an amplitude higher than the threshold voltage can be applied to the bidirectional threshold transition layer. Under the action of the external strong electric field, charge carriers are injected into the material from the electrodes in large quantities through tunneling and rapidly fill the deep-level traps. When the traps are completely filled, the quasi-Fermi level inside the material shifts, causing the effective bandgap to collapse or an insulator-metal phase transition to occur, causing the material to instantly jump from a high-resistivity state to a low-resistivity state, forming a conduction path. At this time, current can pass through without obstruction, and the corresponding memory cell is selected. This process is usually called threshold enable operation or writing logic data "1" (i.e., the enable state). Conversely, when it is necessary to disconnect the cell or write logic data "0", simply remove the voltage applied across the bidirectional threshold switching layer, or reduce the voltage below the holding voltage. Due to the lack of a continuous electric field to excite and sustain the charge carriers, the filled charge carriers rapidly recombine or are recaptured by defects, the metallic properties within the material disappear, and it reverts to its original disordered insulating state. At this point, the conductive path disappears, and the device automatically returns to a high-resistance state, corresponding to writing logic data "0" (i.e., the off state). This process is commonly referred to as threshold recovery operation.

[0063] Furthermore, this switching process of the bidirectional threshold switching layer exhibits high reversibility and bidirectional symmetry. Regardless of whether a positive or negative voltage pulse is applied, as long as the amplitude exceeds the threshold voltage, the turn-on operation can be triggered; and once the voltage is removed, the device can always automatically return to the high-resistivity state. This fast switching characteristic, which can be achieved without changing the chemical composition of the materials, makes it an indispensable storage element in high-density three-dimensional memory arrays.

[0064] Figure 5 This is a schematic diagram illustrating the application of a write pulse according to the first embodiment of this disclosure. Figure 5 Figure (A) is a schematic diagram of applying a first write pulse according to an embodiment of this disclosure. Figure 5 Figure (B) is a schematic diagram of applying a second write pulse according to an embodiment of this disclosure.

[0065] Reference Figure 2 , Figure 3 and Figure 5As shown, the memory 200 also includes a write drive circuit 204, which is coupled to the memory cell 300. The write drive circuit 204 is configured to: apply a first write pulse 500A to the memory cell 300, causing the first memory layer 304 to store first logic data and the second memory layer 308 to store second logic data; apply a second write pulse 500B to the memory cell 300, causing the first memory layer 304 to store the first logic data and the second memory layer 308 to store the first logic data, wherein the pulse direction of the second write pulse 500B and the first write pulse 500A is the same, and the pulse amplitude and pulse duration of the second write pulse 500B and the first write pulse 500A are different.

[0066] In some embodiments, both the second write pulse 500B and the first write pulse 500A are positive write pulses, meaning that the pulse directions of the second write pulse 500B and the first write pulse 500A are the same. Of course, in other embodiments, both the second write pulse and the first write pulse can also be negative write pulses. For ease of understanding, the following description will use the example of both the second write pulse 500B and the first write pulse 500A being positive write pulses. It should be noted that the pulse direction of the positive write pulse mentioned herein is the direction from the top electrode (i.e., the third electrode layer 310) to the bottom electrode (i.e., the first electrode layer 302), that is, the pulse directions of both the second write pulse 500B and the first write pulse 500A are the direction from the third electrode layer 310 to the first electrode layer 302.

[0067] As a first example, the first storage layer 304 is a resistive switching layer, and the second storage layer 308 is a bidirectional threshold switching layer. The write drive circuit 204 can apply corresponding voltages to the selected bit line and the selected word line respectively to form a positive electric field between the corresponding top electrode and bottom electrode, that is, to apply a positive first write pulse 500A to the selected storage cell 300. The first write pulse 500A can have a small pulse amplitude and a short pulse duration, such as... Figure 5 As shown in Figure (A), the bidirectional threshold conversion layer can store logic data "1" and the resistive switching layer can store logic data "0", that is, the selected storage unit 300 can store two bits of logic data "10".

[0068] As a second example, the first storage layer 304 is a resistive switching layer, and the second storage layer 308 is a bidirectional threshold switching layer. The write drive circuit 204 can apply corresponding voltages to the selected bit line and the selected word line respectively to form a positive electric field between the corresponding top electrode and bottom electrode, that is, to apply a positive second write pulse 500B to the selected storage cell 300. The second write pulse 500B can have a large pulse amplitude and a long pulse duration, such as... Figure 5As shown in Figure (B), the bidirectional threshold conversion layer can store logic data "1" and the resistive switching layer can store logic data "1", that is, the selected storage unit 300 can store two bits of logic data "11".

[0069] In some embodiments, the pulse amplitude 502 of the first write pulse ranges from 20 μA to 30 μA, and the pulse amplitude 504 of the second write pulse ranges from 50 μA to 100 μA, meaning the pulse amplitude 504 of the second write pulse is greater than the pulse amplitude 502 of the first write pulse. Of course, in other embodiments, the pulse amplitude of the second write pulse may be less than the pulse amplitude of the first write pulse, and this disclosure does not impose any special limitations on this. It should be noted that the pulse amplitude mentioned herein refers to the maximum current (or peak value) reached by the electrical pulse signal within a short period of time. It is one of the most crucial characteristic parameters of the pulse signal and directly determines the pulse intensity.

[0070] In some embodiments, the pulse duration of the first write pulse ranges from 5 nanoseconds to 100 nanoseconds. Figure 5 In Figure (A), t1 to t2 represent the pulse duration of the first write pulse, i.e., (t2-t1) ranges from 5 nanoseconds to 100 nanoseconds; the pulse duration of the second write pulse ranges from 20 nanoseconds to 1000 nanoseconds. Figure 5 In Figure (B), t3 to t4 represent the pulse duration of the second write pulse, i.e., (t4-t3) ranges from 20 nanoseconds to 1000 nanoseconds. Furthermore, the pulse duration of the second write pulse is longer than that of the first write pulse; for example, the pulse duration of the first write pulse is 50 nanoseconds, and the pulse duration of the second write pulse is 100 nanoseconds. The pulse durations of both the first and second write pulses are not limited to those shown in this example and can be other values. Of course, in other embodiments, the pulse duration of the second write pulse can be shorter than that of the first write pulse, and this disclosure does not impose any special limitations on this. It should be noted that the pulse duration mentioned herein refers to the duration for which a single electrical pulse signal maintains its effective amplitude from rise to fall.

[0071] In practical applications, the pulse amplitude and pulse duration of the write pulse can be reasonably selected based on the material of the first storage layer 304, the material of the second storage layer 308, and the data to be written. This disclosure does not impose any special restrictions on this.

[0072] Figure 6 This is a schematic diagram illustrating the application of a write pulse according to a second embodiment of this disclosure. Figure 6 Figure (A) is a schematic diagram of applying a third write pulse according to an embodiment of this disclosure. Figure 6 Figure (B) is a schematic diagram of applying a fourth write pulse according to an embodiment of this disclosure.

[0073] Reference Figure 2 , Figure 3 and Figure 6 As shown, the write drive circuit 204 is further configured to: apply a third write pulse 600A to the memory cell 300, causing the first memory layer 304 to store the second logic data and the second memory layer 308 to store the first logic data; apply a fourth write pulse 600B to the memory cell 300, causing the first memory layer 304 to store the second logic data and the second memory layer 308 to store the second logic data, wherein the pulse direction of the fourth write pulse 600B and the third write pulse 600A is the same, the pulse direction of the fourth write pulse 600B and the first write pulse 600A is opposite, and the pulse amplitude and pulse duration of the fourth write pulse 600B and the third write pulse 600A are different.

[0074] In some embodiments, both the fourth write pulse 600B and the third write pulse 600A are reverse write pulses, meaning that the pulse directions of the fourth write pulse 600B and the third write pulse 600A are the same. Of course, in other embodiments, both the fourth write pulse and the third write pulse can be forward write pulses. For ease of understanding, the following description will use the example of both the fourth write pulse 600B and the third write pulse 600A being reverse write pulses. It should be noted that the pulse direction of the reverse write pulse mentioned herein is from the bottom electrode (i.e., the first electrode layer 302) to the top electrode (i.e., the third electrode layer 310), that is, the pulse directions of both the fourth write pulse 600B and the third write pulse 600A are from the first electrode layer 302 to the third electrode layer 310.

[0075] As a first example, the first storage layer 304 is a resistive switching layer, and the second storage layer 308 is a bidirectional threshold switching layer. The write drive circuit 204 can apply corresponding voltages to the selected bit line and the selected word line respectively to form a reverse electric field between the corresponding top electrode and bottom electrode, that is, to apply a reverse third write pulse 600A to the selected storage cell 300. The third write pulse 600A can have a small pulse amplitude and a short pulse duration, such as... Figure 5 As shown in Figure (A), the bidirectional threshold conversion layer can store logic data "0" and the resistive switching layer can store logic data "0", that is, the selected storage unit 300 can store two bits of logic data "00".

[0076] As a second example, the first storage layer 304 is a resistive switching layer, and the second storage layer 308 is a bidirectional threshold switching layer. The write drive circuit 204 can apply corresponding voltages to the selected bit line and the selected word line respectively to form a reverse electric field between the corresponding top electrode and bottom electrode, that is, to apply a reverse fourth write pulse 600B to the selected storage cell 300. The fourth write pulse 600B can have a large pulse amplitude and a long pulse duration, such as... Figure 5 As shown in Figure (B), the bidirectional threshold conversion layer can store logic data "0" and the resistive switching layer can store logic data "1", that is, the selected storage unit 300 can store two bits of logic data "01".

[0077] In some embodiments, the pulse amplitude 602 of the third write pulse ranges from 20 µA to 30 µA, and the pulse amplitude 604 of the fourth write pulse ranges from 50 µA to 100 µA, that is, the pulse amplitude 604 of the fourth write pulse is greater than the pulse amplitude 602 of the third write pulse. Of course, in other embodiments, the pulse amplitude of the fourth write pulse may be less than the pulse amplitude of the third write pulse, and this disclosure does not impose any special limitations on this.

[0078] In some embodiments, the pulse duration of the third write pulse ranges from 5 nanoseconds to 100 nanoseconds. Figure 6 In Figure (A), t5 to t6 represent the pulse duration of the third write pulse, i.e., (t6-t5) ranges from 5 nanoseconds to 100 nanoseconds; the pulse duration of the fourth write pulse ranges from 20 nanoseconds to 1000 nanoseconds. Figure 6 In Figure (B), t7 to t8 represent the pulse duration of the fourth write pulse, i.e., the range of (t8-t7) is 20 nanoseconds to 1000 nanoseconds. Furthermore, the pulse duration of the fourth write pulse is longer than that of the third write pulse; for example, the pulse duration of the third write pulse is 50 nanoseconds, and the pulse duration of the fourth write pulse is 100 nanoseconds. The pulse durations of the third and fourth write pulses are not limited to those shown in this example and can also be other values. Of course, in other embodiments, the pulse duration of the second write pulse can be shorter than that of the first write pulse, and this disclosure does not impose any special limitations on this.

[0079] In practical applications, the pulse amplitude and pulse duration of the write pulse can be reasonably selected based on the material of the first storage layer 304, the material of the second storage layer 308, and the data to be written. This disclosure does not impose any special restrictions on this.

[0080] Based on a concept similar to the memory described above, this disclosure provides a method for manufacturing a memory.

[0081] Figure 7 This is a flowchart illustrating a method for manufacturing a memory according to an embodiment of this disclosure. (Refer to...) Figure 7 As shown, the manufacturing method includes: S701: Provides a substrate; S702: A memory cell is formed on a substrate. The memory cell includes a first electrode layer, a first memory layer, a second electrode layer, a second memory layer, and a third electrode layer stacked sequentially. The material of the second memory layer is different from that of the first memory layer. Both the first and second memory layers are configured to store either first logic data or second logic data. The second logic data is different from the first logic data.

[0082] In some embodiments, the materials of the first electrode layer, the second electrode layer, and the third electrode layer may include amorphous carbon, such as α-phase carbon. The first electrode layer, the second electrode layer, and the third electrode layer are all used to conduct electrical signals. It should be noted that the materials of any two of the first electrode layer, the second electrode layer, and the third electrode layer may be the same or different, and this disclosure does not impose any particular limitation in this regard.

[0083] In some embodiments, the material of one of the first storage layer 304 and the second storage layer 308 may include a bidirectional threshold selection switch (OTS) material, and the material of the other of the first storage layer 304 and the second storage layer 308 may include a memory material (SM) with resistive switching or phase-change characteristics, that is, the materials of the first storage layer 304 and the second storage layer 308 are different. The OTS material may include zinc telluride (Zn). a Te b Germanium telluride (Ge) a Te b ), niobium oxide (Nb) a O b ), silicon arsenide tellurium (Si a As b Te c The material may contain at least one of the following: vanadium oxide, iron oxide, neodymium nickel oxide, samarium nickel oxide, lanthanum cobalt oxide, gadolinium cobalt oxide, aluminum telluride, boron telluride, germanium selenide, germanium sulfide, and antimony telluride, where a, b, and c are all positive numbers. The SM material may include hafnium oxide (HfO). x Titanium oxide (TiO) x ), tantalum oxide (TaO) x ), silicon dioxide (SiO) x Nickel oxide (NiO) x ), Tin oxide (SnO) x ) and aluminum oxide (AlO x At least one of the following, where x is a positive number.

[0084] In some embodiments, one of the first logical data and the second logical data can be logical data "1", and the other of the first logical data and the second logical data can be logical data "0". For example, the first logical data can be logical data "1", and the second logical data can be logical data "0". Yet another example is that the first logical data can be logical data "0", and the second logical data can be logical data "1".

[0085] Based on a concept similar to the memory described above, this disclosure provides a method for operating a memory.

[0086] Figure 8 This is a flowchart illustrating a memory operation method provided in an embodiment of this disclosure. (Refer to...) Figure 8 As shown, the operation method includes: S801: Apply a first write pulse to the memory cell, such that the first storage layer of the memory cell stores first logical data and the second storage layer of the memory cell stores second logical data, wherein the material of the second storage layer is different from the material of the first storage layer, and the second logical data is different from the first logical data; S802: Apply a second write pulse to the storage cell, so that the first storage layer stores the first logic data and the second storage layer stores the first logic data, wherein the pulse direction of the second write pulse and the first write pulse are the same, and the pulse amplitude and pulse duration of the second write pulse and the first write pulse are different.

[0087] S803: Apply a third write pulse to the memory cell, so that the first memory layer stores the second logic data and the second memory layer stores the first logic data; S804: Apply a fourth write pulse to the memory cell, so that the first memory layer stores the second logic data and the second memory layer stores the second logic data. The fourth write pulse and the third write pulse have the same pulse direction, the fourth write pulse and the first write pulse have opposite pulse directions, and the pulse amplitude and pulse duration of the fourth write pulse and the third write pulse are different.

[0088] Figure 9 This is a schematic diagram of the read windows of different memories provided in embodiments of this disclosure. Wherein, Figure 9 Figure (A) is a schematic diagram of the read window of the selector-only memory provided in an embodiment of this disclosure. Figure 9 Figure (B) is a schematic diagram of the read window of the resistive random access memory provided in an embodiment of this disclosure. Figure 9 Figure (C) is a schematic diagram of the read window of the memory 200 provided in an embodiment of this disclosure.

[0089] Reference Figure 9As shown, the read window of the selector-only memory is denoted as R1, the read window of the resistive random access memory is denoted as R2, and the read window of the memory 200 provided in this embodiment is denoted as R3, where R3 > R1 > R2. That is, the read window of the memory 200 provided in this embodiment is larger than the read window of the selector-only memory and the read window of the memory 200 provided in this embodiment is larger than the read window of the resistive random access memory.

[0090] Figure 10 This is a current distribution diagram of different memories under different voltages provided in embodiments of this disclosure. Figure 10 Figure (A) is a current distribution diagram of the selector-only memory under different voltages provided in the embodiments of this disclosure. Figure 10 Figure (B) in the figure is a current distribution diagram of the resistive random access memory provided in the embodiments of this disclosure under different voltages. Figure 10 Figure (C) in the present disclosure is a current distribution diagram of the memory 200 under different voltages provided in the embodiment of the present disclosure.

[0091] Reference Figure 10 As shown, the current of the memory 200 provided in this embodiment of the present disclosure at Vt / 2 (half of the threshold voltage) is less than the current of the selector-only memory at Vt / 2, and the current of the memory 200 provided in this embodiment of the present disclosure at Vt / 2 is less than that of the resistive random access memory at Vt / 2. Therefore, the memory 200 provided in this embodiment of the present disclosure can effectively reduce the leakage current of the memory cell array.

[0092] The products disclosed in the several product embodiments provided in this disclosure can be arbitrarily combined to obtain new product embodiments without conflict.

[0093] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0094] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0095] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0096] The above description is merely an embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A memory, characterized in that, include: A storage unit comprising a first electrode layer, a first storage layer, a second electrode layer, a second storage layer, and a third electrode layer stacked sequentially, wherein the material of the second storage layer is different from the material of the first storage layer; Both the first storage layer and the second storage layer are configured to store either the first logical data or the second logical data, wherein the second logical data is different from the first logical data.

2. The memory according to claim 1, characterized in that, The thickness of the first storage layer is the same as the thickness of the second storage layer.

3. The memory according to claim 1, characterized in that, The orthographic projections of the first storage layer and the second storage layer overlap.

4. The memory according to claim 1, characterized in that, The second electrode layer includes a first barrier layer, a sub-electrode layer and a second barrier layer stacked sequentially, wherein the first barrier layer is located between the first storage layer and the sub-electrode layer, and the second barrier layer is located between the sub-electrode layer and the second storage layer.

5. The memory according to claim 4, characterized in that, The materials of the first barrier layer and the second barrier layer include metal nitrides; the material of the sub-electrode layer includes carbon.

6. The memory according to claim 1, characterized in that, The first storage layer is one of a bidirectional threshold conversion layer and a resistive switching layer, and the second storage layer is the other of the bidirectional threshold conversion layer and the resistive switching layer.

7. The memory according to claim 6, characterized in that, The resistive switching layer is made of at least one of germanium selenide arsenic, germanium telluride arsenic, germanium selenide telluride selenium, germanium selenide, selenium arsenide, germanium telluride, silicon telluride, hafnium oxide, titanium oxide, tantalum oxide, silicon oxide, nickel oxide, tin oxide, and aluminum oxide; the bidirectional threshold switching layer is made of at least one of zinc telluride, germanium telluride, niobium oxide, silicon arsenide telluride, vanadium oxide, iron oxide, neodymium nickel oxide, samarium nickel oxide, lanthanum cobalt oxide, gadolinium cobalt oxide, aluminum telluride, boron telluride, germanium selenide, germanium sulfide, and antimony telluride.

8. The memory according to claim 1, characterized in that, The memory includes a write drive circuit coupled to the memory cell; the write drive circuit is configured to: A first write pulse is applied to the memory cell, causing the first memory layer to store the first logical data and the second memory layer to store the second logical data; A second write pulse is applied to the memory cell, such that the first memory layer stores the first logical data and the second memory layer stores the first logical data, wherein the pulse direction of the second write pulse and the first write pulse are the same, and the pulse amplitude and pulse duration of the second write pulse and the first write pulse are different; A third write pulse is applied to the memory cell, causing the first memory layer to store the second logical data and the second memory layer to store the first logical data; A fourth write pulse is applied to the memory cell, such that the first memory layer stores the second logical data and the second memory layer stores the second logical data. The fourth write pulse and the third write pulse have the same pulse direction, the fourth write pulse and the first write pulse have opposite pulse directions, and the pulse amplitude and pulse duration of the fourth write pulse and the third write pulse are different.

9. The memory according to claim 8, characterized in that, The pulse amplitude of the first write pulse and the third write pulse ranges from 20 μA to 30 μA, and the pulse duration of the first write pulse and the third write pulse ranges from 5 nanoseconds to 100 nanoseconds; the pulse amplitude of the second write pulse and the fourth write pulse ranges from 50 μA to 100 μA, and the pulse duration of the second write pulse and the fourth write pulse ranges from 20 nanoseconds to 1000 nanoseconds, and the pulse duration of the second write pulse and the fourth write pulse is greater than the pulse duration of the first write pulse and the third write pulse.

10. A method for operating a memory, characterized in that, For operating the memory according to any one of claims 1 to 9, including: A first write pulse is applied to a memory cell of the memory, such that a first storage layer of the memory cell stores first logical data and a second storage layer of the memory cell stores second logical data, wherein the material of the second storage layer is different from the material of the first storage layer, and the second logical data is different from the first logical data; A second write pulse is applied to the memory cell, such that the first memory layer stores the first logical data and the second memory layer stores the first logical data, wherein the pulse direction of the second write pulse and the first write pulse are the same, and the pulse amplitude and pulse duration of the second write pulse and the first write pulse are different; A third write pulse is applied to the memory cell, causing the first memory layer to store the second logical data and the second memory layer to store the first logical data; A fourth write pulse is applied to the memory cell, such that the first memory layer stores the second logical data and the second memory layer stores the second logical data. The fourth write pulse and the third write pulse have the same pulse direction, the fourth write pulse and the first write pulse have opposite pulse directions, and the pulse amplitude and pulse duration of the fourth write pulse and the third write pulse are different.

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