Systems and methods for stacked memory packages

Abstract

A memory device includes a plurality of memory dies arranged in a stack, where electrical connectors are configured to transmit signals to and from the memory dies. The memory dies are encapsulated within a first molding compound such that ends of the electrical connectors extend to an active surface of the first molding compound. The first molding compound has a recess in the active surface. A memory controller die is located in the recess. The memory controller die is encapsulated in a second molding compound in the recess and has an active surface that is coplanar with the active surface of the first molding compound.

Description

Background Technology

[0001] This disclosure relates to non-volatile memory.

[0002] Semiconductor memories are widely used in a variety of electronic devices, such as cellular phones, digital cameras, personal digital assistants, medical electronic devices, mobile computing devices, servers, solid-state drives, non-mobile computing devices, and other devices. Semiconductor memories can include non-volatile memory or volatile memory. Non-volatile memory allows information to be stored and retained even when it is not connected to a power source (e.g., a battery).

[0003] Memory structures in a memory system typically contain many memory cells and various control lines. Memory structures can be three-dimensional (3D) and can include vertical NAND strings. Other memory structures can also be used.

[0004] Memory systems may have control circuitry to perform various operations (e.g., read, write, and erase). Some or all of the control circuitry may reside on a separate die (e.g., the memory structure may be located on the memory die, and the control circuitry may be located on a control die bonded to the memory die). Memory dies (with or without control dies) may be arranged in a stacked configuration. In some cases, a memory system may include a memory controller die and / or other dies connected to the stack of memory dies. Electrically connecting the dies in a reliable and cost-effective manner in such memory systems can be challenging. Attached Figure Description

[0005] Elements with the same number represent common parts in different figures.

[0006] Figure 1 It is a block diagram depicting one implementation of a storage system.

[0007] Figure 2A This is a block diagram of one implementation scheme for a memory die.

[0008] Figure 2B This is a block diagram of one implementation scheme for an integrated memory component.

[0009] Figure 3A and Figure 3B Different implementation schemes of the memory component are described.

[0010] Figure 4 A die stack with electrical conductors (bonding wires) is shown.

[0011] Figure 5 A die stack including a stepped region with electrical conductors is shown.

[0012] Figures 6A to 6CAn example of an encapsulated die stack is shown.

[0013] Figures 7A to 7I An example of an encapsulated die stack with an additional die located in a recess is shown.

[0014] Figures 8A to 8C An example of a recess formed for an additional die is shown.

[0015] Figures 9A to 9B An example of a die stack with a bonding line on one side is shown.

[0016] Figures 10A to 10B An example of an encapsulated die stack with two die stacks is shown, each die stack having a bonding line on one side.

[0017] Figure 11 An example is shown that includes positioning one or more additional dies in a recess and filling the recess with a molding compound. Detailed Implementation

[0018] A die stack can be formed from multiple dies, which may include memory dies and may be encapsulated (e.g., using a molding compound). Bonding lines may extend from the die stack (e.g., vertically) to establish connections between the die stack and additional dies (e.g., memory controller dies, volatile memory dies, and / or integrated passive device (IPD) dies). The ends of the bonding lines may be exposed along the active surface of a sealant (e.g., a molding compound). In an example, a recess (e.g., a trench) is formed above the die stack in the sealant, and one or more additional dies are located in the recess such that the active surfaces of one or more additional dies are coplanar with the active surface of the sealant, and the ends of the bonding lines are exposed along that active surface. For example, the additional dies may be mounted face-down on a flat surface of a carrier (e.g., where the active surfaces contact the flat surface of the carrier). Another sealant (a second molding compound) then fills the recess around one or more additional dies in the recess such that they maintain a coplanar arrangement. The carrier can be removed to expose the active surface of the sealant and the additional die (which are coplanar). The redistribution layer (RDL) can then be attached to the ends of the exposed bonding wires and to the bonding pads on the active surface of the additional die to form a proper electrical connection between the die stack and the additional die.

[0019] This technology relates to technical problems associated with connecting and packaging die stacks (e.g., stacks comprising multiple memory dies) and additional dies (e.g., one or more memory controller dies, volatile memory dies, and / or integrated passive device dies). This technology provides a solution comprising forming recesses or trenches in a sealant within an encapsulated die stack, positioning additional dies (e.g., memory controllers) within the recesses such that they have active surfaces coplanar with the ends of bonding wires, and filling the recesses with sealant to maintain a coplanar arrangement. A redistribution layer (RDL) can then connect the additional dies and the die stack.

[0020] Figure 1 This is a block diagram of one embodiment of the storage system 100 implementing the techniques described herein. In one embodiment, the storage system 100 is a solid-state drive (“SSD”). The storage system 100 may also be a memory card, a USB drive, or other type of storage system. The proposed techniques are not limited to any one type of storage system. The storage system 100 is connected to a host 102, which may be a computer, server, electronic device (e.g., a smartphone, tablet, or other mobile device), electrical appliance, or another device that uses memory and has data processing capabilities. In some embodiments, the host 102 is separate from but connected to the storage system 100. In other embodiments, the storage system 100 is embedded within the host 102.

[0021] Figure 1 The components of the storage system 100 depicted are circuits. The storage system 100 includes a memory controller 120 (or memory controller) connected to a non-volatile storage device 130 and a local high-speed memory 140 (e.g., DRAM, SRAM, MRAM). The local high-speed memory 140 is a non-transitory memory, which may include volatile or non-volatile memory. The memory controller 120 uses the local high-speed memory 140 to perform certain operations. For example, the local high-speed memory 140 may store a logic-to-physical address translation table (“L2P table”).

[0022] The memory controller 120 includes a host interface 152 that connects to and communicates with the host 102. In one embodiment, the host interface 152 implements NVM Express (NVMe) via PCI Express (PCIe). Other interfaces, such as SCSI, SATA, etc., may also be used. The host interface 152 is also connected to a network on-chip (NOC) 154. The NOC is a communication subsystem on an integrated circuit. The NOC can span synchronous and asynchronous clock domains or use non-clock asynchronous logic. NOC technology applies networking theory and methods to on-chip communication, resulting in significant improvements over conventional buses and crossbar interconnects. Compared to other designs, the NOC improves the scalability of the system-on-chip (SoC) and the power efficiency of complex SoCs. The wires and links of the NOC are shared by many signals. Because all links in the NOC can operate simultaneously on different data packets, a high level of parallelism is achieved. Therefore, as the complexity of integrated subsystems continues to increase, the NOC provides enhanced performance (such as throughput) and scalability compared to previous communication architectures (e.g., dedicated point-to-point signal lines, shared buses, or segmented buses with bridges). In other implementations, NOC 154 can be replaced by a bus.

[0023] Connected to and communicating with NOC 154 are processor 156, ECC engine 158, memory interface 160, and local memory controller 164. Local memory controller 164 is used to operate and communicate with local high-speed memory 140 (e.g., DRAM, SRAM, MRAM).

[0024] ECC engine 158 performs error correction services. For example, ECC engine 158 performs data encoding and decoding. In one embodiment, ECC engine 158 is a software-programmable electrical circuit. For example, ECC engine 158 may be a programmable processor. In other embodiments, ECC engine 158 is a custom-designed dedicated hardware circuit without any software. In yet another embodiment, the functionality of ECC engine 158 is implemented by processor 156.

[0025] Processor 156 performs various controller memory operations, such as programming, erasing, reading, and memory management processes. In one embodiment, processor 156 is programmed by firmware. In other embodiments, processor 156 is a custom-designed dedicated hardware circuit without any software. Processor 156 may also implement a translation module as software / firmware processing or dedicated hardware circuitry. In many systems, non-volatile memory is internally addressed to the memory system using physical addresses associated with one or more memory dies. However, the host system will use logical addresses to address various memory locations. This allows the host to assign data to consecutive logical addresses while the memory system is free to store data as desired between locations on one or more memory dies. To implement this system, memory controller 120 (e.g., translation module) performs address translation between logical addresses used by the host and physical addresses used by the memory dies. An example specific implementation maintains a table identifying the current translation between logical and physical addresses (i.e., the L2P table mentioned above). Entries in the L2P table may include identifiers for logical addresses and their corresponding physical addresses. Although logical address to physical address tables (or L2P tables) include the word "table," they do not need to be tables in the literal sense. Instead, logical address to physical address tables (or L2P tables) can be any type of data structure. In some examples, the memory space of the storage system is so large that local memory 140 cannot hold all the L2P tables. In this case, the entire set of L2P tables is stored in storage device 130, and a subset of the L2P tables is cached (the L2P cache) in local memory 140.

[0026] Memory interface 160 communicates with non-volatile memory device 130. In one embodiment, memory interface 160 provides a switching mode interface. Other interfaces may also be used. In some example implementations, memory interface 160 (or another part of memory controller 120) implements a scheduler and buffer for transferring data to and receiving data from one or more memory dies.

[0027] In one embodiment, the non-volatile memory device 130 includes one or more memory dies. Figure 2A This is a functional block diagram of one embodiment of a memory die 200 including a non-volatile memory device 130. Each memory die in one or more memory dies of the non-volatile memory device 130 can be implemented as follows: Figure 2A The memory die 200. Figure 2AThe components depicted are circuits. Memory die 200 includes a memory structure 202 (e.g., a memory array) that may include non-volatile memory cells (also referred to as non-volatile memory units), as described in more detail below. The array terminal lines of memory structure 202 include various layers of word lines organized into rows and various layers of bit lines organized into columns. However, other orientations may also be implemented. Memory die 200 includes row control circuitry 220, the output of which is connected to a corresponding word line of memory structure 202. Row control circuitry 220 receives a set of M row address signals and one or more various control signals from system control logic 260, and typically includes circuitry such as a row decoder 222, an array driver 224, and a block select circuitry 226 for both read and write (programming) operations. Row control circuitry 220 may also include read / write circuitry. Memory die 200 also includes column control circuitry 210, which includes read / write circuitry 225. Read / write circuitry 225 may include a sense amplifier and a data latch. The sense amplifier input / output is connected to the corresponding bit lines of memory structure 202. Although only a single block is shown for memory structure 202, the memory die may include multiple arrays that can be accessed individually. Column control circuitry 210 receives a set of N column address signals and one or more various control signals from system control logic 260, and typically includes circuitry such as column decoder 212, array terminal receiver or driver circuitry 214, block select circuitry 216, read / write circuitry, and I / O multiplexer circuitry.

[0028] System control logic 260 receives data and commands from memory controller 120 and provides output data and status to the host. In some embodiments, system control logic 260 (which includes one or more circuits) includes a state machine 262 that provides die-level control for memory operations. In one embodiment, state machine 262 is programmable by software. In other embodiments, state machine 262 does not use software and is implemented entirely in hardware (e.g., electrical circuitry). In yet another embodiment, state machine 262 is replaced by a microcontroller or microprocessor on or off the memory chip. System control logic 260 may also include a power control module 264 that controls the power and voltage supplied to rows and columns of memory structure 202 during memory operations. System control logic 260 includes a storage device 266 (e.g., RAM, registers, latches, etc.) that can be used to store parameters for operating memory structure 202.

[0029] Commands and data are transmitted between memory controller 120 and memory die 200 via memory controller interface 268 (also referred to as the "communication interface"). Memory controller interface 268 is an electrical interface used for communicating with memory controller 120. Examples of memory controller interface 268 include a switching mode interface and an Open NAND Flash Interface (ONFI). Other I / O interfaces may also be used.

[0030] In some embodiments, all components of memory die 200 (including system control logic 260) may be formed as part of a single die. In other embodiments, some or all of the system control logic 260 may be formed on a different die than the die containing memory structure 202.

[0031] In one embodiment, memory structure 202 includes a three-dimensional memory array of non-volatile memory cells, wherein multiple memory levels are formed over a single substrate, such as a wafer. The memory structure can include any type of non-volatile memory formed monolithically in memory cells having one or more physical levels of active regions located over a silicon substrate (or other type of substrate). In one example, the non-volatile memory cells include vertical NAND strings with charge trapping layers.

[0032] In another embodiment, memory structure 202 includes a two-dimensional memory array of non-volatile memory cells. In one example, the non-volatile memory cells are NAND flash memory cells utilizing floating gates. Other types of memory cells (e.g., NOR flash memory) may also be used.

[0033] The exact type of memory array architecture or memory cell included in memory structure 202 is not limited to the examples above. Many different types of memory array architectures or memory technologies can be used to form memory structure 202. For the purposes of the embodiments of the new claims presented herein, no specific non-volatile memory technology is required. Other examples of suitable technologies for memory cells of memory structure 202 include ReRAM memory (resistive random access memory), magnetoresistive memory (e.g., MRAM, spin-torque MRAM, spin-orbit MRAM), FeRAM, phase-change memory (e.g., PCM), etc. Examples of suitable technologies for memory cell architectures of memory structure 202 include two-dimensional arrays, three-dimensional arrays, cross-point arrays, stacked two-dimensional arrays, vertical bitline arrays, etc.

[0034] One example of a ReRAM crosspoint memory includes a reversible resistive switching element arranged as a crosspoint array accessed by X-lines and Y-lines (e.g., word lines and bit lines). In another embodiment, the memory cell may include a conductive bridge memory element. A conductive bridge memory element may also be referred to as a programmable metallized cell. The conductive bridge memory element can be used as a state-changing element based on the physical relocation of ions within a solid electrolyte. In some cases, the conductive bridge memory element may include two solid metal electrodes, one relatively inert (e.g., tungsten) and the other electrochemically active (e.g., silver or copper), with a solid electrolyte film between the two electrodes. As temperature increases, ion mobility also increases, resulting in a decrease in the programming threshold of the conductive bridge memory cell. Therefore, the conductive bridge memory element can have a wide range of programming thresholds that vary with temperature.

[0035] Another example is magnetoresistive random access memory (MRAM) that stores data via magnetic memory elements. This element is formed of two ferromagnetic layers, each of which can remain magnetized, separated by a thin insulating layer. One of these layers is a permanent magnet set to a specific polarity; the magnetization of the other layer can be changed to match the magnetization of an external field, thereby storing memory. Memory devices are constructed from a grid of such memory cells. In one embodiment for programming, each memory cell is located between a pair of write lines arranged perpendicular to each other, parallel to the cell, one above and one below. When current flows through the pair of write lines, an induced magnetic field is generated. MRAM-based memory implementations will be discussed in more detail below.

[0036] Phase-change memories (PCMs) utilize the unique behavior of chalcogenides. One embodiment uses a GeTe-Sb₂Te₃ superlattice to achieve a non-thermal phase transition by simply changing the coordination state of germanium atoms with a laser pulse (or a light pulse from another source). Therefore, the programming dose is the laser pulse. A memory cell can be disabled by blocking it from receiving light. In other PCM embodiments, the memory cell is programmed by a current pulse. It should be noted that the use of "pulse" herein does not require a square pulse, but rather includes (continuous or discontinuous) vibrations or bursts of sound, current, voltage, light, or other waves. These memory elements within a single selectable memory cell or bit may include another cascaded element as a selector, such as a bidirectional threshold switch or a metallic insulator substrate.

[0037] Those skilled in the art will recognize that the techniques described herein are not limited to a single particular memory structure, memory construction, or material composition, but encompass many related memory structures as described herein and as understood by those skilled in the art.

[0038] Figure 2AThe components can be divided into two parts: (1) memory structure 202 and (2) peripheral circuitry, which includes... Figure 2A All other components depicted herein. A key characteristic of memory circuitry is its capacity, which can be increased by increasing the area of ​​the memory die of memory system 100 on memory structure 202; however, this reduces the area of ​​the memory die available for peripheral circuitry. This can impose fairly strict limitations on these components of the peripheral circuitry. For example, the need to fit sense amplifier circuitry within the available area can significantly limit the sense amplifier design architecture. Regarding system control logic 260, the reduced area availability can limit the available functionality that can be implemented on-chip. Therefore, the fundamental trade-off in the design of the memory die for memory system 100 is the amount of area dedicated to memory structure 202 and the amount of area dedicated to peripheral circuitry.

[0039] Another area where the memory structure 202 and peripheral circuitry are often inconsistent is the processing involved in forming these regions, as these regions typically involve different processing techniques and trade-offs in using different techniques on a single die. For example, when the memory structure 202 is NAND flash memory, it is an NMOS structure, while the peripheral circuitry is typically CMOS-based. For instance, components such as sense amplifier circuitry, charge pumps, logic elements in state machines, and other peripheral circuitry in system control logic 260 typically employ PMOS devices. The processing operations used to manufacture CMOS dies will differ in many ways from those optimized for NMOS flash NAND memory or other memory cell technologies. Three-dimensional NAND structures, in particular, can benefit from specialized processing operations.

[0040] To mitigate these limitations, the implementation scheme described below can... Figure 2AThe components are separated onto individually formed dies, which are then bonded together. More specifically, the memory structure 202 can be formed on a single die (referred to as the memory die), and some or all of the peripheral circuitry elements (including one or more control circuits) can be formed on separate dies (referred to as the control die). For example, the memory die can be formed solely of memory elements, such as flash NAND memory, MRAM memory, PCM memory, ReRAM memory, or other memory cell arrays of other memory types. Some or all of the peripheral circuitry (even including elements such as decoders and sense amplifiers) can then be moved to separate control dies. This allows each memory die within the memory die to be individually optimized according to its technology. For example, a NAND memory die can be optimized for an NMOS-based memory array structure without worrying about CMOS elements that have now been moved to a control die that can be optimized for CMOS processing. This frees up more space for peripheral elements, which can now incorporate additional capabilities that would otherwise be difficult to incorporate due to the limited margin of the same die for maintaining the memory cell array. Two dies can then be bonded together in a bonded multi-die memory circuit, with an array on one die connected to peripheral components on the other die. While the following will focus on a bonded memory circuit with one memory die and one control die, other embodiments may use more dies, such as, for example, two memory dies and one control die.

[0041] Figure 2B It shows Figure 2A An alternative arrangement of the arrangement, which can be implemented using wafer-to-wafer bonding to provide bonded die pairs. Figure 2B A functional block diagram of one embodiment of the integrated memory assembly 207 is depicted. One or more integrated memory assemblies 207 may be used to implement the non-volatile memory device 130 of the memory system 100. The integrated memory assembly 207 includes two types of semiconductor dies (or more simply, "dies"). Memory structure die 201 includes memory structure 202. Memory structure 202 includes non-volatile memory cells. Control die 211 includes control circuitry 260, 210, and 220 (as described above). In some embodiments, control die 211 is configured to be connected to memory structure 202 within memory structure die 201. In some embodiments, memory structure die 201 and control die 211 are coupled together.

[0042] Figure 2B An example of peripheral circuitry (including control circuitry) is shown, which is formed in the peripheral circuitry or control die 211 of the memory structure 202 formed in the memory structure die 201. General components and Figure 2ASimilarly labeled. System control logic 260, row control circuitry 220, and column control circuitry 210 are located in control die 211. In some embodiments, all or part of column control circuitry 210 and all or part of row control circuitry 220 are located on memory structure die 201. In some embodiments, some circuitry in system control logic 260 is located on memory structure die 201.

[0043] System control logic 260, row control circuitry 220, and column control circuitry 210 can be formed using a common process (e.g., CMOS process), so that additional elements and functionalities (such as ECC) more commonly found on memory controller 120 may require few or no additional process steps (i.e., the same process steps used to manufacture memory controller 120 can also be used to manufacture system control logic 260, row control circuitry 220, and column control circuitry 210). Therefore, while moving such circuitry from a die such as memory structure die 201 can reduce the number of steps required to manufacture such a die, adding such circuitry to a die such as control die 211 may not require many additional process steps. Control die 211 may also be referred to as a CMOS die because some or all of the control circuitry 260, 210, and 220 are implemented using CMOS technology.

[0044] Figure 2B A column control circuit 210, including read / write circuitry 225 on a control die 211, is shown. This column control circuit is coupled to a memory structure 202 on a memory structure die 201 via an electrical path 206. For example, the electrical path 206 may provide electrical connections between the column decoder 212, driver circuitry 214, and block select circuitry 216 and the bit lines of the memory structure 202. The electrical path may extend from the column control circuitry 210 in the control die 211 through pads on the control die 211 that are bonded to corresponding pads on the memory structure die 201, which are connected to the bit lines of the memory structure 202. Each bit line of the memory structure 202 may have a corresponding electrical path in the electrical path 206, including a pair of bonded pads connected to the column control circuitry 210. Similarly, a row control circuitry 220, including a row decoder 222, an array driver 224, and block select circuitry 226, is coupled to the memory structure 202 via an electrical path 208. Each electrical path in electrical path 208 may correspond to a word line, a virtual word line, or a select gate line. Additional electrical paths may also be provided between the control die 211 and the memory structure die 201.

[0045] For the purposes of this document, the phrase "control circuitry" or "one or more control circuits" may include any or any combination of the following: memory controller 120, state machine 262, power control module 264, all or part of system control logic 260, all or part of row control circuitry 220, all or part of column control circuitry 210, read / write circuitry 225, sense amplifier, microcontroller, microprocessor, and / or other similar functional circuitry. Control circuitry may consist of hardware only or a combination of hardware and software (including firmware). For example, a controller programmed by firmware to perform the functions described herein is an example of control circuitry. Control circuitry may include processors, FPGAs, ASICs, integrated circuits, or other types of circuitry.

[0046] For the purposes of this document, the term "device" may include, but is not limited to, one or more of the following: storage system 100, memory controller 120, storage device 130, memory die 200, integrated memory assembly 207, and / or control die 204.

[0047] In some embodiments, the integrated memory assembly 207 contains more than one control die 204 and more than one memory structure die 200. In some embodiments, the integrated memory assembly 207 includes a stack of multiple control dies 204 and multiple memory structure dies 200.

[0048] Figure 3A A side view depicts an embodiment of an integrated memory component 207 (e.g., a stack including control dies 204 and memory structure dies) stacked on a substrate 271. The integrated memory component 207 has three control dies 204 and three memory structure dies 200. In some embodiments, there are more than three memory structure dies 200 and more than three control dies 204. Figure 3A In the original embodiment, there are an equal number of memory structure dies 200 and control dies 204; however, in one embodiment, there are more memory structure dies 200 than control dies 204. For example, one control die 204 can control multiple memory structure dies 200.

[0049] Each control die 204 is attached (e.g., bonded) to at least one of the memory structure dies 200. Some of the bonding pads 282 / 284 are depicted. More bonding pads may be present. The space between the two dies 200, 204 bonded together is filled with a solid layer 280, which may be formed of epoxy resin or other resins or polymers. The solid layer 280 protects the electrical connection between the dies 200, 204 and further secures the dies together. Various materials may be used as the solid layer 280.

[0050] The integrated memory components 207 can be stacked, for example, with a stepped offset, so that the bonding pads at each level are not covered and are accessible from above. Bonding lines 270 connected to the bonding pads connect the control die 204 to the substrate 271. These lines can span the width of each control die 204 (i.e., into...). Figure 3A (Multiple such joining lines are formed on the page.)

[0051] A through-silicon via (TSV) 276 for memory die can be used to route signals through memory structure die 200. A through-silicon via (TSV) 278 for control die 204 can be used to route signals through control die 204. TSVs 276 and 278 can be formed before, during, or after the formation of integrated circuits in dies 200 and 204. TSVs can be formed by etching through the holes in the wafer. The holes can then be lined with a barrier layer to prevent metal diffusion. The barrier layer can then be lined with a seed layer, and the seed layer can be plated with an electrical conductor such as copper, but other suitable materials such as aluminum, tin, nickel, gold, doped polysilicon, and alloys or combinations thereof can also be used.

[0052] Solder balls 272 may optionally be attached to contact pads 274 on the lower surface of substrate 271. Solder balls 272 may be used to electrically and mechanically couple integrated memory component 207 to a host device such as a printed circuit board. Solder balls 272 may be omitted if integrated memory component 207 is to be used in an LGA package. Solder balls 272 may form part of the interface between integrated memory component 207 and memory controller 120.

[0053] Figure 3B A side view depicting another embodiment of an integrated memory assembly 207 stacked on a substrate 271. Figure 3B The integrated memory component 207 has three control dies 204 and three memory structure dies 200. In some embodiments, there are more than three memory structure dies 200 and more than three control dies 204. In this example, each control die 204 is coupled to at least one memory structure die 200. Alternatively, the control die 204 may be coupled to two or more memory structure dies 200.

[0054] Some of the bonding pads 282 and 284 are shown. More bonding pads may be present. The space between the two joined dies 200 and 204 is filled with a solid layer 280, which may be formed of epoxy resin or other resins or polymers. Figure 3A The example in the middle is the opposite. Figure 3BThe integrated memory component 207 in the memory structure does not have a stepped offset. A through-silicon via (TSV) 276 can be used to route signals through the memory structure die 200. A through-silicon via (TSV) 278 can be used to route signals through the control die 204.

[0055] Solder balls 272 may optionally be attached to contact pads 274 on the lower surface of substrate 271. Solder balls 272 may be used to electrically and mechanically couple integrated memory component 207 to host devices such as printed circuit boards. Solder balls 272 may be omitted if integrated memory component 207 is to be used as an LGA package.

[0056] As briefly discussed above, the control die 204 and the memory structure die 200 can be bonded together. Bonding pads on each die 200, 204 can be used to bond the two dies together. In some embodiments, in a so-called Cu-Cu bonding process, the bonding pads are directly bonded to each other without solder or other additives. In a Cu-Cu bonding process, the bonding pads are controlled to be highly flat and formed in a highly controlled environment largely free of environmental particles that could otherwise deposit on the bonding pads and prevent a tight bond. Under such properly controlled conditions, the bonding pads are aligned and pressed against each other to form a bond based on surface tension. Such a bond can be formed at room temperature, although heat can also be applied. In embodiments using Cu-Cu bonding, the bonding pads can be approximately 5 μm squares and spaced apart from each other at a pitch of 5 μm to 5 μm. Although this process is referred to herein as Cu-Cu bonding, the term can also be applied when the bonding pads are formed of materials other than Cu.

[0057] When the area of ​​the bonding pads is small, it can be difficult to bond semiconductor dies together. The size and spacing of the bonding pads can be further reduced by providing a thin film layer on the surface of the semiconductor die, including the bonding pads. The thin film layer is disposed around the bonding pads. When the dies are placed together, the bonding pads can bond to each other, and the film layers on the respective dies can bond to each other. Such a bonding technique can be referred to as hybrid bonding. In embodiments using hybrid bonding, the bonding pads can be approximately 5 μm squares and spaced apart from each other with a pitch of 1 μm to 5 μm. Bonding techniques can be used to provide bonding pads with even smaller sizes and pitches.

[0058] Some embodiments may include a membrane on the surfaces of dies 200, 204. If no such membrane is initially provided, the space between the dies may be underfilled with epoxy resin or other resins or polymers. The underfill material may be applied as a liquid, which then hardens into a solid layer. This underfilling step protects the electrical connection between dies 200, 204 and further secures the dies together. Various materials are available as underfill materials.

[0059] Figures 4 to 5 Another example of a stacked semiconductor die 106 in semiconductor package 136 is shown. Semiconductor die 106 can be, for example, a memory die such as a NAND flash memory die, but other types of dies 106 can be used. The memory die can be in the form of an integrated memory assembly (also known as a CMOS bonding array or “CbA” module) comprising memory dies bonded to a control die (e.g., a logic or CMOS die). Semiconductor die 106 can be offset ( Figure 3A ) or double offset ( Figure 4 The die stacks are arranged in a stepped configuration on top of each other to form a die stack 110, which is shown as extending in the z direction (e.g., the dies are stacked along the z direction). Figure 4 The dual-offset configuration may include a spacer block 112 to support the upper die 106 during in-line bonding and encapsulation. In another embodiment, the spacer block may be omitted.

[0060] In the example shown, semiconductor package 136 includes eight semiconductor dies 106. However, in other embodiments, die stack 110 may include more or fewer than eight semiconductor dies, including, for example, 2, 4, 16, and 32 semiconductor dies. Dies 106 can be secured to each other in die stack 110 using DAF (die attachment film). As an example, DAF may be 8988UV epoxy resin from Henkel Corporation, California, USA.

[0061] In some examples, the memory controller die 114 may be mounted on top of the die stack 110. The memory controller die 114 may be an ASIC for controlling the flow of data and signals to / from the die stack 110 (e.g., it may include some or all of the circuitry of the memory controller 120, such as host interface circuitry 152 and memory interface circuitry 160).

[0062] Once the die stack 110 and the memory controller die 114 are mounted on the carrier 101, the corresponding dies 106 and 114 can be electrically connected to each other using the bonding wire 118. Figure 4 and Figure 5Simplified edge and perspective views are shown, with some bonding lines shown for illustrative purposes. More bonding lines 118 may be present than shown. Each semiconductor die 106 may include a row of die bonding pads 121 along one or both edges of the die 106. It should be understood that each die 106 may include more than... Figure 5 More die bonding pads 121 are shown. Each die bonding pad 121 in a row of semiconductor dies can be electrically connected to the corresponding die bonding pad 121 in the next adjacent row of semiconductor dies using bonding lines 118 formed as described below.

[0063] To connect the bonding lines 118, in one embodiment, column bumps 126 may initially be deposited on each die bonding pad in the die bonding pads 121. After the column bumps 126 are deposited on the bonding pads 121, stitch bonds 118 may be formed on the column bumps 126 on die 106 (e.g., on the bottom die 106) up to the corresponding column bumps 126 on the next higher die (e.g., the second die 106 starting from the bottom). This process may be repeated upwards along the die stack 110 until bonding lines 118 are formed between all corresponding die bonding pads 121 in the columns of die bonding pads in the die stack 110.

[0064] To form the fan-out package of this technology, external electrical connections can be made from the die stack upwards (e.g., along the z-direction). Thus, the die stack 110 may also include vertical direct connection 122 for external electrical connections (e.g., forming electrical connectors configured to transmit signals to and from a plurality of memory dies in the stack). Figure 4 and Figure 5 The vertical direct line 122 shown is only an example, and there may be more or fewer vertical direct lines 122 in other embodiments.

[0065] After the electrical connection is formed, the die stack 110 can be encapsulated in molding compound 134 (sealant), such as Figure 6AAs shown. The molding compound can be applied to the surface of carrier 101 to surround and encapsulate die stack 110 and memory controller die 114, as well as bonding lines 118 and 122. Molding compound 134 may include, for example, solid epoxy resin, phenolic resin, fused silica, crystalline silica, carbon black, and / or metal hydroxide. Such molding compound can be obtained from, for example, Sumitomo Corp. and Nitto-Denko Corp., both headquartered in Japan. Other molding compounds from other manufacturers are also considered. The molding compound can be applied according to various known processes, including FFT (flow-free thin) molding, transfer molding, or injection molding techniques.

[0066] At this stage, the corresponding fan-out package can be confined within the molding compound 134. As shown, the total coverage area (length and width) of the semiconductor die 106 and the total coverage area of ​​the die stack 110 can be slightly smaller than the coverage area of ​​the molding compound 134 in the fan-out package. As explained below, RDL pads can be attached to the molding compound, and these RDL pads can have the same coverage area as the surface of the molding compound to which they are attached. Multiple semiconductor packages 136 can be formed on a first temporary carrier 101. The molding compound can be applied to the entire surface of the rigid carrier 101 to form a molding compound that encapsulates all packages 136 on the carrier 101.

[0067] like Figure 6B As illustrated (showing the result of polishing), the polishing process can be performed on the top surface of the molding compound 134. The polishing process exposes the vertical bonding line 122 and also exposes the cylindrical bump 126 on the top of the memory controller die 114. The surfaces of the molding compound 134 of each fan-out package 136 that include exposed electrical connections are referred herein to as the active surface 134a of the fan-out package 136 and the molding compound 134.

[0068] like Figure 6C As shown, RDL 161 and solder balls 162 can be attached to active surface 134a. RDL 161 includes a first surface with adhesive to directly attach RDL 161 to the active surface 134a of molding compound 134. The first surface of RDL 161 includes a plurality of contact pads having positions and configurations that mate with exposed vertical direct bonding lines 122 and exposed cylindrical bumps 126 on active surface 134a.

[0069] The RDL 161 includes a conductive pattern formed by a plurality of electrical traces and vias (electrical conductors) that electrically couple (effectively, redistribute) the vertical direct connection line 122 and the cylindrical bump 126 to selected solder balls in the solder balls 162. It should be understood that the pattern of solder balls 162, electrical traces, and vias is shown by way of example only, and in other embodiments, the RDL 161 may include other patterns of solder balls 162, traces, and vias.

[0070] In another example (different) Figure 6C In the example shown, one or more dies (such as controller dies and / or other dies) can provide better performance than Figure 6C Some advantageous arrangements are combined with stacks of memory dies (e.g., CbA dies). For example, aspects of this technology include forming die stacks that do not include memory controller dies (e.g., memory dies or CbA dies, such as die stack 110), adding wires (e.g., Figure 4 The bonding lines 118 and 122 are then added, followed by the application of a molding compound. Subsequently, one or more recesses (such as trenches, notches, openings, or other recesses) can be formed in the active surface of the molding compound (e.g., at a location above the stack) to accommodate one or more additional dies (e.g., memory controller dies and / or other dies). The additional dies can be mounted on a carrier aligned with the recesses (trenches, notches, openings, or recesses), with their active sides along a flat surface of the carrier positioned to contact the active surface of the molding compound, such that the active surfaces of the additional dies are coplanar with the active surfaces of the molding compound. A second molding compound can be used to encapsulate the additional dies (e.g., to fill trenches in the first molding compound) and physically attach the additional dies to the package comprising the die stack (e.g., to maintain a coplanar arrangement). RDLs can then be attached such that they connect bonding pads on the active surfaces of the additional dies to the ends of the vertical bonding lines, which are positioned along a common plane. In this arrangement, the column bump 126 may be unnecessary, and the bonding pads on the additional die (e.g., memory controller die 114) can be bonded to the corresponding pads of the RDL without the column bump 126, which can improve reliability and reduce cost.

[0071] Figures 7A to 7I The various aspects of using this technology are illustrated and superiority over alternative methods is provided (e.g., superiority over...). Figures 6A to 6C Examples of methods for stacking encapsulated dies, highlighting their various advantages. Figure 7A An encapsulated die stack 750 is shown, comprising a die stack 110 (e.g., a memory die, which may be bonded or otherwise bonded to a control die) on a carrier 101, wherein bonding lines 118 and 122 are covered by a first molding compound 134. Figure 6A In contrast, in this example, the memory controller die 114 is not placed on the die stack 110 before being encapsulated by the first molding compound 134.

[0072] Figure 7B The image shows the result after removing carrier 101. Figure 7A The encapsulated die stack 750. In some cases, a portion of the carrier 101 and / or the intermediate layer between the carrier 101 and the die stack 110 may be retained at this stage.

[0073] Figure 7C The encapsulated die stack 750 is shown after the removal of the first molding compound 134 to expose the end of the bonding line 122 along the active surface 134a of the first molding compound 134 (e.g., by grinding, polishing, or otherwise removing material to achieve a flat surface). Double-sided grinding or other such techniques may be used to remove any remaining portion of the carrier 101 and / or intermediate layer from opposite sides of the encapsulated die stack 750. Additionally, the first molding compound 134 is removed to form a recess 752 in the active surface 134a (e.g., by removing a portion of the first molding compound 134 after exposing the active surface 134a, such that the recess 752 extends into the first molding compound 134). The recess 752 can be formed in any suitable manner (e.g., mechanical grinding, drilling, scraping, or other mechanical removal; laser ablation; chemical or chemical-mechanical removal, or other methods or combinations thereof). The recess 752 can have any suitable shape (e.g., circular, square, rectangular, or other shapes). In one example, recess 752 is formed by a trench that can extend across multiple encapsulated die stacks. Recess 752 is shown located above die stack 110 (e.g., in the middle or near the encapsulated die stack 750). In other examples, recess 752 may be located at or near the edge of the encapsulated die stack. In some examples, more than one recess may be provided.

[0074] Figure 7D It shows Figure 7C Examples of how the encapsulated die stack 750 can be combined with additional dies. (e.g.) Figure 7C As illustrated, multiple encapsulated die stacks 750 are formed, and... Figure 7D The image shows two encapsulated die stacks. The encapsulated die stack 750 is relative to... Figure 7CThe arrangement is inverted (e.g., active surface 134a is the lower surface and recess 752 faces downwards), with a second carrier 754 (wafer / panel carrier) located below the encapsulated die stack 750. An additional die 756 is mounted on surface 754a of the second carrier 754, with the active surface facing downwards (e.g., the active surface is positioned along and in contact with surface 754a). The active surface of the additional die 756 may have bonding pads for connecting the additional die 756 to the dies of the die stack 110. The additional dies 756 may be spaced in a predetermined pattern. The encapsulated die stack 750 may be aligned with and positioned such that the additional die 756 is located in the recess 752, and the active surface 134a of the encapsulated die stack 750 contacts surface 754a. Surface 754a may be flat or substantially flat, such that the active surface 134a is positioned in contact with surface 754a, and the active surface 134a of the first molding compound 134 (sealant) is positioned coplanarly with the active surface of the additional die 756.

[0075] Figure 7E A second carrier 754 with the encapsulated die stack 750 is shown after the encapsulated die stack 750 is placed such that the active surface 134a contacts the surface 754a, thereby aligning the active surface of the additional die 756 with the active surface 134a of the first molded compound 134. Figure 7E A second molding compound 760 (second sealant) is also shown, which is applied to cover and fill the spaces between the encapsulated die stacks 750. The second molding compound 760 also fills recesses 752. For example, the recesses 752 may be in the form of grooves open at one or more sides, allowing the second molding compound 760 to flow into the recesses 752 (e.g., perpendicular to). Figure 7E (The plane of the cross-sectional view). By filling the recess 752, the second molding compound physically attaches the additional die 756 and the encapsulated die stack 750, so that the coplanar arrangement shown can be maintained (e.g., after the removal of the second carrier 754).

[0076] Figure 7F The encapsulated die stack 750 is shown after the removal of the second carrier 754 and excess second molding compound 760 (e.g., by grinding, polishing, or other means). Removing the second carrier 754 exposes the active surface 756a of the additional die 756 (e.g., exposes the bonding pads on the active surface 756a). Also exposed are the ends of the bonding lines 122 at the active surface 134a of the first molding compound 134, which are coplanar with the active surface 756a.

[0077] Figure 7GThe encapsulated die stack 750 is shown after attaching RDL 161 and solder balls 162. Figure 7G In the middle, the encapsulated die stack 750 relative to Figure 7F The active surfaces 756a and 134a are inverted so that they face upward (positive z-direction) to connect with RDL 161. For example, the lower surface of RDL 161 may be flat or substantially flat, such that the bonding pads along the lower surface contact the corresponding bonding pads on the active surface 756a of the additional die 756 and the ends of the bonding lines 122 at the active surface 134a, enabling bonding without pillar bumps or other such features. RDL 161 connects the pads on the active surface 756a to the ends of the bonding lines 122 at the active surface of the sealant. The combination of the second carrier 754, the second molding compound 760 (second sealant), and RDL 161 can be considered as an example of a component for aligning the active surfaces of the die and the active surfaces of the sealant in a coplanar arrangement, maintaining the coplanar arrangement, and electrically connecting the pads on the active surfaces of the die to the ends of the electrical connectors on the active surfaces of the sealant.

[0078] Figure 7H It shows Figure 7G The encapsulated die stack 750 is obtained by dicing the package to separate individual packages 770. Each individual package 770 includes a die stack connected to additional dies via an RDL 161 having solder balls 162 for connection to additional circuitry (e.g., to a host and / or an additional package).

[0079] Figure 7I A more detailed view of a portion of package 770 is shown, including an interface extending along plane 772 between RDL 161 and the encapsulated die stack 750 (e.g., active surfaces 756a and 134a may extend along plane 772, where they can be bonded to RDL 161). Pairs of bonding pads 774 connect an additional die 756 to RDL 161 (e.g., bonding pads on the active surface 756a of the additional die 756 bond to corresponding bonding pads on the lower surface of RDL 161). A bonding wire 776 connects bonding lines 122 to RDL 161. Circuitry in the additional die 756 can be connected to components of the dies in the encapsulated die stack 750 via RDL 161. Circuitry in the additional die 756 can also be connected to components outside package 770 via solder balls 162.

[0080] In the example, the additional die 756 includes a memory controller die (e.g., a die including some or all of the components of memory controller 120), which is connected via RDL 161 to memory cells in the encapsulated die stack 750. For example, Figure 7I The additional die 756 may be a memory controller die connected to a memory die (to integrate a memory assembly or otherwise) via a pair of bonding pads 774, RDL 161, bonding pads 776, and bonding wires 122. For example, such connections may be used to transmit power supply voltages, clock signals, user data, address data, and / or other electrical signals.

[0081] In some examples, the recess 752 is formed as a trench that can extend across multiple encapsulated die stacks. Figure 8A This shows that the recess 752 extends into the first molding compound and from one edge of the active surface 134a. Figure 8A The front edge of the middle extends to the opposite edge. Figure 8A An example of a groove (at the far edge) is provided, which divides the active surface 134a into two parts, each of which may have an exposed end of a bonding line. The dimensions (depth and lateral dimensions) of the recess 752 are sufficient to accommodate one or more additional dies 756 for connection to the encapsulated die stack 750.

[0082] Figure 8B An example is shown, which provides three additional dies 756_1, 756_2, and 756_3, each of which can be connected via RDL ( Figure 8B(Not shown) is connected to the encapsulated die stack 750 and / or connected to each other and / or connected to external circuitry. While the memory controller die is an example of an additional die that can be included in the additional die 756, the technology is not limited to any one or more specific additional dies. For example, additional die 756_1 may be a memory controller die having some or all of the circuitry and / or other control circuitry of the memory controller 120 (e.g., formed as an application-specific integrated circuit or ASIC). Additional die 765_2 may be a volatile or non-volatile memory (e.g., for use as local or high-speed memory) connected to the memory controller die 756_1. In one example, additional die 756_2 is a dynamic random access memory (DRAM) die, static RAM (SRAM) or other volatile memory die. Additional die 756_3 may be an integrated passive device (IPD) die containing one or more passive components (such as capacitors). In some cases, the capacitors of the IPD die 756_3 can be used by a charge pump to generate a voltage for memory operation that can be higher than the supply voltage (e.g., the supply voltage provided by the host). In some examples, the additional die 756 may include multiple dies performing different functions (e.g., rather than just a single memory controller die), and these dies, which may be smaller than the memory controller die, may be referred to as chiplets. In chiplet design, the memory controller die is divided into independent modules, which may also include AI accelerators, LDPC engines, interfaces, etc. By breaking down a single control die into multiple sub-blocks (i.e., chiplets), functionality can be added or removed from the memory device based on specific performance requirements or desired features.

[0083] Forming the recess 752 as a groove extending from one side of the encapsulated die stack to the opposite side can have several advantages. For example, Figure 8C An example of an encapsulated die stack 750 during the formation of the second molding compound 760 is shown, with arrows illustrating the flow of the second molding compound 760 through the recess 752. Achieving flow in this manner ensures that the recess 752 is adequately filled around the additional die 756 without significant voids, gaps, or air bubbles, allowing the additional die 756 to be firmly and uniformly maintained in a coplanar arrangement.

[0084] Although Figures 8A to 8C The example shows a recess 752 extending intermediately across the active surface 134a, such that it is located directly above the die stack 110 and has an end of a bonding line exposed on either side of the active surface 134a; however, other arrangements are possible, and the technique is not limited to any particular configuration of the active surface and the recess. For example, different arrangements of the active surface and the recess can be convenient for different die stack arrangements.

[0085] Figure 9A An example of an encapsulated die stack 980 is shown, which includes a die stack 982 that is stepped on only one side, such that all bonding wires 122 are on one side of the die stack 982. Figure 9A On the left side of the encapsulated die stack 980. In this example, the recess 752 is located on the other (right) side of the encapsulated die stack 980 (e.g., above the center region of the topmost die in the die stack 982).

[0086] Figure 9B A top view of the encapsulated die stack 980 is shown. Additional dies 756_1, 756_2, and 756_3 are shown in a recess 752 surrounded by a second molding compound 760. The end of the bonding wire 122 is exposed on one side of the recess 752. Figure 9B The active surface 134a is located on the left side of the active surface 134a. The active surface 134a is coplanar with the exposed (upper) surfaces of the additional dies 756_1, 756_2, and 756_3 to facilitate bonding with the flat surface via the RDL. The connection corresponding to the RDL can be configured accordingly to have bonding pads aligned with the ends of the bonding lines 122 of the active surface 134a and aligned with the bonding pads on the additional dies 756_1, 756_2, and 756_3.

[0087] Figures 10A to 10B Another example of an encapsulated die stack 1080 comprising two die (e.g., memory die) stacks 1082 and 1084 is shown. In this arrangement, each stack is stepped only on one side. The stepped sides of the stacks having bonding lines 122 are arranged such that they are located on either side of the central portion of the encapsulated die stack 1080 forming a recess 752 therein. Figure 10A An encapsulated die stack 1080 with RDL 161 is shown, while Figure 10B A die stack 1080 without RDL 161 is shown in a top view (e.g., along the plane in which the components are joined) such that the ends of the bonding line 122 are visible in the active surfaces 134a and 134b on either side of the recess 752. Figure 10B Five additional dies 756_1 to 756_5 are shown located in recess 752. The number, location, and function of such additional dies are not limited to any of the examples described. Furthermore, the number and location of die stacks in an encapsulated die stack are not limited to the examples described.

[0088] Figure 11An example of a method is shown, comprising: forming a stack 1102 including a plurality of memory dies; forming an electrical connector 1104 (e.g., bonding wire 122) extending from the plurality of memory dies in the stack; forming a first molding compound 1106 (e.g., first molding compound 134) encapsulating the plurality of memory dies; and removing a portion of the first molding compound to expose an active surface of the first molding compound such that the ends of the electrical connectors are exposed at the active surface 1108 of the first molding compound (e.g., removing the first molding compound 134 to expose the active surface 134a and the ends of the bonding wire 122). The method further includes: forming a recess 1110 (e.g., recess 752) in the active surface of a first molding compound; positioning one or more additional dies in the recess, wherein the active surfaces of the one or more additional dies are coplanar 1112 with the active surface of the first molding compound (e.g., additional die 756); and filling the recess 1114 around the one or more additional dies with a second molding compound (e.g., filling recess 752 with second molding compound 760) when the one or more additional dies are in the recess.

[0089] Compared to other approaches, this technology offers several advantages. For example, by implementing the connection of additional dies (e.g., memory controller dies) without pillar bumps, aspects of this technology can reduce cost and complexity while improving reliability (e.g., pillar bumps can increase cost and failure rate). Height (the dimension along the z-direction) can be reduced (e.g., by using thinner dies). Area can be reduced (e.g., by placing passive devices in the IPD in a recess above the stack, rather than placing passive devices next to the stack).

[0090] According to an example, an apparatus includes a plurality of memory dies arranged in a stack, an electrical connector configured to transmit signals to and from the plurality of memory dies in the stack, and a first molding compound. The plurality of memory dies are encapsulated within the first molding compound such that an end of the electrical connector extends to an active surface of the first molding compound. The first molding compound has a recess in its active surface and a second molding compound within the recess. A memory controller die is located within the recess. The memory controller die is encapsulated within the second molding compound and has an active surface coplanar with the active surface of the first molding compound.

[0091] In one or more embodiments, the device includes a redistribution layer (RDL) extending across the active surface of the memory controller and the active surface of the first molding compound.

[0092] In one or more embodiments, the RDL has a first surface that extends along and contacts the active surface of the memory controller and the active surface of the first molding compound.

[0093] In one or more embodiments, the RDL includes an electrical trace that is electrically connected at an end of an electrical connector at an active surface of the first molding compound and to a pad on an active surface of a memory controller die.

[0094] In one or more embodiments, the RDL has a second surface parallel to the first surface, the second surface having a plurality of solder balls electrically connected to the trace.

[0095] In one or more embodiments, the device further includes one or more additional dies located in the recess, each of the one or more additional dies having bonding pads along an active surface coplanar with the active surface of the memory controller die.

[0096] In one or more embodiments, one or more additional dies include an integrated passive device (IPD) die containing multiple capacitors.

[0097] In one or more embodiments, one or more additional dies include volatile memory dies.

[0098] In one or more embodiments, the recess is a trench that extends across the active surface of the first molding compound from a first edge to a second edge, and the end of the electrical connector extends into the region on either side of the active surface of the first molding compound in the trench.

[0099] An example of one method includes: forming a stack comprising a plurality of memory dies; forming an electrical connector extending from the plurality of memory dies in the stack; forming a first molding compound encapsulating the plurality of memory dies; and removing a portion of the first molding compound to expose an active surface of the first molding compound such that an end of the electrical connector is exposed at the active surface of the first molding compound. The method further includes: forming a recess in the active surface of the first molding compound; positioning one or more additional dies in the recess, wherein the active surfaces of the one or more additional dies are coplanar with the active surfaces of the first molding compound; and filling the recess around the one or more additional dies with a second molding compound while the one or more additional dies are in the recess.

[0100] In one or more embodiments, forming a depression in the active surface of the first molding compound includes forming a groove extending across the first molding compound by grinding or ablating the first molding compound.

[0101] In one or more embodiments, positioning one or more additional dies includes positioning one or more of a memory controller die, a volatile memory die, and / or an integrated passive device (IPD) die.

[0102] In one or more embodiments, the method further includes attaching a redistribution layer (RDL) across the active surface of the first molding compound and the active surface of each of the one or more additional dies.

[0103] In one or more embodiments, attaching the RDL includes electrically connecting the electrical traces in the RDL to the end of an electrical connector at the active surface of a first molded compound, and electrically connecting them to pads on the active surface of one or more additional dies.

[0104] In one or more embodiments, connecting electrical traces in the RDL to the ends of electrical connectors and to pads forms an electrical connection between control circuitry from one or more additional dies and components of the memory die, the components of which include word lines and bit lines of a memory array formed in the memory die.

[0105] In one or more embodiments, the method further includes forming a plurality of solder balls on a second surface of the RDL, the second surface of the RDL being opposite to a first surface of the RDL, the first surface of the RDL being positioned and in contact with the active surface of a first molding compound and the active surface of each of one or more additional dies.

[0106] In one or more embodiments, positioning one or more additional dies in a recess, wherein the active surfaces of the one or more additional dies are coplanar with the active surfaces of the first molding compound, comprises: attaching the active surface of each of the one or more additional dies to a flat surface of a carrier, and placing the flat surface of the carrier and the active surface of the first molding compound together such that the one or more additional dies are located in the recess.

[0107] In one or more embodiments, filling a depression around one or more additional dies with a second molding compound includes causing the second molding compound to flow into the depression while the flat surface of the carrier maintains the active surface of each of the one or more additional dies coplanar with the active surface of the first molding compound.

[0108] An example of a storage system includes: a plurality of memory dies stacked along a first direction; an electrical connector electrically connected to the plurality of memory dies, the electrical connector extending along the first direction through a sealant extending around the plurality of memory dies and terminating at an active surface of the sealant; a memory controller die connected to the stack of memory dies via the electrical connector; and a component for aligning the active surface of the memory controller die with the active surface of the sealant in a coplanar arrangement, maintaining the coplanar arrangement, and electrically connecting pads on the active surface of the memory controller die to the end of the electrical connector at the active surface of the sealant.

[0109] In one or more embodiments, the active surface of the sealant includes a trench, and the memory controller die is located in the trench together with the integrated passive device (IPD) die and the volatile memory die.

[0110] For the purposes of this document, references to “implementation scheme,” “one implementation scheme,” “some implementation schemes,” or “another implementation scheme” in the specification may be used to describe different implementation schemes or the same implementation scheme.

[0111] For the purposes of this document, a connection can be a direct connection or an indirect connection (e.g., via one or more other parts). In some cases, when an element is referred to as being connected or coupled to another element, the element may be directly connected to that other element or indirectly connected to it via one or more intermediate elements. When an element is referred to as being directly connected to another element, there are no intermediate elements between the element and the other elements (other than adhesives or molten metal that may be used to connect, attach, mount, or couple the first and second elements). If two devices are directly or indirectly connected, the two devices are "in communication," allowing electronic signals to be transmitted between the two devices.

[0112] For the purposes of this document, the term "based on" may be understood as "at least partially based on".

[0113] For the purposes of this document, the use of numerical terms such as “first” object, “second” object, and “third” object without additional context may not imply an order of objects, but may be used for identification purposes to distinguish different objects.

[0114] The foregoing detailed description has been provided for purposes of illustration and description. It is not intended to be exhaustive or limiting to the exact forms disclosed. Many modifications and variations are possible in accordance with the foregoing teachings. The described embodiments were chosen to best explain the principles of the proposed technology and its practical application, thereby enabling others skilled in the art to fully utilize the technology in the various embodiments and with various modifications suitable for the specific intended use. The scope is intended to be defined by the claims appended herein.

Claims

1. An apparatus, the apparatus comprising: Multiple memory dies, the multiple memory dies being arranged in a stack; An electrical connector configured to transmit signals to and from the plurality of memory dies in the stack; A first molding compound encapsulates the plurality of memory dies such that the end of the electrical connector extends to the active surface of the first molding compound; The depression in the active surface of the first molded compound; A memory controller die, wherein the memory controller die is located in the recess; and A second molding compound encapsulates the memory controller die, the second molding compound having an active surface coplanar with the active surface of the first molding compound.

2. The apparatus according to claim 1, further comprising: A redistribution layer (RDL) extends across the active surface of the memory controller and the active surface of the first molding compound.

3. The apparatus according to claim 2, wherein, The RDL has a first surface that extends along and contacts the active surface of the memory controller and the active surface of the first molding compound.

4. The apparatus according to claim 3, wherein, The RDL includes electrical traces that are electrically connected at the active surface of the first molding compound to the end of the electrical connector and to pads on the active surface of the memory controller die.

5. The apparatus according to claim 4, wherein, The RDL has a second surface parallel to the first surface, and the second surface has a plurality of solder balls electrically connected to the electrical trace.

6. The apparatus according to claim 1, further comprising: One or more additional dies are located in the recess, each of the one or more additional dies having a bonding pad along an active surface coplanar with the active surface of the memory controller die.

7. The apparatus according to claim 6, wherein, The one or more additional dies include an integrated passive device (IPD) die containing multiple capacitors.

8. The apparatus according to claim 6, wherein, The one or more additional dies include volatile memory dies.

9. The apparatus according to claim 1, wherein, The recess is a groove extending across the active surface of the first molding compound from a first edge to a second edge, and the end of the electrical connector extends into the region of the active surface of the first molding compound on either side of the groove.

10. A method, the method comprising: Forming a stack consisting of multiple memory dies; Forming electrical connectors extending from the plurality of memory dies in the stack; Forming a first molding compound to encapsulate the plurality of memory dies; A portion of the first molding compound is removed to expose the active surface of the first molding compound, such that the end of the electrical connector is exposed at the active surface of the first molding compound; A depression is formed in the active surface of the first molding compound; One or more additional dies are positioned in the recess, wherein the active surfaces of the one or more additional dies are coplanar with the active surfaces of the first molding compound; as well as When the one or more additional dies are in the recess, the recess around the one or more additional dies is filled with a second molding compound.

11. The method according to claim 10, wherein, Forming the depression in the active surface of the first molding compound includes forming a groove extending across the first molding compound by grinding or ablating the first molding compound.

12. The method according to claim 10, wherein, Positioning the one or more additional dies includes positioning one or more of a memory controller die, a volatile memory die, and / or an integrated passive device (IPD) die.

13. The method according to claim 10, further comprising: A redistribution layer (RDL) is attached across the active surface of the first molding compound and the active surface of each of the one or more additional dies.

14. The method according to claim 13, wherein, Attaching the RDL includes: electrically connecting the electrical traces in the RDL to the end of the electrical connector at the active surface of the first molding compound, and electrically connecting them to pads on the active surface of the one or more additional dies.

15. The method according to claim 14, wherein, Connecting the electrical traces in the RDL to the end of the electrical connector and to the pads forms an electrical connection from the control circuitry in the one or more additional dies to components of the memory die, the components of the memory die including word lines and bit lines of the memory array formed in the memory die.

16. The method according to claim 13, further comprising: A plurality of solder balls are formed on a second surface of the RDL, the second surface being opposite to a first surface of the RDL, the first surface being positioned along the active surface of the first molding compound and the active surface of each of the one or more additional dies, and in contact with the active surface of the first molding compound and the active surface of each of the one or more additional dies.

17. The method according to claim 10, wherein, Positioning the one or more additional dies in the recess, wherein the active surfaces of the one or more additional dies are coplanar with the active surface of the first molding compound, comprises: attaching the active surface of each of the one or more additional dies to a flat surface of a carrier, and placing the flat surface of the carrier and the active surface of the first molding compound together such that the one or more additional dies are located in the recess.

18. The method according to claim 17, wherein, Filling the depressions around the one or more additional dies with the second molding compound includes causing the second molding compound to flow into the depressions while the flat surface of the carrier maintains the active surface of each of the one or more additional dies coplanar with the active surface of the first molding compound.

19. A storage system, the storage system comprising: Multiple memory dies, the multiple memory dies being stacked along a first direction; An electrical connector electrically connected to a plurality of memory dies, the electrical connector extending along a first direction through a sealant extending around the plurality of memory dies and terminating at an active surface of the sealant; A memory controller die, the memory controller die being connected to a stack of memory dies via the electrical connector; and A component for aligning the active surface of the memory controller die with the active surface of the sealant in a coplanar arrangement, maintaining the coplanar arrangement, and electrically connecting the pads on the active surface of the memory controller die to the end of an electrical connector at the active surface of the sealant.

20. The storage system according to claim 19, wherein, The active surface of the sealant includes a trench, and the memory controller die is located in the trench together with the integrated passive device (IPD) die and the volatile memory die.

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