Deep trench capacitor and method of making the same

Abstract

The application discloses a deep trench capacitor and a preparation method thereof, and relates to the technical field of semiconductor device manufacturing. The method comprises the following steps: sequentially depositing a bottom ceramic plating layer and a silicon dioxide plating layer on an etching substrate sheet; performing photoetching and wet etching to form a patterned single-layer catalytic layer array; performing vapor-phase metal-assisted chemical etching; etching while forming a downward magnetic field in a reaction chamber to form a through silicon via; and sequentially preparing a bottom electrode, a dielectric layer and a top electrode in the through silicon via by using atomic layer deposition, wherein the bottom ceramic plating layer is used as a catalytic layer for vapor-phase metal-assisted chemical etching. The application guides the direction of metal-assisted chemical etching by using the downward magnetic field, thereby ensuring the perpendicularity of the through silicon via; the bottom ceramic plating layer is used as an etching catalyst, thereby avoiding the introduction of noble metal impurities and improving the process compatibility; and the atomic layer deposition technology is combined to form uniform electrodes and dielectric layers in a high aspect ratio structure, thereby obtaining a deep trench capacitor with high capacitance density and low leakage current.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device manufacturing technology, specifically to a deep trench capacitor and its preparation method, which is suitable for the manufacturing of capacitors with high aspect ratio silicon through-hole structures and can be widely used in fields such as three-dimensional integration, power integrity improvement, and RF device packaging. Background Technology

[0002] In the field of integrated circuit manufacturing, with the continuous improvement of chip integration and the shrinking of feature size, power integrity and signal integrity have become key bottlenecks restricting system performance. To effectively suppress power supply noise and signal crosstalk, and maintain stable voltage levels and waveform quality, decoupling capacitors play an indispensable role in circuits. Traditional discrete capacitors, due to their large package parasitic parameters and low integration density, are difficult to meet the needs of modern high-performance chips. Therefore, directly integrating capacitors into silicon chips has become an important development direction. Deep trench capacitors, as one of the most promising silicon integrated capacitor technologies, achieve extremely high capacitance density by etching high aspect ratio deep trench structures in a silicon substrate and constructing metal-insulator-metal stacks within the trenches. This allows for a large effective electrode area within a limited planar area, resulting in extremely high capacitance density. Therefore, they are widely used in 3D integration, power distribution network optimization, and RF device packaging.

[0003] Currently, the fabrication of deep trench capacitors typically relies on deep silicon etching processes to form trenches or holes with high aspect ratios, followed by the sequential formation of the bottom electrode, dielectric layer, and top electrode within the trench using methods such as atomic layer deposition. However, with the ever-increasing demands for capacitance density, the required aspect ratio is also growing, posing a series of significant challenges to traditional etching processes: Although wet etching is less expensive, its isotropic nature makes it difficult to control the etching direction. In high aspect ratio structures, it is prone to lateral drilling, which leads to uncontrolled hole morphology. While dry etching, such as the Bosch process, can achieve a high aspect ratio, the equipment is expensive, the process is complex, and high-energy ion bombardment can easily cause etching damage to the substrate, affecting the reliability and yield of the device.

[0004] In recent years, metal-assisted chemical etching (MEC) technology has attracted attention due to its ability to achieve high aspect ratio etching without damage. However, in existing methods, metal catalyst particles are usually introduced through solution deposition or physical evaporation, making it difficult to precisely control their position and distribution. This leads to problems such as poor verticality of etched holes and hole displacement, which seriously affect the uniformity of subsequent electrode deposition and the stability of capacitance performance. In addition, in existing processes, the catalyst layer is often only used as an intermediate layer in the etching process and needs to be completely removed after etching. Its single function fails to form an effective process integration with subsequent electrode fabrication, resulting in waste of materials and process steps.

[0005] This invention addresses the shortcomings of the prior art by providing a deep trench capacitor and its preparation method that enables vertical etching guidance, uses the underlying ceramic coating as an etching catalyst, and avoids the introduction of impurities. This solves the problems of difficult-to-control etching direction, single function of catalyst layer, and low process integration in existing processes. Summary of the Invention

[0006] The technical problem to be solved by this invention is: to address the issues of difficulty in controlling the etching direction, single function of the catalyst layer, and low process integration in the existing deep trench capacitor manufacturing process, and to provide a deep trench capacitor and its manufacturing method that can achieve vertical etching guidance and use the bottom ceramic coating as an etching catalyst.

[0007] To address the aforementioned problems, this invention provides a method for fabricating a deep trench capacitor, comprising the following steps: S1. Sequentially deposit a bottom ceramic coating and a silicon dioxide coating on an etched substrate; S2. A positive photoresist layer is coated on the side of the silicon dioxide coating away from the underlying ceramic coating. A through-silicon via (TSV) hole outline is formed in the positive photoresist layer. The silicon dioxide coating outside the TSV hole outline is removed by wet etching, and the positive photoresist layer is stripped off. S3. Remove the underlying ceramic coating outside the outline of the through-silicon via, and then use wet etching to remove the remaining silicon dioxide coating to form a patterned monolayer catalyst array on the etched substrate. S4. The etched substrate after step S3 is placed in a reaction chamber containing etching solution. The reaction chamber is heated to generate etchant vapor. The etchant vapor is used to perform vapor-phase metal-assisted chemical etching. At the same time as etching, a downward magnetic field is formed in the reaction chamber. Through-silicon vias are formed vertically in the etched substrate. S5: The bottom electrode, dielectric layer and top electrode are deposited sequentially in the through silicon via.

[0008] As an optional implementation, the etched substrate is made of silicon. The material of the bottom ceramic coating is titanium nitride, and the thickness of the bottom ceramic coating is 3-15nm; the thickness of the silicon dioxide coating is 10-50nm.

[0009] As an optional implementation, in step S3, the etched substrate is placed in a mixed solution containing ammonia and hydrogen peroxide to remove the underlying ceramic coating outside the contour of the through-silicon via.

[0010] As an optional implementation, in step S4, the etching solution is prepared by mixing hydrogen peroxide, hydrofluoric acid and deionized water, and the ratio of hydrogen peroxide, hydrofluoric acid and deionized water is 1:3-6:2-7. In step S4, the heating and etching temperature in the reaction chamber is controlled at 50-90℃.

[0011] As an optional implementation, in step S4, the average magnetic field gradient of the downward magnetic field is 9.5 T / m, and the magnetic flux density gradually increases from 0 to 190 mT.

[0012] As an optional implementation, in step S5, the bottom electrode, the dielectric layer, and the top electrode are prepared using an atomic layer deposition method.

[0013] As an optional implementation, the specific steps for fabricating the bottom electrode and the top electrode include: Heated to 380°C in a vacuum chamber filled with nitrogen at a pressure of 100 Pa; A pulse is introduced to induce a chemical adsorption reaction in titanium tetrachloride, which is then purged with nitrogen gas. Ammonia gas is pulsed in to induce a chemical reaction that produces titanium nitride. Nitrogen gas is then introduced to purge and remove the reaction byproducts.

[0014] As an optional implementation, the specific steps for preparing the dielectric layer include: Heating to 200-250℃ in a vacuum chamber filled with nitrogen at a pressure of 100 Pa; A pulsed infusion of trimethylaluminum causes a chemisorption reaction, which is then purged with nitrogen gas. A pulse is introduced into deionized water to produce a chemical reaction that generates aluminum oxide. Nitrogen gas is then introduced to purge and remove the reaction byproducts. Repeat the above pulse and purging cycle until the target thickness is reached.

[0015] As an optional implementation, the bottom electrode is a titanium nitride layer with a thickness of 10-30 nm; The dielectric layer is an aluminum oxide layer with a thickness of 10-30 nm; The top electrode is a titanium nitride layer with a thickness of 1-100 nm.

[0016] On the other hand, the present invention also provides a deep trench capacitor, which is prepared by the aforementioned deep trench capacitor preparation method. The deep trench capacitor includes an etched substrate, in which a through-silicon via is provided. The inner wall of the through-silicon via is provided with a bottom electrode, a dielectric layer and a top electrode in sequence from the outside to the inside. The bottom ceramic coating is located at the bottom of the through-silicon via and is in contact with the bottom electrode.

[0017] Firstly, in terms of etching precision, this invention applies a downward magnetic field during the vapor-phase metal-assisted chemical etching process, using the magnetic field force to guide the action direction of the catalyst particles, ensuring that the etching reaction proceeds strictly in the vertical direction, effectively avoiding lateral drilling. This significantly improves the verticality, aspect ratio, and morphological consistency of the silicon via, laying a reliable geometric foundation for the subsequent fabrication of high-density capacitor structures.

[0018] Secondly, in terms of process integration, this invention uses a bottom ceramic coating as a catalyst layer for metal-assisted etching. After etching, there is no need to introduce additional precious metal catalyst materials, nor is there a need for special design around the seed crystal layer, thereby reducing the risk of impurity contamination and simplifying process connection.

[0019] Furthermore, in terms of pattern precision control, a patterned monolayer catalyst array is formed on the underlying ceramic coating by combining photolithography with wet etching, which enables precise control of the position and size of catalyst particles, ensuring the uniformity of the etched hole array distribution and the accuracy of its position. This is beneficial for maintaining the consistency of electrical performance between devices while increasing capacitance density.

[0020] In addition, regarding film quality, atomic layer deposition technology is used to sequentially form the bottom electrode, dielectric layer and top electrode in silicon vias with high aspect ratio. With its excellent step coverage and thickness controllability, continuous, uniform and void-free thin film stacks can be obtained inside the deep holes, ensuring the leakage current characteristics, breakdown voltage and long-term reliability of the capacitor.

[0021] Finally, in terms of material system selection, titanium nitride is used as the electrode material and alumina as the dielectric material. The resulting metal-insulator-metal structure has good thermal stability and chemical inertness, and can withstand the high temperature treatment in subsequent processes. At the same time, it has low leakage current, high dielectric constant and excellent frequency characteristics, which fully meet the stringent requirements of high-performance integrated devices for decoupling capacitors.

[0022] In summary, this invention achieves the controllable fabrication of high aspect ratio vertical through-silicon vias and the in-situ integration of high-quality metal-insulator-metal capacitors through the synergistic effects of magnetic field-guided etching, catalyst compatibility retention, and atomic layer deposition technology. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are merely some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0024] Figure 1This is a schematic diagram of the etched substrate for forming the outline of the silicon via holes after sputtering a bottom ceramic coating, a silicon dioxide coating, and coating with positive photoresist, as provided in an embodiment of the present invention. Figure 2 This is a schematic diagram of the structure of the catalyst structure cluster containing the underlying ceramic coating after removing the positive photoresist and part of the silicon dioxide coating, as provided in an embodiment of the present invention. Figure 3 A schematic diagram of the single-layer catalyst structure cluster after removing part of the bottom ceramic coating and the residual silica coating, provided in an embodiment of the present invention; Figure 4 This is a cross-sectional view of the etched substrate after vapor phase metal-assisted chemical etching, as provided in an embodiment of the present invention. Figure 5 A cross-sectional view of a through-silicon via (TSV) after forming a bottom electrode, a dielectric layer, and a top electrode, as provided in an embodiment of the present invention. Figure 6 The scanning electron microscope cross-sectional morphology of the deep trench array obtained by metal-assisted chemical etching process provided in the embodiments of the present invention. Figure 1 ; Figure 7 The scanning electron microscope cross-sectional morphology of a deep trench array with depth measurement markers obtained by metal-assisted chemical etching process provided in this embodiment of the invention. Figure 2 ; In the figure: 1. Etched substrate; 2. Bottom ceramic coating; 3. Silicon dioxide coating; 4. Positive photoresist layer; 5. Through-silicon via (TSV) hole outline; 6. TSV; 7. Bottom electrode; 8. Dielectric layer; 9. Top electrode. Detailed Implementation

[0025] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0026] Example 1: This embodiment provides a method for fabricating a deep trench capacitor. This method guides the direction of metal-assisted chemical etching with a downward magnetic field, ensuring the perpendicularity of the through-silicon vias (TSVs). An underlying ceramic coating is used as an etching catalyst to ensure effective etching while avoiding the introduction of precious metal impurities. The method specifically includes the following detailed steps: Step S1: Sequentially deposit the bottom ceramic coating 2 and the silicon dioxide coating 3 on the etched substrate 1. Before thin film deposition, the etched substrate 1 needs to undergo rigorous surface cleaning, which is a crucial step in semiconductor manufacturing. Specifically, a high-quality wafer can be taken and cut into etched substrate 1 of appropriate size using a laser dicing machine. The obtained wafer is then ultrasonically cleaned with methanol, acetone, and isopropanol to remove organic contaminants and particulate impurities from the surface. After drying with a nitrogen gun, the naturally grown oxide layer on the substrate surface is removed with a standard concentration of hydrofluoric acid solution. Finally, it is dried again with a high-purity nitrogen gun to ensure that the substrate surface exhibits a hydrogen-terminated hydrophobic state, thereby providing an extremely clean interface environment for subsequent high-quality thin film deposition. Optionally, the material of the etched substrate 1 can be any one of silicon, germanium, silicon carbide, gallium arsenide, and gallium nitride. These semiconductor materials each have their own characteristics in terms of bandgap width, carrier mobility, and breakdown field strength. Among them, single-crystal silicon is the most mature semiconductor material, with low cost and extremely high lattice integrity; wide bandgap semiconductors such as silicon carbide and gallium nitride are suitable for high-power device applications under high temperature and high pressure. The method in this embodiment shows good universality for all the above-mentioned semiconductor substrates.

[0027] On the cleaned etched substrate 1, a bottom ceramic coating 2 is sequentially evaporated or sputtered under high vacuum using electron beam evaporation or radio frequency sputtering. Optionally, the bottom ceramic coating 2 is made of titanium nitride, and its thickness is 3-15 nm. In this embodiment, titanium nitride is used as a complementary metal-oxide-semiconductor compatible catalyst for metal-assisted chemical etching (MAC) to prepare deep trench capacitors. Compared with traditional MAC processes using precious metals such as gold and silver as catalysts, this method avoids the deep-level damage introduced by precious metals from a physical mechanism perspective. Precious metal catalysts tend to form deep-level impurity centers in semiconductor substrates such as silicon, leading to fatal defects such as increased carrier recombination and significantly increased leakage current. Titanium nitride, on the other hand, is not only chemically stable but also does not introduce deep-level impurities into the silicon substrate, effectively ensuring the lattice perfection and electrical integrity of the semiconductor substrate. This results in a significant increase in the carrier lifetime of the final deep trench capacitor and an order-of-magnitude reduction in leakage current density.

[0028] Subsequently, a silicon dioxide coating 3 is prepared using plasma-enhanced chemical vapor deposition (PECVD). The reaction gases are typically high-purity oxygen and silane diluted in nitrogen, with nitrogen as the carrier gas. The reaction chamber pressure is controlled within a suitable vacuum range. The substrate is heated to the conventional temperature for low-temperature PECVD to avoid thermal damage or thermal stress mismatch to the deposited titanium nitride layer. Under the action of a radio frequency power supply, the reaction gases are ionized to generate plasma, causing active particles to chemically react with the substrate surface to form a dense silicon dioxide film. Optionally, the thickness of the silicon dioxide coating 3 is controlled between 10-50 nm.

[0029] Step S2: A positive photoresist layer 4 is uniformly coated on the side of the silicon dioxide coating 3 away from the underlying ceramic coating 2. A through-silicon via (TSV) hole outline 5 is formed in the positive photoresist layer 4. The silicon dioxide coating 3 outside the TSV hole outline 5 is removed using wet etching, and the positive photoresist layer 4 is then peeled off. The specific operation is as follows: Positive photoresist is spin-coated onto the dehydrated and baked wafer surface, followed by isothermal pre-baking to remove residual solvent moisture from the photoresist and improve adhesion between the positive photoresist and the wafer surface. Using a high-resolution lithography machine, alignment marks such as crosshairs are precisely aligned, and the high-density hole pattern designed on the photomask is transferred to the positive photoresist layer 4 for exposure. After exposure, post-exposure baking is performed to cure the photosensitive material. Subsequently, the exposed wafer is developed in a dedicated positive photoresist developer. The developer fully dissolves the positive photoresist that has undergone photochemical reactions, thereby clearly developing the silicon via hole outline 5 required for deep trench capacitors on the positive photoresist layer 4. After development, the wafer is vigorously rinsed with deionized water and then spin-dried. Figure 1 As can be seen, at this point, a stacked structure consisting of a bottom ceramic coating 2, a silicon dioxide coating 3, and a positive photoresist layer 4 with silicon via hole outlines 5 has been sequentially formed above the etched substrate 1. Subsequently, using the patterned positive photoresist layer 4 as a mask barrier layer, a wet etching process, such as a buffered oxide etchant, is used to thoroughly and isotropically remove the silicon dioxide coating 3 exposed outside the silicon via hole outlines 5. Etching automatically stops after reaching the bottom titanium nitride film because the etchant has extremely high etch selectivity for titanium nitride. After etching, a dedicated photoresist stripper or oxygen plasma stripping process is used to completely remove the remaining positive photoresist layer 4 from the surface. Figure 2 It can be seen that at this time, a double-layer structure is left on the wafer surface, consisting of a patterned silicon dioxide coating 3 and a completely covered underlying ceramic coating 2, forming a preliminary catalyst structure cluster.

[0030] Step S3: Remove the underlying ceramic coating 2 outside the via hole contour 5, and then use wet etching to remove the remaining silicon dioxide coating 3 to form a patterned monolayer catalyst array on the etched substrate 1. Optionally, immerse the etched substrate 1 in a mixed solution containing ammonia and hydrogen peroxide to chemically remove the underlying ceramic coating 2 outside the via hole contour 5. This mixed solution can oxidize and dissolve the exposed titanium nitride layer under mild conditions, while the titanium nitride area protected by the residual silicon dioxide film above remains intact. Afterwards, use a wet process such as a buffered oxide etchant to completely remove the remaining silicon dioxide coating 3, which serves as a hard mask. Figure 3 As can be seen, after the above pattern transfer steps, only the bottom ceramic coating 2 with a specific two-dimensional array pattern is retained on the surface of the etched substrate 1, thus successfully constructing a single-layer catalyst structure cluster composed of titanium nitride disc arrays. This pattern transfer method greatly ensures the consistency of catalyst size and the sharpness of edges, laying a solid physical foundation for subsequent high-verticality etching.

[0031] In step S4, the etched substrate 1, after completing step S3, is placed into a specially designed reaction chamber containing etching solution. The reaction chamber is heated to generate etchant vapor, which is used for vapor-phase metal-assisted chemical etching. Simultaneously, a downward magnetic field is formed within the reaction chamber, vertically etching through-silicon vias 6 with extremely high aspect ratios into the substrate 1. Optionally, the etching solution is prepared by mixing hydrogen peroxide, hydrofluoric acid, and deionized water, with a ratio of hydrogen peroxide, hydrofluoric acid, and deionized water of 1:3-6:2-7; the heating and etching temperature within the reaction chamber is controlled at 50-90°C. In this process, this embodiment employs vapor-phase metal-assisted chemical etching, overcoming the bottleneck of the irreconcilable contradiction between depth and rate in traditional deep-trench silicon etching scenarios. In traditional liquid-phase metal-assisted chemical etching (LC-CA) processes, the mass transfer efficiency of the liquid etchant decreases sharply within narrow holes as the etching depth increases, making it difficult to remove reaction byproducts. This easily leads to problems such as severe etching rate attenuation, limited aspect ratio, and bottom passivation. In this embodiment, a mixed vapor containing hydrogen fluoride and hydrogen peroxide, generated by heating, allows gaseous reaction molecules to reach every microscopic region of the deep trench bottom and deep hole sidewalls extremely uniformly and rapidly due to its large mean free path and extremely fast diffusion kinetics. Catalyzed by titanium nitride catalyst particles at the bottom, hydrogen peroxide gains electrons and is reduced, simultaneously injecting holes into the silicon substrate. This causes the silicon atoms immediately below the titanium nitride to be oxidized and rapidly complexed and carried away by the hydrogen fluoride vapor. This ensures that the intense etching reaction remains synchronous and efficient throughout the entire micro / nano structure, eliminating the necking effect and achieving vertically uniform etching of deep cavities and holes while maintaining a constant etching rate.

[0032] More importantly, optionally, a downward magnetic field is formed within the cavity during etching. This magnetic field has an average magnetic field gradient of 9.5 T / m, with the magnetic flux density gradually increasing from 0 to 190 mT. Introducing a macroscopic downward gradient magnetic field into the purely chemical reaction system of vapor phase etching resolves the core contradiction between uniformity and directionality. In traditional magnetic field-free processes, ion movement inevitably involves chaotic thermal motion, and the catalyst distribution is prone to lateral shift or rotation as the etching depth increases, leading to fatal morphological defects such as tilted sidewalls, localized cross-linking of pores, or even over-etching. In this embodiment, by setting a downward magnetic field with an average magnetic field gradient of 9.5 T / m and a magnetic flux density gradually increasing from 0 to 190 mT, the downward magnetic field improves the spatial distribution and mass transfer state of active species and the catalyst layer near the etching interface, thereby suppressing lateral shift and improving the consistency between the via extension direction and the substrate surface normal direction. The downward magnetic field can be achieved in several ways. For example, a Helmholtz coil can be placed outside or inside the reaction chamber to generate a uniform magnetic field region after a direct current is applied. Alternatively, a permanent magnet circuit structure can be used, in which a magnetic circuit system consisting of multiple permanent magnet units, pole plates, and soft iron circuits is set up inside the reaction chamber to form a large-area, uniform, and adjustable magnetic field in the etching area. The magnetic field parameters required in this embodiment can be precisely controlled by adjusting the current flowing through the coil or by optimizing the arrangement and spacing of the permanent magnets.

[0033] The magnetic field exerts a downward directional constraint on the titanium nitride catalyst layer on the silicon wafer substrate inside the reaction chamber, ensuring the catalyst moves vertically, thereby achieving vertical etching of the silicon via 6. This external magnetic field confinement effect suppresses the lateral diffusion behavior of ions and the probability of random collisions, ensuring the absolute flatness of the etching reaction interface and the perpendicularity of the downward cutting direction. It effectively avoids morphological defects such as sidewall roughness and tilting. Figure 4 It can be seen that, under the catalytic effect of the titanium nitride monolayer catalyst structure cluster and the guidance of the magnetic field, the etched substrate 1 is hollowed out vertically downwards, forming silicon vias 6 with smooth sidewalls, flat bottoms, and a consistent array distribution. Figure 6 and Figure 7 The scanning electron microscope images clearly show that the depth of the fabricated deep trench array reaches 200 μm or even deeper, and its verticality and sidewall quality are at a very high level.

[0034] Step S5: The bottom electrode 7, dielectric layer 8, and top electrode 9 are deposited sequentially within the through-silicon via 6. Optionally, this embodiment uses atomic layer deposition (ALD) to prepare the bottom electrode 7, dielectric layer 8, and top electrode 9. The advantage of this embodiment in terms of process integration is that the underlying ceramic coating 2 is used as a catalyst during the preceding etching process and remains at the bottom of the through-silicon via after etching; this layer does not serve as a seed layer for the bottom electrode but is used to avoid the introduction of noble metal impurities and maintain the compatibility of the material system. This not only eliminates the cumbersome catalyst stripping and cleaning steps and prevents the risk of high aspect ratio hole collapse caused by the surface tension of the cleaning solution, but also ensures that the subsequent bottom electrode film can be continuously deposited on the inner wall and bottom of the through-silicon via. Optionally, the bottom electrode 7 is a titanium nitride layer with a thickness of 10-30 nm; the dielectric layer 8 is an alumina layer with a thickness of 10-30 nm; and the top electrode 9 is a titanium nitride layer with a thickness of 1-100 nm. Specifically, the specific steps for preparing the bottom electrode 7 and top electrode 9 by atomic layer deposition include: The substrate with through-silicon vias 6 was placed into the atomic layer deposition reaction chamber and evacuated to a high vacuum. The chamber was heated under a continuous supply of high-purity protective nitrogen gas, and the chamber pressure was maintained at around 100 Pa. The chamber temperature was allowed to rise steadily to 380°C, and a computer-programmed experimental reaction was set to conduct a periodic experiment.

[0035] First, the control valve is opened to introduce the gaseous precursor titanium tetrachloride into the reaction chamber with an ultra-short pulse time of 0.2s. These precursor molecules will quickly diffuse into the high aspect ratio pores through Knudsen diffusion and undergo a self-limiting chemisorption reaction on the exposed inner wall and bottom surface until all active sites on the surface are completely occupied and the reaction automatically stops.

[0036] Subsequently, high-flow-rate high-purity nitrogen gas is introduced for a long-term deep purging process to completely remove excess titanium tetrachloride precursors and reaction byproducts such as hydrogen chloride that have not been adsorbed from the reaction chamber.

[0037] Next, ammonia, the second precursor, is introduced into the reaction chamber with a 0.2s pulse. The ammonia molecules undergo ligand exchange and chemical reaction with the titanium-containing precursor material previously adsorbed on the surface, generating a dense and pure titanium nitride lattice layer layer by layer. Nitrogen is then introduced again for deep purging to remove excess ammonia precursor and gaseous reaction byproducts such as ammonium chloride.

[0038] Through such repeated precursor pulse alternation and gas purging cycles, relying on the self-limiting characteristic of growing only a fixed single-atom layer thickness in each cycle, titanium nitride bottom electrode 7 and top electrode 9 with good chemical stability, high mechanical strength and low resistivity are finally formed on the inner wall of the hole.

[0039] Similarly, the specific steps for preparing dielectric layer 8 include: Heating to 200-250°C within a vacuum chamber purged with nitrogen at a pressure of 100 Pa creates an ideal window for achieving optimal thin film quality and insulation properties in alumina atomic layer deposition.

[0040] First, trimethylaluminum is pulsed in as a metal source precursor to undergo a chemical adsorption reaction, and nitrogen gas is introduced for thorough purging. Next, deionized water is pulsed in as an oxygen source to induce a chemical reaction. Water molecules hydrolyze and replace the methyl ligand of trimethylaluminum, generating an extremely dense alumina network and releasing methane gas as a byproduct. Nitrogen gas is then introduced again to purge and remove the reaction byproducts.

[0041] The high-precision pulse and purge cycle was repeated until the target thickness was reached, and finally an alumina dielectric layer 8 with excellent density, low leakage current, high breakdown field strength and strong bonding force with the interface of the upper and lower titanium nitride electrodes was formed.

[0042] Combination Figure 5 As can be seen, through the above-mentioned precise atomic layer deposition process, the bottom electrode 7, the dielectric layer 8, and the top electrode 9 are sequentially stacked from bottom to top and from outside to inside inside the deep silicon via 6, thus constructing a three-dimensional deep trench capacitor structure with a high effective electrode relative area.

[0043] As an optional implementation, in step S1, a titanium nitride bottom ceramic coating 2 with a precise thickness of 3 nm is deposited on the etched substrate 1 by precisely controlling the power and time of radio frequency sputtering; subsequently, a silicon dioxide coating 3 with a precise thickness of 10 nm is deposited by chemical vapor deposition. This combination of ultrathin mask and catalyst reduces the time cost and material consumption of the front-end process. In step S4, the heating etching temperature in the reaction chamber is controlled at a relatively low level of 50°C, and the etching solution is prepared with a precise ratio of hydrogen peroxide, hydrofluoric acid, and deionized water of 1:3:2. The lower temperature combined with a relatively high concentration of etchant allows the etching reaction to proceed under a mild but kinetically driven state, which is beneficial for obtaining extremely smooth microscopic sidewalls. Finally, in step S5, by setting the number of atomic layer deposition cycles, a titanium nitride bottom electrode 7 with a thickness of 10 nm is precisely grown, followed by the growth of an alumina dielectric layer 8 with a thickness of 10 nm, and finally the deposition of an ultrathin titanium nitride top electrode 9 with a thickness of 1 nm. This ultra-thin sandwich stack structure can maximize the retention of internal space within extremely small physical apertures, which not only significantly improves the thin film filling yield in extremely narrow holes, but also achieves extremely high absolute capacitance values ​​per hole. It is very suitable for decoupling applications of advanced process chips with extreme requirements for capacitance density and relatively low operating voltage.

[0044] As an optional implementation, in step S1, a 9 nm thick titanium nitride ceramic underlayer 2 is deposited; subsequently, a 30 nm thick silicon dioxide layer 3 is deposited. This combination of moderate thicknesses achieves a perfect balance between process tolerance and mask strength. In step S4, the heating etching temperature in the reaction chamber is controlled at the optimal temperature of 70°C, while the etching solution is prepared with a ratio of hydrogen peroxide, hydrofluoric acid, and deionized water of 1:4.5:4.5. This compromise reaction condition not only ensures an excellent etching rate of up to 1.7 μm / min, but also, with the assistance of a downward magnetic field with an average magnetic field gradient of 9.5 T / m and a magnetic flux density gradually increasing from 0 to 190 mT, the aspect ratio of the pore morphology exceeds 40:1. In step S5, a 20 nm thick titanium nitride bottom electrode 7, a 20 nm thick alumina dielectric layer 8, and a 50 nm thick titanium nitride top electrode 9 are grown sequentially. The 20 nm thick alumina dielectric layer achieves a high balance between leakage current control and dielectric constant improvement, enabling the entire capacitor structure to possess both high charge storage capacity and long-term reliable insulation life, making it one of the most ideal choices for the core storage unit of current three-dimensional dynamic random access memory.

[0045] As an optional implementation, in step S1, a 15 nm thick titanium nitride ceramic underlayer 2 is deposited; subsequently, a 50 nm thick silicon dioxide coating 3 is deposited. This thick mask strategy can withstand extremely long etching times and is suitable for fabricating extremely deep vias. In step S4, the etching temperature is increased to a relatively high temperature of 90°C, and the ratio of hydrogen peroxide, hydrofluoric acid, and deionized water in the etching solution is configured as 1:6:7. The high-temperature, high-dilution vapor system endows the reactants with extremely high activation energy and excellent gas-phase fluidity, maintaining undiminished etching chemical reactions even at the bottom of holes hundreds of micrometers deep. In step S5, a 30 nm thick titanium nitride bottom electrode 7, a 30 nm thick alumina dielectric layer 8, and a 100 nm thick ultra-thick titanium nitride top electrode 9 are grown sequentially. This robust design with thick electrodes and a thick dielectric layer, while slightly sacrificing the space utilization of a single aperture, significantly improves its withstand voltage performance and completely blocks leakage current. It is extremely suitable for power distribution network optimization in high-voltage, high-current impact environments, as well as for high-reliability packaging decoupling of power semiconductor devices or radio frequency devices.

[0046] To further illustrate the etching effect of the method described in this embodiment, it is necessary to briefly explain the basic principles and specific processes of traditional wet etching and traditional dry etching.

[0047] Traditional wet etching is a process that uses a chemical solution to react with the material for material removal. Its characteristic is isotropy, meaning the etching rate is essentially the same in all directions. For example, the wet etching used in this control experiment is a standard HNA mixed solution isotropic wet etching process in the field. Specifically, after the silicon substrate is cleaned with RCA, a pattern is defined using photoresist as a mask. It is then immersed in a hydrofluoric acid-nitric acid-acetic acid etching solution at room temperature for non-directional liquid-phase etching. After etching, it is terminated by rinsing with water and drying. This process is isotropic etching, with significant lateral drilling. For the fabrication of high aspect ratio structures, wet etching makes it difficult to control the etching direction, easily leading to deviations in hole morphology from the design. The aspect ratio is typically no higher than 20:1, the sidewall roughness is greater than 25 nm, and the room temperature etching rate is approximately 0.5 μm / min.

[0048] Traditional dry etching, such as the Bosch process, uses a combination of ion bombardment in plasma and chemical reaction to achieve high aspect ratios. The dry etching used in this control experiment is a conventional reactive ion etching process without sidewall passivation. Specifically, the patterned substrate is placed in the etching chamber, a vacuum is drawn, and SF6 / CF4 fluorine-based etching gas is introduced to excite plasma for a single etching reaction, without sidewall protection or cyclic passivation steps. This process exhibits weak anisotropy, lateral etching, and an aspect ratio generally not exceeding 30:1. High-energy ion bombardment can easily cause some physical damage to the substrate, resulting in a sidewall roughness greater than 15 nm and an etching rate of approximately 1.2 μm / min.

[0049] The vapor-phase metal-assisted chemical etching combined with magnetic field confinement technology used in this embodiment differs from the two traditional processes mentioned above in its etching mechanism. Table 1 below records the comparison data of key technical indicators between the metal-assisted chemical etching process of this embodiment and the traditional wet etching and dry etching processes.

[0050] Table 1: Comparison of Key Technical Indicators for Different Etching Processes Table 1 shows that the metal-assisted chemical etching method of this embodiment achieves a depth-to-width ratio of 40:1, a sidewall roughness of less than 1 nm, and an etching rate of 1.7 μm / min. In contrast, the conventional wet etching process in the control group has a depth-to-width ratio of only 20:1, a sidewall roughness greater than 25 nm, and an etching rate as slow as 0.5 μm / min. Although the conventional dry etching process in another control group has a depth-to-width ratio of 30:1, the sidewall roughness caused by high-energy physical bombardment is still greater than 15 nm, and the etching rate is only 1.2 μm / min, which is inferior to this embodiment. From the experimental results in Table 1 and the detailed analysis above, it can be concluded that the vapor-phase metal-assisted chemical etching combined with magnetic field confinement technology of this embodiment surpasses the two traditional etching methods by a significant margin in the three core dimensions of depth-to-width ratio, sidewall smoothness limit, and vertical etching rate. In particular, the increased aspect ratio and the achievement of atomic-level smoothness of the sidewalls enable a significant increase in the effective electrode area per unit volume under the stringent constraints of maintaining the same physical dimensions of the trench width, occupying the same wafer area, and having identical dielectric materials and thicknesses. This results in an overall increase in chip capacitance density of more than 1.33 times. This is of positive significance for breaking through the physical storage performance bottleneck of deep trench capacitors in integrated circuits under Moore's Law.

[0051] In summary, the deep trench capacitor fabrication method provided in this embodiment demonstrates excellent industrial application value in terms of usage and technical effects. By using the underlying ceramic coating 2 as an etching catalyst and retaining it as a compatible residual layer, the introduction of precious metal impurities is avoided, greatly simplifying the originally lengthy and expensive manufacturing process. By introducing a downward magnetic field in the vapor-phase chemical etching process, the challenges of lateral drilling and etching attenuation in deep hole fabrication are overcome. Finally, combined with atomic layer deposition technology, a deep trench capacitor with regular morphology, clear interface, and excellent performance is created.

[0052] Example 2: This embodiment provides a deep trench capacitor, which is manufactured using the metal-assisted chemical etching method described in Embodiment 1. This deep trench capacitor directly inherits and solidifies many advanced process features of the method described in Embodiment 1 in terms of its three-dimensional spatial layout, material layer connectivity, and overall morphological distribution.

[0053] Combination Figure 5The cross-sectional view of the system product shown illustrates that the deep trench capacitor provided in this embodiment primarily comprises a robust etched substrate 1 with excellent conductivity and support properties. At a macroscopic level, the interior of the etched substrate 1 is precisely etched with a high-density array of holes; at a microscopic level, the etched substrate 1 contains one or more extremely regular through-silicon vias (TSVs) 6. These TSVs 6 are characterized by an ultra-high aspect ratio of over 40:1, sidewall roughness controlled within 1 nm, and exhibit a near-ideal vertical columnar cavity morphology, thanks to the magnetic field orientation confinement mechanism during the etching process.

[0054] Within the internal space of each through-silicon via (TSV) 6, various functional material films are concentrically and conformally stacked, extending from the bottom of the via towards its opening and contracting from the outermost peripheral wall towards the central axis of the via. Specifically, tightly adhered to the flat bottom of the TSV 6 is the residual, unremoved bottom ceramic coating 2. This bottom ceramic coating 2 does not serve as a seed layer for the bottom electrode; its main function is to provide catalysis during the preceding vapor-phase metal-assisted chemical etching process and to prevent the introduction of noble metal impurities by retaining the TiN system. A bottom electrode 7 is comprehensively, continuously, and seamlessly wrapped around the upper surface of the bottom ceramic coating 2 and the smooth inner wall of the TSV 6. The bottom electrode 7 and the bottom ceramic coating 2 form a stable contact interface, thus constituting the lower electrode system of the deep trench capacitor.

[0055] Above the inner surface of the bottom electrode 7, a dense dielectric layer 8 is further stacked and wrapped in an absolutely conformal manner. The dielectric layer 8 completely isolates the bottom electrode 7 from the outside and acts as the core energy storage dielectric of the entire deep trench capacitor. Its thickness of 10-30nm not only ensures the safety of high breakdown voltage, but also minimizes the distance between the positive and negative plates, increasing the capacitance density. Finally, above the inner surface of the dielectric layer 8, a top electrode 9 is also tightly attached in a conformal deposition manner. The top electrode 9 fills the remaining central cavity area inside the through-silicon via 6 (or covers its inner wall to form a central hollow tubular electrode according to different design requirements), and extends outward to the upper opening of the through-silicon via 6, forming the upper plate system of the deep trench capacitor. The bottom electrode 7, dielectric layer 8, and top electrode 9 are nested layer by layer, jointly reconstructing a three-dimensional spatially folded and expanded "metal-insulator-metal" supercapacitor architecture inside the extremely narrow through-silicon via 6.

[0056] From the perspective of the installation location and connection relationship of the technical features, the above-mentioned stacked structure exhibits strong interdependence at the microscale. The etched substrate 1 serves as the outermost mechanical framework and heat dissipation channel; the bottom ceramic coating 2 is embedded at the bottom of the framework, serving as the foundation of the bottom electrode 7; the bottom electrode 7 is attached and climbs upwards to cover the entire sidewall; the dielectric layer 8 is seamlessly embedded between the two metal plates; and the top electrode 9 serves as the core conductor penetrating the center. The materials of each layer are tightly bonded in situ through chemical bonds, with no physical peeling or bubble void defects at the interface, thus ensuring the high integrity of the deep trench capacitor in terms of physical morphology and the stability of its functional operation.

[0057] In summary, the deep trench capacitor provided in this embodiment exhibits superior structural advantages in terms of usage and technical performance. It folds and hides a large charge storage area within the silicon vias 6 deep within the etched substrate 1, resulting in a negligible chip area occupied on the macroscopic horizontal plane, while amplifying the energy storage efficiency by tens of times in the microscopic vertical space. The in-situ retention and utilization of the underlying ceramic coating 2 primarily serves as an etching catalyst residue layer, preventing the introduction of impurities and improving overall process compatibility. This deep trench capacitor possesses comprehensive advantages such as low leakage current, high capacitance density, excellent frequency response, and environmental tolerance, demonstrating extremely broad prospects for commercial mass production.

Claims

1. A method for preparing a deep trench capacitor, characterized in that, Includes the following steps: S1. A bottom ceramic coating (2) and a silicon dioxide coating (3) are sequentially deposited on an etched substrate (1); S2. A positive photoresist layer (4) is coated on the side of the silicon dioxide coating (3) away from the underlying ceramic coating (2), a silicon via hole outline (5) is formed in the positive photoresist layer (4), the silicon dioxide coating (3) located outside the silicon via hole outline (5) is removed by wet etching, and the positive photoresist layer (4) is stripped off. S3. Remove the bottom ceramic coating (2) located outside the outline (5) of the through-silicon via, and then use wet etching to remove the remaining silicon dioxide coating (3) to form a patterned monolayer catalyst array on the etched substrate (1); S4. The etched substrate (1) after completing step S3 is placed into a reaction chamber containing etching solution. The reaction chamber is heated to generate etchant vapor. The etchant vapor is used to perform gas phase metal-assisted chemical etching. At the same time as etching, a downward magnetic field is formed in the reaction chamber. A through-silicon via (6) is formed in the etched substrate (1) by vertical etching. S5. A bottom electrode (7), a dielectric layer (8) and a top electrode (9) are sequentially deposited in the through-silicon via (6), wherein the bottom ceramic coating (2) is used for the gas-phase metal-assisted chemical etching catalysis.

2. The method for preparing a deep trench capacitor according to claim 1, characterized in that: The etched substrate (1) is made of silicon substrate. The material of the bottom ceramic coating (2) is titanium nitride, and the thickness of the bottom ceramic coating (2) is 3-15nm; the thickness of the silicon dioxide coating (3) is 10-50nm.

3. The method for preparing a deep trench capacitor according to claim 1, characterized in that: In step S3, the etched substrate (1) is placed in a mixed solution containing ammonia and hydrogen peroxide to remove the underlying ceramic coating (2) outside the through-silicon via (TSV) hole outline (5).

4. The method for preparing a deep trench capacitor according to claim 1, characterized in that: In step S4, the etching solution is made by mixing hydrogen peroxide, hydrofluoric acid and deionized water, and the ratio of hydrogen peroxide, hydrofluoric acid and deionized water is 1:3-6:2-7 by volume. In step S4, the heating and etching temperature in the reaction chamber is controlled at 50-90℃.

5. The method for preparing a deep trench capacitor according to claim 1, characterized in that: In step S4, the downward magnetic field is a gradient magnetic field set along the etching extension direction of the silicon via, and the magnetic flux density gradually increases along the etching direction.

6. The method for preparing a deep trench capacitor according to claim 1, characterized in that: In step S5, the bottom electrode (7), the dielectric layer (8), and the top electrode (9) are prepared using atomic layer deposition.

7. The method for preparing a deep trench capacitor according to claim 6, characterized in that, The specific steps for preparing the bottom electrode (7) and the top electrode (9) include: Heated to 380°C in a vacuum chamber filled with nitrogen at a pressure of 100 Pa; A pulse is introduced to induce a chemical adsorption reaction in titanium tetrachloride, which is then purged with nitrogen gas. Ammonia gas is pulsed in to induce a chemical reaction that produces titanium nitride. Nitrogen gas is then introduced to purge and remove the reaction byproducts.

8. The method for preparing a deep trench capacitor according to claim 6, characterized in that, The specific steps for preparing the dielectric layer (8) include: Heating to 200-250℃ in a vacuum chamber filled with nitrogen at a pressure of 100 Pa; A pulsed infusion of trimethylaluminum causes a chemisorption reaction, which is then purged with nitrogen gas. A pulse is introduced into deionized water to produce a chemical reaction that generates aluminum oxide. Nitrogen gas is then introduced to purge and remove the reaction byproducts. Repeat the above pulse and purging cycle until the target thickness is reached.

9. The method for preparing a deep trench capacitor according to claim 1, characterized in that: The bottom electrode (7) is a titanium nitride layer with a thickness of 10-30 nm; The dielectric layer (8) is an aluminum oxide layer with a thickness of 10-30 nm; The top electrode (9) is a titanium nitride layer with a thickness of 1-100 nm.

10. A deep trench capacitor, manufactured using the method for preparing a deep trench capacitor as described in any one of claims 1 to 9, characterized in that, The deep trench capacitor includes an etched substrate (1) with a through-silicon via (6) inside. The inner wall of the through-silicon via (6) is provided with a bottom electrode (7), a dielectric layer (8) and a top electrode (9) from the outside to the inside. The bottom ceramic coating (2) is located at the bottom of the through-silicon via (6) and is in contact with the bottom electrode (7).

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