A semiconductor device and a manufacturing method

Abstract

The application provides a semiconductor device and a manufacturing method. After a first wafer and a second wafer are mixedly bonded, a capacitor structure is formed at a bonding interface. The temperature of the mixed bonding is not more than 300 DEG C, so that the performance degradation of the capacitor caused by a high-temperature process is avoided. Furthermore, the capacitor structure is arranged at the bonding interface, so that the interconnection path length is greatly shortened, and the interconnection resistance is reduced. In addition, the capacitor structure arranged at the bonding interface can improve the quality factor, and can be used for 5G millimeter filtering.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology and relates to a semiconductor device and its manufacturing method. Background Technology

[0002] Metal-Insulator-Metal (MIM) capacitors are key capacitive components in integrated circuits. Their core structure consists of two layers of metal electrode plates sandwiching a layer of high-dielectric-constant insulating material. In semiconductor manufacturing processes, the main methods for integrating logic chips and MIM capacitors include:

[0003] (a) Monolithic integrated capacitors: MIM capacitors are fabricated directly on logic chip wafers using semiconductor processes. Since the fabrication process of MIM capacitors is incompatible with that of logic chips, additional specialized photomasks and process steps are required, increasing the difficulty of the process and the production cost.

[0004] (ii) Copper-copper thermocompression bonding: The logic chip and the MIM capacitor are bonded together by copper-copper thermocompression bonding process. The bonding temperature of copper-copper thermocompression bonding process is high, far exceeding 300℃, which will lead to the degradation of the dielectric layer performance of the capacitor.

[0005] (iii) Adhesive bonding: The logic chip and the MIM capacitor are bonded together using adhesives such as benzocyclobutene or epoxy resin, but this will introduce additional parasitic capacitance, affecting high-frequency characteristics (such as 5G millimeter wave band).

[0006] Therefore, how to provide a semiconductor device and its fabrication method to reduce process difficulty and improve device performance has become a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0007] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a semiconductor device and manufacturing method to solve the problems of high process difficulty and low device performance when integrating logic chips and MIM capacitors in the prior art.

[0008] To achieve the above and other related objectives, the present invention provides a method for fabricating a semiconductor device, comprising the following steps:

[0009] A first wafer is provided, in which a logic chip is formed, a first dielectric layer is formed on the first wafer, and a first bonding conductive post and a capacitor first electrode plate are formed in the first dielectric layer, wherein the first bonding conductive post and the capacitor first electrode plate are spaced apart.

[0010] A second wafer is provided, on which a second electrode plate of a capacitor and a second dielectric layer covering the second electrode plate of the capacitor are formed, and a second bonding conductive pillar is formed in the second dielectric layer, wherein the second bonding conductive pillar and the second electrode plate of the capacitor are spaced apart;

[0011] The first wafer having the first dielectric layer and the second wafer having the second dielectric layer are mixed-bonded, and the bonding temperature of the mixed bonding does not exceed 300°C. The first bonding conductive post and the second bonding conductive post are electrically connected. The first electrode plate of the capacitor, the second electrode plate of the capacitor, and the dielectric layer between the first electrode plate of the capacitor and the second electrode plate of the capacitor constitute a capacitor structure.

[0012] Optionally, before mixing and bonding the side of the first wafer having the first dielectric layer and the side of the second wafer having the second dielectric layer, the method further includes a step of plasma activation treatment on the side of the first wafer having the first dielectric layer and the side of the second wafer having the second dielectric layer.

[0013] Optionally, the gas used for plasma activation treatment is a mixture of N2 and H2, and the temperature of plasma activation treatment does not exceed 300°C.

[0014] Optionally, after mixing and bonding the side of the first wafer having the first dielectric layer and the side of the second wafer having the second dielectric layer, the method further includes a step of repairing oxygen vacancies in the dielectric layer between the first electrode plate of the capacitor and the second electrode plate of the capacitor.

[0015] Optionally, the gas used for oxygen vacancy repair is O3, and the temperature for oxygen vacancy repair does not exceed 300°C.

[0016] Optionally, the second dielectric layer is a stack of HfO2 layers / SiO2 layers.

[0017] Optionally, a first nitrogen-doped silicon carbide layer is further formed on the first wafer, the first nitrogen-doped silicon carbide layer covers the first dielectric layer, and the first nitrogen-doped silicon carbide layer exposes the first bonding conductive pillar.

[0018] A second nitrogen-doped silicon nitride layer is also formed on the second wafer. The second nitrogen-doped silicon carbide layer covers the second dielectric layer, and the second nitrogen-doped silicon carbide layer exposes the second bonding conductive pillar.

[0019] When the first wafer having the first dielectric layer and the second wafer having the second dielectric layer are mixed-bonded, the first nitrogen-doped silicon carbide layer and the second nitrogen-doped silicon carbide layer are in contact.

[0020] The present invention also provides a semiconductor device, comprising:

[0021] A first wafer, wherein a logic chip is provided in the first wafer, a first dielectric layer is provided on the first wafer, and a first bonding conductive post and a first capacitor electrode plate are provided in the first dielectric layer, wherein the first bonding conductive post and the first capacitor electrode plate are spaced apart.

[0022] The second wafer is located on the side of the first wafer having the first dielectric layer. The side of the second wafer facing the first wafer is provided with a second electrode plate of a capacitor and a second dielectric layer covering the second electrode plate of the capacitor. The second dielectric layer is provided with a second bonding conductive post, and the second bonding conductive post and the second electrode plate of the capacitor are spaced apart.

[0023] The first wafer having the first dielectric layer and the second wafer having the second dielectric layer are mixed and bonded together. The first and second bonded conductive pillars are electrically connected. The first electrode plate, the second electrode plate, and the dielectric layer between the first and second electrode plates constitute a capacitor structure.

[0024] Optionally, the second dielectric layer is a stack of HfO2 layers / SiO2 layers.

[0025] Optionally, the first wafer is further provided with a first nitrogen-doped silicon carbide layer, the first nitrogen-doped silicon carbide layer covering the first dielectric layer, and the first nitrogen-doped silicon carbide layer exposing the first bonding conductive pillar.

[0026] The second wafer is further provided with a second nitrogen-doped silicon nitride layer on the side facing the first wafer. The second nitrogen-doped silicon carbide layer covers the second dielectric layer, and the second nitrogen-doped silicon carbide layer exposes the second bonding conductive pillar.

[0027] The first nitrogen-doped silicon carbide layer and the second nitrogen-doped silicon carbide layer are in contact with each other.

[0028] As described above, in the semiconductor device and manufacturing method of the present invention, after the first wafer and the second wafer are mixed and bonded, a capacitor structure is formed at the bonding interface. The temperature of the mixed bonding does not exceed 300°C to avoid degradation of capacitor performance caused by high-temperature processes. Furthermore, setting a capacitor structure at the bonding interface greatly shortens the interconnect path length and reduces the interconnect resistance. In addition, setting a capacitor structure at the bonding interface can improve the quality factor and enable it to be used for 5G millimeter filtering. Attached Figure Description

[0029] Figure 1 The diagram shown is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention.

[0030] Figure 2 The diagram shown is a schematic diagram of a first wafer provided in an embodiment of the present invention, on which a first dielectric layer is formed and an opening in the first dielectric layer is formed.

[0031] Figure 3 The diagram shows a first bonding conductive pillar and a first electrode plate of a capacitor formed in the opening of the first dielectric layer in an embodiment of the present invention.

[0032] Figure 4 The diagram shown is a schematic diagram of a second wafer provided in an embodiment of the present invention, on which a second electrode plate of a capacitor is formed.

[0033] Figure 5 The diagram shows a second dielectric layer formed on a second wafer and an opening in the second dielectric layer in an embodiment of the present invention.

[0034] Figure 6 This is a schematic diagram showing the formation of a second bonded conductive pillar in the opening of the second dielectric layer in an embodiment of the present invention.

[0035] Figure 7 The diagram shown is a schematic representation of the co-bonding of a first wafer and a second wafer in an embodiment of the present invention.

[0036] Component labeling: 1-First wafer; 2-First dielectric layer; 200-First region first dielectric layer opening; 201-Second region first dielectric layer opening; 3-First bonding conductive pillar; 4-First electrode plate of capacitor; 5-Second wafer; 6-Second electrode plate of capacitor; 7-Second dielectric layer; 700-Second dielectric layer opening; 8-Second bonding conductive pillar; 9-Capacitor structure; S1~S3-Steps. Detailed Implementation

[0037] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0038] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, whole, step, or component, but does not exclude the presence or addition of one or more other features, wholes, steps, or components.

[0039] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0040] In the context of this application, the structure described above the first feature may include embodiments in which the first feature and the second feature are in direct contact, or embodiments in which an additional feature is disposed between the first feature and the second feature, such that the first feature and the second feature may not be in direct contact.

[0041] Please see Figures 1 to 7 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0042] This embodiment provides a method for fabricating a semiconductor device. Please refer to [link / reference]. Figure 1 The diagram shows a flowchart of a semiconductor device fabrication method according to an embodiment of the present invention, including the following steps:

[0043] S1: A first wafer is provided, in which a logic chip is formed, a first dielectric layer is formed on the first wafer, and a first bonding conductive post and a capacitor first electrode plate are formed in the first dielectric layer, wherein the first bonding conductive post and the capacitor first electrode plate are spaced apart.

[0044] S2: A second wafer is provided, on which a second electrode plate of a capacitor and a second dielectric layer covering the second electrode plate of the capacitor are formed, and a second bonding conductive pillar is formed in the second dielectric layer, wherein the second bonding conductive pillar and the second electrode plate of the capacitor are spaced apart;

[0045] S3: The side of the first wafer having the first dielectric layer and the side of the second wafer having the second dielectric layer are mixed-bonded, and the bonding temperature of the mixed bonding does not exceed 300°C. The first bonding conductive post and the second bonding conductive post are electrically connected. The first electrode plate of the capacitor, the second electrode plate of the capacitor, and the dielectric layer between the first electrode plate of the capacitor and the second electrode plate of the capacitor constitute a capacitor structure.

[0046] The fabrication method of the semiconductor device in this embodiment will be described in detail below with reference to the specific accompanying drawings.

[0047] First, please refer to Figure 2 and Figure 3 Step S1: Provide a first wafer 1, in which a logic chip is formed, and a first dielectric layer 2 is formed on the first wafer 1. A first bonding conductive post 3 and a capacitor first electrode plate 4 are formed in the first dielectric layer 2, wherein the first bonding conductive post 3 and the capacitor first electrode plate 4 are spaced apart.

[0048] As an example, the first wafer 1 can be any suitable semiconductor wafer. In this embodiment, the first wafer 1 is a silicon wafer, and a logic chip is formed in the first wafer 1 through the front-end process of the logic chip.

[0049] As an example, the first dielectric layer 2 is a dielectric layer in the back-end process of the logic chip. The first dielectric layer 2 adopts a low dielectric constant (Low K) dielectric layer to reduce the parasitic capacitance between metal wires, thereby reducing signal transmission delay and chip power consumption.

[0050] As an example, such as Figure 2 As shown, after the first dielectric layer 2 is formed on the first wafer 1, the first dielectric layer 2 is etched using an etching process to form a first dielectric layer opening in the first dielectric layer 2.

[0051] As an example, the first dielectric layer opening includes a first region first dielectric layer opening 200 and a second region first dielectric layer opening 201, which are spaced apart. The first region first dielectric layer opening 200 is used to subsequently form a first bonding conductive post, and the second region first dielectric layer opening 201 is used to subsequently form a capacitor first electrode plate.

[0052] As an example, such as Figure 3 As shown, the first bonding conductive post 3 is formed in the first dielectric layer opening 200 in the first region, and the first electrode plate 4 of the capacitor is formed in the first dielectric layer opening 201 in the second region.

[0053] As an example, a metal layer is filled in the first dielectric layer opening 200 in the first region and the first dielectric layer opening 201 in the second region to form the first bonding conductive pillar 3 and the first electrode plate 4 of the capacitor; specifically, in this embodiment, the metal layer filled in the first dielectric layer opening 200 in the first region and the first dielectric layer opening 201 in the second region is a copper metal layer.

[0054] As an example, during the process of filling the first dielectric layer opening 200 in the first region and the first dielectric layer opening 201 in the second region with a deposition process, the metal layer is also formed on top of the first dielectric layer 2. Then, a chemical mechanical polishing (CMP) process is used to remove the metal layer on top of the first dielectric layer 2, leaving the metal layer located in the first dielectric layer opening 200 in the first region and the first dielectric layer opening 201 in the second region.

[0055] As an example, the height difference of the first bonded conductive pillar 3 after CMP is less than 5 nm to improve the yield of subsequent hybrid bonding.

[0056] Next, please refer to Figures 4 to 6 Step S2: Provide a second wafer 5, on which a second capacitor electrode plate 6 and a second dielectric layer 7 covering the second capacitor electrode plate 6 are formed, and a second bonding conductive post 8 is formed in the second dielectric layer 7, wherein the second bonding conductive post 8 and the second capacitor electrode plate 6 are spaced apart.

[0057] As an example, the second wafer 5 can be any suitable semiconductor wafer. In this embodiment, the second wafer 5 is a high-resistivity silicon wafer.

[0058] As an example, in this embodiment, the material of the second electrode plate 6 of the capacitor is TiN, and the step of forming the second electrode plate 6 of the capacitor on the second wafer 5 includes:

[0059] (a) A TiN layer is formed on the second wafer 5 using a deposition process;

[0060] (ii) The TiN layer is etched using an etching process to form the second electrode plate 6 of the capacitor.

[0061] As an example, such as Figure 5 As shown, after the second electrode plate 6 of the capacitor is formed, the second dielectric layer 7 covering the second electrode plate 6 of the capacitor is formed on the second wafer 5.

[0062] As an example, the second dielectric layer 7 includes a high dielectric constant (High K) material layer; specifically, in this embodiment, the second dielectric layer 7 is a stack of HfO2 layer / SiO2 layer.

[0063] As an example, after the second dielectric layer 7 is formed on the second wafer 5, the second dielectric layer 7 is etched using an etching process to form a second dielectric layer opening 700 in the second dielectric layer 7. The second dielectric layer opening 700 is subsequently used to form a second bonding conductive pillar.

[0064] As an example, such as Figure 6As shown, a metal layer is filled into the opening 700 of the second dielectric layer to form the second bonding conductive pillar 8. Specifically, in this embodiment, the metal layer filled into the opening 700 of the second dielectric layer is a copper metal layer.

[0065] As an example, during the process of filling the opening 700 of the second dielectric layer with a metal layer using a deposition process, a metal layer is also formed on top of the second dielectric layer 7. Then, a chemical mechanical polishing (CMP) process is used to remove the metal layer on top of the second dielectric layer 7, leaving the metal layer located in the opening 700 of the second dielectric layer.

[0066] As an example, the height difference of the second bonding conductive pillar 8 after CMP is less than 5 nm to improve the yield of subsequent hybrid bonding.

[0067] As an example, the second dielectric layer 7 is provided with an interconnect layer to electrically connect the second bonding conductive post 8 and the capacitor second electrode plate 6.

[0068] Next, please refer to Figure 7 Step S3: The first wafer 1 with the first dielectric layer 2 and the second wafer 5 with the second dielectric layer 7 are mixed and bonded. The bonding temperature of the mixed bonding does not exceed 300°C. The first bonding conductive post 3 and the second bonding conductive post 8 are electrically connected. The first electrode plate 4, the second electrode plate 6, and the dielectric layer between the first electrode plate 4 and the second electrode plate 6 constitute the capacitor structure 9.

[0069] As an example, the dielectric layer between the first electrode plate 4 and the second electrode plate 6 constitutes the capacitor dielectric layer. Specifically, in this embodiment, the second dielectric layer 7 serves as the capacitor dielectric layer. Since the second dielectric layer 7 is a stack of HfO2 layers / SiO2 layers, that is, the capacitor dielectric layer includes a stack of HfO2 layers / SiO2 layers, it provides a high capacitance density (>50nF / mm²). 2 ) and low leakage current (<10) -8 A / cm 2 ).

[0070] As an example, before the first wafer 1 having the first dielectric layer 2 and the second wafer 5 having the second dielectric layer 7 are mixed-bonded, a step of plasma activation treatment is included on the side of the first wafer 1 having the first dielectric layer 2 and the side of the second wafer 5 having the second dielectric layer 7. By performing the plasma activation treatment on the mixed-bonding interface, the bonding energy is enhanced, improving the subsequent mixed-bonding yield.

[0071] As an example, the gas used in the plasma activation treatment is a mixture of N2 and H2, and the temperature of the plasma activation treatment does not exceed 300°C to avoid damage to the capacitor dielectric layer due to excessively high temperature.

[0072] Specifically, in this embodiment, during the plasma activation treatment, the ratio of N2 to H2 is 4:1, the treatment temperature is 200°C, and the treatment time is 5 minutes.

[0073] As an example, after the plasma activation treatment is completed, the side of the first wafer 1 with the first dielectric layer 2 and the side of the second wafer 5 with the second dielectric layer 7 are mixed and bonded. The temperature of the mixed bonding does not exceed 300°C to avoid damage to the capacitor dielectric layer due to excessively high temperature.

[0074] Specifically, in this embodiment, the bonding temperature of the hybrid bonding is 200°C, the bonding pressure is 5kN, and the bonding time is 10 minutes.

[0075] As an example, after the hybrid bonding is completed, the hybrid bonded structure can be placed in a furnace tube for low-temperature annealing to improve the bonding strength and achieve permanent bonding; specifically, in this embodiment, the low-temperature annealing temperature in the furnace tube is 300°C.

[0076] As an example, the first dielectric layer 2 is a Low K dielectric layer, and the second dielectric layer 7 is a High K dielectric layer (HfO2 layer / SiO2 layer). In order to make the first dielectric layer 2 have a low dielectric constant, it is usually loose and porous with weak mechanical strength. If the first dielectric layer 2 is directly subjected to plasma activation treatment, it is easily damaged by plasma. In addition, if the loose and porous first dielectric layer 2 is directly contacted with HfO2 and annealed, the pores in the first dielectric layer 2 may absorb moisture or cause voids at the bonding interface. At the same time, the first dielectric layer 2 and HfO2 have different coefficients of thermal expansion, which can easily generate stress when the temperature changes, potentially leading to delamination. In this embodiment, a first nitrogen-doped silicon carbide layer is further formed on the first wafer 1, which covers the first dielectric layer 2 and exposes the first bonding conductive pillar 3; a second nitrogen-doped silicon nitride layer is further formed on the second wafer 4, which covers the second dielectric layer 7 and exposes the second bonding conductive pillar 8; wherein, when the side of the first wafer 1 with the first dielectric layer 2 and the side of the second wafer 5 with the second dielectric layer 7 are mixed-bonded, the first nitrogen-doped silicon carbide layer and the second nitrogen-doped silicon carbide layer are in contact and connected, and the coefficients of thermal expansion are consistent at the bonding interface, thereby reducing the interface thermal stress.

[0077] As an example, under the action of mixed bonding and low-temperature annealing, the copper atom layers of the first bonded conductive pillar 3 and the second bonded conductive pillar 8 directly diffuse and fuse to form a metallurgical bond. There are almost no scattering centers at the interface, and electrons can pass freely as if they were passing through a whole piece of copper, thus reducing resistance.

[0078] As an example, in a traditional TSV (Through Silicon Via) plus microbump solution, the signal path is typically: logic chip → microbump → redistribution layer → TSV → another microbump → capacitor. This path involves multiple heterojunctions, and the resistivity of the solder is usually an order of magnitude higher than that of pure copper. Furthermore, the TSV itself has a certain aspect ratio resistance. In this embodiment, the second electrode plate 6 of the capacitor structure 9 is directly connected to the power distribution network (PDN) of the logic chip via bonded copper pillars (the second bonded conductive pillar 8 and the first bonded conductive pillar 3), eliminating the TSV and microbump. Current only needs to flow vertically through the extremely short bonding interface between the second bonded conductive pillar 8 and the first bonded conductive pillar 3, shortening the interconnect path length and reducing the interconnect resistance to less than 1 Ω / μm. 2 .

[0079] As an example, in this embodiment, the capacitor structure 9 is disposed at the bonding interface between the first wafer 1 and the second wafer 5, and the quality factor Q is improved to over 100 at a frequency of 28GHz, which can be used for 5G millimeter filtering.

[0080] As an example, the reason why placing the capacitor structure 9 at the bonding interface can improve the quality factor Q is that:

[0081] (i) If the capacitor structure 9 is placed inside the logic chip, the lower plate of the capacitor is very close to the silicon substrate (first wafer 1, a lossy semiconductor material). The frequency signal will be coupled to the substrate through parasitic capacitance, generating eddy current loss and severely reducing the Q value. In this embodiment, the capacitor structure 9 is placed at the bonding interface, with a high-resistivity silicon substrate (second wafer 5, with minimal loss) on one side and the bonding interface and the back of the logic chip on the other side, making the capacitor structure 9 like an ideal, low-loss passive component, thus improving the Q value.

[0082] (ii) The first electrode plate 4 of the capacitor in the capacitor structure 9 is the metal layer of the logic chip. Therefore, the circuit that needs to be filtered (such as the amplifier) ​​can be directly connected to the capacitor on the metal layer with almost no extra leads. The parasitic inductance is minimized, ensuring that the capacitor is still a capacitor at 28GHz, instead of becoming an inductor.

[0083] (iii) The capacitor structure 9 is fabricated at the bonding interface. Before the first wafer 1 and the second wafer 5 are bonded, the optimal HfO2 / SiO2 stack can be deposited separately on the second wafer 5. This dielectric material is usually not allowed in the standard BEOL process of logic chips (because the introduction of new materials is costly and risky). Through the bonding process, the two heterogeneous materials (high-K dielectric and high-precision metal) are seamlessly integrated together, realizing the "complementary advantages" of performance.

[0084] As an example, after the first wafer 1 with the first dielectric layer 2 and the second wafer 5 with the second dielectric layer 7 are mixed and bonded, the method further includes a step of repairing oxygen vacancies in the dielectric layer between the first electrode plate 4 and the second electrode plate 6 of the capacitor. By repairing oxygen vacancies in the dielectric layer, the oxygen vacancies in the HfO2 layer / SiO2 layer of the capacitor dielectric layer are repaired, the leakage current of the capacitor structure 9 is reduced, and its reliability and high-frequency performance are improved.

[0085] As an example, the gas used for oxygen vacancy repair is O3, and the temperature for oxygen vacancy repair does not exceed 300°C to avoid damage to the capacitor dielectric layer due to excessively high temperature; specifically, in this embodiment, the temperature for oxygen vacancy repair is 150°C.

[0086] As an example, after the first wafer 1 with the first dielectric layer 2 and the second wafer 5 with the second dielectric layer 7 are mixed and bonded, helium leak detection can be used to verify that there are no micro-gaps at the bonding interface.

[0087] As an example, the process steps can be adjusted according to requirements. For example, the second wafer 5 can be provided first, followed by the first wafer 1, or the first wafer 1 and the second wafer 5 can be provided simultaneously, without being limited to this embodiment.

[0088] As an example, based on 300mm wafer test data, the bonding yield in this embodiment is greater than 99.9%.

[0089] As an example, the high-frequency loss in this embodiment is reduced by 60% (frequency 10GHz).

[0090] Thus, a semiconductor device has been fabricated. Please refer to [link / reference]. Figure 7The semiconductor device includes a first wafer 1 and a second wafer 5. The first wafer 1 has a logic chip and a first dielectric layer 2. The first dielectric layer 2 has a first bonding conductive post 3 and a first capacitor electrode plate 4, which are spaced apart. The second wafer 5 is located on the side of the first wafer 1 with the first dielectric layer 2. The side of the second wafer 5 facing the first wafer 1 has a second capacitor electrode plate 6 and a second dielectric layer 7 covering the second capacitor electrode plate 6. The second dielectric layer 7 has a second bonding conductive post 8, which is spaced apart from the second capacitor electrode plate 6. The side of the first wafer 1 with the first dielectric layer 2 and the side of the second wafer 5 with the second dielectric layer 7 are mixed-bonded together. The first bonding conductive post 3 and the second bonding conductive post 8 are electrically connected. The first capacitor electrode plate 4, the second capacitor electrode plate 6, and the dielectric layer between the first capacitor electrode plate 4 and the second capacitor electrode plate 6 constitute a capacitor structure 9.

[0091] As an example, the first wafer 1 can be any suitable semiconductor wafer. In this embodiment, the first wafer 1 is a silicon wafer.

[0092] As an example, the first dielectric layer 2 is a low dielectric constant (Low K) dielectric layer, which reduces the parasitic capacitance between metal wires, thereby reducing signal transmission delay and chip power consumption.

[0093] As an example, the first bonding conductive post 3 is made of copper, and the first electrode plate 4 of the capacitor is made of copper.

[0094] As an example, the second wafer 5 can be any suitable semiconductor wafer. In this embodiment, the second wafer 5 is a high-resistivity silicon wafer.

[0095] As an example, the material of the second electrode plate 6 of the capacitor is TiN.

[0096] As an example, the second dielectric layer 7 includes a high dielectric constant (High K) material layer; specifically, in this embodiment, the second dielectric layer 7 is a stack of HfO2 layer / SiO2 layer.

[0097] As an example, the second bonding conductive post 8 is made of copper.

[0098] As an example, the dielectric layer between the first electrode plate 4 and the second electrode plate 6 constitutes the capacitor dielectric layer. Specifically, in this embodiment, the second dielectric layer 7 serves as the capacitor dielectric layer. Since the second dielectric layer 7 is a stack of HfO2 layers / SiO2 layers, that is, the capacitor dielectric layer includes a stack of HfO2 layers / SiO2 layers, it provides a high capacitance density (>50nF / mm²). 2 ) and low leakage current (<10) -8 A / cm 2 ).

[0099] As an example, the first wafer 1 is further provided with a first nitrogen-doped silicon carbide layer, which covers the first dielectric layer 2 and exposes the first bonding conductive pillar 3; the second wafer 5 is further provided with a second nitrogen-doped silicon nitride layer on the side facing the first wafer 1, which covers the second dielectric layer 7 and exposes the second bonding conductive pillar 8; wherein the first nitrogen-doped silicon carbide layer and the second nitrogen-doped silicon carbide layer are in contact connection.

[0100] In summary, in the semiconductor device and fabrication method of the present invention, after the first wafer and the second wafer are mixed and bonded, a capacitor structure is formed at the bonding interface. The mixing and bonding temperature does not exceed 300°C, avoiding performance degradation of the capacitor caused by high-temperature processes. Furthermore, setting the capacitor structure at the bonding interface greatly shortens the interconnect path length and reduces the interconnect resistance. In addition, setting the capacitor structure at the bonding interface can improve the quality factor, enabling its use in 5G millimeter-scale filtering. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0101] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a semiconductor device, characterized in that, Includes the following steps: A first wafer is provided, in which a logic chip is formed, a first dielectric layer is formed on the first wafer, and a first bonding conductive post and a capacitor first electrode plate are formed in the first dielectric layer, wherein the first bonding conductive post and the capacitor first electrode plate are spaced apart. A second wafer is provided, on which a second electrode plate of a capacitor and a second dielectric layer covering the second electrode plate of the capacitor are formed, and a second bonding conductive pillar is formed in the second dielectric layer, wherein the second bonding conductive pillar and the second electrode plate of the capacitor are spaced apart; The first wafer having the first dielectric layer and the second wafer having the second dielectric layer are mixed-bonded, and the bonding temperature of the mixed bonding does not exceed 300°C. The first bonding conductive post and the second bonding conductive post are electrically connected. The first electrode plate of the capacitor, the second electrode plate of the capacitor, and the dielectric layer between the first electrode plate of the capacitor and the second electrode plate of the capacitor constitute a capacitor structure.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that: Before mixing and bonding the side of the first wafer having the first dielectric layer and the side of the second wafer having the second dielectric layer, the method further includes a step of plasma activation treatment on the side of the first wafer having the first dielectric layer and the side of the second wafer having the second dielectric layer.

3. The method for fabricating a semiconductor device according to claim 2, characterized in that: The gas used for plasma activation treatment is a mixture of N2 and H2, and the temperature of plasma activation treatment does not exceed 300°C.

4. The method for fabricating a semiconductor device according to claim 1, characterized in that: After the first wafer with the first dielectric layer and the second wafer with the second dielectric layer are mixed and bonded, the method further includes a step of repairing oxygen vacancies in the dielectric layer between the first electrode plate and the second electrode plate of the capacitor.

5. The method for fabricating a semiconductor device according to claim 4, characterized in that: The gas used for oxygen vacancy repair is O3, and the temperature for oxygen vacancy repair does not exceed 300°C.

6. The method for fabricating a semiconductor device according to claim 1, characterized in that: The second dielectric layer is a stack of HfO2 layers / SiO2 layers.

7. The method for fabricating a semiconductor device according to claim 1, characterized in that: A first nitrogen-doped silicon carbide layer is also formed on the first wafer. The first nitrogen-doped silicon carbide layer covers the first dielectric layer and exposes the first bonding conductive pillar. A second nitrogen-doped silicon nitride layer is also formed on the second wafer. The second nitrogen-doped silicon carbide layer covers the second dielectric layer, and the second nitrogen-doped silicon carbide layer exposes the second bonding conductive pillar. When the first wafer having the first dielectric layer and the second wafer having the second dielectric layer are mixed and bonded, the first nitrogen-doped silicon carbide layer and the second nitrogen-doped silicon carbide layer are in contact.

8. A semiconductor device, characterized in that, include: A first wafer, wherein a logic chip is provided in the first wafer, a first dielectric layer is provided on the first wafer, and a first bonding conductive post and a first capacitor electrode plate are provided in the first dielectric layer, wherein the first bonding conductive post and the first capacitor electrode plate are spaced apart. The second wafer is located on the side of the first wafer having the first dielectric layer. The side of the second wafer facing the first wafer is provided with a second electrode plate of a capacitor and a second dielectric layer covering the second electrode plate of the capacitor. The second dielectric layer is provided with a second bonding conductive post, and the second bonding conductive post and the second electrode plate of the capacitor are spaced apart. The first wafer having the first dielectric layer and the second wafer having the second dielectric layer are mixed and bonded together. The first and second bonded conductive pillars are electrically connected. The first electrode plate, the second electrode plate, and the dielectric layer between the first and second electrode plates constitute a capacitor structure.

9. The semiconductor device according to claim 8, characterized in that: The second dielectric layer is a stack of HfO2 layers / SiO2 layers.

10. The semiconductor device according to claim 8, characterized in that: The first wafer is further provided with a first nitrogen-doped silicon carbide layer, which covers the first dielectric layer and exposes the first bonding conductive pillar. The second wafer is further provided with a second nitrogen-doped silicon nitride layer on the side facing the first wafer. The second nitrogen-doped silicon carbide layer covers the second dielectric layer, and the second nitrogen-doped silicon carbide layer exposes the second bonding conductive pillar. The first nitrogen-doped silicon carbide layer and the second nitrogen-doped silicon carbide layer are in contact with each other.

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