Preparation method of low-loss super-junction soft-recovery diode

Abstract

The application discloses a preparation method of a low-loss super-junction soft-recovery diode and relates to the technical field of power semiconductor device manufacturing. The application comprises the following steps: after an initial section of the P-type column is completed, a cycle step is repeatedly executed to form a P / N column super-junction structure, the P / N column super-junction structure is alternately arranged, and the cycle step comprises the following steps: N-type epitaxial layer growth, alignment photolithography to form a P-type column injection window, P-type impurity ion injection and activation annealing; and high-temperature push-junction annealing treatment is performed on the P / N column super-junction structure to form a continuous P-type column. The application successfully forms a P / N column super-junction structure by growing a first N-type epitaxial layer on a P-type silicon substrate, adopting deep ultraviolet photolithography technology and a P-type impurity ion injection process, ensures that the diode has ideal withstand voltage performance and low-loss characteristics, and ensures the high consistency and stability of the P / N structure through multiple cycle steps, thereby improving the overall performance of the diode.

Description

Technical Field

[0001] This invention belongs to the field of power semiconductor device manufacturing technology, and in particular relates to a method for preparing a low-loss superjunction soft recovery diode. Background Technology

[0002] Power semiconductor devices play a crucial role in power conversion systems, with fast recovery diodes being key components for achieving efficient power conversion. With the development of new energy and industrial power supplies, higher demands are being placed on the performance of diodes operating under high voltage and high frequency conditions. Currently, mainstream fast recovery diodes primarily achieve rapid turn-off through a combination of traditional PIN structures and carrier lifetime control technology, a mature process with relatively low cost. To overcome the conduction loss bottleneck of traditional structures under high voltage, superjunction structures have emerged. Superjunction structures optimize the electric field distribution by employing alternating P-type and N-type semiconductor regions, simultaneously achieving high withstand voltage and low on-resistance. Existing superjunction diode fabrication mainly employs deep trench etching and filling or multiple epitaxial growth combined with ion implantation processes. These methods have been validated in laboratory settings and in some mass production, providing an important foundation for the development of high-performance power diodes.

[0003] However, existing superjunction diode fabrication processes still have significant drawbacks, making it difficult to achieve precise alignment and doping control between multilayer structures. When using deep trench etching and filling processes, issues such as trench wall damage, uneven filling, and interface defects can lead to charge imbalance in the P / N pillars, affecting the device's breakdown voltage and conduction characteristics. In schemes combining multiple epitaxial growth with ion implantation, if precise alignment control is lacking, it can easily cause vertical displacement and continuity interruptions in the P-type pillars, resulting in distorted electric field distribution and decreased carrier migration efficiency. This problem directly restricts the performance stability and mass production consistency of superjunction diodes in high-voltage, high-frequency applications, preventing the coordinated optimization of reduced conduction losses and improved switching speeds, and making it difficult to meet the urgent needs of new energy and other fields for high-efficiency, high-reliability power devices.

[0004] To address these issues, we provide a method for fabricating a low-loss superjunction soft recovery diode. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides a method for fabricating a low-loss superjunction soft recovery diode. The technical problem this invention aims to solve is: how to solve the problems of charge imbalance, positional shift, and continuity interruption in the fabrication process of existing superjunction diodes by employing multiple epitaxial growth combined with ion implantation processes, along with precise alignment control and high-temperature push-junction annealing.

[0006] This invention relates to a method for fabricating a low-loss superjunction soft recovery diode, comprising:

[0007] S1. Provided Type silicon substrate, for the A pretreated silicon substrate is obtained by pretreatment, and a first N-type epitaxial layer is grown on the pretreated substrate. The doping concentration and thickness of the first N-type epitaxial layer are set according to the target voltage rating.

[0008] S2. A vertically aligned P-type pillar implantation window is formed on the N-type epitaxial layer using photolithography. P-type impurity ion implantation is performed within the P-type pillar implantation window to form a local P-type doped region. The local P-type doped region is activated and annealed to form the initial segment of the P-type pillar.

[0009] S3. After completing the initial segment of the P-type pillar, the cyclic steps are repeated to form a P / N pillar superjunction structure. The P / N pillar superjunction structure is arranged alternately. The cyclic steps include N-type epitaxial layer growth, alignment photolithography to form P-type pillar implantation windows, P-type impurity ion implantation, and activation annealing.

[0010] S4. The P / N column superjunction structure is subjected to high-temperature push-bond annealing to form a continuous P-type column;

[0011] S5. A top N-type epitaxial transition layer is grown on the surface of the continuous P-type pillars, an anode electrode is formed on the surface of the top N-type epitaxial transition layer, and a cathode electrode is formed on the back side of the pretreated substrate to obtain a diode chip structure. The diode chip structure is then packaged to obtain a low-loss superjunction soft recovery diode device.

[0012] The present invention is further configured such that the Doping concentration of silicon substrate The thickness is 300±25μm, and the crystal orientation is <100>. The pretreatment includes organic contamination removal, particulate contamination removal, and natural oxide layer removal. The monolayer thickness of the first N-type epitaxial layer is 5±0.2μm, and the doping concentration is... .

[0013] The present invention is further configured such that the photolithography process employs deep ultraviolet lithography technology, the wavelength of which is <300nm; the P-type impurity ion implantation uses boron ions, and the implantation energy of which is 80keV and the implantation dose is [missing information]. The P-type column injection window is aligned using alignment marks, the vertical alignment deviation is <0.1μm, and the lateral dimension of the P-type column injection window is within the micrometer range.

[0014] The present invention is further configured such that the activation annealing adopts a rapid thermal annealing process, wherein the annealing temperature of the rapid thermal annealing process is 1050℃ and the holding time is 30s.

[0015] The present invention is further configured such that the number of times the cyclic steps are repeated is ≥5 times, and the total thickness of the P / N pillar superjunction structure is ≥30μm.

[0016] The present invention is further configured such that the high-temperature push-bonding annealing treatment is carried out under an inert atmosphere, and the annealing temperature of the high-temperature push-bonding annealing treatment is 1150°C and the holding time is 120 min.

[0017] The present invention is further configured such that the thickness of the top N-type epitaxial transition layer is 1 μm and the doping concentration is [missing information]. The anode electrode is formed of an Al-Cu alloy, and the cathode electrode is formed of a Ti / Ni multilayer metal.

[0018] The present invention is further configured such that the packaging includes fixing the diode chip structure onto a packaging substrate, the cathode electrode forming an electrical connection with the packaging substrate, and the anode electrode being electrically connected to a corresponding external pin via metal bonding wires to obtain the low-loss superjunction soft recovery diode device.

[0019] The beneficial effects of this invention are as follows: This invention, through... The first N-type epitaxial layer was grown on a silicon substrate. Using deep ultraviolet lithography and P-type impurity ion implantation, a P / N pillar superjunction structure was successfully formed, ensuring that the diode has ideal voltage withstand performance and low loss characteristics. Through multiple cycle steps, the high consistency and stability of the P / N structure were ensured, thereby improving the overall performance of the diode.

[0020] The P / N pillar superjunction structure was further optimized using high-temperature push-junction annealing to form continuous P-type pillars, reducing material defects and improving the device's current recovery capability and thermal stability. The growth of the top-layer N-type epitaxial transition layer and the formation of precise electrodes ensured the diode's high conductivity and long-term stable operation. Attached Figure Description

[0021] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below.

[0022] Figure 1 This is a flowchart of the overall method of the present invention.

[0023] Figure 2 This is a flowchart illustrating the fabrication and stacking optimization of the superjunction structure of this invention.

[0024] Figure 3 This is a flowchart of the post-processing and electrode packaging performance optimization process of the present invention.

[0025] Figure 4 This is a schematic diagram of the cross-sectional structure of the device of the present invention. Detailed Implementation

[0026] The technical solutions of the present invention will be described below with reference to the accompanying drawings. The described embodiments are only some embodiments of the present invention, and not all embodiments.

[0027] Example 1

[0028] Please see Figures 1-4 This invention relates to a method for fabricating a low-loss superjunction soft recovery diode, comprising:

[0029] S1. Provided Type silicon substrate, for A pretreated silicon substrate is obtained by preprocessing it, and a first N-type epitaxial layer is grown on the pretreated substrate. The doping concentration and thickness of the first N-type epitaxial layer are set according to the target voltage rating. Doping concentration of silicon substrate The thickness is 300±25μm, the crystal orientation is <100>, and the pretreatment includes organic contamination removal, particulate contamination removal, and natural oxide layer removal. The monolayer thickness of the first N-type epitaxial layer is 5±0.2μm, and the doping concentration is [missing information]. .

[0030] An N-type drift epitaxial layer is epitaxially grown on a pretreated substrate to form... Drift zone The drift region is 100 μm thick. The drift layer serves as an electron transport channel, and the first N-type epitaxial layer is... The initial single layer of the drift layer.

[0031] By precisely controlling the doping concentration and thickness of the N-type epitaxial layer, the diode is ensured to have low energy loss under different voltage conditions, thus improving the overall efficiency.

[0032] S2. Vertically aligned P-type pillar implantation windows are formed on the N-type epitaxial layer using photolithography. P-type impurity ion implantation is performed within these windows to form localized P-type doped regions. These localized P-type doped regions are then activated and annealed to form the initial segment of the P-type pillar. The photolithography process uses deep ultraviolet (DUV) lithography with a wavelength <300 nm. Boron ions are used for P-type impurity ion implantation, with an implantation energy of 80 keV and an implantation dose of [missing value]. The P-type column injection window is aligned using alignment marks, with a vertical alignment deviation of <0.1μm. The lateral dimensions of the P-type column injection window are within the micrometer range. Activation annealing employs a rapid thermal annealing process at a temperature of 1050℃ and a holding time of 30s.

[0033] The P-pillar implantation and activation annealing process optimizes the soft recovery characteristics of the diode, reduces switching losses, and improves the performance stability of the diode in high-speed applications. Deep ultraviolet lithography ensures precise alignment of the P-pillar implantation window with a deviation of less than 0.1 μm, guaranteeing the consistency and reliability of the diode structure and improving equipment stability.

[0034] S3. After completing the initial P-type pillar segment, repeat the cyclic steps to construct a P / N pillar superjunction structure. The P / N pillar superjunction structures are arranged alternately. The cyclic steps include N-type epitaxial layer growth, alignment photolithography to form the P-type pillar implantation window, P-type impurity ion implantation, and activation annealing. The cyclic steps are repeated ≥5 times, and the total thickness of the P / N pillar superjunction structure is ≥30μm.

[0035] By repeatedly performing the process steps, a P / N pillar superjunction structure with a thickness of at least 30 μm is formed, which enhances the scalability of the process and ensures the wide applicability of the diode in different power levels and devices.

[0036] S4. The P / N column superjunction structure was subjected to high-temperature push-bond annealing to form a continuous P-type column. The high-temperature push-bond annealing was carried out in an inert atmosphere, with an annealing temperature of 1150℃ and a holding time of 120min.

[0037] After forming continuous P-type pillars, P-type doping is performed on the top of the continuous P-type pillars. Buffer section and Injection segment, Buffer section and The injection segment is the functional segment at the top of the P-pillar. The buffer section has a depth of 2μm. The injection depth is 2μm. The injection section is used for forward hole injection. The buffer section is used for reverse carrier buffering. Buffer section and The injection section is located in the top region of the P-pillar near the anode side of the superjunction region.

[0038] A continuous P-type pillar is formed by high-temperature push-junction annealing at 1150℃, which ensures the stability and structural integrity of the diode at high operating temperatures and meets the requirements of high-power applications.

[0039] S5. A top-layer N-type epitaxial transition layer is grown on the surface of a continuous P-type pillar. An anode electrode is formed on the surface of the top-layer N-type epitaxial transition layer, and a cathode electrode is formed on the back side of the pretreated substrate to obtain a diode chip structure. The diode chip structure is then packaged to obtain a low-loss superjunction soft recovery diode device. The thickness of the top-layer N-type epitaxial transition layer is 1 μm, and the doping concentration is [missing information]. The anode electrode is formed of an Al-Cu alloy, and the cathode electrode is formed of a Ti / Ni multilayer metal. The packaging includes fixing the diode chip structure onto a packaging substrate, electrically connecting the cathode electrode to the packaging substrate, and electrically connecting the anode electrode to the corresponding external pin via metal bonding wires to obtain a low-loss superjunction soft recovery diode device.

[0040] The anode metal consists of a Ti / Ni contact layer and an Al-Cu dominant layer, with a Ti / Ni thickness of approximately 200 nm and an Al-Cu thickness of approximately 3 μm. The cathode metal layer is a Ti / Ni stack located on the back side of the substrate.

[0041] The diode chip structure, from top to bottom, includes an anode metal layer, a top N-type epitaxial transition layer, and a P / N pillar superjunction structure. Drift layer Silicon substrate and cathode metal layer. Injection segment and The buffer section is located in the superjunction region near the anode side.

[0042] The growth of the top N-type epitaxial transition layer and the formation of electrodes ensure the diode's excellent heat dissipation performance. At the same time, reasonable packaging improves the device's durability and integration, facilitating efficient application in various power electronic systems.

[0043] Example 2

[0044] Please see Figure 2 Based on Example 1, the feasibility of forming a superjunction structure that meets the requirements for structural dimensions and interlayer alignment on the same production line under actual production conditions by implementing the superjunction structure fabrication and cyclic stacking process is verified. The specific implementation method is as follows:

[0045] 1. Data Source Explanation

[0046] This example is derived from a batch of 650V superjunction diode chips produced on a power semiconductor manufacturing line in June 2024.

[0047] A total of 25 6-inch silicon wafers were used in a certain batch. All wafers were fabricated and stacked under the same production line, the same process route, and the same equipment configuration. No equipment switching or process parameter version changes occurred during the key processes.

[0048] The data involved in this embodiment are all derived from the actual production records and online measurement records of the trial production batch, including:

[0049] Wafer incoming material inspection records, epitaxial process batch records, epitaxial layer thickness optical measurement data, wafer resistance test data, photolithography alignment deviation detection records, critical dimension electron microscopic inspection records, ion implantation equipment logs, doping concentration depth distribution detection records, and cross-sectional structure electron microscopic inspection records.

[0050] The optical measurement data for epitaxial layer thickness are the results of routine optical thickness measurements on the production line.

[0051] 2. Substrate pretreatment and preparation of the first N-type epitaxial layer

[0052] Substrate source and measurement basis:

[0053] This batch adopts Type <100> silicon substrate. The substrate's equivalent doping concentration level is not less than... The doping level is determined based on the incoming material inspection report provided by the supplier and serves as the basis for substrate selection in this batch.

[0054] The target wafer thickness is 300±25μm. The incoming material inspection record shows that the measured average thickness of the 25 wafers is 301.6μm, the minimum is 289.8μm, and the maximum is 323.1μm.

[0055] Measured results of surface condition after pretreatment:

[0056] The substrate underwent sequential organic contamination cleaning, particle cleaning, and natural oxide layer removal. After cleaning, surface particle detection was performed on each wafer, with the smallest detectable particle size being 0.12 μm. The detection results showed:

[0057] The median number of particles per tablet was 19, and the 95th percentile was 27.

[0058] Growth and measurement data of the first N-type epitaxial layer:

[0059] The first N-type epitaxial layer was completed in the same epitaxial furnace. The process batch record shows that the target thickness of the epitaxial layer was 5 ± 0.2 μm, and the target doping concentration was [missing information]. .

[0060] After epitaxy was completed, optical measurements of the epitaxial layer thickness and wafer resistance tests were performed on all wafers. The statistical results are as follows:

[0061] The average epitaxial layer thickness is 5.06 μm, with a standard deviation of 0.07 μm. The median value of single-wafer thickness inhomogeneity is 0.18 μm, corresponding to a calculated average equivalent doping concentration of the epitaxial layer. .

[0062] 3. Formation of the injection window for P-type columns and preparation of the initial segment of the P-type column

[0063] Injection window formation and alignment data source:

[0064] Deep ultraviolet lithography was performed on the surface of the first N-type epitaxial layer to form a P-type pillar injection window. After lithography, alignment deviation was checked on randomly selected wafers from the batch, with nine measurement points selected for each wafer. The measurement results show:

[0065] The average horizontal alignment deviation was 0.042 μm, with a 95th percentile of 0.086 μm. The average vertical alignment deviation was 0.045 μm, with a 95th percentile of 0.089 μm.

[0066] The basis for the actual measurement of the horizontal dimension of the injection window:

[0067] The lateral dimensions of the P-type pillar implantation window were measured using an electron microscope. The data for the lateral dimensions of the implantation window were obtained from statistical analysis of multi-point measurements across multiple wafers.

[0068] The designed size is 1.20 μm, the measured average size is 1.18 μm, and the standard deviation is 0.04 μm.

[0069] Measurement records of boron ion implantation and doping distribution:

[0070] According to the ion implantation equipment log, the parameters for this batch of boron ion implantation are: implantation energy 80keV, implantation dose... .

[0071] After implantation, the doping concentration depth distribution of the two wafers was measured. This doping concentration depth distribution measurement is a routine quality control method for the ion implantation process on the production line. The test results showed that the peak boron concentration corresponded to a depth within the range of 0.24-0.28 μm, and the deviations of the integrated dose from the set value were +3.1% and -2.4%, respectively.

[0072] Measured results of doping profile after activation annealing:

[0073] After rapid thermal annealing at 1050℃ for 30 seconds, two wafers were subjected to resistance profile doping detection, which is a routine quality control method for the annealing process on the production line.

[0074] Within the depth range of 0.2–0.8 μm, the measured average value of the main concentration plateau region is: .

[0075] 4. Formation of superjunction structures by cyclic stacking and its results

[0076] Actual implementation of the cyclic stacking process:

[0077] After completing the initial section of the P-type pillar, the following steps are repeated according to the established process route: N-type epitaxial layer growth, photolithography to form the implantation window, boron ion implantation, and rapid thermal annealing.

[0078] The above-mentioned cyclic process was performed 6 times in this batch, and the target thickness of the N-type epitaxial layer was set to 5±0.2μm in each cycle.

[0079] Measured data on the total thickness of the superjunction structure:

[0080] After completing all 6 cycles, representative wafers were selected from the batch, and cross-sectional scanning electron microscopy was performed on 3 wafers, including the center and edge regions of the wafers.

[0081] The test results showed that the total thicknesses of the superjunction structure regions were 30.5 μm, 30.8 μm and 31.2 μm, respectively.

[0082] Alignment and injection parameter adjustment records during the loop:

[0083] During the cycle, the alignment deviation data after each round of photolithography is monitored. When a change in alignment deviation is detected, the alignment parameters of the photolithography equipment are adjusted based on the measured alignment deviation results of the corresponding round, and the relevant adjustment process is recorded in the photolithography equipment process log.

[0084] In subsequent cycles, when adjusting the boron ion implantation dose, the implantation dose is achieved by modifying the process parameter table of the ion implantation equipment. Adjusted to The adjustment process is also recorded in the equipment process log.

[0085] Based on the production records and measurement data of the aforementioned actual trial batches, after completing six cycles of stacking on the same production line, a superjunction structure with a total thickness of not less than 30 μm and an interlayer alignment deviation of less than 0.1 μm was obtained. The results, derived from actual production and testing records, demonstrate that the superjunction structure preparation and stacking process is engineering feasible and process stable under trial conditions.

[0086] The foregoing has only described certain exemplary embodiments of the present invention by way of illustration. Undoubtedly, those skilled in the art can modify the described embodiments in various ways without departing from the spirit and scope of the present invention. Therefore, the foregoing drawings and descriptions are illustrative in nature and should not be construed as limiting the scope of protection of the claims of the present invention.

Claims

1. A method for fabricating a low-loss superjunction soft recovery diode, Includes, characterized in that: S1. Provided Type silicon substrate, for the A pretreated silicon substrate is obtained by pretreatment, and a first N-type epitaxial layer is grown on the pretreated substrate. The doping concentration and thickness of the first N-type epitaxial layer are set according to the target breakdown voltage level. S2. A vertically aligned P-type pillar implantation window is formed on the N-type epitaxial layer using photolithography. P-type impurity ion implantation is performed within the P-type pillar implantation window to form a local P-type doped region. The local P-type doped region is activated and annealed to form the initial segment of the P-type pillar. S3. After completing the initial segment of the P-type pillar, the cyclic steps are repeated to form a P / N pillar superjunction structure. The P / N pillar superjunction structure is arranged alternately. The cyclic steps include N-type epitaxial layer growth, alignment photolithography to form P-type pillar implantation windows, P-type impurity ion implantation, and activation annealing. S4. The P / N column superjunction structure is subjected to high-temperature push-bond annealing to form a continuous P-type column; S5. A top N-type epitaxial transition layer is grown on the surface of the continuous P-type pillars, an anode electrode is formed on the surface of the top N-type epitaxial transition layer, and a cathode electrode is formed on the back side of the pretreated substrate to obtain a diode chip structure. The diode chip structure is then packaged to obtain a low-loss superjunction soft recovery diode device.

2. The method for fabricating a low-loss superjunction soft recovery diode according to claim 1, characterized in that: The Doping concentration of silicon substrate The thickness is 300±25μm, and the crystal orientation is <100>. The pretreatment includes organic contamination removal, particulate contamination removal, and natural oxide layer removal. The monolayer thickness of the first N-type epitaxial layer is 5±0.2μm, and the doping concentration is... .

3. The method for fabricating a low-loss superjunction soft recovery diode according to claim 1, characterized in that: The photolithography process employs deep ultraviolet (DUV) lithography technology with a wavelength <300 nm. The P-type impurity ion implantation uses boron ions, with an implantation energy of 80 keV and an implantation dose of [missing value]. The P-type column injection window is aligned using alignment marks, the vertical alignment deviation is <0.1μm, and the lateral dimension of the P-type column injection window is within the micrometer range.

4. The method for fabricating a low-loss superjunction soft recovery diode according to claim 1, characterized in that: The activation annealing adopts a rapid thermal annealing process, wherein the annealing temperature of the rapid thermal annealing process is 1050℃ and the holding time is 30s.

5. The method for fabricating a low-loss superjunction soft recovery diode according to claim 1, characterized in that: The number of times the cyclic step is repeated is ≥5 times, and the total thickness of the P / N pillar superjunction structure is ≥30μm.

6. The method for fabricating a low-loss superjunction soft recovery diode according to claim 1, characterized in that: The high-temperature push-bonding annealing treatment is carried out under an inert atmosphere, and the annealing temperature is 1150℃ and the holding time is 120min.

7. The method for fabricating a low-loss superjunction soft recovery diode according to claim 1, characterized in that: The thickness of the top-layer N-type epitaxial transition layer is 1 μm, and the doping concentration is [missing information]. The anode electrode is formed of an Al-Cu alloy, and the cathode electrode is formed of a Ti / Ni multilayer metal.

8. The method for fabricating a low-loss superjunction soft recovery diode according to claim 1, characterized in that: The packaging includes fixing the diode chip structure onto a packaging substrate, electrically connecting the cathode electrode to the packaging substrate, and electrically connecting the anode electrode to the corresponding external pin through metal bonding wires to obtain the low-loss superjunction soft recovery diode device.

Images