A low trigger voltage transient voltage suppressor based on base region resistance modulation and a manufacturing method thereof

Abstract

This invention provides a low trigger voltage transient voltage suppressor based on base region resistance modulation and its manufacturing method. The transient voltage suppressor includes at least one transient voltage suppressor unit. The unit includes a first electrode, a second electrode, and a semiconductor structure disposed between them. The semiconductor structure includes a semiconductor substrate, a drift region, a base region, and a trigger structure disposed within the base region. The trigger structure includes a highly doped region of a second conductivity type and two highly doped regions of a first conductivity type located on both sides thereof. The highly doped region of the second conductivity type is electrically connected to the first electrode, and the two highly doped regions of the first conductivity type remain in a floating state. A lateral base region resistance path is formed between the highly doped regions through the base region material. When a transient voltage is applied, the lateral base region resistance path generates a potential difference to trigger the device to conduct. After conduction, the current forms a longitudinal conduction path through the drift region and the semiconductor substrate, achieving low trigger voltage and low dynamic resistance.

Description

Technical Field

[0001] This invention relates to the field of semiconductor protection device technology, and in particular to a low trigger voltage transient voltage suppressor based on base region resistance modulation and its manufacturing method, which is suitable for electrostatic discharge protection of low voltage interfaces (such as USB Type-C). Background Technology

[0002] With the rapid development of consumer electronics, mobile communications, and automotive electronics, the operating voltage of integrated circuits continues to decrease while signal speeds continue to increase. High-speed interfaces such as USB Type-C, Thunderbolt, and HDMI 2.1 have operating voltages on their signal pins as low as 1.8V or even 1.2V, placing more stringent requirements on electrostatic discharge (ESD) protection devices.

[0003] Existing transient voltage suppressors (TVS) typically rely on the avalanche breakdown mechanism of PN junctions to trigger conduction, which has the following shortcomings in low-voltage applications: 1. Trigger voltage is too high, and the protection window is insufficient. Traditional TVS devices typically have trigger voltages above 3V, with some high-voltage devices even reaching 5V~6V. When the operating voltage of the protected circuit drops below 2V, the excessively high trigger voltage prevents the protection device from conducting in time during the initial stage of overvoltage, which can easily cause subsequent sensitive circuits to be subjected to excessively high transient voltages and suffer damage.

[0004] 2. The dynamic resistance is relatively large, limiting the clamping capability. Under surge current, the clamping voltage of traditional TVS devices increases significantly with increasing current. For applications requiring ESD protection at 8kV or 16kV levels as specified in the IEC 61000-4-2 standard, high dynamic resistance can cause the clamping voltage to exceed the tolerance range of low-voltage CMOS devices, reducing the protection effectiveness.

[0005] 3. Existing avalanche-triggered TVS structures have certain limitations in low-voltage applications. Existing TVS devices mostly employ avalanche breakdown or avalanche-related triggering mechanisms, and their triggering characteristics are closely related to the local electric field distribution. In low-voltage applications, a trade-off often needs to be made between trigger voltage, leakage current, and device reliability, increasing the difficulty of device design. Furthermore, multiple avalanche processes may introduce hot carrier effects and interface defect accumulation, thereby affecting the long-term reliability of the device.

[0006] 4. The triggering mechanism is simple, and the degree of adjustment is limited. Although existing transverse TVS structures can achieve planar integration, their triggering behavior still mainly relies on local PN junction breakdown. The trigger voltage is strongly correlated with junction parameters, and the adjustment means are limited, making it difficult to achieve refined design for different interface requirements.

[0007] 5. The trigger path is coupled with the main conduction path, making it difficult to simultaneously achieve both low trigger voltage and high current discharge capability. In existing TVS structures, the trigger region and the main conduction region typically overlap significantly, and the trigger current and the main discharge current share the same conduction path. When a lower trigger voltage is required, the device's high current carrying capacity is often affected; conversely, increasing the conduction capability can easily lead to a deterioration of the trigger characteristics. Therefore, how to effectively separate the triggering function from the main conduction function to simultaneously achieve low trigger voltage and low dynamic resistance remains a pressing technical problem to be solved in this field.

[0008] Therefore, there is an urgent need to provide a new transient voltage suppressor structure that can achieve low trigger voltage while also taking into account low dynamic resistance and high current discharge capability, and improve the adjustability of trigger characteristics and device reliability. Summary of the Invention

[0009] To address at least one technical problem in the prior art, embodiments of the present invention provide a low trigger voltage transient voltage suppressor based on base region resistance modulation and its manufacturing method, which facilitates stable triggering under low voltage conditions while also achieving low dynamic resistance and good reliability. To achieve the above technical objectives, the technical solution adopted by embodiments of the present invention is as follows: In a first aspect, embodiments of the present invention provide a low trigger voltage transient voltage suppressor based on base region resistance modulation, comprising: at least one transient voltage suppressor unit; the transient voltage suppressor unit comprising: A first electrode, a second electrode, and a semiconductor structure disposed between the first electrode and the second electrode; the first electrode is disposed on the front side of the semiconductor structure, and the second electrode is disposed on the back side of the semiconductor structure; the semiconductor structure comprises, from bottom to top: The semiconductor substrate is a semiconductor region of the second conductivity type; the back side of the semiconductor substrate is electrically connected to the second electrode; The drift region is a semiconductor region of the second conductivity type, which is disposed on the semiconductor substrate and continuously in contact with the semiconductor substrate. The base region is a semiconductor region of the first conductivity type, disposed above the drift region; A trigger structure is disposed in the top region of the base region, including a first conductivity type highly doped region, a second conductivity type highly doped region and another first conductivity type highly doped region; An insulating dielectric layer is provided on the semiconductor structure and disposed on the base region; the second conductivity type highly doped region is electrically connected to the first electrode through a contact hole provided in the insulating dielectric layer above it; the insulating dielectric layer above one first conductivity type highly doped region and the other first conductivity type highly doped region is not provided with a contact hole, thereby electrically isolating them from the first electrode and keeping them in a floating state; The first highly doped region of the first conductivity type and the other highly doped region of the first conductivity type are respectively located on both sides of the second highly doped region of the second conductivity type along the first lateral direction; the first highly doped region of the first conductivity type and the second highly doped region of the second conductivity type, as well as the other highly doped region of the first conductivity type and the second highly doped region of the second conductivity type, are respectively laterally spaced through a portion of the base region, and no direct conductive connection is formed between them, so as to form a lateral base region resistance path in the base region; The second conductivity type consists of a highly doped region, a base region, a drift region, and a semiconductor substrate forming a longitudinal conduction path.

[0010] Furthermore, the doping concentration of the drift region is 1x10⁻⁶. 16 cm -3 Up to 5x10 17 cm -3 ; The thickness of the drift region is 0.5 μm to 5 μm.

[0011] Furthermore, the doping concentration of the base region is 1x10⁻⁶. 16 cm -3 Up to 1x10 17 cm -3 Its thickness ranges from 0.2 μm to 1 μm.

[0012] Furthermore, the lateral spacing between the first highly doped region of the first conductivity type and the second highly doped region of the second conductivity type, and / or the lateral spacing between the other highly doped region of the first conductivity type and the second highly doped region of the second conductivity type, is configured to adjust the trigger voltage of the transient voltage suppressor.

[0013] Furthermore, the lateral spacing is between 0.4 μm and 0.7 μm.

[0014] Furthermore, the doping concentrations of the one highly doped region of the first conductivity type, the highly doped region of the second conductivity type, and the other highly doped region of the first conductivity type are all greater than 1 x 10⁻⁶. 19 cm -3 The junction depth is less than the depth of the base region, and the junction depth is 0.05μm to 0.2μm.

[0015] Furthermore, the low trigger voltage transient voltage suppressor based on base region resistance modulation also includes: A trench isolation structure is disposed on both sides of the transient voltage suppressor unit in a first lateral direction and extends in a second lateral direction perpendicular to the first lateral direction; the trench isolation structure penetrates downward from the base region surface to the drift region; There is a gap between the trench isolation structure and the one highly doped region of the first conductivity type and the other highly doped region of the first conductivity type.

[0016] Furthermore, the spacing of the interval regions is greater than the lateral diffusion range of the highly doped region of the first conductivity type.

[0017] Furthermore, the transient voltage suppressor unit is configured as a plurality of units; the plurality of transient voltage suppressor units are arranged in parallel in the first lateral direction to form a first array, and the plurality of transient voltage suppressor units are arranged in parallel in the second lateral direction to form a second array; the first array and the second array together form a two-dimensional array structure; and the plurality of transient voltage suppressor units share a first electrode and a second electrode.

[0018] Secondly, embodiments of the present invention provide a method for manufacturing a low-trigger voltage transient voltage suppressor based on base region resistance modulation, for forming the low-trigger voltage transient voltage suppressor based on base region resistance modulation as described above, characterized by comprising the following steps: Step S10: An N-type drift region is formed on a semiconductor substrate by epitaxial growth or ion implantation; Step S20: A P-type base region is formed on the surface of the drift region by ion implantation and annealing; In step S30, a second conductivity type highly doped region, a first conductivity type highly doped region, and another first conductivity type highly doped region are sequentially formed in the base region through photolithography and ion implantation, and the lateral spacing between the three is precisely controlled. This forms the semiconductor structure of the device; Optionally, in step S40, a trench isolation structure is formed by etching and filling processes; Step S50: Deposit interlayer insulating dielectric layer and etch contact holes; Step S60: Deposit and pattern a metal layer on the front side of the semiconductor structure to form the first electrode; Step S70: After thinning the back side of the semiconductor substrate, a back metal layer is deposited to form the second electrode; Step S30 and step S40 are interchangeable.

[0019] The beneficial effects of the technical solution provided by the embodiments of the present invention are as follows: 1. Low trigger voltage with flexible modulation This invention triggers the parasitic conduction path by causing a local base region potential rise due to a voltage drop in the lateral base region resistance path. Compared to traditional TVS devices that rely on PN junction avalanche breakdown, this invention achieves conduction without relying on a high electric field triggering mechanism, which helps reduce the trigger voltage. By adjusting the lateral spacing between highly doped regions and the base region doping concentration in the trigger structure, the equivalent resistance of the lateral base region resistance path can be modulated, thereby achieving continuous adjustment of the trigger voltage and making it suitable for the protection requirements of different low-voltage interfaces.

[0020] 2. Low dynamic resistance, significantly improved clamping capability. After triggering conduction, the main discharge current travels along the longitudinal conduction path, passing through the highly doped region of the second conductivity type, the base region, the drift region, and the semiconductor substrate, and is finally discharged from the second electrode on the back side. Because the drift region and the semiconductor substrate form a continuous conduction path, and the substrate has low resistivity and a large conduction cross-sectional area, the dynamic resistance of the device is significantly reduced. Under high current surge conditions, the clamping voltage rise is small, effectively improving the protection capability for the protected circuit.

[0021] 3. It does not primarily rely on avalanche breakdown mechanisms, exhibiting superior reliability and controllability. The triggering process of this invention is based on the opening of the parasitic conduction path caused by the modulation of the base region resistance, rather than mainly relying on the avalanche breakdown of the PN junction. This can reduce the local high electric field intensity inside the device, reduce hot carrier injection and interface state degradation, and thus maintain stable electrical characteristics under multiple ESD stresses, significantly improving the long-term reliability of the device.

[0022] 4. The trigger path is separated from the main discharge path, resulting in stronger robustness. In this invention, the trigger current is mainly distributed along the transverse base region resistance path in the base region, while the main discharge current is transmitted along the longitudinal conduction path, achieving spatial separation between the trigger path and the main discharge path. This structure avoids large currents acting directly on the trigger region, thereby reducing local heat accumulation and current congestion effects, and improving the device's resistance to secondary breakdown and overall robustness.

[0023] 5. Supports two-dimensional array expansion, resulting in more uniform current distribution. The triggering structure of the present invention can be formed into a parallel two-dimensional array structure on the layout. This two-dimensional array structure helps to reduce local current density, improve current distribution uniformity, and suppress hot spot effect, thereby improving the surge carrying capacity and reliability of the device.

[0024] 6. Low leakage current, suitable for low-power applications. Since the triggering process of this invention is mainly based on base region resistor modulation, the device maintains a reverse cutoff state within the normal operating voltage range, resulting in low leakage current. This makes it suitable for low-voltage applications with high static power consumption requirements.

[0025] 7. The structure combines lateral control capability with longitudinal conductivity advantage. This invention employs a structural design combining lateral triggering and longitudinal conduction. The lateral structure is used to regulate the triggering characteristics, while the longitudinal structure is used to achieve low-impedance conduction. Compared to traditional single-conduction-path structures, this invention achieves effective synergy between triggering characteristics and conduction performance.

[0026] 8. High process compatibility, suitable for large-scale manufacturing. The device structure of this invention can be implemented based on standard CMOS or BCD process platforms, and the triggering characteristics can be adjusted through layout parameters (such as lateral spacing d) without changing the basic process flow. Therefore, this invention has good manufacturing consistency and scalability, and is suitable for multi-channel array integration and large-scale mass production.

[0027] 9. Optional trench isolation structure for further performance enhancement. By introducing a trench isolation structure that penetrates into the drift region in the base region, the lateral current spread can be effectively limited, and the parasitic coupling between adjacent units can be reduced, thereby further improving the uniformity of current distribution and the overall stability of the device. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of the transient voltage suppressor unit structure in an embodiment of the present invention.

[0029] Figure 2 This is a schematic diagram of the current path during the triggering and conduction process in an embodiment of the present invention.

[0030] Figure 3 This is a schematic diagram of multiple transient voltage suppressor units arranged in parallel in the first lateral direction in an embodiment of the present invention.

[0031] Figure 4 This is a layout of the two-dimensional array structure in an embodiment of the present invention.

[0032] Figure 5 This is a comparison chart of the current-voltage curves of the embodiment of the present invention and a traditional avalanche TVS device.

[0033] Figure 6 This is a schematic graph illustrating the relationship between the device trigger voltage and the lateral spacing of the highly doped region in an embodiment of the present invention. Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0035] In the description of the embodiments of the present invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the present invention. In addition, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0036] In the description of the embodiments of the present invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can also refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in the present invention based on the specific circumstances.

[0037] Furthermore, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0038] In the following embodiments, the first conductivity type is P-type and the second conductivity type is N-type; Example 1; This embodiment proposes a low trigger voltage transient voltage suppressor (hereinafter referred to as the device) based on base region resistance modulation, such as... Figure 1 As shown, it includes: at least one transient voltage suppressor unit; the transient voltage suppressor unit includes: A first electrode 100, a second electrode 600, and a semiconductor structure disposed between the first electrode 100 and the second electrode 600; the first electrode 100 is disposed on the front side of the semiconductor structure, and the second electrode 600 is disposed on the back side of the semiconductor structure; the semiconductor structure constitutes the core functional area of ​​the device; the semiconductor structure includes, from bottom to top: Semiconductor substrate 601 is a semiconductor region of the second conductivity type; the back side of semiconductor substrate 601 is electrically connected to second electrode 600; The drift region 500, a semiconductor region of the second conductivity type, is disposed on and continuously in contact with the semiconductor substrate 601. The drift region 500 and the semiconductor substrate 601 thus form a continuous bulk conduction path, thereby creating a low-impedance conduction path, and current is discharged through the second electrode 600 disposed on the back side of the semiconductor substrate. The doping concentration of the drift region 500 is preferably 1 x 10⁻⁶. 16 cm -3 Up to 5x10 17 cm -3 The drift region 500 serves as the main current discharge channel after the device is turned on. Its doping concentration and thickness can be optimized according to the requirements of conduction resistance and withstand voltage. Its thickness is preferably 0.5μm to 5μm. Furthermore, the thickness of the drift region 500 can be set according to the device's withstand voltage and conduction capability requirements, and the thickness of the drift region 500 is preferably 2μm to 5μm; The base region 300 is a semiconductor region of the first conductivity type, disposed above the drift region 500; its doping concentration is preferably 1x10⁻⁶. 16 cm -3 Up to 1x10 17 cm -3 Its thickness is preferably 0.2 μm to 1 μm; the base region 300 and the drift region 500 form a PN junction; The trigger structure 200 is disposed in the top region of the base region 300, and includes a first conductivity type highly doped region 201, a second conductivity type highly doped region 202 and another first conductivity type highly doped region 203; An insulating dielectric layer 700 is provided on the semiconductor structure and is disposed above the base region 300; the second conductivity type highly doped region 202 is electrically connected to the first electrode 100 through a contact hole provided in the insulating dielectric layer 700 above it; the insulating dielectric layer 700 above one first conductivity type highly doped region 201 and the other first conductivity type highly doped region 203 is not provided with contact holes, thereby electrically isolating them from the first electrode 100 and keeping them in a floating state; The first highly doped region 201 and the other highly doped region 203 of the first conductivity type are used to define the boundary region of the lateral base region resistance path, and form a corresponding lateral base region resistance path with the second highly doped region 202 of the second conductivity type. The first highly doped region 201 and the other highly doped region 203 of the first conductivity type are respectively located on both sides of the second highly doped region 202 along the first lateral direction; in Figure 1In the illustrated embodiment, the left-right direction is the first lateral direction, and the direction perpendicular to the paper plane is the second lateral direction; both the first and second lateral directions are lateral directions; the first highly doped region 201 and the second highly doped region 202, as well as the other highly doped region 203 and the second highly doped region 202, are respectively laterally spaced through a portion of the base region, and no direct conductive connection is formed between them, so as to form a lateral base region resistance path within the base region; Figure 1 In the middle, the lateral base region resistance path includes a first lateral base region resistance path 301 formed by the base region portion between the first conductivity type highly doped region 201 and the second conductivity type highly doped region 202, and a second lateral base region resistance path 302 formed by the base region portion between the other first conductivity type highly doped region 203 and the second conductivity type highly doped region 202. The second conductivity type, consisting of the highly doped region 202, the base region 300, the drift region 500, and the semiconductor substrate 601, forms a vertical conduction path.

[0039] Furthermore, the lateral spacing between the first conductivity type highly doped region 201 and the second conductivity type highly doped region 202, and / or the lateral spacing between the other first conductivity type highly doped region 203 and the second conductivity type highly doped region 202, is configured to adjust the trigger voltage of the transient voltage suppressor.

[0040] Figure 1 The diagram shows the lateral spacing d between the first conductivity type highly doped region 201 and the second conductivity type highly doped region 202.

[0041] Preferably, the lateral spacing is between 0.4 μm and 0.7 μm.

[0042] The equivalent resistance of the lateral base region resistance path is determined by the lateral spacing between the first conductivity type highly doped region and the second conductivity type highly doped region and the base region doping concentration. Therefore, by adjusting the lateral spacing between the first conductivity type highly doped region and the second conductivity type highly doped region and / or adjusting the base region doping concentration, the equivalent resistance of the lateral base region resistance path can be adjusted, thereby achieving continuous adjustment of the trigger voltage.

[0043] Furthermore, the junction depths of the first conductivity type highly doped region 201, the second conductivity type highly doped region 202, and the other first conductivity type highly doped region 203 are all less than the depth of the base region 300, preferably 0.05 μm to 0.2 μm, so that the base region 300 remains laterally continuous.

[0044] Furthermore, the doping concentrations of the first conductivity type highly doped region 201, the second conductivity type highly doped region 202, and the other first conductivity type highly doped region 203 are all greater than 1 x 10⁻⁶. 19 cm -3 .

[0045] The working principle of this application is as follows: When a positive ESD pulse is applied to the first electrode 100 (which is at a positive potential relative to the second electrode 600), the device undergoes the following process, as follows: Figure 2 As shown; Phase 1: Pre-triggering phase; In the first stage, the transverse base region resistance path serves as the trigger path; the trigger current is mainly distributed along the transverse base region resistance path in the base region. In the initial state, the PN junction between the second conductivity type highly doped region 202 and the base region 300 is in the cutoff state, with only a very small leakage current. Since one of the first conductivity type highly doped regions 201 and the other first conductivity type highly doped region 203 are in a floating state, after the charge carriers are injected into the base region 300 by the second conductivity type highly doped region 202, a lateral trigger current is formed in the lateral base region resistance path (the first lateral base region resistance path 301 and the second lateral base region resistance path 302) and a voltage drop is generated, thereby causing a local base region potential rise.

[0046] Phase Two: Triggering the Conduction Phase; In the second stage, the longitudinal conduction path serves as a parasitic conduction path; When the local base region potential rises to a predetermined threshold, the parasitic bipolar transistor corresponding to the parasitic conduction path formed by the second conductivity type highly doped region 202, the base region 300, the drift region 500, and the semiconductor substrate 601 is forward biased and enters the conduction state. At this time, charge carriers are injected from the highly doped region 202 of the second conductivity type and transported to the second electrode 600 through the base region 300, the drift region 500 and the semiconductor substrate 601.

[0047] Phase 3: Low-resistance discharge phase; After the conduction is triggered, the current mainly flows along the longitudinal conduction path, which then serves as the main discharge path. Current flows along the highly doped region 202, the base region 300, the drift region 500, and the semiconductor substrate 601 of the second conductivity type, and flows out from the second electrode 600; Once the ESD stress disappears, the device returns to a high-resistance turn-off state, maintaining only a very low reverse leakage current.

[0048] In the above process, the transverse base region resistance path is used to realize the triggering function, and the longitudinal conduction path is used to carry the main discharge current, thereby achieving decoupling between the triggering path and the main conduction path.

[0049] After the device is triggered to conduct, the main discharge current is transmitted along the longitudinal conduction path. Since the drift region 500 and the semiconductor substrate 601 form a continuous conduction path, and the substrate has a low resistivity and a large conduction cross-sectional area, the dynamic resistance of the device is significantly reduced.

[0050] Furthermore, the low trigger voltage transient voltage suppressor based on base region resistance modulation also includes: The trench isolation structure 400 is disposed on both sides of the transient voltage suppressor unit in a first lateral direction and extends in a second lateral direction perpendicular to the first lateral direction; the trench isolation structure 400 penetrates downward from the surface of the base region 300 to the drift region 500. There is a gap between the trench isolation structure 400 and the one first conductivity type highly doped region 201 and the other first conductivity type highly doped region 203; The trench isolation structure 400 typically includes an isolation trench and a dielectric material or polysilicon filled within the isolation trench; the trench isolation structure 400 can effectively limit lateral current propagation and reduce parasitic coupling between adjacent units.

[0051] Furthermore, the spacing of the interval regions is greater than the lateral diffusion range of the first conductivity type highly doped regions 201 and 203.

[0052] Furthermore, such as Figure 3 and Figure 4 As shown, the transient voltage suppressor unit is configured in multiple ways; the multiple transient voltage suppressor units are arranged in parallel in the first lateral direction to form a first array, and the multiple transient voltage suppressor units are arranged in parallel in the second lateral direction to form a second array; the first array and the second array together form a two-dimensional array structure; and the multiple transient voltage suppressor units share a first electrode 100 and a second electrode 600. Therefore, multiple transient voltage suppressor units can form parallel conduction structures in both the first and second lateral directions, and can be arranged in parallel to form a two-dimensional array structure to achieve current distribution in the two-dimensional direction, thereby further improving the uniformity of current distribution and the robustness of the device.

[0053] Multiple transient voltage suppressor units can be arranged regularly or quasi-regularly in the first lateral direction and the second lateral direction; the multiple transient voltage suppressor units are configured to have basically equal current densities in the on state.

[0054] A comparison of the current-voltage curves of the device proposed in this application with those of avalanche TVS devices is shown below. Figure 5 ;from Figure 5 As can be seen from the data, the device proposed in this application has lower trigger voltage Vt1 and sustaining voltage Vh compared to traditional avalanche TVS devices, making it more suitable for protected circuits with low operating voltages. Furthermore, the current-voltage curve of the device shows that it has lower dynamic resistance, resulting in a smaller clamping voltage rise under high current surge conditions and a significantly improved clamping capability.

[0055] from Figure 6 It can be seen that the lateral spacing d (between the first type of highly doped region 201 and the second type of highly doped region 202, and between the other first type of highly doped region 203 and the second type of highly doped region 202) and the base region doping concentration have an effect on the trigger voltage of the transient voltage suppressor; under the condition of a certain base region doping concentration, the trigger voltage Vt1 increases with the increase of the lateral spacing d; Different base region doping concentrations correspond to different families of trigger voltage curves, further demonstrating that this application can adjust the trigger voltage Vt1 by coordinating two parameters: the lateral spacing d and the base region doping concentration.

[0056] Example 2; This embodiment proposes a method for manufacturing a low trigger voltage transient voltage suppressor based on base region resistance modulation, including the following steps: Step S10: An N-type drift region 500 is formed on the semiconductor substrate 601 by epitaxial growth or ion implantation. Step S20: A P-type base region 300 is formed on the surface of the drift region 500 by ion implantation and annealing; In step S30, a second conductivity type highly doped region 202, a first conductivity type highly doped region 201, and another first conductivity type highly doped region 203 are sequentially formed in the base region 300 through photolithography and ion implantation, and the lateral spacing between the three is precisely controlled. The second conductivity type highly doped region 202 forms corresponding lateral base region resistance paths with the first conductivity type highly doped region 201 and with the other first conductivity type highly doped region 203, respectively; This forms the semiconductor structure of the device; Optionally, in step S40, a trench isolation structure 400 is formed by etching and filling processes; Step S50: Deposit interlayer insulating dielectric layer 700, and etch contact holes; Step S60: Deposit and pattern a metal layer on the front side of the semiconductor structure to form the first electrode 100; In step S70, after thinning the back side of the semiconductor substrate, a back metal layer is deposited to form the second electrode 600.

[0057] The above process flow is highly compatible with existing semiconductor manufacturing processes. The trigger structure and lateral base region resistor path can be adjusted through layout parameters without changing the basic process flow, thereby enabling device designs with different trigger voltage specifications.

[0058] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Various modifications, substitutions, or variations made by those skilled in the art without departing from the spirit and substance of the present invention should fall within the scope of protection defined by the claims of the present invention.

Claims

1. A low trigger voltage transient voltage suppressor based on base region resistance modulation, characterized in that, include: At least one transient voltage suppressor unit; The transient voltage suppressor unit includes: A first electrode (100), a second electrode (600), and a semiconductor structure disposed between the first electrode (100) and the second electrode (600); the first electrode (100) is disposed on the front side of the semiconductor structure, and the second electrode (600) is disposed on the back side of the semiconductor structure; the semiconductor structure includes, from bottom to top: The semiconductor substrate (601) is a semiconductor region of the second conductivity type; the back side of the semiconductor substrate (601) is electrically connected to the second electrode (600); The drift region (500) is a semiconductor region of the second conductivity type, which is disposed on the semiconductor substrate (601) and continuously in contact with the semiconductor substrate (601); The base region (300) is a semiconductor region of the first conductivity type, disposed on the drift region (500); A trigger structure (200) is disposed in the top region of the base region (300), including a first conductivity type highly doped region (201), a second conductivity type highly doped region (202) and another first conductivity type highly doped region (203); An insulating dielectric layer (700) is provided on the semiconductor structure, and the insulating dielectric layer (700) is disposed on the base region (300); the second conductivity type highly doped region (202) is electrically connected to the first electrode (100) through a contact hole provided in the insulating dielectric layer (700) above it; the insulating dielectric layer (700) above one first conductivity type highly doped region (201) and the other first conductivity type highly doped region (203) is not provided with contact holes, thereby electrically isolating them from the first electrode (100) and keeping them in a floating state; The first highly doped region (201) and the other highly doped region (203) are respectively located on both sides of the second highly doped region (202) along the first lateral direction; the first highly doped region (201) and the second highly doped region (202) are laterally spaced through a portion of the base region, and no direct conductive connection is formed between them, so as to form a lateral base region resistance path in the base region; The second conductivity type, consisting of a highly doped region (202), a base region (300), a drift region (500), and a semiconductor substrate (601), forms a vertical conduction path.

2. The low trigger voltage transient voltage suppressor based on base region resistance modulation as described in claim 1, characterized in that, The doping concentration of the drift region (500) is 1x10⁻⁶. 16 cm -3 Up to 5x10 17 cm -3 ; The thickness of the drift region (500) is 0.5 μm to 5 μm.

3. The low trigger voltage transient voltage suppressor based on base region resistance modulation as described in claim 1, characterized in that, The doping concentration of the base region (300) is 1x10⁻⁶. 16 cm -3 Up to 1x10 17 cm -3 Its thickness ranges from 0.2 μm to 1 μm.

4. The low trigger voltage transient voltage suppressor based on base region resistance modulation as described in claim 1, characterized in that, The lateral spacing between the first highly doped region (201) of the first conductivity type and the second highly doped region (202), and / or the lateral spacing between the other highly doped region (203) of the first conductivity type and the second highly doped region (202) of the second conductivity type, is configured to adjust the trigger voltage of the transient voltage suppressor.

5. The low trigger voltage transient voltage suppressor based on base region resistance modulation as described in claim 4, characterized in that, The lateral spacing is between 0.4 μm and 0.7 μm.

6. The low trigger voltage transient voltage suppressor based on base region resistance modulation as described in claim 1, characterized in that, The doping concentrations of the first conductivity type highly doped region (201), the second conductivity type highly doped region (202), and the other first conductivity type highly doped region (203) are all greater than 1 x 10⁻⁶. 19 cm -3 The junction depths are all less than the depth of the base region (300), and the junction depths are all between 0.05 μm and 0.2 μm.

7. The low trigger voltage transient voltage suppressor based on base region resistance modulation as described in claim 1, characterized in that, The low trigger voltage transient voltage suppressor based on base region resistance modulation further includes: A trench isolation structure (400) is disposed on both sides of the transient voltage suppressor unit in a first lateral direction and extends in a second lateral direction perpendicular to the first lateral direction; the trench isolation structure (400) penetrates downward from the surface of the base region (300) to the drift region (500); There is a gap between the trench isolation structure (400) and the one first conductivity type highly doped region (201) and the other first conductivity type highly doped region (203).

8. The low trigger voltage transient voltage suppressor based on base region resistance modulation as described in claim 7, characterized in that, The spacing of the interval regions is greater than the lateral diffusion range of the first conductivity type highly doped region (201, 203).

9. The low trigger voltage transient voltage suppressor based on base region resistance modulation as described in any one of claims 1 to 8, characterized in that, The transient voltage suppressor unit is configured in multiple ways; the multiple transient voltage suppressor units are arranged in parallel in the first lateral direction to form a first array, and the multiple transient voltage suppressor units are arranged in parallel in the second lateral direction to form a second array; the first array and the second array together form a two-dimensional array structure; and the multiple transient voltage suppressor units share a first electrode (100) and a second electrode (600).

10. A method for manufacturing a low trigger voltage transient voltage suppressor based on base region resistance modulation, used to form a low trigger voltage transient voltage suppressor based on base region resistance modulation as described in any one of claims 7 to 9, characterized in that, Includes the following steps: Step S10: An N-type drift region (500) is formed on a semiconductor substrate (601) by epitaxial growth or ion implantation; Step S20: A P-type base region (300) is formed on the surface of the drift region (500) by ion implantation and annealing; In step S30, a second conductivity type highly doped region (202), a first conductivity type highly doped region (201) and another first conductivity type highly doped region (203) are sequentially formed in the base region (300) through photolithography and ion implantation, and the lateral spacing between the three is precisely controlled. This forms the semiconductor structure of the device; Step S40: A trench isolation structure (400) is formed through etching and filling processes; Step S50: Deposit interlayer insulating dielectric layer (700), etch contact holes; Step S60: Deposit and pattern a metal layer on the front side of the semiconductor structure to form the first electrode (100); Step S70: After thinning the back side of the semiconductor substrate, a back metal layer is deposited to form the second electrode (600); Step S30 and step S40 are interchangeable.

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