Parasitic zener diode device and method of manufacturing the same

Abstract

The application discloses a kind of parasitic zener diode devices and its manufacturing method, the parasitic zener diode device, comprising: P well formed in the two sides of active region;N well formed between P well;P type body region formed in N well;N type heavily doped region formed in P type body region;Poly-silicon is formed on the P well of the two sides of N type heavily doped region;P type heavily doped region is formed in the P well outside poly-silicon;Wherein, P type heavily doped region and P type body region injection are electrically connected by P well.The application effectively improves the breakdown voltage of parasitic zener diode under the premise of not increasing plate-making process, meets the actual use requirement of circuit.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and in particular to a parasitic Zener diode device and its manufacturing method. Background Technology

[0002] Zener diodes are semiconductor devices designed using the reverse breakdown characteristics of a PN junction. Their core function is to allow current to flow when the reverse voltage reaches the breakdown voltage, while maintaining a relatively constant voltage across them. Therefore, they are widely used in voltage regulation circuits. The PN junction of a Zener diode is fabricated using a heavily doped process, resulting in a thin depletion layer that enables breakdown at relatively low reverse voltages.

[0003] There is a parasitic Zener diode device in the prior art, see reference. Figure 1 As shown, one end of the device is an N-type heavily doped region, and the other end is a P-type body region. The P-type body region is led out from the surface P-type heavily doped region through a P-well. The high concentration of the P-type body region allows for a lower breakdown voltage. However, in practical applications, the actual breakdown voltage of this parasitic Zener diode is 0.5~2V lower than expected, failing to meet the breakdown voltage requirements of some circuits. Currently, there is no effective solution in the existing technology to improve the breakdown voltage of this type of parasitic Zener diode without increasing the fabrication process. Summary of the Invention

[0004] The summary of this invention introduces a series of simplified concepts, all of which are simplifications of existing technologies in the field, and will be further explained in detail in the detailed description section. This summary is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0005] In view of the defect that the breakdown voltage of existing parasitic Zener diode devices is lower than expected (0.5V~2V), the technical problem to be solved by the present invention is to provide a parasitic Zener diode device and its manufacturing method that can effectively improve the breakdown voltage of parasitic Zener diodes without increasing the board-making process and meet the actual use requirements of circuits.

[0006] To solve the above-mentioned technical problems, the parasitic Zener diode device provided by the present invention is characterized by comprising: a P-well 101, an N-well 102, polysilicon 103, a P-type body region 104, an N-type heavily doped region 105, and a P-type heavily doped region 106. P-wells 101 are formed on both sides of the active region; N-well 102 is formed between P-wells 101; P-type body region 104 formed in N-well 102; An N-type heavily doped region 105 is formed in the P-type body region 104; Polycrystalline silicon 103 is formed on P-wells 101 on both sides of the N-type heavily doped region 105; A heavily doped P-type region 106 is formed in the P-well 101 outside the polysilicon 103; The P-type heavily doped region 106 and the P-type body region implantation 104 are electrically connected through the P-well 101.

[0007] Preferably, the parasitic Zener diode device is further improved in that the N-type impurities in the N-well 102 and the P-type impurities in the P-type body region 104 compensate each other, thereby reducing the effective net doping concentration in the P-type body region 104.

[0008] Preferably, in a further improvement of the parasitic Zener diode device, the N-type heavily doped region 105 and the P-type body region 104 form a PN junction, constituting the reverse breakdown region of the Zener diode.

[0009] Preferably, in a further improvement of the parasitic Zener diode device, the heavily doped P-type region 106 is a high-concentration P-type doped region, serving as an external lead-out terminal of the P-type body region 104.

[0010] To address the aforementioned technical problems, this invention provides a method for manufacturing a parasitic Zener diode device, comprising the following steps: Step 1: Selectively implant P-type impurities into the active region to form P-well 101. The P-well 101 is formed only in the two sides of the device structure. At the same time, selectively implant N-type impurities into a preset area of ​​the P-type body region of the active region to form N-well 102. Step 2: Polysilicon 103 is formed by depositing polysilicon and then photolithography and etching. Step 3: Using polysilicon 103 as a mask, self-aligned implantation of P-type body region 104 is performed so that P-type body region 104 covers the upper part of the region where N-well 102 is located. Step 4: An N-type heavily doped region 105 is formed on the upper part of the P-type body region 104 by ion implantation, and a P-type heavily doped region 106 is formed in the P-well 101 outside the polysilicon 103, thus completing the device fabrication.

[0011] Preferably, in a further improved method for manufacturing parasitic Zener diode devices, in step 1, the injection depth and impurity concentration of the N-well 102 are determined according to the design parameters of the P-type body region 104, thereby achieving effective impurity compensation for the P-type body region 104.

[0012] Preferably, in a further improved method for manufacturing parasitic Zener diode devices, in step 3, the P-type impurities in the P-type body region 104 and the N-type impurities in the N-well 102 compensate for each other, thereby reducing the effective net doping concentration in the P-type body region 104.

[0013] Preferably, in a further improved method for manufacturing parasitic Zener diode devices, in step 4, the N-type heavily doped region 105 forms one end of the device and forms a PN junction with the P-type body region 104.

[0014] The core working principle of this invention is to reduce the effective net doping concentration of the P-type body region through a dual process of N-well compensation and P-well implantation removal in the P-type body region. Based on the breakdown voltage characteristics of Zener diodes, reducing the net doping concentration of the P-type body region increases the depletion layer thickness of the PN junction, thereby improving the reverse breakdown voltage of the device. Furthermore, the entire process does not require additional fabrication steps and can be completed using existing semiconductor manufacturing processes.

[0015] Based on the technical solution and working principle of the present invention, the present invention can achieve at least the following technical effects compared with the prior art; (1) Existing technologies only achieve low breakdown voltage through high concentration of P-type body region, without means to control the net doping concentration of P-type body region, and cannot improve breakdown voltage without changing the pattern.

[0016] This invention utilizes existing ion implantation processes to control the net doping concentration through N-well compensation and removal of local P-well implantation. Without requiring additional fabrication steps, it precisely increases the breakdown voltage to the expected value, meeting circuit requirements. Effectively improving the breakdown voltage of parasitic Zener diodes by 0.5~2V without adding fabrication steps, it overcomes the deficiency of low breakdown voltage in existing devices.

[0017] (2) The existing parasitic Zener diode structure is a combination of a single P-well + P-type body region + N-type heavily doped region, without the design and layout of an N-well.

[0018] This invention only adds N-wells to the P-type body region of the existing structure and adjusts the layout of the P-wells. It does not change the core processes and equipment requirements of existing technologies, is highly compatible with existing manufacturing processes, and requires no additional investment in equipment and process development costs. The device structure is rationally designed, has strong process compatibility, and can be directly integrated into existing semiconductor device manufacturing processes.

[0019] (3) Existing technologies cannot precisely control the net doping concentration of the P-type body region, resulting in deviations in the device breakdown voltage.

[0020] This invention achieves precise control of the net doping concentration in the P-type body region through a dual approach: the impurity compensation effect of N-well injection combined with the removal of the superposition effect of local P-well injection. This stabilizes the device breakdown voltage at the expected value, improves the performance consistency of the device, and achieves high breakdown voltage stability.

[0021] (4) In the prior art, the high doping of the P-type body region leads to an excessively thin depletion layer, resulting in relatively large voltage fluctuations during reverse breakdown.

[0022] By reducing the net doping concentration in the P-type body region, the thickness of the PN junction depletion layer increases, resulting in stronger voltage retention capability during reverse breakdown and superior voltage regulation characteristics, making it suitable for more demanding voltage regulation circuit scenarios. Attached Figure Description

[0023] The accompanying drawings are intended to illustrate the general characteristics of the methods, structures, and / or materials used in specific exemplary embodiments of the invention, supplementing the description in the specification. However, the drawings are schematic diagrams not drawn to scale and may not accurately reflect the precise structural or performance characteristics of any of the given embodiments. The drawings should not be construed as limiting or restricting the range of numerical values ​​or properties covered by exemplary embodiments of the invention. The invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0024] Figure 1 This is a schematic diagram of the existing technology structure.

[0025] Figure 2 This is a schematic diagram of the overall structure of the present invention.

[0026] Figure 3 This is a schematic diagram of the intermediate structure of the manufacturing method of the present invention. Figure 1 .

[0027] Figure 4 This is a schematic diagram of the intermediate structure of the manufacturing method of the present invention. Figure 2 .

[0028] Figure 5 This is a schematic diagram of the intermediate structure of the manufacturing method of the present invention. Figure 3 .

[0029] Figure 6 This is a schematic diagram of the intermediate structure of the manufacturing method of the present invention. Figure 4 .

[0030] Explanation of reference numerals in the attached figures: P-trap 101; N-well 102; Polycrystalline silicon 103; P-type body region 104; 105 N-type heavily doped region; P-type heavily doped region 106. Detailed Implementation

[0031] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can fully understand other advantages and technical effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through different specific embodiments, and various details in this specification can also be applied based on different viewpoints, with various modifications or changes made without departing from the overall design concept of the invention. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. The following exemplary embodiments of the present invention can be implemented in many different forms and should not be construed as being limited to the specific embodiments set forth herein. It should be understood that these embodiments are provided to make the disclosure of the present invention thorough and complete, and to fully convey the technical solutions of these exemplary embodiments to those skilled in the art. It should be understood that when an element is referred to as "connected" or "combined" to another element, the element can be directly connected or combined to the other element, or there may be intermediate elements. The difference is that when an element is referred to as "directly connected" or "directly combined" to another element, there are no intermediate elements. Throughout the drawings, the same reference numerals always denote the same elements. Example 1

[0032] The parasitic Zener diode device in this embodiment is applied to a semiconductor voltage regulator circuit, and its structure is as follows: Figure 2 As shown, it includes: P-well 101, N-well 102, polysilicon 103, P-type body region 104, N-type heavily doped region 105 and P-type heavily doped region 106; P-wells 101 are formed on both sides of the active region. The P-wells 101 are semiconductor regions formed by P-type impurity ion implantation. They are only distributed on both sides of the device structure. No P-wells 101 are distributed in the core region of the P-type body region 104 to avoid the superposition implantation of P-type impurities. An N-well 102 is formed between P-wells 101. The N-well 102 is a semiconductor region formed by N-type impurity ion implantation. It is precisely implanted into the core region of the P-type body region 104. The impurity concentration of the N-well 102 is matched with the partial impurity concentration of the P-type body region 104 to achieve impurity compensation for the P-type body region 104. A P-type body region 104 is formed in the N-well 102. The P-type body region 104 is a P-type doped region formed by self-aligned ion implantation. It is one end of the device and covers the area where the N-well 102 is located. It is electrically connected to the heavily doped P-type region 106 on the surface through the P-wells 101 on both sides. An N-type heavily doped region 105 is formed in the P-type body region 104; Polysilicon 103 is formed on P-wells 101 on both sides of the heavily doped N-type region 105. The heavily doped N-type region 105 is a high-concentration N-type doped region formed by ion implantation. It is the other end of the device and forms a PN junction with the P-type body region 104, constituting the core breakdown region of the Zener diode. The polysilicon 103 is a semiconductor structure formed by deposition and photolithography. It is located on both sides above the device structure and serves as a self-aligned mask for the subsequent P-type body region 104. A heavily doped P-type region 106 is formed in the P-well 101 outside the polysilicon 103. The heavily doped P-type region 106 is a high-concentration P-type doped region formed by ion implantation. It is located on the surface of the P-well 101 and serves as the lead-out terminal of the P-type body region 104 to realize the electrical connection between the device and the external circuit.

[0033] In this embodiment, the ion implantation process of each doped region adopts conventional ion implantation equipment and process parameters in existing semiconductor manufacturing, without the need for additional board fabrication steps. The position and size of each region are adjusted according to the actual circuit design requirements to ensure that the N-well 102 is completely located within the P-type body region 104, and the P-well 101 is retained on both sides of the device. Example 2

[0034] This embodiment provides a method for manufacturing the device structure of Embodiment 1, which relies on existing semiconductor device manufacturing processes and does not require additional pattern making steps. The method includes the following steps: Step 1: Select the active region of the semiconductor substrate as the device fabrication area. Using ion implantation, selectively implant P-type impurities (such as boron) into the active region to form P-wells 101. During implantation, the photolithography mask is used to control the formation of P-wells 101 only on both sides of the device structure; no P-type impurities are implanted in the predetermined core region of the P-type body region. Simultaneously, within the predetermined core region of the P-type body region in the active region, selectively implant N-type impurities (such as phosphorus) to form N-wells 102. The implantation depth and impurity concentration of N-wells 102 are determined according to the design parameters of the P-type body region to ensure effective impurity compensation can be achieved subsequently. (Refer to...) Figure 3 As shown; Step 2: On the surface of the active region after the implantation of P-well 101 and N-well 102, polysilicon material is deposited using chemical vapor deposition (CVD) to a thickness that is typical for existing semiconductor processes. Subsequently, the polysilicon material is patterned using photolithography and etching processes to form polysilicon 103 located on both sides above the device structure. Polysilicon 103 serves as a mask for subsequent self-aligned implantation. Figure 4 As shown; Step 3: Using polysilicon 103 as a self-aligned mask, an ion implantation process is employed to create a P-type body region 104. P-type impurities are implanted into the active region between polysilicon 103, and this region covers the N-well 102 formed in Step 1. This allows the N-type impurities in the N-well 102 and the P-type impurities in the P-type body region 104 to compensate for each other, reducing the net P-type doping concentration in this region. (Refer to...) Figure 5 As shown; Step 4: Using ion implantation, a high concentration of N-type impurities is implanted into one end region of the device to form a heavily N-type doped region 105, which forms a PN junction with the P-type body region 104; a high concentration of P-type impurities is implanted into the surfaces of the P-wells 101 on both sides of the device to form heavily P-type doped regions 106, thus completing the fabrication of the entire parasitic Zener diode device. (Refer to...) Figure 6 As shown.

[0035] In this embodiment, all process steps adopt conventional processes and equipment in existing semiconductor manufacturing, without adding any additional board-making process. The resulting parasitic Zener diode device has a breakdown voltage that is 0.5~2V higher than that of existing devices, which just makes up for the deficiency of low breakdown voltage of existing devices, and the device has better voltage regulation characteristics.

[0036] Optionally, those skilled in the art can adjust the impurity implantation concentration and implantation depth of the N-well 102 according to the breakdown voltage requirements of the actual circuit, thereby achieving different degrees of control over the net doping concentration of the P-type body region 104, and thus obtaining parasitic Zener diode devices with different breakdown voltages.

[0037] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It will also be understood that, unless explicitly defined herein, terms such as those defined in a general dictionary shall be interpreted as having the meaning consistent with their meaning in the relevant field context, and not as having an idealized or overly formal meaning.

[0038] The present invention has been described in detail above through specific embodiments and examples, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A parasitic Zener diode device, characterized in that, include: P-well (101), N-well (102), polysilicon (103), P-type body region (104), N-type heavily doped region (105) and P-type heavily doped region (106); P-wells (101) are formed on both sides of the active region. N-wells (102) are formed between P-wells (101); P-type body region (104) formed in N-well (102); N-type heavily doped region (105) formed in P-type body region (104); Polycrystalline silicon (103) is formed on the P-wells (101) on both sides of the N-type heavily doped region (105). A heavily doped P-type region (106) is formed in the P-well (101) outside the polysilicon (103). The P-type heavily doped region (106) and the P-type body region implantation (104) are electrically connected through the P-well (101).

2. The parasitic Zener diode device according to claim 1, characterized in that: The N-type impurities in the N-well (102) and the P-type impurities in the P-type body region (104) compensate each other, reducing the effective net doping concentration in the P-type body region (104).

3. The parasitic Zener diode device according to claim 1, characterized in that: The N-type heavily doped region (105) and the P-type body region (104) form a PN junction, constituting the reverse breakdown region of the Zener diode.

4. The parasitic Zener diode device according to claim 1, characterized in that, The heavily doped P-type region (106) is a high-concentration P-type doped region, serving as the external lead-out of the P-type body region (104).

5. A method for manufacturing a parasitic Zener diode device, characterized in that, Includes the following steps: Step 1: Selectively implant P-type impurities into the active region to form a P-well (101). The P-well (101) is formed only in the two sides of the device structure. At the same time, N-type impurities are selectively implanted into a preset area of ​​the P-type body region of the active region to form an N-well (102). Step 2: Polysilicon is deposited and then photolithographically and etched to form polysilicon (103). Step 3: Using polysilicon (103) as a mask, self-aligned implantation is performed on the P-type body region (104) so ​​that the P-type body region (104) covers the upper part of the region where the N-well (102) is located; Step 4: An N-type heavily doped region (105) is formed on the upper part of the P-type body region (104) by ion implantation, and a P-type heavily doped region (106) is formed in the P-well (101) outside the polysilicon (103), thus completing the device fabrication.

6. The method for manufacturing a parasitic Zener diode device according to claim 5, characterized in that: In step 1, the injection depth and impurity concentration of the N-well (102) are determined according to the design parameters of the P-type body region (104) to achieve effective impurity compensation for the P-type body region (104).

7. The method for manufacturing a parasitic Zener diode device according to claim 5, characterized in that: In step 3, the P-type impurities in the P-type body region (104) and the N-type impurities in the N-well (102) compensate each other, reducing the effective net doping concentration in the P-type body region (104).

8. The method for manufacturing a parasitic Zener diode device according to claim 5, characterized in that: In step 4, the N-type heavily doped region (105) forms one end of the device and forms a PN junction with the P-type body region (104).

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