A drift step recovery diode with a hybrid anode structure

Abstract

The application belongs to the technical field of semiconductor, and particularly provides a drift step recovery diode with a mixed anode structure, which is used to solve the problems of high manufacturing difficulty and high manufacturing cost caused by the super junction structure in the existing drift step recovery diode. In the anode structure, an N-type anode region 8 is introduced, which, together with a first P-type lightly doped layer 10 and an N-type drift region 4, forms a parasitic NPN transistor. Meanwhile, between the N-type anode region 8 and a P-type anode region 11, a Schottky contact diode is formed by the anode metal 1 and the first P-type lightly doped region 10. The first P-type lightly doped region 10, a second P-type lightly doped region 5 and the N-type drift region 4 constitute a junction field effect transistor. Through the NPN transistor, the junction field effect transistor and the Schottky contact diode, the drift step recovery diode is optimized in coordination, and the pulse performance of the drift step recovery diode is significantly improved without using the super junction structure.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology and relates to semiconductor pulse switching devices, specifically providing a drift step recovery diode (DSRD) with a hybrid anode structure. Background Technology

[0002] As a core component of Ultra Wide Band (UWB) systems, UWB pulse signal generators are used to generate extremely short non-sinusoidal pulse signals in the nanosecond or sub-nanosecond range, serving as the information carrier and time-domain transmission basis for carrier-free communication, high-precision positioning and ranging. UWB pulse signal generators convert continuous or low-speed excitation signals into extremely short non-sinusoidal pulse signals in the nanosecond or sub-nanosecond range using semiconductor pulse switches. Drift step recovery diodes (DSRDs) have become one of the mainstream semiconductor pulse switches due to their excellent ultra-fast recovery characteristics.

[0003] Currently, the main optimization method for the pulse output characteristics of drift step recovery diodes (DSRDs) is to optimize the withstand voltage layer structure to accelerate the extraction of carriers in the drift region; such as... Figure 2 As shown, the optimization of the withstand voltage layer structure is mainly achieved through a superjunction structure, which introduces P-type pillars into the N-type drift region, forming a superjunction structure based on the alternating N-type / P-type pillar structure. However, this superjunction structure has extremely high charge requirements for the N-type / P-type pillars, making it extremely difficult to manufacture. It also leads to a significant increase in the drift region thickness of the high-voltage DSRD, drastically increasing the manufacturing difficulty and cost of the DSRD. To address this problem, this invention proposes a drift step recovery diode with a hybrid anode structure. Summary of the Invention

[0004] The purpose of this invention is to provide a drift step recovery diode (DSRD) with a hybrid anode structure to solve the problems of high manufacturing difficulty and high manufacturing cost caused by the superjunction structure in existing drift step recovery diodes, and to significantly improve the pulse performance of the drift step recovery diode without using the superjunction structure.

[0005] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0006] A drift step recovery diode with a hybrid anode structure includes: a cathode structure, a voltage-resistant layer structure, a hybrid anode structure, a trench structure, and a charge storage structure, wherein the voltage-resistant layer structure is located on the cathode structure, the charge storage structure and the trench structure are located on the voltage-resistant layer structure, and the hybrid anode structure is located within the charge storage structure.

[0007] The pressure-resistant layer structure is an N-type drift region 4;

[0008] The charge storage structure is a first P-type lightly doped region 10;

[0009] The hybrid anode structure includes: an N-type anode region 8, a P-type anode region 11, and an anode metal 9; the N-type anode region and the P-type anode region are located on opposite sides of the surface of the first P-type lightly doped region, and both form ohmic contacts with the anode metal on the upper surface; at the same time, the anode metal forms a Schottky contact with the first P-type lightly doped region between the N-type anode region and the P-type anode region.

[0010] The trench structure includes: a passivation layer 7, an insulating medium 6, and a second P-type lightly doped region 5; the trench structure is located on one side of the N-type anode region in the hybrid anode structure and extends into the N-type drift region; the second P-type lightly doped region is located at the bottom of the trench, the passivation layer is located on the trench wall, and the insulating medium is filled in the trench; furthermore, the anode metal extends along the edge of the trench structure towards the bottom of the trench and forms an ohmic contact with the second P-type lightly doped region.

[0011] Furthermore, the cathode structure includes: cathode metal 1, N-type substrate 2, and N-type field cutoff layer 3. The N-type field cutoff layer 3 is located on the lower surface of the N-type drift region 4, the N-type substrate 2 is located on the lower surface of the N-type field cutoff layer 3, and the cathode metal 1 is located on the lower surface of the N-type substrate 2.

[0012] Furthermore, the N-type anode region, together with the first P-type lightly doped layer and the N-type drift region, forms a parasitic NPN transistor.

[0013] Furthermore, the first P-type lightly doped region 10, the second P-type lightly doped region 5, and the N-type drift region 4 constitute a junction field-effect transistor.

[0014] Furthermore, the anode metal forms a Schottky contact diode with the first P-type lightly doped region.

[0015] Furthermore, the passivation layer is made of silicon dioxide, and the insulating medium is made of polyimide.

[0016] Based on the above technical solution, the beneficial effects of the present invention are as follows:

[0017] This invention provides a drift step recovery diode (DSRD) with a hybrid anode structure. A composite anode structure consisting of an N-type anode region, a second lightly doped P-type region, and a Schottky contact is introduced on the anode side of the DSRD device. Based on this composite anode structure, the carrier injection efficiency on the anode side is effectively controlled through the synergistic effect of the P-type and N-type anode regions. Specifically, the P-type anode region can inject holes into the N-drift region, forming conductivity modulation and reducing the equivalent on-resistance of the drift region. Meanwhile, the N-type anode region can provide an electron compensation channel to a certain extent, suppressing the accumulation of excessive holes near the anode and in the drift region. Therefore, this invention can ensure both forward conduction current and drift region conductivity modulation while avoiding the problems of excessive charge storage and long reverse recovery time in traditional structures.

[0018] Meanwhile, a JFET structure is formed by using a second lightly doped P-type region, an N-type drift region, and a first lightly doped P-type region. This prevents the N-type anode region from directly forming an uncontrolled anode short-circuit path. When the device is forward-biased, the current flowing through the anode side into the N-type drift region is modulated by the depletion layer of the lightly doped P-type region. Based on this JFET structure, the carrier concentration in the N-type drift region can be limited and shaped by the lightly doped P-type region during the forward pumping phase. On the one hand, the lightly doped P-type region can provide the necessary hole injection to modulate the conductivity of the N-type drift region, thereby reducing the forward voltage drop of the device. On the other hand, the clamping effect of the JFET structure can suppress excessive carrier injection and avoid storing too many minority carriers in the drift region. Ultimately, this invention can reduce the amount of stored charge that needs to be extracted during the reverse recovery phase while ensuring forward conduction capability.

[0019] Furthermore, the first P-type lightly doped region forms a Schottky contact with the anode, which allows the carrier injection and base potential in the first P-type lightly doped region to be modulated by the Schottky barrier. This reduces the base region stored charge and base region driving capability of the anti-parallel parasitic NPN transistor composed of the N-type anode region, the first P-type lightly doped region, and the N-type drift region, accelerates the expansion of the space charge region in the drift region, and shortens the transition time from the low-resistance on state to the high-resistance off state. Ultimately, this invention has the advantages of fast turn-off, high dV / dt, low reverse recovery loss, and high pulse efficiency. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the cell structure of the drift step recovery diode with a hybrid anode structure in this invention.

[0021] Figure 2 This is the equivalent circuit diagram of the drift step recovery diode with a hybrid anode structure in this invention.

[0022] Figure 3This is a mapping diagram of the cell structure and equivalent circuit of the drift step recovery diode with a hybrid anode structure in this invention.

[0023] Figure 4 This is a schematic diagram of the cell structure of a conventional drift step recovery diode in the prior art.

[0024] Figure 5 This is a schematic diagram of the cell structure of a fully superjunction drift step recovery diode in the prior art.

[0025] Figure 6 This is a schematic diagram of the cell structure of a drift step recovery diode with an anode short-circuit structure in the prior art.

[0026] Figure 7 This is a comparison diagram of the carrier distribution of a drift step recovery diode with a hybrid anode structure in an embodiment of the present invention and a conventional drift step recovery diode in a comparative example under forward injection conditions.

[0027] Figure 8 This is a comparison chart of the pulse performance of a drift step recovery diode with a hybrid anode structure in an embodiment of the present invention and a conventional drift step recovery diode in a comparative example.

[0028] In the above figures: 1. Cathode metal, 2. N-type substrate, 3. N-type field cutoff layer, 4. N-type drift region, 5. Second P-type lightly doped region, 6. Insulating medium, 7. Passivation layer, 8. N-type anode region, 9. Anode metal, 10. First P-type lightly doped region, 11. P-type anode region. Detailed Implementation

[0029] To make the objectives, technical solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0030] This embodiment provides a drift step recovery diode (DSRD) with a hybrid anode structure, whose cell structure is as follows: Figure 1 As shown, it specifically includes: a cathode structure, a pressure-resistant layer structure, a hybrid anode structure, a trench structure, and a charge storage structure. The pressure-resistant layer structure is located on top of the cathode structure, the charge storage structure and the trench structure are located on top of the pressure-resistant layer structure, and the hybrid anode structure is located within the charge storage structure.

[0031] Furthermore, the pressure-resistant layer structure is an N-type drift region 4 (N-Drift).

[0032] Furthermore, the charge storage structure is a first P-type lightly doped region 10 (P0).

[0033] Furthermore, the hybrid anode structure includes: an N-type anode region 8 (N +), P-type anode region 11 (P + The N-type anode region 8 and the P-type anode region 11 are located on opposite sides of the surface of the first P-type lightly doped region 10, and both form ohmic contacts with the anode metal 9 on the upper surface. At the same time, the anode metal 9 forms a Schottky contact with the first P-type lightly doped region 10 between the N-type anode region 8 and the P-type anode region 11. The lead-out terminal on the upper surface of the anode metal 9 is the anode of the drift step recovery diode.

[0034] Furthermore, the trench structure includes: a silicon dioxide passivation layer 7, a polyimide insulating medium 6, and a second P-type lightly doped region 5; the trench structure is located on one side of the N-type anode region 8 in the hybrid anode structure and extends into the N-type drift region 4; the second P-type lightly doped region 5 is located at the bottom of the trench, the silicon dioxide passivation layer 7 is located on the trench wall, and the polyimide insulating medium 6 is filled in the trench; and the anode metal 9 extends along the edge of the trench structure towards the bottom of the trench and forms an ohmic contact with the second P-type lightly doped region 5.

[0035] Furthermore, the cathode structure includes: cathode metal 1, N-type substrate 2 (N-sub), and N-type field cutoff layer 3 (N-FS); the N-type field cutoff layer 3 is located on the lower surface of the N-type drift region 4, the N-type substrate 2 is located on the lower surface of the N-type field cutoff layer 3, the cathode metal 1 is located on the lower surface of the N-type substrate 2, and the lead-out end of the lower surface of the cathode metal 1 is the cathode of the drift step recovery diode.

[0036] In terms of working principle:

[0037] like Figure 2 The diagram shows the equivalent circuit of the drift step recovery diode with a hybrid anode structure in this embodiment. Furthermore, to more intuitively illustrate the working principle of the invention, this equivalent circuit is mapped onto the original cell structure, as shown below. Figure 3 As shown; by Figure 2 and Figure 3As can be seen, in this invention, the P-type anode region 11, the first P-type lightly doped region 10, the N-type drift region 4, and the N-type field-stop layer 3 together constitute a PPNN structure, forming a drift step recovery diode. Simultaneously, this invention introduces an N-type anode region 8 within the anode structure, which, together with the first P-type lightly doped region 10 and the N-type drift region 4, forms a parasitic NPN transistor, creating a conduction path during device reversal to improve reverse current. Furthermore, between the N-type anode region 8 and the P-type anode region 11, the anode metal 9 and the first P-type lightly doped region 10 form a Schottky contact diode, further reducing the base barrier of the parasitic NPN transistor and facilitating conduction path formation. Moreover, in this invention, the first P-type lightly doped region 10, the second P-type lightly doped region 5, and the N-type drift region 4 constitute a junction field-effect transistor (JFET) to protect the base region of the parasitic NPN transistor and prevent false triggering of the NPN transistor during switching. Additionally, the second P-type lightly doped region 5... Together with the N-type drift region 4 and the N-type field cutoff layer 3, they form a PNN structure, which can also form a drift step recovery diode, thereby improving the effective storage area utilization efficiency of the device.

[0038] When the device withstands voltage: the collector of the NPN transistor is connected to a positive potential, and the NPN transistor will not conduct at this time. In contrast, the anode of the drift step recovery diode is grounded and the cathode is connected to a positive potential. In addition, the junction field-effect transistor (JFET) can protect the base region of the NPN transistor and prevent the NPN transistor from being falsely triggered during switching. Therefore, in this embodiment, the withstand voltage of the drift step recovery diode is mainly borne by the voltage-resistant junction formed by the N-type drift region 4, the first P-type lightly doped region 10, and the second P-type lightly doped region 5. Here, the peak electric field is far away from the device surface, which helps to improve the withstand voltage of the device.

[0039] When the device is forward-biased: the collector of the NPN transistor is grounded and the emitter is connected to a positive potential, while the anode of the drift step recovery diode is connected to a positive potential and the cathode is grounded, and the junction field-effect transistor (JFET) is in the on state; as the anode voltage increases, the NPN transistor controls electrons to migrate from the N-type drift region 4 to the anode metal, reducing the carrier concentration stored in the first P-type lightly doped region 10, based on the diffusion rate calculation formula ( V SCR The depletion layer expansion rate is given by J, the reverse current is given by q, and the electron charge is given by n. m As can be seen from the carrier concentration, the depletion layer in this embodiment expands more easily and faster.

[0040] When the device is turned off: the emitter of the NPN transistor is grounded and the collector is connected to a positive potential, while the anode of the drift step recovery diode is grounded and the cathode is connected to a positive potential. At the initial turn-off, an electric field cannot be established because there are a large number of free carriers near the voltage junction. As holes are discharged from the voltage junction, their concentration drops to a certain value, and an electric field can be established at the voltage junction. When the voltage (VF) of the Schottky diode exceeds the peak voltage (VPT) of the NPN transistor, the electric field at the junction of the N-type anode region 8 and the first P-type lightly doped region 10 reaches its maximum value, and the electron carriers can reach saturation velocity, which helps the device to turn off quickly, thereby improving the pulse output characteristics of the device.

[0041] like Figure 4 The described cell structure is that of a traditional drift step recovery diode, such as... Figure 5 The diagram shows the cell structure of a fully superjunction drift step recovery diode, which introduces P-pillars to form a superjunction structure based on the traditional drift step recovery diode; as shown... Figure 6 The diagram shows the cell structure of a drift step recovery diode with an anode short-circuit structure, which introduces an N-type heavily doped region (N0) based on the traditional drift step recovery diode. + The P-type base region and the N-type drift region together form an anti-parallel NPN transistor. This anti-parallel NPN transistor creates a conduction path during the reverse process, increasing the reverse current and thus improving pulse performance. Furthermore, in the drift step recovery diode with an anode short-circuit structure, to facilitate the implementation of the heavily doped N-type region (N... + Lateral injection of the P-type base region (P-Base) introduces a trench structure, and further introduces a heavily doped P-type shielding layer (P-Shielding) to protect the bottom of the trench structure from electric field breakdown, while also protecting the P-type base region of the anti-parallel NPN transistor.

[0042] As can be seen from the above, compared to Figure 5 The fully superjunction drift step recovery diode shown in this invention does not require a superjunction structure to adjust the static electric field. Instead, it achieves dynamic current modulation through a JFET structure formed on the anode side, while simultaneously improving forward injection, reverse extraction, and fast turn-off processes. Therefore, compared to superjunction technology, the manufacturing process of this invention is simpler and easier to implement. Compared to... Figure 6The drift step recovery diode with an anode short-circuit structure shown in this invention utilizes two P-type doped regions and an N-type drift region to form a JFET structure, dynamically clamping and controlling the forward injection channel and the reverse extraction channel. Simultaneously, a Schottky contact is formed between the first lightly doped P-type region 10 and the anode, allowing the base potential and base charge of the parasitic anti-parallel NPN transistor to be controlled by the Schottky barrier, ultimately achieving lower stored charge, faster reverse recovery, and higher dV / dt output. Furthermore, with... Figure 4 The conventional drift step recovery diode (DSRD) shown is a comparative example, such as... Figure 7 The figure shown is a comparison of the carrier distribution of the drift step recovery diode with a hybrid anode structure and a conventional drift step recovery diode under forward injection conditions in this embodiment. Figure 7 As can be seen, compared to traditional DSRD, the carrier concentration in the N-type drift region of the DSRD in this invention is significantly reduced. This indicates that by using a first lightly doped P-type region 10, a second lightly doped P-type region 5, and an N-type drift region to form a JFET structure, and by making the first lightly doped P-type region 10 form a Schottky contact with the anode, excess carrier injection during the forward pumping phase can be effectively limited, thereby reducing the stored charge in the drift region. Ultimately, this invention requires less charge to be extracted during reverse recovery, and has the advantages of fast reverse recovery speed, short turn-off time, and steep voltage rise time. Figure 8 The figure shown is a comparison of the pulse performance of the drift step recovery diode with a hybrid anode structure and a conventional drift step recovery diode in this embodiment. This result is consistent with... Figure 7 The carrier concentration distributions in them correspond to each other; by Figure 7 This indicates that the present invention can reduce the stored charge in the N-type drift region, while Figure 8 This further indicates that the lower stored charge allows for faster charge extraction during the reverse recovery phase, more rapid expansion of the space charge region, and a more abrupt transition of the device from a low-resistance state to a high-resistance state. Consequently, the current in the external circuit can be converted into a voltage rise in a shorter time, ultimately resulting in a faster voltage rise rate and a higher voltage peak value.

[0043] The above description is merely a specific embodiment of the present invention. Any feature disclosed in this specification may be replaced by other equivalent or similar features unless otherwise specified. All disclosed features, or steps in all methods or processes, may be combined in any way except for mutually exclusive features and / or steps.

Claims

1. A drift step recovery diode with a hybrid anode structure, characterized in that, include: The structure comprises a cathode structure, a pressure-resistant layer structure, a hybrid anode structure, a trench structure, and a charge storage structure, wherein the pressure-resistant layer structure is located on top of the cathode structure, the charge storage structure and the trench structure are located on top of the pressure-resistant layer structure, and the hybrid anode structure is located within the charge storage structure. The pressure-resistant layer structure is an N-type drift region (4); The charge storage structure is a first P-type lightly doped region (10). The hybrid anode structure includes: an N-type anode region (8), a P-type anode region (11), and an anode metal (9); the N-type anode region and the P-type anode region are located on opposite sides of the surface of the first P-type lightly doped region, and both form ohmic contacts with the anode metal on the upper surface; at the same time, between the N-type anode region and the P-type anode region, the anode metal forms a Schottky contact with the first P-type lightly doped region; The trench structure includes: a passivation layer (7), an insulating medium (6), and a second P-type lightly doped region (5); the trench structure is located on one side of the N-type anode region in the hybrid anode structure and extends into the N-type drift region; the second P-type lightly doped region is located at the bottom of the trench, the passivation layer is located on the trench wall, and the insulating medium is filled in the trench; and the anode metal extends along the edge of the trench structure to the bottom of the trench and forms an ohmic contact with the second P-type lightly doped region.

2. The drift step recovery diode with a hybrid anode structure according to claim 1, characterized in that, The cathode structure includes: cathode metal (1), N-type substrate (2) and N-type field cutoff layer (3), wherein the N-type field cutoff layer is located on the lower surface of the N-type drift region, the N-type substrate is located on the lower surface of the N-type field cutoff layer, and the cathode metal is located on the lower surface of the N-type substrate.

3. The drift step recovery diode with a hybrid anode structure according to claim 1, characterized in that, The N-type anode region, together with the first P-type lightly doped layer and the N-type drift region, forms a parasitic NPN transistor.

4. The drift step recovery diode with a hybrid anode structure according to claim 1, characterized in that, The first lightly doped P-type region, the second lightly doped P-type region, and the N-type drift region constitute a junction field-effect transistor.

5. The drift step recovery diode with a hybrid anode structure according to claim 1, characterized in that, The anode metal forms a Schottky contact diode with the first P-type lightly doped region.

6. The drift step recovery diode with a hybrid anode structure according to claim 1, characterized in that, The passivation layer is made of silicon dioxide, and the insulating medium is made of polyimide.

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