Semiconductor structure and method of manufacturing the same

Abstract

The application relates to the technical field of semiconductors, and discloses a semiconductor structure and a preparation method thereof, which comprises the following steps: forming a first germanium-silicon layer on one side of a base layer, wherein the first germanium-silicon layer comprises an intrinsic region, and a first polysilicon layer is formed on the side of the intrinsic region away from the base layer; removing the base layer, forming a sacrifice layer on the side of the intrinsic region away from the first polysilicon layer, and forming an isolation layer on the side of the sacrifice layer; removing the sacrifice layer to obtain a collector groove penetrating through the isolation layer, and selectively epitaxially forming a collector region in the collector groove; and performing a patterning treatment on the polysilicon layer to form an emitter structure; and the width of the collector region is less than or equal to the width of the emitter structure. The application can guarantee that the doping concentration distribution of the collector region is in a target range, improve the reliability of the collector region, reduce the device area, improve the integration degree, and reduce the parasitic capacitance and resistance.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to a semiconductor structure and its fabrication method. Background Technology

[0002] In the fabrication process of heterojunction bipolar transistors (HBTs), the process involves first forming a doped collector region, followed by deposition of the base region and polysilicon emitter region. This results in the collector region being subjected to multiple heat transfers from the deposition processes of the base and emitter regions, causing the impurity redistribution at the collector to deviate from the ideal state, thus affecting device performance. Furthermore, the impurity distribution in the collector region formed by ion implantation exhibits an inherent Gaussian distribution and a low activation rate, requiring additional thermal processing for activation. This thermal processing further deviates the impurity distribution in the collector region from the ideal state, leading to a smaller difference in doping concentration between the collector and base regions. Consequently, the PN junction performance between the collector and base regions is poor, impacting device performance. Additionally, the collector of HBTs formed using this technology is located on the side of the emitter and base regions, and the collector area is much larger than the emitter area. The large overall device area due to the collector's lead-out method introduces parasitic parameters (such as parasitic resistance, capacitance, and inductance), which affect and degrade device performance.

[0003] Therefore, a new semiconductor structure and manufacturing method are needed to ensure that the doping concentration of the collector region is distributed within the target range, improve the performance of the semiconductor structure, and at the same time reduce the device area and reduce parasitic parameters. Summary of the Invention

[0004] This invention provides a semiconductor structure and its fabrication method to solve the problems in related technologies, such as the collector doping being affected by the deposition process of the base region and emitter region, causing the impurity distribution in the collector region to deviate from the ideal state, and the large overall area and large parasitic parameters of HBT devices.

[0005] In a first aspect, the present invention provides a method for preparing a semiconductor structure, the method comprising: A first germanium-silicon layer is formed on one side of the substrate layer. The first germanium-silicon layer includes an intrinsic region. A first polycrystalline silicon layer is formed on the side of the intrinsic region facing away from the substrate layer. Remove the substrate layer and form a sacrificial layer on the side of the intrinsic region opposite to the first polysilicon layer, and form an isolation layer on the side of the sacrificial layer; The sacrificial layer is removed to obtain a collector groove that penetrates the isolation layer, and a collector region is selectively formed by epitaxy within the collector groove; The first polysilicon layer is patterned to form an emitter structure; the width of the collector region is less than or equal to the width of the emitter structure.

[0006] The semiconductor structure fabrication method provided by this invention, in a first aspect, involves first depositing a first polysilicon layer and a first germanium-silicon layer, and then forming a collector region through epitaxial growth. This avoids the impact of the polysilicon and germanium-silicon layer deposition processes on the impurity distribution in the collector region, reduces the thermal tolerance of impurities in the collector region, and ensures that the doping concentration distribution in the collector region is within the target range. This allows for a significant abrupt change in impurity distribution from the collector region to the base region, resulting in a clear difference. In a second aspect, a collector groove formed by a sacrificial layer is used to predefine the position of the collector region, and the collector region is directly formed within the collector groove through epitaxial growth. This eliminates the need for etching processes on the collector region, avoiding etching damage and enabling… This allows for better control of the doping morphology of the collector region, resulting in a significant abrupt change in impurity distribution from the collector to the base region. This creates a distinct PN junction between the intrinsic regions of the collector and base regions, improving the reliability of the collector region. Thirdly, the final emitter structure, collector region, and base region are stacked, with the emitter structure and collector region located on the upper and lower sides of the base region, respectively. This enables a dramatic reduction in the lateral dimensions of the device, freeing it from the constraints of traditional epitaxial buried layer processes and enhancing the device's integration. Furthermore, the width of the collector region is less than or equal to the width of the emitter structure, allowing the collector area to be close to the emitter area. This significantly reduces the parasitic capacitance between the collector and base and the base resistance, improving the device's high-frequency performance.

[0007] In one alternative embodiment, a first polysilicon layer is formed on the side of the intrinsic region opposite to the substrate layer, comprising: A dielectric layer is formed on the side of the first germanium-silicon layer opposite to the substrate layer; the dielectric layer includes a first dielectric layer, a second dielectric layer, and a third dielectric layer stacked together; An emitter window is formed by opening a window in the dielectric layer. The emitter window penetrates the dielectric layer and exposes the surface of the intrinsic region. A first polycrystalline silicon layer is formed within the emitter window and on the surface of the dielectric layer.

[0008] In one optional embodiment, the second dielectric layer includes a second polysilicon layer; the material of the second polysilicon layer is type-1 doped polysilicon or undoped polysilicon; the material of the first germanium-silicon layer is type-1 doped germanium-silicon. The steps for patterning the first polysilicon layer to form the emitter structure include: The first polysilicon layer and the third dielectric layer are patterned, and the first polysilicon layer and the third dielectric layer outside the intrinsic region are removed, while the first polysilicon layer corresponding to the intrinsic region is retained to form an emitter structure; the emitter structure fills the emitter window and covers the side of the emitter window; the side of the emitter structure exposes the second dielectric layer.

[0009] The semiconductor structure fabrication method provided by the present invention includes a second dielectric layer comprising a second polysilicon layer. By controlling the doping of the second polysilicon layer, the base electrode can be positioned on either side or opposite sides of the base region. Thus, the base electrode can be led out on the emitter side or / or on the collector side as needed, thereby improving the design flexibility of the semiconductor structure.

[0010] In one alternative embodiment, a sacrificial layer is formed on the side of the intrinsic region opposite to the first polysilicon layer, comprising: An initial sacrificial layer is formed on the side of the first germanium-silicon layer opposite to the first polysilicon layer; The initial sacrificial layer, the first germanium-silicon layer, and the first dielectric layer are simultaneously patterned to obtain the sacrificial layer based on the initial sacrificial layer, the first base region layer based on the first germanium-silicon layer, and the first dielectric layer retaining the width of the side portion of the emitter window. The width of the sacrificial layer is greater than the width of the emitter window; the sacrificial layer covers the surface of the intrinsic region.

[0011] In one alternative embodiment, after forming the sacrificial layer and before forming the isolation layer, the preparation method further includes: By selective epitaxy, a second germanium-silicon layer is formed on the side of the first base region layer. The thickness of the second germanium-silicon layer is greater than the thickness of the first base region layer. The second germanium-silicon layer also covers part of the side of the sacrificial layer. The first base region layer and the second germanium-silicon layer together form the initial base region. The preparation method also includes: The initial base region is graphically processed to form the base region; A base is formed on the side of the second germanium-silicon layer opposite to the second polysilicon layer, and / or, a base is formed on the side of the second polysilicon layer opposite to the second germanium-silicon layer.

[0012] The semiconductor structure fabrication method provided by this invention, on the one hand, increases the thickness of the subsequently formed base region by forming a second germanium-silicon layer on the side of the first base region layer, with the first and second germanium-silicon layers together forming the initial base region layer, thereby increasing the thickness of the intrinsic region and improving device performance; on the other hand, by controlling the condition of the second polysilicon layer, base electrodes can be formed on any side or opposite sides of the base region, thereby allowing base electrodes to be led out on any or both surfaces of the semiconductor structure as needed, improving the flexibility of device design; when base electrode lead-out structures are led out on both surfaces of the semiconductor structure, parasitic capacitance and parasitic resistance can be further reduced, thereby improving device performance.

[0013] In one alternative embodiment, a sacrificial layer is formed on the side of the intrinsic region opposite to the first polysilicon layer, comprising: An initial sacrificial layer is formed on the side of the first germanium-silicon layer opposite to the first polysilicon layer; The initial sacrificial layer is graphically processed, and the initial sacrificial layer corresponding to the intrinsic region is retained to form the sacrificial layer.

[0014] In one alternative embodiment, after forming the sacrificial layer and before forming the isolation layer, the preparation method further includes: By selective epitaxy, a second germanium-silicon layer is formed on the surface of the first germanium-silicon layer on the side of the sacrificial layer, and the second germanium-silicon layer also covers part of the side of the sacrificial layer; the first germanium-silicon layer and the second germanium-silicon layer together form the initial base region; The preparation method also includes: The initial base region is graphically processed to form the base region; A base electrode is formed on the surface of the base region on the side of the collector region; the base electrode is located on the side of the collector region, and the base electrode and the collector region are located on the same side of the base region.

[0015] The semiconductor structure fabrication method provided by the present invention forms a second germanium-silicon layer on the surface of a first germanium-silicon layer on the side of the sacrificial layer. The first and second germanium-silicon layers together form an initial base region layer, which can increase the thickness of the subsequently formed base region, thereby increasing the thickness of the intrinsic region and thus improving the performance of the device.

[0016] In one optional embodiment, after selectively epitaxially forming a current collector region within the current collector groove, the fabrication method further includes: Forming an initial base region including a first germanium-silicon layer; Remove the isolation layer; perform graphical processing on the initial base region to form the base region; the base region includes the intrinsic region and the non-intrinsic region located on the side of the intrinsic region.

[0017] In one alternative implementation, prior to forming the emitter structure, the method further includes: A collector electrode is formed on the surface of the collector region away from the intrinsic region; a collector electrode lead-out structure is formed on the side of the collector electrode away from the collector region; a first insulating layer is provided on the side of the collector electrode lead-out structure; After the emitter structure is formed, it also includes: An emitter is formed on the surface of the emitter structure facing away from the intrinsic region; the emitter and collector are located on opposite sides of the base region; an emitter lead-out structure is formed on the side of the emitter facing away from the emitter structure, and a second insulating layer is provided on the side of the emitter lead-out structure.

[0018] In a second aspect, the present invention provides a semiconductor structure prepared by the method for preparing the semiconductor structure described in the first aspect. Attached Figure Description

[0019] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0020] Figure 1 This is a schematic flowchart of a method for fabricating a semiconductor structure according to an embodiment of the present invention; Figure 2 This is a schematic diagram of a specific process for fabricating a semiconductor structure according to an embodiment of the present invention; Figure 3 This is a schematic diagram of the substrate layer in a method for fabricating a semiconductor structure according to an embodiment of the present invention; Figure 4 This is a schematic diagram of a method for fabricating a semiconductor structure according to an embodiment of the present invention, in which a shallow trench isolation region is formed; Figure 5 This is a schematic diagram of the formation of a first germanium-silicon layer in a method for fabricating a semiconductor structure according to an embodiment of the present invention; Figure 6 This is a schematic diagram of the formation of a dielectric layer in a method for fabricating a semiconductor structure according to an embodiment of the present invention; Figure 7 This is a schematic diagram of the structure forming the emitter window and the first sidewall protective layer in a method for fabricating a semiconductor structure according to an embodiment of the present invention; Figure 8 This is a schematic diagram of the formation of a first polycrystalline silicon layer and a fourth dielectric layer in a semiconductor structure fabrication method according to an embodiment of the present invention. Figure 9 This is a schematic diagram of a semiconductor structure bonded to a first temporary substrate in a method for fabricating a semiconductor structure according to an embodiment of the present invention; Figure 10 This is a schematic diagram of the structure of removing the substrate layer in a method for fabricating a semiconductor structure according to an embodiment of the present invention; Figure 11 This is a schematic diagram of the structure forming an initial sacrificial layer in a method for fabricating a semiconductor structure according to an embodiment of the present invention; Figure 12 This is a schematic diagram of the structure forming a sacrificial layer and a first base region layer in a semiconductor structure fabrication method according to an embodiment of the present invention; Figure 13 This is a schematic diagram of the formation of a second germanium-silicon layer in a semiconductor structure fabrication method according to an embodiment of the present invention; Figure 14This is a schematic diagram of the structure forming an isolation layer in a method for fabricating a semiconductor structure according to an embodiment of the present invention; Figure 15 This is a schematic diagram of the process of removing the sacrificial layer and forming a collector groove in a semiconductor structure fabrication method according to an embodiment of the present invention; Figure 16 This is a schematic diagram of the structure forming the collector region in a method for fabricating a semiconductor structure according to an embodiment of the present invention; Figure 17 This is a schematic diagram of the base region formed in a method for fabricating a semiconductor structure according to an embodiment of the present invention; Figure 18 This is a schematic diagram of the formation of the base and collector electrodes in a semiconductor structure fabrication method according to an embodiment of the present invention; Figure 19 This is a schematic diagram of a semiconductor structure bonded to a second temporary substrate in a method for fabricating a semiconductor structure according to an embodiment of the present invention; Figure 20 This is a schematic diagram of the formation of an emitter structure and an emitter structure in a method for fabricating a semiconductor structure according to an embodiment of the present invention; Figure 21A This is a schematic diagram of the formation of the emitter lead-out structure in Example 1 of a semiconductor structure fabrication method according to an embodiment of the present invention; Figure 21B This is a schematic diagram of the formation of the emitter lead-out structure and the base lead-out structure in Example 2 of a semiconductor structure fabrication method according to an embodiment of the present invention; Figure 22 This is a schematic flowchart of another method for preparing a semiconductor structure according to an embodiment of the present invention; Figure 23 This is a schematic diagram of the structure forming the initial sacrificial layer in another method for fabricating a semiconductor structure according to an embodiment of the present invention; Figure 24 This is a schematic diagram of the structure forming a sacrificial layer in another method for fabricating a semiconductor structure according to an embodiment of the present invention; Figure 25 This is a schematic diagram of the formation of a second germanium-silicon layer in another method for preparing a semiconductor structure according to an embodiment of the present invention; Figure 26 This is a schematic diagram of the structure forming an isolation layer in a method for fabricating a semiconductor structure according to an embodiment of the present invention; Figure 27 This is a schematic diagram of a semiconductor structure fabrication method according to an embodiment of the present invention, in which a sacrificial layer is removed to form a current collector groove; Figure 28This is a schematic diagram of the structure forming the collector region in another method for fabricating a semiconductor structure according to an embodiment of the present invention; Figure 29 This is a schematic diagram of the base region formed in another method for fabricating a semiconductor structure according to an embodiment of the present invention; Figure 30 This is a schematic diagram of the formation of the base and collector electrodes in another method for fabricating a semiconductor structure according to an embodiment of the present invention; Figure 31 This is a schematic diagram of a structure bonded to a second temporary substrate in another method for fabricating a semiconductor structure according to an embodiment of the present invention; Figure 32 This is a schematic diagram of the formation of an emitter structure and an emitter structure in another method for fabricating a semiconductor structure according to an embodiment of the present invention.

[0021] Figure label: 10. Substrate layer; 11. Substrate silicon; 12. Buried oxide layer; 13. Top silicon layer; 14. Shallow trench isolation region; 201, First germanium-silicon layer; 202, Second germanium-silicon layer; 20, First base layer; 21, Base region; 22, Base electrode; 23, First contact hole; 24, First metal block; 25, Base pad; 30. Dielectric layer; 31. First dielectric layer; 32. Second dielectric layer; 33. Third dielectric layer; 34. Fourth dielectric layer; 35. Isolation layer; 36. First sidewall protection layer; 37. Second sidewall protection layer; 38. Third sidewall protection layer; 39. Fourth sidewall protection layer; 301. Emitter window; 40. First polysilicon layer; 41. Emitter structure; 42. Emitter; 43. Third contact hole; 44. Third metal block; 45. Emitter pad; 50. Sacrificial layer; 51. First sacrificial film layer; 52. Second sacrificial film layer; 500. Initial sacrificial layer; 501. First initial sacrificial layer; 502. Second initial sacrificial layer; 60. Current collector groove; 61. Current collector area; 62. Current collector; 63. Second contact hole; 64. Second metal block; 65. Current collector pad; 70. Barrier layer; 71. First insulating layer; 72. Second insulating layer; 81. First temporary substrate; 82. Second temporary substrate; 91. First edge region; 92. Second edge region. Detailed Implementation

[0022] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It is understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the invention and not all structures. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0023] In the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concepts of the present invention. Various structural schematic diagrams according to embodiments of the present invention are shown in the accompanying drawings. These drawings are not to scale, and some details are enlarged for clarity, and some details may be omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate in practice due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed. In the context of the present invention, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0024] In related technologies, the collector of HBT devices is located on the side of the emitter and base regions. The way the collector is led out results in a large overall device area, which introduces parasitic parameters (such as parasitic resistance, parasitic capacitance, and parasitic inductance), affecting and degrading device performance. In addition, due to limitations in epitaxial processes and photolithography tolerance, the collector area of ​​traditional HBTs is much larger than that of the emitter, which also leads to large parasitic capacitance and limits the high-frequency performance of the device.

[0025] Furthermore, in traditional fabrication processes, the doped collector region is formed first, followed by the deposition of the base region and polysilicon emitter region. This results in the collector region being subjected to multiple heat effects from the deposition processes of the base and emitter regions, causing the impurity redistribution at the collector electrode to deviate from the ideal state, thus affecting device performance. Additionally, damage may occur during the patterning process to form the collector region, leading to device failure. Moreover, the impurity distribution in collector regions formed by ion implantation has an inherent Gaussian distribution, and the activation rate of ion-implanted collector regions is low, requiring additional thermal treatment for activation. However, the thermal treatment process further deviates the impurity distribution in the collector region from the ideal state, resulting in a smaller difference in doping concentration between the collector and base regions, leading to poor PN junction performance between the collector and base regions, thus affecting device performance.

[0026] Therefore, a new semiconductor structure and manufacturing method are needed to reduce device area, lower parasitic parameters, and ensure that the doping concentration of the collector region is within the target range, thereby improving the performance of the semiconductor structure.

[0027] like Figure 1 As shown, this embodiment provides a method for fabricating a semiconductor structure, which includes, but is not limited to, steps S101 to S104.

[0028] Step S101: A first germanium-silicon layer is formed on one side of the substrate layer. The first germanium-silicon layer includes an intrinsic region. A first polycrystalline silicon layer is formed on the side of the intrinsic region facing away from the substrate layer.

[0029] In practice, the substrate can be silicon, silicon-on-insulator (SOI) wafers, etc. In some examples, the first polysilicon layer can be N-type doped polysilicon, which can be formed by in-situ doping or ion implantation doping. The first germanium-silicon layer is type I heavily doped SiGe.

[0030] Step S102: Remove the substrate layer, form a sacrificial layer on the side of the intrinsic region opposite to the first polysilicon layer, and form an isolation layer on the side of the sacrificial layer.

[0031] In practice, different removal methods can be selected for different substrate layers. Specifically, one or more methods such as chemical mechanical polishing, dry etching, or wet etching can be used to remove a portion of the substrate layer. The sacrificial layer includes at least a silicon nitride film. The isolation layer can be made of silicon dioxide or similar materials. The width of the sacrificial layer is greater than the width of the emitter window; the sacrificial layer covers the intrinsic region surface.

[0032] Step S103: Remove the sacrificial layer to obtain a collector groove that penetrates the isolation layer, and selectively epitaxially form a collector region within the collector groove.

[0033] In practice, the doping types of the collector region and the first germanium-silicon layer are opposite. In some examples, the collector layer is an epitaxially formed N-type doped silicon.

[0034] Step S104: The first polysilicon layer is patterned to form an emitter structure; the width of the collector region is less than or equal to the width of the emitter structure.

[0035] In practice, patterning can be performed using methods such as photolithography, etching, or laser etching. The emitter structure and collector region are located on the upper and lower sides of the base region, respectively, with the positions of the collector region and emitter structure corresponding vertically.

[0036] Compared with related technologies, this application, after depositing the first polysilicon layer and the first germanium silicon layer, uses a sacrificial layer to predefine the position of the collector region and forms the collector region in the collector groove through epitaxial growth. This avoids the impact of the deposition process of the polysilicon layer and the germanium silicon layer on the distribution of impurities in the collector region. The epitaxial growth directly forms the collector region without the need for an etching process, thus avoiding etching damage to the collector region.

[0037] Compared to ion implantation, epitaxial growth allows for better control of the doping morphology (i.e., the distribution of doped ions within the collector region) of the collector region. Firstly, in-situ doping in epitaxial growth allows for precise control of impurity distribution, resulting in a more abrupt PN junction, whereas ion implantation inherently produces a Gaussian distribution of impurities. Secondly, epitaxy achieves high activation rates without additional heat treatment, while the heat treatment in ion implantation inevitably leads to a more gradual doping morphology. Therefore, epitaxial growth allows for a significant abrupt change in impurity distribution from the collector region to the base region, forming a distinct PN junction between the intrinsic regions of the collector and base regions. Furthermore, it achieves high activation rates without requiring additional activation processes, simplifying the manufacturing process.

[0038] The semiconductor structure fabrication method provided in this embodiment, firstly, involves depositing a first polysilicon layer and a first germanium-silicon layer, followed by epitaxial growth to form a collector region. This avoids the impact of the polysilicon and germanium-silicon layer deposition processes on the impurity distribution in the collector region, reduces the thermal tolerance of impurities in the collector region, and ensures that the doping concentration of the collector region is within the target range. This allows for a significant abrupt change in impurity distribution from the collector region to the base region, resulting in a clear difference. Secondly, the location of the collector region is predefined using a collector groove formed by a sacrificial layer, and the collector region is directly formed within the collector groove through epitaxial growth. This eliminates the need for etching processes on the collector region, avoiding etching damage and enabling... This allows for better control of the doping morphology of the collector region, resulting in a significant abrupt change in impurity distribution from the collector to the base region. This creates a distinct PN junction between the intrinsic regions of the collector and base regions, improving the reliability of the collector region. Thirdly, the final emitter structure, collector region, and base region are stacked, with the emitter structure and collector region located on the upper and lower sides of the base region, respectively. This enables a dramatic reduction in the lateral dimensions of the device, freeing it from the constraints of traditional epitaxial buried layer processes and enhancing the device's integration. Furthermore, the width of the collector region is less than or equal to the width of the emitter structure, allowing the collector area to be close to the emitter area. This significantly reduces the parasitic capacitance between the collector and base and the base resistance, improving the device's high-frequency performance.

[0039] For HBT devices, the RF performance formula is as follows:

[0040] in, f T Indicates the cutoff frequency of the device; C diff Indicates diffusion capacitance; C BE This represents the emitter junction depletion layer capacitance and emitter parasitic capacitance; C BC This represents the collector depletion layer capacitance and the collector parasitic capacitance; R E Indicates the emitter region resistance; R C Indicates the collector region resistance; g m Indicates the transconductance of the device.

[0041]

[0042] in, f MAX Indicates the highest oscillation frequency; f T Indicates the cutoff frequency of the device; R B Indicates the base region resistance; C BC This represents the collector depletion layer capacitance and the collector parasitic capacitance.

[0043] Based on the device RF performance formula, the HBT device formed in this embodiment exhibits [performance characteristics]. C BC and R B This represents a significant improvement over the traditional HBT structure.

[0044] In some alternative implementations, the width of the sacrificial layer is greater than the width of the emitter window; the sacrificial layer covers the intrinsic region surface.

[0045] In some alternative embodiments, after selectively epitaxially forming the current collector region within the current collector groove, the fabrication method further includes: Forming an initial base region including a first germanium-silicon layer; Remove the isolation layer; perform graphical processing on the initial base region to form the base region; the base region includes the intrinsic region and the non-intrinsic region located on the side of the intrinsic region.

[0046] In some alternative implementations, prior to forming the emitter structure, the following steps are also included: A collector electrode is formed on the surface of the collector region away from the intrinsic region; a collector electrode lead-out structure is formed on the side of the collector electrode away from the collector region; a first insulating layer is provided on the side of the collector electrode lead-out structure; After the emitter structure is formed, it also includes: An emitter is formed on the surface of the emitter structure facing away from the intrinsic region; the emitter and collector are located on opposite sides of the base region; an emitter lead-out structure is formed on the side of the emitter facing away from the emitter structure, and a second insulating layer is provided on the side of the emitter lead-out structure.

[0047] In some optional embodiments, the fabrication method further includes: forming a base on the surface of the intrinsic region on the side of the emitter structure; the base and the emitter are located on the same side of the base region; And / or, a base is formed on the surface of the non-intrinsic region on the side of the collector region; the base and the collector are located on the same side of the base region.

[0048] In some alternative embodiments, the fabrication method further includes: forming a base lead-out structure on the side of the base opposite to the intrinsic region; the base lead-out structure is located inside the first insulating layer, and / or the base lead-out structure is located inside the second insulating layer.

[0049] In specific implementation, the base region includes a first side and a second side that are arranged opposite to each other; the emitter is located on the first side of the base region; the collector is located on the second side of the base region; and the base is located on the first side and / or the second side of the base region.

[0050] In some alternative embodiments, a first polysilicon layer is formed on the side of the first germanium-silicon layer opposite to the substrate layer, including: A dielectric layer is formed on the side of the first germanium-silicon layer facing away from the substrate layer; the dielectric layer includes a first dielectric layer, a second dielectric layer and a third dielectric layer stacked together; the first dielectric layer is relatively close to the first germanium-silicon layer.

[0051] An emitter window is formed by opening a window in the dielectric layer. The emitter window penetrates the dielectric layer and exposes the surface of the intrinsic region. A first polycrystalline silicon layer is formed within the emitter window and on the surface of the dielectric layer.

[0052] In some alternative embodiments, both the first dielectric layer and the third dielectric layer are made of silicon oxide.

[0053] In some alternative implementations, the material of the second dielectric layer is silicon nitride or polycrystalline silicon.

[0054] In some alternative embodiments, the first germanium-silicon layer is made of type-1 doped germanium-silicon, i.e., the base region is made of type-1 doped germanium-silicon. The first polysilicon layer is made of type-2 doped polysilicon, i.e., the emitter structure is made of type-2 doped polysilicon. The collector region is made of type-2 doped silicon. The types of type-1 doping and type-2 doping are opposite.

[0055] In some alternative implementations, one of the first type doping and the second type doping is a P-type doping and the other is an N-type doping.

[0056] In some alternative embodiments, the second dielectric layer includes a second polysilicon layer; the material of the second polysilicon layer is type-1 doped polysilicon or undoped polysilicon, and the material of the first germanium-silicon layer is type-1 doped germanium-silicon.

[0057] In specific implementations, the second dielectric layer may include a second polysilicon layer or a dielectric layer such as silicon nitride. When the second dielectric layer includes a second polysilicon layer, the conductivity of the second dielectric layer can be controlled by controlling the doping of the second polysilicon layer. When the material of the second polysilicon layer is type-1 doped polysilicon, it is conductive, and since the doping type of the second polysilicon layer and the first germanium-silicon layer is the same, it can be used to bring out the first germanium-silicon layer, and then to subsequently bring out the base region.

[0058] In some examples, when the material of the second polysilicon layer is type-1 doped polysilicon, the second polysilicon layer is conductive. Since the first germanium-silicon layer is also type-1 doped, the second polysilicon layer can be used to extract the signal from the base region. Therefore, the base can be provided on the collector side and / or the emitter structure side as needed, and the base extraction structure can be provided on either side of the semiconductor structure, or the base extraction structures can be provided on opposite sides of the semiconductor structure at the same time.

[0059] In other examples, when the material of the second polysilicon layer is undoped polysilicon, the second polysilicon layer is insulating and the base cannot be led out at the location of the second dielectric layer. Therefore, the base can only be located on the side of the collector region.

[0060] The semiconductor structure fabrication method provided in this embodiment includes a second polysilicon layer as the second dielectric layer. By controlling the doping of the second polysilicon layer, the base can be positioned on either side or opposite sides of the base region. Thus, the base can be led out on the emitter side or / or the collector side as needed, thereby improving the design flexibility of the semiconductor structure.

[0061] In some alternative implementations, the semiconductor structure is a heterojunction bipolar transistor.

[0062] In some optional embodiments, the second polysilicon layer is made of P-type doped polysilicon or undoped polysilicon, the first germanium-silicon layer / base region is made of P-type doped germanium-silicon, the first polysilicon layer / emitter structure is made of N-doped polysilicon, the collector region is made of N-doped silicon, and the formed semiconductor structure is an NPN type semiconductor structure. In some optional embodiments, the heterojunction bipolar transistor is an NPN type device.

[0063] In some optional embodiments, the second polysilicon layer is made of N-type doped polysilicon or undoped polysilicon, the first germanium-silicon layer / base region is made of N-type doped germanium-silicon, the first polysilicon layer / emitter structure is made of P-doped polysilicon, the collector region is made of P-doped silicon, and the formed semiconductor structure is a PNP type semiconductor structure. In some optional embodiments, the heterojunction bipolar transistor is a PNP type device.

[0064] In some optional embodiments, a sacrificial layer is formed on the side of the intrinsic region opposite to the first polysilicon layer, including: forming an initial sacrificial layer on the side of the first germanium-silicon layer opposite to the first polysilicon layer; simultaneously patterning the initial sacrificial layer, the first germanium-silicon layer, and the first dielectric layer to obtain the sacrificial layer based on the initial sacrificial layer, obtain the first base region layer based on the first germanium-silicon layer, and retain the width of the side portion of the emitter window of the first dielectric layer. In some optional embodiments, the width of the sacrificial layer is greater than the width of the emitter window; the sacrificial layer covers the surface of the intrinsic region.

[0065] In practice, the first dielectric layer is used as a stop layer, and the initial sacrificial layer and the first germanium-silicon layer are etched simultaneously to obtain the sacrificial layer based on the initial sacrificial layer and the first base region layer based on the first germanium-silicon layer. Then, the second dielectric layer is used as a stop layer to etch the first dielectric layer, leaving a portion of the first dielectric layer on the side of the emitter window, which serves as an isolation structure between the subsequent emitter structure and the base region.

[0066] The semiconductor structure fabrication method provided in this embodiment uses a first dielectric layer as an etch stop layer to etch and form a sacrificial layer and a first base region layer, and uses a second dielectric layer as an etch stop layer to retain a portion of the width of the first dielectric layer on the side of the emitter window. This eliminates the need for an additional stop layer, reduces process difficulty, simplifies the process flow, improves the accuracy of patterning, and thus improves the accuracy of the sacrificial layer and the accuracy of the subsequently formed collector region, thereby improving the process yield.

[0067] In some alternative embodiments, after the sacrificial layer is formed and before the isolation layer is formed, the fabrication method further includes: selectively epitaxially forming a second germanium-silicon layer on the side of the first base region layer, the thickness of the second germanium-silicon layer being greater than the thickness of the first base region layer, and the second germanium-silicon layer also covering a portion of the side of the sacrificial layer; the first base region layer and the second germanium-silicon layer together constitute the initial base region.

[0068] In practice, the base region includes the intrinsic region and the non-intrinsic region on its sides. The intrinsic region is the first base region layer, and the non-intrinsic region is the second germanium-silicon layer.

[0069] The semiconductor structure fabrication method provided in this embodiment increases the thickness of the subsequently formed base region by forming a second germanium-silicon layer on the side of the first base region layer and the second germanium-silicon layer on the side of the first base region layer together forming the initial base region layer, thereby increasing the thickness of the intrinsic region and improving the performance of the device.

[0070] In some optional embodiments, the material of the second polysilicon layer is type-1 doped polysilicon; the step of patterning the first polysilicon layer to form an emitter structure includes: patterning the first polysilicon layer and the third dielectric layer, removing the first polysilicon layer and the third dielectric layer outside the intrinsic region, retaining the first polysilicon layer corresponding to the intrinsic region, and forming an emitter structure; the emitter structure fills the emitter window and covers the side of the emitter window; the side of the emitter structure exposes the second dielectric layer.

[0071] In some optional embodiments, the fabrication method further includes: patterning the initial base region to form a base region; forming a base electrode on the side of the second germanium-silicon layer opposite to the second polysilicon layer, with the base electrode and the collector electrode located on the same side of the base region; and / or forming a base electrode on the side of the second polysilicon layer opposite to the second germanium-silicon layer, with the base electrode and the emitter electrode located on the same side of the base region.

[0072] In specific implementation, the formation process of the second dielectric layer is as follows: a second polysilicon layer is deposited on the surface of the first dielectric layer, followed by type I ion implantation or self-doping type I deposition to obtain a type I doped second polysilicon layer. In the subsequent step of forming the emitter structure, the second dielectric layer is exposed on the side of the emitter structure, so a base can be formed on the surface of the second polysilicon layer, thereby enabling front-side connection to the base region (or simultaneous front and back-side connection to reduce connection resistance). Here, the front side refers to the surface side of the base region where the emitter structure is located, and the back side refers to the surface side of the base region where the collector region is located. In some examples, a P-type doped second polysilicon layer is obtained by performing P-type ion implantation or self-doping P-type deposition on the second polysilicon.

[0073] In some optional embodiments, a base electrode is provided on both the first and second sides of the base region, and the fabrication method further includes: forming a base electrode lead-out structure on the surface of the base electrode; the base electrode lead-out structure is located on the first side and / or the second side of the base region.

[0074] In some alternative implementations, base electrodes are provided on both the first and second sides of the base region, and base electrode lead-out structures are led out from both surfaces of the semiconductor structure.

[0075] The semiconductor structure fabrication method provided in this embodiment allows the base to be located on the first and / or second side of the base region. The base can be led out on any or both surfaces of the semiconductor structure as needed, improving the flexibility of device design. When both surfaces of the semiconductor structure have base lead-out structures, parasitic capacitance and parasitic resistance can be further reduced, thereby improving device performance.

[0076] In some optional embodiments, a sacrificial layer is formed on the side of the intrinsic region opposite to the first polysilicon layer, including: forming an initial sacrificial layer on the side of the first germanium-silicon layer opposite to the first polysilicon layer; patterning the initial sacrificial layer, retaining the initial sacrificial layer corresponding to the intrinsic region, and forming a sacrificial layer.

[0077] In some optional embodiments, after the sacrificial layer is formed and before the isolation layer is formed, the preparation method further includes: selectively epitaxially forming a second germanium-silicon layer on the surface of a first germanium-silicon layer on the side of the sacrificial layer, the thickness of the second germanium-silicon layer being greater than the thickness of the first germanium-silicon layer, and the second germanium-silicon layer also covering a portion of the side of the sacrificial layer; the first germanium-silicon layer and the second germanium-silicon layer together form an initial base region.

[0078] The semiconductor structure fabrication method provided by the present invention forms a second germanium-silicon layer on the surface of a first germanium-silicon layer on the side of the sacrificial layer. The first and second germanium-silicon layers together form an initial base region layer, which can increase the thickness of the subsequently formed base region, thereby increasing the thickness of the intrinsic region and thus improving the performance of the device.

[0079] In some optional embodiments, the fabrication method further includes: patterning the initial base region to form a base region; forming a base electrode on the surface of the base region on the side of the collector region; the base electrode is located on the side of the collector region, and the base electrode and the collector region are located on the same side of the base region.

[0080] In practice, the base region formed after patterning includes the intrinsic region and its lateral extrinsic regions. The intrinsic region is the first germanium-silicon layer, and the extrinsic regions include the stacked first and second germanium-silicon layers.

[0081] In some optional embodiments, the first polysilicon layer is patterned to form an emitter structure, including: using a third dielectric layer as a stop layer, the first polysilicon layer is patterned to remove the first polysilicon layer outside the intrinsic region, and retain the first polysilicon layer corresponding to the intrinsic region to form an emitter structure; the emitter structure fills the emitter window and covers the side of the emitter window; the emitter structure is correspondingly disposed with the collector region; the projection of the emitter structure on the base region covers the projection of the collector region on the base region.

[0082] In some alternative embodiments, an isolation layer is formed on the side of the sacrificial layer, including: forming an initial isolation layer on the surface and side of the sacrificial layer; removing the initial isolation layer on top of the sacrificial layer using chemical mechanical polishing; and retaining the initial isolation layer on the side of the sacrificial layer to form an isolation layer. The upper surface of the isolation layer and the upper surface of the sacrificial layer are coplanar.

[0083] In some alternative embodiments, before forming a polysilicon layer within the emitter window and on the surface of the dielectric layer, the method further includes: forming a first sidewall protective layer on the sidewall of the emitter window; the material of the first sidewall protective layer is silicon dioxide.

[0084] In some alternative embodiments, a germanium-silicon layer is formed on one side of the substrate layer, including: providing a substrate layer, the substrate layer being a silicon-on-insulator wafer, the substrate layer including a substrate silicon, a buried oxide layer and a top silicon layer stacked sequentially; and epitaxially forming a germanium-silicon layer on the surface of the top silicon layer facing away from the buried oxide layer.

[0085] In some optional embodiments, a first transition layer is further disposed between the germanium-silicon layer and the top silicon layer; the first transition layer is a type I lightly doped silicon layer; the germanium-silicon layer is a type I heavily doped SiGe; the doping concentration of the germanium-silicon layer is greater than that of the first transition layer. A second transition layer is further disposed on the side of the germanium-silicon layer opposite to the first transition layer; the second transition layer is made of silicon. The thickness of the germanium-silicon layer is 10 nm to 100 nm.

[0086] In some alternative embodiments, after forming a polycrystalline silicon layer on the side of the germanium-silicon layer opposite to the substrate layer, the method further includes forming a fourth dielectric layer on the side of the polycrystalline silicon layer opposite to the substrate layer.

[0087] In practice, the fourth dielectric layer comprises multiple sub-dielectric layers. After the fourth dielectric layer is formed, the process further includes performing a chemical mechanical polishing process to make the side of the fourth dielectric layer facing away from the polysilicon layer planar.

[0088] The semiconductor structure fabrication method provided in this embodiment, by forming a fourth dielectric layer, can avoid damage to the polysilicon layer when the wafer is flipped and bonded to the surface of the first temporary substrate.

[0089] In some alternative embodiments, before patterning the substrate layer and the germanium-silicon layer, the fabrication method further includes: bonding the fourth dielectric layer to the surface of the first temporary substrate on the side opposite to the polysilicon layer; removing the substrate silicon by chemical mechanical polishing, dry etching, or wet etching; removing the buried oxide layer by dry etching or wet etching; and removing the top silicon by chemical mechanical polishing, dry etching, or wet etching.

[0090] In some optional embodiments, before forming the emitter structure, the method further includes: forming a collector electrode on the surface of the collector region and forming a base electrode on the surface of the base region on the side of the collector region; the base electrode is located on the side of the collector electrode, and the base electrode and the collector electrode are located on the same side of the base region; forming a collector electrode lead-out structure on the side of the collector electrode facing away from the collector region and forming a base electrode lead-out structure on the side of the base electrode facing away from the base region; and providing a first insulating layer on the sides of the collector electrode lead-out structure and the base electrode lead-out structure.

[0091] In practice, a collector electrode can be formed by depositing a metal layer on the surface of the collector region and then annealing it. The material of the collector electrode is alloyed polycrystalline silicon.

[0092] In some alternative implementations, prior to forming the emitter structure, the method further includes: bonding the collector side to the surface of the second temporary substrate; and removing the first temporary substrate and a third dielectric layer of at least a portion of its thickness.

[0093] In some optional embodiments, after forming the emitter structure, the method further includes: forming an emitter on the surface of the emitter structure; the emitter and the collector being located on opposite sides of the base region; and forming an emitter lead-out structure on the side of the emitter facing away from the emitter structure, wherein a second insulating layer is provided on the side of the emitter lead-out structure.

[0094] In practice, the emitter can be formed by depositing a metal layer on the surface of the emitter structure and then annealing it. The material of the emitter is alloyed polycrystalline silicon.

[0095] In some alternative embodiments, after the semiconductor structure is fabricated, the second temporary substrate is removed.

[0096] In some alternative embodiments, the fabrication method further includes: forming a second sidewall protective layer on the side of the collector region during the step of forming the collector region; forming a third sidewall protective layer on the side of the base region after forming the base region; and forming a fourth sidewall protective layer on the side of the emitter structure after forming the emitter structure.

[0097] In some optional embodiments, the base lead-out structure includes a first contact hole, a first metal block, and a base pad; the collector lead-out structure includes a second contact hole, a second metal block, and a collector pad; the emitter lead-out structure includes a third contact hole, a third metal block, and an emitter pad; a first insulating layer is disposed on the side of the collector lead-out structure; a second insulating layer is disposed on the side of the emitter lead-out structure; and the base lead-out structure is located within the first insulating layer and / or the second insulating layer.

[0098] In some alternative implementations, the first contact hole, the first metal block, and the base pad in the base lead-out structure are electrically connected and connected to the base. The second contact hole, the second metal block, and the collector pad in the collector lead-out structure are electrically connected and connected to the collector. The third contact hole, the third metal block, and the emitter pad in the emitter lead-out structure are electrically connected and connected to the emitter.

[0099] In some optional embodiments, the first and second insulating layers include a plurality of interconnect layers, with a barrier layer disposed between adjacent interconnect layers; each interconnect layer corresponds to a contact hole, metal block, or pad of an electrode lead-out structure. The electrode lead-out structure is an emitter lead-out structure, a base lead-out structure, or a collector lead-out structure; the contact hole is a first contact hole, a second contact hole, or a third contact hole; the metal block is a first metal block, a second metal block, or a third metal block; and the pad is an emitter pad, a base pad, or a collector pad.

[0100] like Figure 2 As shown, the present invention also provides a specific flowchart of a method for preparing a semiconductor structure, including but not limited to steps S201 to S213.

[0101] Step S201: Provide a substrate layer 10, and form a first germanium-silicon layer 201 on one side of the substrate layer 10, such as... Figure 3 , Figure 4 and Figure 5 As shown.

[0102] In specific implementation, the substrate is an SOI wafer, which includes a substrate silicon 11, a buried oxide layer 12, and a top silicon layer 13 stacked sequentially, such as... Figure 3 As shown, the thickness of the buried oxide layer 12 includes, but is not limited to, 0.05~1μm, and the thickness of the top silicon layer 13 includes, but is not limited to, 0.01~2μm. In some examples, step S201 further includes: forming shallow trench isolation regions 14 and active regions located between adjacent shallow trench isolation regions 14 in the top silicon layer 13, such as... Figure 4 As shown. Then, a first germanium-silicon layer 201 is epitaxially grown on the surface of the top silicon layer 13 facing away from the buried oxide layer 12, as shown. Figure 5As shown. The thickness of the first germanium-silicon layer 201 is 10 nm to 100 nm. In some embodiments, a first transition layer (not shown in the figure) is further disposed between the first germanium-silicon layer 201 and the top silicon layer 13; the first transition layer is a lightly doped P-type silicon layer; the first germanium-silicon layer 201 is a heavily doped P-type silicon layer; the doping concentration of the first germanium-silicon layer 201 is greater than that of the first transition layer. A second transition layer (not shown in the figure) is also disposed on the side of the first germanium-silicon layer 201 facing away from the first transition layer; the second transition layer is made of silicon. During the epitaxial growth of the first germanium-silicon layer 201, the first germanium-silicon layer 201 containing monocrystalline silicon is formed on the surface of the active region, while the first edge region 91 containing polycrystalline silicon is formed on the surface of the shallow trench isolation region 14.

[0103] In step S202, a dielectric layer 30 is formed on the side of the first germanium-silicon layer 201 facing away from the substrate layer; the dielectric layer 30 includes a stacked first dielectric layer 31, a second dielectric layer 32, and a third dielectric layer 33; the first dielectric layer is relatively close to the first germanium-silicon layer 201. Figure 6 As shown.

[0104] In a specific implementation, the materials of the first dielectric layer 31 and the third dielectric layer 33 are silicon dioxide; the second dielectric layer 32 includes a second polycrystalline silicon layer.

[0105] In step S203, an emitter window 301 is formed by opening a window in the dielectric layer 30. The emitter window 301 penetrates the dielectric layer 30 and exposes the surface of the intrinsic region. A first sidewall protective layer 36 is formed on the sidewall of the emitter window 301, such as... Figure 7 As shown. A first polysilicon layer 40 is formed within the emitter window 301 and on the surface of the dielectric layer 30, as... Figure 8 As shown.

[0106] In specific implementations, the material of the first sidewall protective layer 36 is silicon dioxide. The first polycrystalline silicon layer 40 is formed by in-situ doping or ion implantation doping. The doping type of the first polycrystalline silicon layer 40 is opposite to that of the first germanium-silicon layer 201. In some examples, the material of the first germanium-silicon layer 201 is P-type doped SiGe, and the first polycrystalline silicon layer 40 is N-type doped polycrystalline silicon.

[0107] Step S204: A fourth dielectric layer 34 is formed on the side of the first polysilicon layer 40 facing away from the substrate layer 10, as shown below. Figure 8 As shown; the fourth dielectric layer 34 is bonded to the surface of the first temporary substrate 81 on the side opposite to the first polysilicon layer 40, as... Figure 9 As shown.

[0108] Step S205: Remove the substrate layer 10 and form an initial sacrificial layer 500 on the side of the first germanium-silicon layer 201 opposite to the first polysilicon layer 40, as shown below. Figure 10 and Figure 11 As shown.

[0109] In specific implementation, such as Figure 11 As shown, the substrate silicon 11 is removed by chemical mechanical polishing, dry etching, or wet etching; the buried oxide layer 12 is removed by dry etching or wet etching; and the top silicon 13 is removed by chemical mechanical polishing, dry etching, or wet etching. In some embodiments, the initial sacrificial layer 500 includes a stacked first initial sacrificial layer 501 and a second initial sacrificial layer 502. The first initial sacrificial layer 501 is a silicon nitride film, and the second initial sacrificial layer 502 is a silicon dioxide film, wherein the second initial sacrificial layer 502 is relatively close to the first germanium-silicon layer 201.

[0110] Step S206 involves simultaneously patterning the initial sacrificial layer 500, the first germanium-silicon layer 201, and the first dielectric layer 31 to obtain a sacrificial layer 50 based on the initial sacrificial layer 500, a first base layer 20 based on the first germanium-silicon layer 201, and retaining the width of the side portion of the first dielectric layer 31 of the emitter window. The width of the sacrificial layer 50 is greater than the width of the emitter window 301; the sacrificial layer 50 covers the intrinsic region surface, such as... Figure 12 As shown.

[0111] In a specific implementation, the formed sacrificial layer includes a first sacrificial film layer 51 and a second sacrificial film layer 52 stacked together, wherein the second sacrificial film layer 52 is relatively close to the first germanium-silicon layer 201.

[0112] Step S207, as follows Figure 13 As shown, a second germanium-silicon layer 202 is formed on the side of the first base region layer 20 by selective epitaxy. The thickness of the second germanium-silicon layer 202 is greater than the thickness of the first base region layer 20. The second germanium-silicon layer 202 also covers part of the side of the sacrificial layer 50. The first base region layer 20 and the second germanium-silicon layer 202 together form the initial base region.

[0113] In specific implementation, the process of forming the second germanium-silicon layer 202 includes two stages. In the first stage, the second germanium-silicon layer 202 is formed on the side of the first base region layer 20. The second germanium-silicon layer 202 includes monocrystalline silicon, and the nucleation rate is relatively fast. The formed second germanium-silicon layer 202 also covers a portion of the width of the second dielectric layer 32 (i.e., the second polycrystalline silicon layer) on the side of the first base region layer 20. In the second stage, a second edge region 92 containing polycrystalline silicon is formed on the surface of the remaining second polycrystalline silicon layer (i.e., the second dielectric layer 32).

[0114] Step S208, an isolation layer 35 is formed on the side of the sacrificial layer 50, such as Figure 14 As shown.

[0115] In practice, an initial isolation layer is first formed on the surface and sides of the sacrificial layer 50. The initial isolation layer on top of the sacrificial layer is removed by chemical mechanical polishing, while the initial isolation layer on the sides of the sacrificial layer 50 is retained to form the isolation layer 35. The upper surface of the isolation layer 35 and the upper surface of the sacrificial layer 50 are coplanar.

[0116] Step S209: Remove the sacrificial layer 50 to obtain a current collector groove 60 penetrating the isolation layer 35, as shown below. Figure 15 As shown, a collector region 61 is selectively epitaxially formed within the collector groove 60, such as... Figure 16 As shown.

[0117] In a specific implementation, the material of the collector region 61 is N-type doped silicon grown epitaxially. In some examples, step S211 further includes forming a second sidewall protective layer 37 on the side of the collector region 61 (i.e., the sidewall of the collector groove 60). The second sidewall protective layer 37 includes a silicon dioxide layer and a silicon nitride layer, wherein the silicon nitride layer is located on the side of the silicon dioxide layer that faces away from the collector region 61, that is, the silicon dioxide layer is located on the inside and the silicon nitride layer is located on the outside.

[0118] Step S210: Remove the isolation layer 35 and perform graphical processing on the initial base region to form the base region. The base region 21 includes intrinsic and extrinsic regions, with the extrinsic regions located to the sides of the intrinsic regions, such as... Figure 17 As shown.

[0119] In practice, the width of the base region 21 is greater than the width of the collector region 61; the side of the collector region 61 exposes part of the surface of the base region 21. The intrinsic region is the first base region layer 20, and the non-intrinsic region is the second germanium-silicon layer 202.

[0120] In step S211, a collector 62 is formed on the surface of the collector region 61, and a base 22 is formed on the surface of the base region 21 on the side of the collector region 61; the base 22 and the collector 62 are located on the same side of the base region 21; a collector lead-out structure is formed on the side of the collector 62 facing away from the collector region 61, and a base lead-out structure is formed on the side of the base 22 facing away from the base region 21; a first insulating layer 71 is provided on the sides of the collector lead-out structure and the base lead-out structure, such as... Figure 18 As shown.

[0121] In specific implementation, step S211 further includes forming a third sidewall protective layer 38, 7 on the side of the base region 21. The third sidewall protective layer 38 includes a silicon dioxide layer and a silicon nitride layer, wherein the silicon nitride layer is located on the side of the silicon dioxide layer facing away from the base region 21, that is, the silicon dioxide layer is located on the inner side and the silicon nitride layer is located on the outer side. The base lead-out structure includes a first contact hole 23, a first metal block 24 and a base pad 25; the collector lead-out structure includes a second contact hole 63, a second metal block 64 and a collector pad 65. The first insulating layer 71 is also provided with a barrier layer 70 located between adjacent interconnect layers.

[0122] Step S212: The first polysilicon layer 40 and the third dielectric layer 33 are patterned. The first polysilicon layer 40 and the third dielectric layer 33 outside the intrinsic region are removed, and the first polysilicon layer 40 corresponding to the intrinsic region is retained to form an emitter structure 41. The emitter structure 41 fills the emitter window 301 and covers the side of the emitter window 301. The side of the emitter structure 41 exposes the second dielectric layer 32. The width of the collector region 61 is less than or equal to the width of the emitter structure 41. Figure 19 and Figure 20 As shown.

[0123] In practice, firstly, the collector lead-out structure is bonded to the surface of the second temporary substrate 82; then, the first temporary substrate 81 and the fourth dielectric layer 34 are removed, such as... Figure 19 As shown. Next, using the second dielectric layer 30 as a stop layer, the first polysilicon layer 40 and the third dielectric layer 33 are patterned. The first polysilicon layer 40 outside the intrinsic region is removed, while the first polysilicon layer 40 corresponding to the intrinsic region is retained, forming the emitter structure 41; simultaneously, the third dielectric layer 33 with a portion of the width on the side of the emitter window is retained, as shown. Figure 17 As shown. The formed emitter structure 41 is correspondingly disposed with the collector region 61; the projection of the emitter structure 41 onto the base region 21 covers the projection of the collector region 61 onto the base region 21. The width of the collector region 61 is less than or equal to the width of the emitter structure 41. The doping types of the collector region 61 and the base region 21 are opposite. In some examples, the materials of the first germanium-silicon layer 201 and the second germanium-silicon layer 202 are P-type doped SiGe, that is, the material of the base region 21 is P-type doped SiGe, and the material of the emitter structure 41 is N-type doped polysilicon.

[0124] Step S213, an emitter 42 is formed on the surface of the emitter structure 41, such as Figure 21A and Figure 21B As shown; an emitter lead-out structure is formed on the side of the emitter 42 facing away from the emitter structure 41, and a second insulating layer 72 is provided on the side of the emitter lead-out structure, such as... Figure 19 As shown.

[0125] In a specific implementation, step S213 further includes forming a fourth sidewall protective layer 39 on the side of the emitter structure 41. The fourth sidewall protective layer 39 includes a silicon dioxide layer and a silicon nitride layer, wherein the silicon nitride layer is located on the side of the silicon dioxide layer opposite to the emitter structure 41, that is, the silicon dioxide layer is located on the inner side and the silicon nitride layer is located on the outer side. The emitter 42 covers the surface of the emitter structure 41. Optionally, the emitter 42 also covers the side of the emitter structure 41 that protrudes from the dielectric layer 30. The emitter lead-out structure includes a third contact hole 43, a third metal block 44, and an emitter pad 45. The second insulating layer 72 is also provided with a barrier layer 70 located between adjacent interconnect layers.

[0126] In Example 1, the material of the second polysilicon layer is undoped polysilicon; the base can only be located on the side of the collector region, such as... Figure 21A As shown.

[0127] In Example 2, the material of the second polysilicon layer is P-type doped polysilicon; step S313 further includes: forming a base 22 on the side of the second polysilicon layer opposite to the second germanium-silicon layer; the base 22 is located on the side of the emitter 42; the base 22 and the emitter 42 are located on the same side of the base region 21; the emitter 42 and the collector 62 are respectively located on opposite sides of the base region 21. A base lead-out structure is formed on the surface of the base 22; the base lead-out structure includes a first contact hole 23, a first metal block 24, and a base pad 25; the base lead-out structure is located within the second insulating layer 72, such as... Figure 21B As shown.

[0128] like Figure 22 As shown, the present invention also provides a specific flowchart of another method for preparing a semiconductor structure, including but not limited to steps S301 to S313.

[0129] Steps S301 to S305 are the same as steps S201 to S205, and will not be repeated here. The structure obtained after forming the initial sacrificial layer in step S303 is as follows: Figure 23 As shown.

[0130] Step S306: The initial sacrificial layer is graphically processed, retaining the initial sacrificial layer corresponding to the intrinsic region to form the sacrificial layer. The width of the sacrificial layer 50 is greater than the width of the emitter window 301; the sacrificial layer 50 covers the surface of the intrinsic region, such as... Figure 24 As shown.

[0131] In a specific implementation, the formed sacrificial layer includes a first sacrificial film layer 51 and a second sacrificial film layer 52 stacked together, wherein the second sacrificial film layer 52 is relatively close to the first germanium-silicon layer 201.

[0132] Step S307, as Figure 25 As shown, by selective epitaxy, a second germanium-silicon layer 202 is formed on the surface of the first germanium-silicon layer 201 on the side of the sacrificial layer 50. The second germanium-silicon layer 202 also covers part of the side of the sacrificial layer 50. The first germanium-silicon layer 201 and the second germanium-silicon layer 202 together form the initial base region.

[0133] In a specific implementation, during the epitaxial growth of the second germanium-silicon layer 202, a second germanium-silicon layer 202 containing monocrystalline silicon is formed on the surface of the first germanium-silicon layer 201, while a second edge region 92 containing polycrystalline silicon is formed on the surface of the first edge region 91.

[0134] Step S308, an isolation layer 35 is formed on the side of the sacrificial layer 50, such as Figure 26As shown.

[0135] In practice, an initial isolation layer is first formed on the surface and sides of the sacrificial layer 50. The initial isolation layer on top of the sacrificial layer is removed using a chemical mechanical polishing process, while the initial isolation layer on the sides of the sacrificial layer 50 is retained to form the isolation layer 35. The upper surface of the isolation layer 35 and the upper surface of the sacrificial layer 50 are coplanar.

[0136] Step S309: Remove the sacrificial layer 50 to obtain a current collector groove 60 penetrating the isolation layer 35, as shown below. Figure 27 As shown, a collector region 61 is selectively epitaxially formed within the collector groove 60, such as... Figure 28 As shown.

[0137] In a specific implementation, the material of the collector region 61 is N-type doped silicon grown epitaxially. In some examples, step S211 further includes forming a second sidewall protective layer 37 on the side of the collector region 61 (i.e., the sidewall of the collector groove 60). The second sidewall protective layer 37 includes a silicon dioxide layer and a silicon nitride layer, wherein the silicon nitride layer is located on the side of the silicon dioxide layer that faces away from the collector region 61, that is, the silicon dioxide layer is located on the inner side and the silicon nitride layer is located on the outer side; Step S310: Remove the isolation layer 35 and perform graphical processing on the initial base region to form the base region 21. The base region includes intrinsic and extrinsic regions, with the extrinsic regions located to the sides of the intrinsic regions, such as... Figure 29 As shown.

[0138] In a specific implementation, the width of the base region 21 is greater than the width of the collector region 61; the side of the collector region 61 exposes part of the surface of the base region. The intrinsic region is the first germanium-silicon layer 201, and the non-intrinsic region is the stacked first germanium-silicon layer 201 and second germanium-silicon layer 202.

[0139] In step S311, a collector electrode 62 is formed on the surface of the collector region 61, and a base electrode 22 is formed on the surface of the second germanium-silicon layer 202 on the side of the collector region 61; the base electrode 22 and the collector electrode 62 are located on the same side of the base region 21; a collector electrode lead-out structure is formed on the side of the collector electrode 62 facing away from the collector region 61, and a base electrode lead-out structure is formed on the side of the base electrode 22 facing away from the base region 21; a first insulating layer 71 is provided on the sides of the collector electrode lead-out structure and the base electrode lead-out structure, such as... Figure 30 As shown.

[0140] In specific implementation, step S213 further includes: forming a third sidewall protective layer 38, 7 on the side of the base region 21. The third sidewall protective layer 38 includes a silicon dioxide layer and a silicon nitride layer, wherein the silicon nitride layer is located on the side of the silicon dioxide layer facing away from the base region 21, that is, the silicon dioxide layer is located on the inner side and the silicon nitride layer is located on the outer side. The base lead-out structure includes a first contact hole 23, a first metal block 24 and a base pad 25; the collector lead-out structure includes a second contact hole 63, a second metal block 64 and a collector pad 65, and the first insulating layer 71 is further provided with a barrier layer 70 located between adjacent interconnect layers.

[0141] Step S312: The first polysilicon layer 40 is patterned by removing the first polysilicon layer 40 outside the intrinsic region, retaining the first polysilicon layer 40 corresponding to the intrinsic region to form an emitter structure 41; the emitter structure 41 fills the emitter window 301 and covers the side of the emitter window 301; the side of the emitter structure 41 exposes the second dielectric layer 32; the width of the collector region 61 is less than or equal to the width of the emitter structure 41, such as... Figure 31 and Figure 32 As shown.

[0142] In practice, firstly, the collector lead-out structure is bonded to the surface of the second temporary substrate 82; then, the first temporary substrate 81 and the fourth dielectric layer 34 are removed, such as... Figure 31 As shown. Next, using the third dielectric layer 33 as a stop layer, the first polysilicon layer 40 is patterned, removing the first polysilicon layer 40 outside the intrinsic region, and retaining the first polysilicon layer 40 corresponding to the intrinsic region to form the emitter structure 41, as shown. Figure 32 As shown. The formed emitter structure 41 is correspondingly disposed with the collector region 61; the projection of the emitter structure 41 onto the base region 21 covers the projection of the collector region 61 onto the base region 21. The width of the collector region 61 is less than or equal to the width of the emitter structure 41. The doping types of the collector region 61 and the base region 21 are opposite. In some examples, the materials of the first germanium-silicon layer 201 and the second germanium-silicon layer 202 are P-type doped SiGe, that is, the material of the base region 21 is P-type doped SiGe, and the material of the emitter structure 41 is N-type doped polysilicon.

[0143] Step S313: An emitter 42 is formed on the surface of the emitter structure 41, and an emitter lead-out structure is formed on the side of the emitter 42 facing away from the emitter structure 41. A second insulating layer 72 is provided on the side of the emitter lead-out structure, such as... Figure 32 As shown.

[0144] In a specific implementation, the emitter 42 covers the surface of the emitter structure 41. Optionally, the emitter 42 also covers the side of the emitter structure 41 that protrudes from the dielectric layer 30. The emitter lead-out structure includes a third contact hole 43, a third metal block 44, and an emitter pad 45. The second insulating layer 72 is also provided with a barrier layer 70 located between adjacent interconnect layers.

[0145] The present invention also provides a semiconductor structure, which is prepared by the above-described semiconductor structure preparation method, comprising: a base region 21, including an intrinsic region and an extrinsic region located on the side of the intrinsic region; an emitter structure 41 located on one side surface of the intrinsic region; the material of the emitter structure 41 is polycrystalline silicon; a collector region 61 located on the side surface of the intrinsic region opposite to the emitter structure 41; the width of the collector region 61 is less than or equal to the width of the emitter structure 41, and the side of the collector region 61 exposes the extrinsic region surface.

[0146] The semiconductor structure provided by this invention has an emitter structure and a collector region correspondingly arranged; the width of the collector region is less than or equal to the width of the emitter structure; the projection of the emitter structure onto the base region covers the projection of the collector region onto the base region; this can further reduce the lateral size of the device; at the same time, it can reduce the collector area, making the collector area close to the emitter area, which can further reduce parasitic capacitance and parasitic resistance, thereby improving device performance.

[0147] In the description of this specification, the references to terms such as "this embodiment," "an embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, those skilled in the art can combine and integrate the different embodiments or examples described in this specification and the features of different embodiments or examples without contradiction. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of the present invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0148] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0149] The above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described above, and various obvious changes, readjustments, combinations, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention. The scope of protection of the present invention is determined by the scope of the appended claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, The preparation method includes: A first germanium-silicon layer is formed on one side of the substrate layer, the first germanium-silicon layer including an intrinsic region, and a first polycrystalline silicon layer is formed on the side of the intrinsic region facing away from the substrate layer. Remove the substrate layer, form a sacrificial layer on the side of the intrinsic region opposite to the first polysilicon layer, and form an isolation layer on the side of the sacrificial layer; Remove the sacrificial layer to obtain a current-collecting groove that penetrates the isolation layer, and selectively epitaxially form a current-collecting region within the current-collecting groove; The first polysilicon layer is patterned to form an emitter structure; the width of the collector region is less than or equal to the width of the emitter structure.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The formation of a first polysilicon layer on the side of the intrinsic region opposite to the substrate layer includes: A dielectric layer is formed on the side of the first germanium-silicon layer opposite to the substrate layer; the dielectric layer includes a first dielectric layer, a second dielectric layer and a third dielectric layer stacked together. An emitter window is formed by opening a window in the dielectric layer, the emitter window penetrating the dielectric layer and exposing the surface of the intrinsic region; A first polycrystalline silicon layer is formed within the emitter window and on the surface of the dielectric layer.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that, The second dielectric layer includes a second polysilicon layer; the material of the second polysilicon layer is type-1 doped polysilicon or undoped polysilicon. The material of the first germanium-silicon layer is type-1 doped germanium-silicon; The steps of patterning the first polysilicon layer to form an emitter structure include: The first polysilicon layer and the third dielectric layer are patterned to remove the first polysilicon layer and the third dielectric layer outside the intrinsic region, while retaining the first polysilicon layer corresponding to the intrinsic region to form an emitter structure; the emitter structure fills the emitter window and covers the side of the emitter window; the side of the emitter structure exposes the second dielectric layer.

4. The method for preparing a semiconductor structure according to claim 3, characterized in that, The formation of a sacrificial layer on the side of the intrinsic region opposite to the first polysilicon layer includes: An initial sacrificial layer is formed on the side of the first germanium-silicon layer opposite to the first polycrystalline silicon layer; The initial sacrificial layer, the first germanium-silicon layer, and the first dielectric layer are simultaneously patterned to obtain a sacrificial layer based on the initial sacrificial layer, a first base region layer based on the first germanium-silicon layer, and a first dielectric layer that retains the width of the side portion of the emitter window. The width of the sacrificial layer is greater than the width of the emitter window; the sacrificial layer covers the surface of the intrinsic region.

5. The method for preparing a semiconductor structure according to claim 4, characterized in that, After the sacrificial layer is formed and before the isolation layer is formed, the preparation method further includes: By selective epitaxy, a second germanium-silicon layer is formed on the side of the first base region layer. The thickness of the second germanium-silicon layer is greater than the thickness of the first base region layer. The second germanium-silicon layer also covers part of the side of the sacrificial layer. The first base region layer and the second germanium-silicon layer together form the initial base region. The preparation method further includes: The initial base region is graphically processed to form the base region; A base is formed on the side of the second germanium-silicon layer opposite to the second polysilicon layer, and / or, a base is formed on the side of the second polysilicon layer opposite to the second germanium-silicon layer.

6. The method for preparing a semiconductor structure according to claim 1, characterized in that, The formation of a sacrificial layer on the side of the intrinsic region opposite to the first polysilicon layer includes: An initial sacrificial layer is formed on the side of the first germanium-silicon layer opposite to the first polycrystalline silicon layer; The initial sacrificial layer is graphically processed, and the initial sacrificial layer corresponding to the intrinsic region is retained to form a sacrificial layer.

7. The method for preparing a semiconductor structure according to claim 1, characterized in that, After the sacrificial layer is formed and before the isolation layer is formed, the preparation method further includes: By selective epitaxy, a second germanium-silicon layer is formed on the surface of the first germanium-silicon layer on the side of the sacrificial layer, and the second germanium-silicon layer also covers a portion of the side of the sacrificial layer; the first germanium-silicon layer and the second germanium-silicon layer together form the initial base region; The preparation method further includes: The initial base region is graphically processed to form the base region; A base electrode is formed on the surface of the base region on the side of the collector region; the base electrode is located on the side of the collector region, and the base electrode and the collector region are located on the same side of the base region.

8. The method for preparing a semiconductor structure according to claim 1, characterized in that, After selectively epitaxially forming a current-collecting region within the current-collecting groove, the fabrication method further includes: Forming an initial base region including a first germanium-silicon layer; Remove the isolation layer; perform graphical processing on the initial base region to form a base region; the base region includes the intrinsic region and the non-intrinsic region located on the side of the intrinsic region.

9. The method for preparing a semiconductor structure according to claim 8, characterized in that, Before forming the emitter structure, the method further includes: A collector electrode is formed on the surface of the collector region facing away from the intrinsic region; a collector electrode lead-out structure is formed on the side of the collector electrode facing away from the collector region; a first insulating layer is provided on the side of the collector electrode lead-out structure; After forming the emitter structure, the method further includes: An emitter is formed on the surface of the emitter structure facing away from the intrinsic region; the emitter and the collector are respectively located on opposite sides of the base region; an emitter lead-out structure is formed on the side of the emitter facing away from the emitter structure, and a second insulating layer is provided on the side of the emitter lead-out structure.

10. A semiconductor structure, characterized in that, It is prepared by the method for preparing the semiconductor structure according to any one of claims 1 to 9.

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