Semiconductor device and method of manufacturing the same, electronic device
By forming enclosed source-drain and fully enclosed gate structures in vertically stacked two-dimensional material transistors, the problem of high contact resistance between metal and two-dimensional materials is solved, thereby improving device performance and miniaturization capabilities.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- BEIJING SUPERSTRING ACAD OF MEMORY TECH
- Filing Date
- 2025-01-13
- Publication Date
- 2026-07-14
AI Technical Summary
In vertically stacked two-dimensional material transistors, the resistance of the metal-two-dimensional material contact is relatively large, which severely restricts the device performance, and the surrounding contact process is quite difficult to achieve.
By forming a multilayer sacrificial structure and a channel structure on a substrate, a surround-type contact source and drain electrode is formed. In a subsequent process, the sacrificial structure is removed to expose the outer peripheral surface of the channel structure, forming a fully surround-type gate structure, thus realizing a metal-two-dimensional material surround-type contact.
It effectively reduces contact resistance, improves the performance of semiconductor devices, and is conducive to the miniaturization of devices.
Smart Images
Figure CN122395975A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor device technology, and more specifically, to a semiconductor device and its manufacturing method, and an electronic device. Background Technology
[0002] With the development of integrated circuit technology, the critical dimensions of semiconductor devices are shrinking, and the types and number of semiconductor devices contained in a single chip are increasing, which means that any slight difference in the manufacturing process can affect the performance of semiconductor devices.
[0003] To minimize product costs, the goal is to fabricate as many semiconductor devices as possible on a substrate with limited area. Since the advent of Moore's Law, the industry has proposed various structural designs and process optimizations for semiconductor devices to meet current product demands. Summary of the Invention
[0004] This application addresses the shortcomings of existing methods by proposing a semiconductor device, its manufacturing method, and an electronic device, which can effectively improve the performance of the semiconductor device.
[0005] In a first aspect, embodiments of this application provide a method for manufacturing a semiconductor device, comprising: A multilayer sacrificial structure and a channel structure located between adjacent sacrificial structures are formed on a substrate; the middle part of the channel structure is connected to the sacrificial structure, and along a first direction parallel to the substrate, the first peripheral part and the second peripheral part at both ends of the middle part protrude from the sacrificial structure; the material of the channel structure includes a metal compound. A first source / drain and a second source / drain are formed, each covering the end of the first peripheral portion of the multilayer channel structure and at least part of the upper and lower surfaces, and covering the end of the second peripheral portion of the multilayer channel structure and at least part of the upper and lower surfaces. Remove the sacrificial structure to expose the circumference of the middle section; A gate dielectric structure and a gate are formed that sequentially surround the peripheral surface of the middle part.
[0006] In some possible embodiments, a multilayer sacrificial structure and a channel structure located between adjacent sacrificial structures are formed on the substrate, including: Alternating sacrificial layers and channel layers are formed on the substrate, and a sacrificial layer and a hard mask structure are formed sequentially on the topmost channel layer; Based on the hard mask structure, the sacrificial layer and the channel layer are self-aligned and etched to form a transition sacrificial structure and a channel structure with the same pattern as the hard mask structure. The transverse etching transition sacrificial structure is formed by forming a sacrificial structure along a first direction parallel to the substrate, such that both the first peripheral portion and the second peripheral portion protrude from the sacrificial structure.
[0007] In some possible embodiments, forming a first source / drain and a second source / drain includes: A first contact electrode is formed on the upper and lower surfaces of the first peripheral portion of the multilayer, and a second contact electrode is formed on the upper and lower surfaces of the second peripheral portion of the multilayer. A first metal layer is formed covering multiple layers of a first peripheral portion and a first contact electrode, and a second metal layer is formed covering multiple layers of a second peripheral portion and a second contact electrode; the first source / drain electrode includes the first metal layer and the first contact electrode, and the second source / drain electrode includes the second metal layer and the second contact electrode.
[0008] In some possible embodiments, a first contact electrode is formed on the upper and lower surfaces of the multilayer first periphery, including: First contact electrodes are deposited on the upper and lower surfaces of the multilayer first peripheral portion.
[0009] In some possible embodiments, a first contact electrode is formed on the upper and lower surfaces of the multilayer first periphery, including: Laser processing is used to form dangling bonds on the surface of the multilayer first peripheral portion; the dangling bonds are used as nucleation points to grow the first contact electrode; the material of the channel structure includes a transition metal chalcogenide; the material of the first contact electrode includes a conductive metal compound.
[0010] In some possible embodiments, a first metal layer is formed covering multiple layers of the first peripheral portion and the first contact electrode, including: A conformal insulating layer is formed covering the multi-layer sacrificial structure, the first peripheral portion, and the first contact electrode; Based on the hard mask structure, self-aligned etching is used to remove the isolation layer covering the first peripheral portion and the side of the first contact electrode of each layer. A first metal layer is formed covering the first peripheral portion of each layer and the side of the first contact electrode.
[0011] In some possible embodiments, forming a first source / drain and a second source / drain includes: Forming a conformal layer covering multiple layers of the first peripheral portion, the second peripheral portion, and the sacrificial structure; Etch the spacer layer to expose at least a portion of the first and second peripheral portions; A conformal covering spacer layer and an intercalation layer of at least a portion of the first peripheral portion and a first metal layer are formed sequentially; and a conformal covering spacer layer and an intercalation layer of at least a portion of the second peripheral portion and a second metal layer are formed sequentially. Based on the annealing process, the intercalation is decomposed and combined with the upper surface, end face and lower surface of the multilayer first peripheral portion to form a multilayer first contact electrode, and combined with the upper surface, end face and lower surface of the multilayer second peripheral portion to form a multilayer second contact electrode; the first source and drain electrode includes a first metal layer and a first contact electrode, and the second source and drain electrode includes a second metal layer and a second contact electrode.
[0012] In some possible embodiments, the intercalation material includes selenium, cobalt, or copper.
[0013] Secondly, embodiments of this application provide a semiconductor device, including: Multi-layered channel structure; the channel structure includes a central section and a first peripheral section and a second peripheral section located at both ends of the central section; the material of the channel structure includes metal compounds; First source and drain electrodes, the first source and drain electrodes cover the end of the first peripheral portion of the multilayer channel structure and at least part of the upper and lower surfaces, and the second source and drain electrodes cover the end of the second peripheral portion of the multilayer channel structure and at least part of the upper and lower surfaces. A multilayer gate dielectric structure and a gate are arranged sequentially around the central peripheral surface.
[0014] In some possible embodiments, the first source and drain include: The multilayer first contact electrode is in contact with the upper and lower surfaces of the multilayer first peripheral portion; A first metal layer covers multiple layers of the first peripheral portion and the first contact electrode; The second source drain includes: The multilayer second contact electrode is in contact with the upper and lower surfaces of the multilayer second peripheral portion; A second metal layer covers multiple layers of the second peripheral portion and the second contact electrode.
[0015] In some possible embodiments, the first source and drain include: The multilayer first contact electrode is formed by the upper surface, end face and lower surface of the multilayer first peripheral portion; A first metal layer covers multiple layers of first contact electrodes; The second source drain includes: The multilayer second contact electrode is formed by the upper surface, end face and lower surface of the multilayer second peripheral portion; A second metal layer covers multiple layers of second contact electrodes.
[0016] Thirdly, embodiments of this application also provide an electronic device, including: a semiconductor device manufactured by any of the semiconductor device manufacturing methods provided in the first aspect above, or any of the semiconductor devices provided in the second aspect above.
[0017] The beneficial technical effects of the technical solutions provided in this application include: The multilayered stacked channel structures are separated by sacrificial structures, and the first and second peripheral portions at both ends of each channel structure protrude from the sacrificial structure, suspended relative to the substrate. This facilitates the formation of a first source / drain electrode that surrounds the upper, lower, and end surfaces of the first peripheral portion, and a second source / drain electrode that surrounds the upper, lower, and end surfaces of the second peripheral portion. Furthermore, the sacrificial structures can be removed in subsequent processes, exposing the outer peripheral surface of the middle portion of the channel structure. A gate dielectric structure and a gate electrode are then formed sequentially around the middle portion in the area previously occupied by the sacrificial structure, forming a fully enclosed gate structure. In the vertically stacked two-dimensional material transistor manufactured according to the embodiments of this application, the first and second source / drain electrodes each form an enclosed contact with the channel structure, effectively reducing contact resistance, improving the performance of the semiconductor device, and contributing to the miniaturization of semiconductor devices.
[0018] Additional aspects and advantages of this application will be set forth in part in the description which follows, and will become apparent from the description or may be learned by practice of this application. Attached Figure Description
[0019] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein: Figure 1 A schematic flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this application; Figure 2 This is a schematic diagram of the film structure after alternatingly stacked sacrificial layer 102 and channel layer 201 are formed on substrate 100, and sacrificial layer 102 and hard mask structure 700 are sequentially formed on the uppermost channel layer 201, according to a semiconductor device manufacturing method provided in this application. Figure 3 This is a schematic diagram of the film structure after forming a transition sacrificial structure 103 and a channel structure 200 with the same pattern as the hard mask structure 700 in a semiconductor device manufacturing method provided in this application embodiment. Figure 4 A schematic diagram of the film structure after lateral etching of the transition sacrificial structure 103 in a semiconductor device manufacturing method provided in this application embodiment; Figure 5 This is a schematic diagram of the film structure after forming the first contact electrode 310 and the second contact electrode 410 in a method for manufacturing a semiconductor device according to an embodiment of this application. Figure 6 This is a schematic diagram of the film structure after the isolation layer 800 is formed in a method for manufacturing a semiconductor device according to an embodiment of this application. Figure 7 This is a schematic diagram of the film structure after self-aligned etching removes the isolation layer 800 covering the first peripheral portion 220 and the side of the first contact electrode 310 in a semiconductor device manufacturing method provided in this application embodiment. Figure 8 A schematic diagram of the film structure after forming a first metal layer 320 covering the first peripheral portion 220 and the side surface of the first contact electrode 310 in a semiconductor device manufacturing method provided in this application embodiment; Figure 9 This is a schematic diagram of the film structure after filling the dielectric layer 105 in a method for manufacturing a semiconductor device according to an embodiment of this application. Figure 10 This is a schematic diagram of the film structure after removing the sacrificial structure 101 in a method for manufacturing a semiconductor device according to an embodiment of this application. Figure 11 This is a schematic diagram of the film structure after forming the gate dielectric structure 500 and the gate 600 in a method for manufacturing a semiconductor device according to an embodiment of this application. Figure 12 A schematic diagram of the film structure after forming the spacer layer 900 in another method for manufacturing a semiconductor device provided in this application embodiment; Figure 13 A schematic diagram of the film structure after etching the spacer layer 900 in another method for manufacturing a semiconductor device provided in this application embodiment; Figure 14 A schematic diagram of the film structure after intercalation 104 is formed in another method for manufacturing a semiconductor device provided in this application embodiment; Figure 15 A schematic diagram of the film structure after forming the first metal layer 320 and the second metal layer 420 in another semiconductor device manufacturing method provided in this application embodiment; Figure 16 A schematic diagram of the film structure after forming the first contact electrode 310 and the second contact electrode 410 in another semiconductor device manufacturing method provided in this application embodiment; Figure 17 A schematic diagram of the film structure after filling the dielectric layer 105 in another method for manufacturing a semiconductor device provided in this application embodiment; Figure 18 A schematic diagram of the film structure after removing the sacrificial structure 101 in another method for manufacturing a semiconductor device provided in this application embodiment; Figure 19 A schematic diagram of the film structure after forming the gate dielectric structure 500 and the gate 600 in another method for manufacturing a semiconductor device provided in this application embodiment; Figure label: 100 - Substrate; 101 - Sacrificial structure; 102 - Sacrificial layer; 103 - Transition sacrificial structure; 104 - Intercalation layer; 105 - Dielectric layer; 200 - Channel structure; 210 - Middle section; 220 - First peripheral section; 230 - Second peripheral section; 201 - Channel layer; 300 - First source / drain electrode; 310 - First contact electrode; 320 - First metal layer; 400 - Second source / drain electrode; 410 - Second contact electrode; 420 - Second metal layer; 500 - Gate dielectric structure; 600 - Gate; 700 - Hard mask structure; 800 - Isolation layer; 900 - Spacer layer. Detailed Implementation
[0020] The embodiments of this application are described below with reference to the accompanying drawings. It should be understood that the embodiments described below with reference to the accompanying drawings are exemplary descriptions for explaining the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions of the embodiments of this application.
[0021] Those skilled in the art will understand that, unless specifically stated otherwise, the terms "described" and "the" as used herein may also include plural forms. It should be further understood that the term "comprising" as used in this application's specification means the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude implementations of other features, information, data, steps, operations, elements, components, and / or combinations thereof supported by this art. It should be understood that when we say an element is "connected" or "coupled" to another element, the element may be directly connected or coupled to the other element, or it may mean that the element and the other element are connected through an intermediate element. Furthermore, "connected" or "coupled" as used herein may include wireless connections or wireless coupling. The term "and / or" as used herein refers to at least one of the items defined by the term; for example, "A and / or B" may be implemented as "A," or as "B," or as "A and B."
[0022] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.
[0023] The research and development concept of this application includes: vertically stacked nanosheet transistors are a type of field-effect transistor, which adopt a fully enclosed gate structure and vertically stack multiple nanowire transistors.
[0024] Vertically stacked nanosheet transistors include vertically stacked two-dimensional material transistors, which use two-dimensional materials to make vertically stacked nanosheets as the channel of the transistor, with the source and drain of metal materials connected at both ends respectively.
[0025] However, due to Fermi level pinning and Schottky barrier, the resistance of the metal-two-dimensional material contact is relatively large, which severely restricts the performance of vertically stacked two-dimensional material transistors.
[0026] In related technologies, the contact methods between metals and two-dimensional materials can be broadly classified into three types: (1) Partial top contact, the source and drain are located at the top of the channel, so that the metal material is in partial top contact with the two-dimensional material.
[0027] (2) Edge contact: The source and drain are located at both ends of the channel, so that the metal material and the two-dimensional material are in edge contact.
[0028] (3) Enclosed contact, where the source and drain surround the edge and part of the top of the channel, so that the metal material surrounds the two-dimensional material.
[0029] Related research indicates that using enveloping contacts to address lattice damage and ohmic contact issues at the metal-two-dimensional semiconductor interface can effectively reduce contact resistance.
[0030] However, in vertically stacked two-dimensional material transistors, the fabrication of enclosed contacts is quite difficult.
[0031] The semiconductor devices, manufacturing methods, and electronic devices provided in this application are intended to solve the aforementioned technical problems in related technologies.
[0032] The technical solution of this application and how it solves the above-mentioned technical problems are described in detail below with specific embodiments. It should be noted that the following embodiments can be referenced, borrowed, or combined with each other, and the same terms, similar features, and similar implementation steps in different embodiments will not be described again.
[0033] This application provides a method for manufacturing a semiconductor device, the process flow diagram of which is shown below. Figure 1 As shown, the method includes steps S101-S104: S101: A multilayer sacrificial structure 101 and a channel structure 200 located between adjacent sacrificial structures 101 are formed on a substrate 100; the middle portion 210 of the channel structure 200 is connected to the sacrificial structure 101, and the first peripheral portion 220 and the second peripheral portion 230 at both ends of the middle portion 210 protrude from the sacrificial structure 101 along a first direction parallel to the substrate 100; the material of the channel structure 200 includes a metal compound.
[0034] Optionally, a schematic diagram of the membrane structure after step S101 is shown below. Figure 4 As shown.
[0035] S102: Form a first source-drain electrode 300 and a second source-drain electrode 400, each covering the end of the first peripheral portion 220 of the multilayer channel structure 200 and at least part of the upper and lower surfaces, and covering the end of the second peripheral portion 230 of the multilayer channel structure 200 and at least part of the upper and lower surfaces.
[0036] Optionally, a schematic diagram of the membrane structure after step S102 is shown below. Figure 8 or Figure 16 As shown.
[0037] S103: Remove the sacrificial structure 101 to expose the circumferential surface of the middle part 210.
[0038] Optionally, a schematic diagram of the membrane structure after step S103 is shown below. Figure 10 or Figure 18 As shown.
[0039] S104: A gate dielectric structure 500 and a gate 600 are formed to sequentially surround the peripheral surface of the central portion 210.
[0040] Optionally, a schematic diagram of the membrane structure after step S104 is shown below. Figure 11 or Figure 19 As shown.
[0041] In this embodiment, the multilayer stacked channel structures 200 are spaced apart by sacrificial structures 101, and the first peripheral portion 220 and the second peripheral portion 230 at both ends of each channel structure 200 protrude from the sacrificial structure 101 and are suspended relative to the substrate 100. This allows the formation of a first source / drain electrode 300 that surrounds the upper surface, lower surface, and end of the first peripheral portion 220, and a second source / drain electrode 400 that surrounds the upper surface, lower surface, and end of the second peripheral portion 230. Furthermore, the sacrificial structure 101 is removed in a subsequent process, thereby exposing the outer peripheral surface of the middle portion 210 of the channel structure 200. A gate dielectric structure 500 and a gate 600 are formed sequentially around the middle portion 210 in the area where the sacrificial structure 101 was previously located, forming a fully enclosed gate structure. In the vertically stacked two-dimensional material transistor manufactured according to the embodiments of this application, the first source / drain 300 and the second source / drain 400 each form an enclosing contact with the first peripheral portion 220 and the second peripheral portion 230 of the channel structure 200, which can effectively reduce contact resistance, improve the performance of the semiconductor device, and facilitate the miniaturization of the semiconductor device. It can be understood that the end, upper surface, and lower surface of the first peripheral portion 220 refer to the end face of the first peripheral portion 220 away from the middle portion 210, the surface of the first peripheral portion 220 away from the substrate 100, and the surface of the first peripheral portion 220 facing the substrate 100, respectively, in the upright state during the manufacturing process of the semiconductor device.
[0042] Similarly, the end, upper surface, and lower surface of the second peripheral portion 230 refer to the end face of the second peripheral portion 230 away from the middle portion 210, the surface of the second peripheral portion 230 away from the substrate 100, and the surface of the second peripheral portion 230 facing the substrate 100 in the upright state during the manufacturing process of the semiconductor device.
[0043] In some possible embodiments, the step S101 described above, which involves forming a multilayer sacrificial structure 101 on the substrate 100 and a channel structure 200 located between adjacent sacrificial structures 101, includes: Alternating sacrificial layers 102 and channel layers 201 are formed on substrate 100, and a sacrificial layer 102 and a hard mask structure 700 are sequentially formed on the uppermost channel layer 201. Optionally, a schematic diagram of the film structure obtained after this step is shown below. Figure 2 As shown.
[0044] Based on the hard mask structure 700, the sacrificial layer 102 and the channel layer 201 are self-aligned and etched to form a transition sacrificial structure 103 and a channel structure 200 with the same pattern as the hard mask structure 700. Optionally, a schematic diagram of the film structure obtained after this step is shown below. Figure 3 As shown.
[0045] The transverse etching transition sacrificial structure 103 forms a sacrificial structure 101 along a first direction parallel to the substrate 100, such that both the first peripheral portion 220 and the second peripheral portion 230 protrude from the sacrificial structure 101. Optionally, a schematic diagram of the film structure obtained after this step is shown below. Figure 4 As shown.
[0046] In this embodiment, in the stacked layers formed on the substrate 100, the channel layer 201 is sandwiched between upper and lower sacrificial layers 102, and a patterned hard mask structure 700 is formed on the uppermost sacrificial layer 102. The pattern of the hard mask structure 700 is transferred to the lower stacked layers to form a transition sacrificial structure 103 and a channel structure 200. The transition sacrificial structure 103 is laterally etched so that the first peripheral portion 220 and the second peripheral portion 230 both protrude from the sacrificial structure 101 and are in a suspended state, exposing their ends, upper surface and lower surface, which facilitates the formation of enclosing contacts with the first source / drain electrode 300 and the second source / drain electrode 400 respectively.
[0047] It is understandable that if a multi-layered channel structure 200 is stacked on the substrate 100, then the first peripheral portion 220, the second peripheral portion 230, and the middle portion 210 also have multiple layers.
[0048] In some possible embodiments, the formation of the first source / drain 300 and the second source / drain 400 in step S102 above includes the following steps: A first contact electrode 310 is formed on the upper and lower surfaces of the multilayer first peripheral portion 220, and a second contact electrode 410 is formed on the upper and lower surfaces of the multilayer second peripheral portion 230. Optionally, a schematic diagram of the film structure obtained after this step is shown below. Figure 5 As shown.
[0049] In this embodiment, a first contact electrode 310 is formed on both the upper and lower surfaces of the exposed first peripheral portion 220 of each layer, such that the end of the edge of the first contact electrode 310 is flush with the end of the edge of the first peripheral portion 220. Similarly, a second contact electrode 410 is formed on both the upper and lower surfaces of the exposed second peripheral portion 230 of each layer, such that the end of the edge of the second contact electrode 410 is flush with the end of the edge of the second peripheral portion 230.
[0050] In some possible embodiments, forming the first contact electrode 310 on the upper and lower surfaces of the multilayer first peripheral portion 220 in the above steps includes: depositing the first contact electrode 310 on the upper and lower surfaces of the multilayer first peripheral portion 220.
[0051] In this embodiment, the first contact electrode 310 can be deposited directly on the upper and lower surfaces of the multilayer first peripheral portion 220 by deposition. The manufacturing process is mature and the yield rate is high.
[0052] Similarly, in some possible embodiments, forming the second contact electrode 410 on the upper and lower surfaces of the multilayer second peripheral portion 230 in the above steps includes: depositing the second contact electrode 410 on the upper and lower surfaces of the multilayer second peripheral portion 230.
[0053] In this embodiment, the second contact electrode 410 can be deposited directly on the upper and lower surfaces of both sides of the multilayer second peripheral portion 230 by deposition. The manufacturing process is mature and the yield is high.
[0054] For example, the first contact electrode 310 and the second contact electrode 410 formed by deposition may include materials such as platinum ditelluride, vanadium ditelluride, niobium ditelluride or tantalum ditelluride.
[0055] In some possible embodiments, forming the first contact electrode 310 on the upper and lower surfaces of the multilayer first peripheral portion 220 in the above steps includes: forming dangling bonds on the surface of the multilayer first peripheral portion 220 by laser processing; growing the first contact electrode 310 using the dangling bonds as nucleation points; the material of the channel structure 200 includes a transition metal chalcogenide; and the material of the first contact electrode 310 includes a conductive metal compound.
[0056] In some possible embodiments, forming the second contact electrode 410 on the upper and lower surfaces of the multilayer second peripheral portion 230 in the above steps includes: forming dangling bonds on the surface of the multilayer second peripheral portion 230 by laser processing; growing the second contact electrode 410 using the dangling bonds as nucleation points; the material of the channel structure 200 includes a transition metal chalcogenide; and the material of the second contact electrode 410 includes a conductive metal compound.
[0057] In this embodiment, laser processing technology can be used to form dangling bonds on the surfaces of the multilayer first peripheral portion 220 and second peripheral portion 230. These dangling bonds can serve as nucleation points for growing conductive first contact electrodes 310 and second contact electrodes 410, which can improve the contact quality of the metal-two-dimensional material interface, reduce contact resistance, and thus improve device performance.
[0058] Optionally, the two-dimensional material includes compounds containing transition metal elements such as molybdenum (Mo) and tungsten (W) and chalcogen elements such as sulfur (S), selenium (Se), or tellurium (Te), such as molybdenum disulfide and tungsten diselenide. These compounds typically have a layered structure, with each layer consisting of alternating metal atoms and chalcogen element atoms. Using lasers of different wavelengths focused onto the first peripheral portion 220 and the second peripheral portion 230 of the two-dimensional material, the high-energy laser causes localized sulfur (S), selenium (Se), or tellurium (Te) defects, exposing dangling bonds. Then, a conductive first contact electrode 310 and a second contact electrode 410 (such as vanadium diselenide, nickel distelluride, cobalt distelluride, niobium distelluride, or vanadium disulfide, etc.) are grown using chemical vapor deposition.
[0059] Optionally, the first contact electrode 310 and the second contact electrode 410 can be manufactured in the same process step.
[0060] A first metal layer 320 is formed covering multiple layers of the first peripheral portion 220 and the first contact electrode 310, and a second metal layer 420 is formed covering multiple layers of the second peripheral portion 230 and the second contact electrode 410; the first source / drain electrode 300 includes the first metal layer 320 and the first contact electrode 310, and the second source / drain electrode 400 includes the second metal layer 420 and the second contact electrode 410. Optionally, the schematic diagram of the film structure obtained after this step is shown below. Figure 8 As shown.
[0061] In this embodiment, a first metal layer 320 is formed, which can simultaneously cover the edges of the multiple layers of first contact electrodes 310 and the edges of the multiple layers of first peripheral portions 220. Therefore, the upper and lower surfaces of the first peripheral portions 220 are covered by the first contact electrodes 310, and the ends of the first peripheral portions 220 are covered by the first metal layer 320. The first source / drain electrode 300 formed by the first metal layer 320 and the first contact electrodes 310 forms an enclosing contact with the first peripheral portions 220. Similarly, a second metal layer 420 is formed, which can simultaneously cover the edges of the multiple layers of second contact electrodes 410 and the edges of the multiple layers of second peripheral portions 230. Therefore, the upper and lower surfaces of the second peripheral portions 230 are covered by the second contact electrodes 410, and the ends of the second peripheral portions 230 are covered by the second metal layer 420. The second source / drain electrode 400 formed by the second metal layer 420 and the second contact electrodes 410 forms an enclosing contact with the second peripheral portions 230.
[0062] Optionally, the first metal layer 320 and the second metal layer 420 can be manufactured in the same process step.
[0063] In some possible embodiments, forming the first metal layer 320 covering the multilayer first peripheral portion 220 and the first contact electrode 310 in the above steps includes: An insulating layer 800 is formed, conformally covering the multilayer sacrificial structure 101, the first peripheral portion 220, and the first contact electrode 310. Optionally, a schematic diagram of the film structure obtained after this step is shown below. Figure 6 As shown.
[0064] Based on the hard mask structure 700, self-aligned etching is used to remove the isolation layer 800 covering the first peripheral portion 220 and the side surface of the first contact electrode 310 of each layer. Optionally, the schematic diagram of the film structure obtained after this step is shown below. Figure 7 As shown.
[0065] A first metal layer 320 is formed, covering the first peripheral portion 220 of each layer and the side surface of the first contact electrode 310. Optionally, a schematic diagram of the film structure obtained after this step is shown below. Figure 8 As shown.
[0066] In this embodiment, before manufacturing the first metal layer 320, an isolation layer 800 is used to cover the sacrificial structure 101 to isolate the sacrificial structure 101 from the subsequently formed first metal layer 320, ensuring that the gate dielectric structure 500 and gate 600 formed after removing the sacrificial structure 101 are insulated from the first metal layer 320.
[0067] In some possible embodiments, forming a second metal layer 420 covering multiple layers of the second peripheral portion 230 and the second contact electrode 410 in the above steps includes: An isolation layer 800 is formed to cover the conformal multilayer sacrificial structure 101, the second peripheral portion 230, and the second contact electrode 410.
[0068] Based on the hard mask structure 700, self-aligned etching is used to remove the isolation layer 800 covering the second peripheral portion 230 and the side of the second contact electrode 410 of each layer.
[0069] A second metal layer 420 is formed covering the second peripheral portion 230 and the side of the second contact electrode 410 of each layer.
[0070] In this embodiment, before manufacturing the second metal layer 420, an isolation layer 800 is used to cover the sacrificial structure 101 to isolate the sacrificial structure 101 from the subsequently formed second metal layer 420, ensuring that the gate dielectric structure 500 and gate 600 formed after removing the sacrificial structure 101 are insulated from the second metal layer 420.
[0071] In some possible embodiments, before removing the sacrificial structure 101 in step S103 to expose the peripheral surface of the intermediate portion 210, the method further includes: Figure 9 As shown, a filling dielectric layer 105 covers the first metal layer 320 and the second metal layer 420; the hard mask structure 700 is removed to expose the sacrificial structure 101.
[0072] The hard mask structure 700 provided in this application embodiment can be used for patterning the sacrificial layer 102 and the channel layer 201, can be used for self-aligned etching of the first metal layer 320 and the second metal layer 420, and can also serve as a protective layer for the sacrificial structure 101. It can simplify the film structure design, reduce costs, and improve production efficiency.
[0073] Next, as Figure 10 As shown, the sacrificial structure 101 is removed, exposing the peripheral surface of the middle part 210.
[0074] Then, as Figure 11 As shown, a gate dielectric structure 500 and a gate 600 are formed sequentially around the peripheral surface of the central portion 210 to form a transistor structure.
[0075] This application also provides another method for manufacturing a semiconductor device. The following describes another method for manufacturing a semiconductor device in detail with reference to the accompanying drawings.
[0076] In another semiconductor device manufacturing method provided in this application embodiment, step S101 is the same as or similar to the previous semiconductor device manufacturing method, and will not be described again here.
[0077] In some possible embodiments, the formation of the first source / drain 300 and the second source / drain 400 in step S102 above includes the following steps: A spacer layer 900 is formed, conformally covering multiple layers of the first peripheral portion 220, the second peripheral portion 230, and the sacrificial structure 101. Optionally, a schematic diagram of the membrane structure obtained after this step is shown below. Figure 12 As shown.
[0078] The spacer layer 900 is etched to expose at least a portion of the first peripheral portion 220 and the second peripheral portion 230. Optionally, a schematic diagram of the film structure obtained after this step is shown below. Figure 13 As shown.
[0079] A conformal covering spacer layer 900 and an intercalation layer 104 covering at least a portion of the first peripheral portion 220, and a first metal layer 320 are sequentially formed. Then, a conformal covering spacer layer 900 and an intercalation layer 104 covering at least a portion of the second peripheral portion 230, and a second metal layer 420 are sequentially formed. Optionally, a schematic diagram of the film structure obtained after this step is shown below. Figures 14-15 As shown.
[0080] Based on the annealing process, the intercalation layer 104 is decomposed and bonded to the upper surface, end face, and lower surface of the multilayer first peripheral portion 220 to form a multilayer first contact electrode 310, and bonded to the upper surface, end face, and lower surface of the multilayer second peripheral portion 230 to form a multilayer second contact electrode 410; the first source / drain electrode 300 includes a first metal layer 320 and a first contact electrode 310, and the second source / drain electrode 400 includes a second metal layer 420 and a second contact electrode 410. Optionally, the schematic diagram of the film structure obtained after this step is shown below. Figure 16 As shown.
[0081] Optionally, in this embodiment, a spacer layer 900 may be grown on the surfaces of the multilayer first peripheral portion 220, the second peripheral portion 230, and the sacrificial structure 101. In this embodiment, the spacer layer 900 may be etched such that at least a portion of the upper and lower surfaces of the first peripheral portion 220 and at least a portion of the upper and lower surfaces of the second peripheral portion 230 are exposed in the spacer layer 900, and the spacer layer 900 always covers the sacrificial structure 101. In this embodiment, an intercalation layer 104 and a first metal layer 320 are sequentially deposited on the exposed surfaces of the spacer layer 900 and the first peripheral portion 220, and an intercalation layer 104 and a second metal layer 420 are sequentially deposited on the exposed surfaces of the spacer layer 900 and the second peripheral portion 230.
[0082] In this embodiment, at a certain temperature, the intercalation layer 104 decomposes, introducing the resulting guest molecules into the two-dimensional material layers such as the first peripheral portion 220 and the second peripheral portion 230. Utilizing the weak van der Waals forces between the two-dimensional material layers, the guest molecules diffuse rapidly between the layers, thereby altering the physical and chemical properties of the two-dimensional material, such as conductivity, to form a multilayer first contact electrode 310 and a multilayer second contact electrode 410. Therefore, the first metal layer 320 contacts the channel structure 200 through the first contact electrode 310, and the second metal layer 420 contacts the channel structure 200 through the second contact electrode 410. This improves the contact quality of the metal-two-dimensional material interface, reduces contact resistance, and thus enhances device performance.
[0083] Optionally, the material of the intercalation 104 may include selenium, which can be decomposed and removed at a temperature of about 150 degrees Celsius. The decomposed material is combined with the two-dimensional material to form the first contact electrode 310 and the second contact electrode 410.
[0084] Optionally, the material of the intercalation 104 may include metal materials such as cobalt and copper, which can induce the two-dimensional material to transform into a metallic state under certain temperature conditions to form the first contact electrode 310 and the second contact electrode 410.
[0085] After forming the first source / drain 300 and the second source / drain 400, similar to the manufacturing method of the previous semiconductor device, the process also includes: Figure 17 As shown, a filling dielectric layer 105 covers the first metal layer 320 and the second metal layer 420; the hard mask structure 700 is removed to expose the sacrificial structure 101.
[0086] Next, as Figure 18 As shown, the sacrificial structure 101 is removed, exposing the peripheral surface of the middle part 210.
[0087] Then, as Figure 19 As shown, a gate dielectric structure 500 and a gate 600 are formed sequentially around the peripheral surface of the central portion 210 to form a transistor structure.
[0088] It should be noted that, in the embodiments of this application, the structure of each film layer of the semiconductor device can be patterned by a patterning process to manufacture each corresponding film layer.
[0089] It should be noted that the "patterning process" mentioned in the embodiments of this application includes processes such as depositing film layers, coating photoresist, mask exposure, development, etching, and photoresist stripping, which are mature fabrication processes in related technologies. The "photolithography process" mentioned in the embodiments of this application includes processes such as coating film layers, mask exposure, and development, which are mature fabrication processes in related technologies. Deposition can employ known processes such as sputtering, evaporation, and chemical vapor deposition; coating can employ known coating processes; and etching can employ known methods; no specific limitations are made here.
[0090] In the description of the embodiments of this application, it should be understood that a "layer" refers to a thin film of a certain material manufactured on a substrate 100 using a deposition or coating process. If the thin film does not require a patterning process or photolithography process during the entire manufacturing process, the thin film can also be called a layer. If the thin film requires a patterning process or photolithography process during the entire manufacturing process, it can be called a thin film before the patterning process and a layer after the patterning process. The "layer" after the patterning process or photolithography process contains at least one "pattern".
[0091] Based on the same inventive concept, such as Figure 11 or Figure 19 As shown, this application provides a semiconductor device, including: The multi-layer channel structure 200 includes a middle portion 210 and a first peripheral portion 220 and a second peripheral portion 230 located at both ends of the middle portion 210; the material of the channel structure 200 includes a metal compound.
[0092] A first source / drain 300 and a second source / drain 400, wherein the first source / drain 300 covers the end of the first peripheral portion 220 of the multilayer channel structure 200 and at least part of the upper and lower surfaces, and the second source / drain 400 covers the end of the second peripheral portion 230 of the multilayer channel structure 200 and at least part of the upper and lower surfaces.
[0093] The multilayer gate dielectric structure 500 and the gate 600 are sequentially surrounded on the peripheral surface of the middle portion 210.
[0094] In the vertically stacked two-dimensional material transistor manufactured in this embodiment, the first source / drain 300 and the second source / drain 400 each form an enclosing contact with the channel structure 200, which can effectively reduce contact resistance, improve the performance of semiconductor devices, and facilitate the miniaturization of semiconductor devices.
[0095] In some possible embodiments, such as Figure 11As shown, the first source / drain electrode 300 includes a multilayer first contact electrode 310 and a first metal layer 320. The multilayer first contact electrode 310 is in contact with the upper and lower surfaces of the multilayer first peripheral portion 220. The first metal layer 320 covers the multilayer first peripheral portion 220 and the first contact electrode 310.
[0096] The second source / drain electrode 400 includes a multilayer second contact electrode 410 and a second metal layer 420. The multilayer second contact electrode 410 is in contact with the upper and lower surfaces of the multilayer second peripheral portion 230. The second metal layer 420 covers the multilayer second peripheral portion 230 and the second contact electrode 410.
[0097] In this embodiment, the first contact electrode 310 contacts the upper and lower surfaces of the multilayer first peripheral portion 220, in conjunction with the first metal layer 320; the second contact electrode 410 contacts the upper and lower surfaces of the multilayer second peripheral portion 230, in conjunction with the second metal layer 420, forming an enclosed contact of the metal-two-dimensional material interface. This can effectively increase the contact area between the metal and the two-dimensional material, improve the contact quality of the metal-two-dimensional material interface, reduce contact resistance, and thus improve device performance.
[0098] In some possible embodiments, such as Figure 19 As shown, the first source / drain electrode 300 includes: a multilayer first contact electrode 310 and a first metal layer 320. The first contact electrode 310 is formed by the upper surface, end face, and lower surface of the multilayer first peripheral portion 220. The first metal layer 320 covers the multilayer first contact electrode 310.
[0099] The second source / drain electrode 400 includes: a multilayer second contact electrode 410 and a second metal layer 420. The second contact electrode 410 is formed by the upper surface, end face and lower surface of the multilayer second peripheral portion 230; the second metal layer 420 covers the multilayer second contact electrode 410.
[0100] In this embodiment, intercalation 104 is used to introduce guest molecules into the first peripheral portion 220 and the second peripheral portion 230, which include two-dimensional materials. Taking advantage of the weak van der Waals forces between the layers of the layered material, the guest molecules diffuse rapidly between the layers, thereby changing the physical and chemical properties of the two-dimensional material, such as conductivity, reducing the contact resistance between the metal and the two-dimensional material, and further reducing the contact resistance between the first metal layer 320 and the first peripheral portion 220, and the contact resistance between the second metal layer 420 and the second peripheral portion 230.
[0101] Based on the same inventive concept, this application also provides an electronic device, including: any of the semiconductor devices provided in the above embodiments, or a semiconductor device manufactured by the manufacturing method of any of the semiconductor devices provided in the above embodiments.
[0102] In this embodiment, since the electronic device uses any of the semiconductor devices provided in the foregoing embodiments or the semiconductor devices manufactured by the manufacturing methods of any of the semiconductor devices provided in the foregoing embodiments, the principles and technical effects are as described in the foregoing embodiments and will not be repeated here.
[0103] Optionally, the electronic device includes a smartphone, computer, tablet, artificial intelligence device, wearable device, or power bank.
[0104] It should be noted that the electronic devices are not limited to the above-mentioned types. Those skilled in the art can set any of the semiconductor devices provided in the above embodiments of this application in different devices according to actual application needs, thereby obtaining the electronic devices provided in the embodiments of this application.
[0105] Those skilled in the art will understand that the electronic devices provided in the embodiments of this application can be specifically designed and manufactured for a desired purpose, or may include known devices in general-purpose computers. These devices have any of the semiconductor devices provided in the various embodiments described above.
[0106] By applying the embodiments of this application, at least the following beneficial effects can be achieved: The multilayered channel structures 200 are spaced apart by sacrificial structures 101, and the first peripheral portion 220 and the second peripheral portion 230 at both ends of each channel structure 200 protrude from the sacrificial structure 101 and are suspended relative to the substrate 100. This allows the formation of a first source / drain 300 that surrounds the upper surface, lower surface, and end of the first peripheral portion 220, and a second source / drain 400 that surrounds the upper surface, lower surface, and end of the second peripheral portion 230. Furthermore, the sacrificial structure 101 is removed in a subsequent process, thereby exposing the outer peripheral surface of the middle portion 210 of the channel structure 200. A gate dielectric structure 500 and a gate 600 are formed sequentially around the middle portion 210 in the area where the sacrificial structure 101 was previously located, forming a fully enclosed gate structure. In the vertically stacked two-dimensional material transistor manufactured in the embodiments of this application, the first source-drain 300 and the second source-drain 400 each form an enclosing contact with the first peripheral portion 220 and the second peripheral portion 230 of the channel structure 200, which can effectively reduce the contact resistance, improve the performance of the semiconductor device, and facilitate the miniaturization of the semiconductor device.
[0107] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.
[0108] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.
[0109] The above description is only a partial implementation of this application. It should be noted that for those skilled in the art, other similar implementation methods based on the technical concept of this application, without departing from the technical concept of this application, also fall within the protection scope of the embodiments of this application.
Claims
1. A method for manufacturing a semiconductor device, characterized in that, include: A multilayer sacrificial structure and a channel structure located between adjacent sacrificial structures are formed on a substrate; the middle portion of the channel structure is connected to the sacrificial structure, and along a first direction parallel to the substrate, the first peripheral portion and the second peripheral portion at both ends of the middle portion protrude from the sacrificial structure; the material of the channel structure includes a metal compound. A first source / drain and a second source / drain are formed, each covering the end of the first peripheral portion of the multi-layered channel structure and at least a portion of the upper and lower surfaces, and covering the end of the second peripheral portion of the multi-layered channel structure and at least a portion of the upper and lower surfaces; Remove the sacrificial structure to expose the circumferential surface of the middle portion; A gate dielectric structure and a gate are formed that sequentially surround the peripheral surface of the central portion.
2. The method for manufacturing a semiconductor device according to claim 1, characterized in that, Forming multiple sacrificial structures on a substrate, and channel structures located between adjacent sacrificial structures, including: Alternating sacrificial layers and channel layers are formed on the substrate, and a sacrificial layer and a hard mask structure are formed sequentially on the topmost channel layer; Based on the hard mask structure, the sacrificial layer and the channel layer are self-aligned and etched to form a transition sacrificial structure and a channel structure with the same pattern as the hard mask structure. The transition sacrificial structure is laterally etched to form the sacrificial structure, such that both the first peripheral portion and the second peripheral portion protrude from the sacrificial structure along a first direction parallel to the substrate.
3. The method for manufacturing a semiconductor device according to claim 1, characterized in that, Forming the first source / drain and the second source / drain includes: A first contact electrode is formed on the upper and lower surfaces of the first peripheral portion of the multilayer, and a second contact electrode is formed on the upper and lower surfaces of the second peripheral portion of the multilayer. A first metal layer is formed covering multiple layers of the first peripheral portion and the first contact electrode, and a second metal layer is formed covering multiple layers of the second peripheral portion and the second contact electrode; the first source / drain electrode includes the first metal layer and the first contact electrode, and the second source / drain electrode includes the second metal layer and the second contact electrode.
4. The method for manufacturing a semiconductor device according to claim 3, characterized in that, A first contact electrode is formed on the upper and lower surfaces of the first peripheral portion of the multilayer, including: First contact electrodes are deposited on the upper and lower surfaces of the first peripheral portion of the multilayer.
5. The method for manufacturing a semiconductor device according to claim 3, characterized in that, A first contact electrode is formed on the upper and lower surfaces of the first peripheral portion of the multilayer, including: Laser processing is used to form dangling bonds on the surface of the first peripheral layer of the multilayer; the first contact electrode is grown using the dangling bonds as nucleation points; the material of the channel structure includes a transition metal chalcogenide; the material of the first contact electrode includes a conductive metal compound.
6. The method for manufacturing a semiconductor device according to claim 3, characterized in that, Forming a first metal layer covering multiple layers of the first peripheral portion and the first contact electrode includes: A conformal insulating layer is formed covering multiple layers of the sacrificial structure, the first peripheral portion, and the first contact electrode; Based on the hard mask structure, self-aligned etching is used to remove the isolation layer covering the first peripheral portion and the side of the first contact electrode in each layer; A first metal layer is formed covering the first peripheral portion and the side surface of the first contact electrode of each layer.
7. The method for manufacturing a semiconductor device according to claim 1, characterized in that, Forming the first source / drain and the second source / drain includes: A conformal spacer layer is formed covering multiple layers of the first peripheral portion, the second peripheral portion, and the sacrificial structure; The spacer layer is etched to expose at least a portion of the first peripheral portion and the second peripheral portion; A conformal intercalation layer and a first metal layer are sequentially formed to cover the spacer layer and at least a portion of the first peripheral portion, and a second metal layer is sequentially formed to cover the spacer layer and at least a portion of the second peripheral portion. Based on the annealing process, the intercalation layer is decomposed and combined with the upper surface, end face and lower surface of the first peripheral layer to form a multilayer first contact electrode, and combined with the upper surface, end face and lower surface of the second peripheral layer to form a multilayer second contact electrode; the first source and drain electrode includes the first metal layer and the first contact electrode, and the second source and drain electrode includes the second metal layer and the second contact electrode.
8. The method for manufacturing a semiconductor device according to claim 7, characterized in that, The intercalation material includes selenium, cobalt, or copper.
9. A semiconductor device, characterized in that, include: A multi-layered channel structure; the channel structure includes a central section and a first peripheral section and a second peripheral section located at both ends of the central section; The channel structure is made of metal compounds; A first source / drain electrode and a second source / drain electrode, wherein the first source / drain electrode covers the end of the first peripheral portion of the multilayer channel structure and at least a portion of the upper and lower surfaces, and the second source / drain electrode covers the end of the second peripheral portion of the multilayer channel structure and at least a portion of the upper and lower surfaces; A multilayer gate dielectric structure and a gate, wherein the gate dielectric structure and the gate are sequentially surrounded on the peripheral surface of the middle portion.
10. The semiconductor device according to claim 9, characterized in that, The first source and drain include: The multilayer first contact electrode is in contact with the upper and lower surfaces of the multilayer first peripheral portion; A first metal layer covers multiple layers of the first peripheral portion and the first contact electrode; The second source and drain include: The multilayer second contact electrode is in contact with the upper and lower surfaces of the multilayer second peripheral portion; A second metal layer covers multiple layers of the second peripheral portion and the second contact electrode.
11. The semiconductor device according to claim 9, characterized in that, The first source and drain include: The multilayer first contact electrode is formed by the upper surface, end face and lower surface of the multilayer first peripheral portion; A first metal layer covers multiple layers of the first contact electrodes; The second source and drain include: The multilayer second contact electrode is formed by the upper surface, end face and lower surface of the multilayer second peripheral portion; A second metal layer covers multiple layers of the second contact electrode.
12. An electronic device, characterized in that, include: A semiconductor device manufactured by the method of manufacturing a semiconductor device as described in any one of claims 1-8 above, or a semiconductor device as described in any one of claims 9-11 above.