A semiconductor device and a method of fabricating the same
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- XUZHOU ZHINENG SEMICON CO LTD
- Filing Date
- 2026-03-05
- Publication Date
- 2026-07-14
Smart Images
Figure CN122395977A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device and its fabrication method. Background Technology
[0002] Group III–V semiconductor materials, especially wide-bandgap semiconductor materials represented by gallium nitride (GaN), have advantages such as high breakdown electric field, fast electron saturation drift velocity, and high temperature resistance. They have been widely used in high-frequency and high-power electronic devices, such as high electron mobility transistors (HEMT) devices.
[0003] During the operation of group III-V semiconductor devices, under high drain bias conditions, a strong local electric field concentration can easily form near the drain side of the gate edge, which can lead to problems such as hot electron effect, increased gate leakage current and reduced breakdown voltage, seriously affecting the reliability and lifespan of the device.
[0004] To improve the electric field distribution inside the device, existing technologies typically introduce a gate field plate into the gate structure, extending the gate metal toward the drain. The gate field plate is then isolated from the semiconductor epitaxial structure through a dielectric layer. This redistributes the electric field on the drain side, reduces the electric field concentration at the gate edge, and thus improves the device's breakdown voltage and reliability.
[0005] In existing gallium nitride (GaN) device fabrication processes, the ohmic contact structures for the source and drain electrodes, which require high-temperature annealing, are typically formed first. Then, the gate structure and its corresponding gate field plate are fabricated to avoid the effects of high-temperature annealing on the gate and its gate field plate, such as metal migration. In this process flow, the gate field plate is generally achieved by depositing a dielectric layer on top of the already formed gate structure, followed by a further metal layer.
[0006] In the aforementioned gallium nitride (GaN) device fabrication process, on the one hand, the gate and gate field plate are formed in separate steps, involving multiple photolithography alignments and metal deposition processes, making the process flow relatively complex; on the other hand, in order to reduce manufacturing costs, existing III-V group semiconductor devices are all moving towards miniaturization, minimizing the area as much as possible during fabrication. A common method for minimizing the area is to shorten the gate-source pitch (Lgs) as much as possible. However, in the existing device fabrication process, it is usually necessary to create holes in the dielectric layer deposited above the gate structure, and deposit metal layers inside the holes and on the surface of the dielectric layer to form the gate field plate. During this process, due to the precision requirements of the photolithography machine, a metal enclosure 13 with a certain distance from the edge of the hole will be formed on the surface of the dielectric layer outside the dielectric hole. (See...) Figure 1 , Figure 1This is a schematic diagram of a metal via structure in the prior art. In this structure, a dielectric layer 10 has dielectric vias 11 extending downwards from its top surface, through which metal 12 is deposited. The metal on the upper surface of the dielectric layer 10 outside the dielectric vias 11 is called a metal via 13, and its width W is greater than 0, for example, 180 nm. If this metal 12 is used to form a gate field plate, it can be seen that the gate field plate extends not only towards the drain side but also towards the source side by a distance not less than that of the metal via 13. Therefore, this structure limits the shortening of Lgs, making it difficult to achieve the goal of reducing device area by shortening Lgs. Summary of the Invention
[0007] In view of the technical problems existing in the prior art, the present invention proposes a semiconductor device and its fabrication method, which can effectively control the internal electric field distribution of the device and improve the fabrication efficiency of the device.
[0008] To address the aforementioned technical problems, according to one aspect of the present invention, a method for fabricating a semiconductor device is provided, comprising: A functional layer is provided, the functional layer comprising at least a channel layer and a barrier layer composed of group III–V compounds, wherein a two-dimensional carrier gas is formed in the channel layer near the barrier layer; the functional layer includes an adjacent gate region and a gate field plate region, a source region adjacent to the gate region, and a drain region adjacent to the gate field plate region. A first dielectric layer is provided at least in the gate field plate region of the functional layer; The first dielectric layer is patterned to form one or more first dielectric steps extending from the gate region to the drain region in a low-to-high manner on the gate field plate region. A first metal layer is deposited and patterned on the gate region and the first dielectric step of the functional layer to form an integrally connected gate and a first gate field plate; and Source and drain are formed in the source and drain regions.
[0009] Optionally, the gate formed on the gate region of the functional layer forms a Schottky contact with the functional layer.
[0010] Optionally, the method for fabricating the semiconductor device further includes: providing a gate control structure at least on the gate region of the functional layer; correspondingly, depositing and patterning a first metal layer on the gate control structure and the first dielectric step in the gate region to form an integrally connected gate and a first gate field plate.
[0011] Optionally, the gate control structure is a gate dielectric layer or a P-type III-V semiconductor layer, wherein when the gate control structure is a gate dielectric layer, there is a continuous two-dimensional carrier gas in the channel layer of the corresponding gate region; when the gate control structure is a P-type III-V semiconductor layer, the two-dimensional carriers in the channel layer of the corresponding gate region are depleted.
[0012] Optionally, the method for fabricating the semiconductor device further includes: Etching the barrier layer of the gate region or injecting ions into the barrier layer depletes the two-dimensional carrier gas in the channel layer of the corresponding gate region.
[0013] Optionally, when a first dielectric layer is provided on the gate field plate region of the functional layer, one or more first dielectric sublayers are sequentially formed to constitute the first dielectric layer.
[0014] Optionally, a corresponding etch stop layer is formed before forming each first dielectric sublayer; correspondingly, when patterning the first dielectric layer, the first dielectric sublayer is etched to the corresponding etch stop layer to form the corresponding dielectric step.
[0015] Optionally, when the first dielectric layer is patterned, the angle between the longitudinal first surface of the first dielectric step and the lower semiconductor layer is an obtuse angle.
[0016] Optionally, after forming an integrally connected gate and gate field plate, the method further includes: Deposit a second dielectric layer on the current structure; For a portion of the gate and the first gate field plate that are integrally connected, the second dielectric layer is etched downwards until a portion of the first metal layer is exposed to obtain the first dielectric trench. For a portion of the source region, corresponding source contact holes are etched downwards from the second dielectric layer; for a portion of the drain region, corresponding drain contact holes are etched downwards from the second dielectric layer. A second metal layer is deposited and patterned on the current structure; wherein at least the second metal in the source contact hole is retained to form a source in the source region, at least the second metal in the drain contact hole is retained to form a drain in the drain region, and at least the second metal in the first dielectric trench is retained to form a gate interconnect metal electrically connected to the gate or the first gate field plate.
[0017] Optionally, when patterning the second metal layer, a portion of the second metal layer that is electrically connected to the gate interconnect metal and extends toward the drain region on the second dielectric layer is also retained to obtain the second gate field plate.
[0018] Optionally, when etching the first dielectric trench, one or more second dielectric steps extending from low to high are formed on the sidewall of the first dielectric trench; correspondingly, when patterning the second metal layer, the second metal layer on the second dielectric step electrically connected to the gate interconnect metal is retained to obtain one or more second gate field plates.
[0019] Optionally, when patterning the second metal layer, a portion of the second metal layer on the second dielectric layer above the gate, which is integrally connected to the second metal in the source contact hole, is also retained to form the source.
[0020] According to another aspect of the present invention, the present invention also provides a semiconductor device, the semiconductor device comprising at least a functional layer and electrodes, the functional layer comprising at least a channel layer and a barrier layer composed of a III-V compound, wherein a two-dimensional carrier gas is formed in a region of the channel layer near the barrier layer; the functional layer comprising an adjacent gate region and a gate field plate region, a source region adjacent to the gate region, and a drain region adjacent to the gate field plate region; the gate field plate region of the functional layer comprising one or more first dielectric steps extending from the gate region to the drain region in a low-to-high manner and a first gate field plate covering the dielectric steps; the electrodes comprising a gate formed in the gate region, a source formed in the source region, and a drain formed in the drain region; wherein the gate is integrally connected to the first gate field plate, and the gate is adjacent to the source and isolated by a dielectric.
[0021] Optionally, the gate further includes a gate control structure. Optionally, the gate control structure is a gate dielectric layer or a P-type III-V semiconductor layer, wherein when the gate control structure is a gate dielectric layer, there is a continuous two-dimensional carrier gas in the channel layer of the corresponding gate region; when the gate control structure is a P-type III-V semiconductor layer, the two-dimensional carriers in the channel layer of the corresponding gate region are depleted.
[0022] Optionally, the barrier layer includes a gate recess, the bottom region of which is the gate region, and the two-dimensional carrier gas in the channel layer corresponding to the gate region is depleted; or, the barrier layer region corresponding to the gate region is an ion implantation region, and the two-dimensional carrier gas in the channel layer corresponding to the gate region is depleted.
[0023] Optionally, the first dielectric step includes one or more first dielectric sublayers; or, the first dielectric step includes one or more first dielectric sublayers, with an etch barrier layer beneath each first dielectric sublayer.
[0024] Optionally, the angle between the longitudinal first surface of the first dielectric step and the lower semiconductor layer is an obtuse angle.
[0025] Optionally, the semiconductor device further includes a second dielectric layer covering the upper surface and side surface of an integral structure of the gate and the first gate field plate. A first dielectric trench is formed in the second dielectric layer above the connection structure of the gate and the first gate field plate. The first dielectric trench includes gate interconnect metal electrically connected to the gate or the first gate field plate. Correspondingly, the gate is isolated from the source through the second dielectric layer.
[0026] Optionally, the semiconductor device further includes a second gate field plate that is integrally connected to the gate interconnect metal on the second dielectric layer and extends toward the drain region.
[0027] Optionally, the sidewall of the first dielectric trench is a first-level or multi-level second dielectric step extending towards the drain region from low to high, and the second gate field covers the first-level or multi-level second dielectric step and is integrally connected with the gate interconnect metal.
[0028] Optionally, the source includes a metal extending over at least a portion of the upper surface of a second dielectric layer.
[0029] This invention reduces the process steps and improves the fabrication efficiency. The integrated gate and gate field plate effectively regulate the electric field distribution inside the device, thereby improving the breakdown performance and reliability of group III-V semiconductor devices. Attached Figure Description
[0030] The preferred embodiments of the present invention will now be described in further detail with reference to the accompanying drawings, wherein: Figure 1 This is a schematic diagram of a metal cladding structure in the prior art; Figure 2 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention; Figure 3 This is a flowchart of the first part of the method for fabricating a semiconductor device according to Embodiment 1 of the present invention; Figure 4 This is a flowchart of the second part of the method for fabricating a semiconductor device according to Embodiment 1 of the present invention; Figure 5 This is a flowchart of the first part of the method for fabricating a semiconductor device according to Embodiment 2 of the present invention; Figure 6 This is a flowchart of the second part of the method for fabricating a semiconductor device according to Embodiment 2 of the present invention; Figure 7 This is a schematic diagram of the structural principle of a semiconductor device according to Embodiment 3 of the present invention; Figure 8 This is a partial structural schematic diagram of the source contact hole 511 obtained by etching the second dielectric layer 220 according to Embodiment 3 of the present invention. Figure 9 A partial flowchart of the method for fabricating a semiconductor device according to Embodiment 4 of the present invention; Figure 10 This is a schematic diagram of the structure of a semiconductor device according to Embodiment 5 of the present invention. Detailed Implementation
[0031] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0032] In the following detailed description, reference can be made to the accompanying drawings, which form part of this application and illustrate specific embodiments of the present application. In the drawings, similar reference numerals describe substantially similar components in different figures. Specific embodiments of the present application are described in sufficient detail below to enable those skilled in the art to implement the technical solutions of the present application. It should be understood that other embodiments may also be utilized, or structural, logical, or electrical changes may be made to the embodiments of the present application.
[0033] See Figure 2 , Figure 2 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention. The method includes the following steps: Step S1, providing a functional layer, the functional layer including at least a channel layer and a barrier layer composed of group III-V compounds, wherein a two-dimensional carrier gas is formed in the channel layer near the barrier layer; the functional layer includes an adjacent gate region and a gate field plate region, a source region adjacent to the gate region, and a drain region adjacent to the gate field plate region.
[0034] Step S2, a first dielectric layer is provided at least on the gate field plate region of the functional layer.
[0035] Step S3: Forming a first dielectric step. Specifically, the first dielectric layer is patterned to form one or more first dielectric steps extending from the gate region to the drain region in a low-to-high manner on the gate field plate region.
[0036] Step S4: Form an integrally connected gate and a first gate field plate. Specifically, a first metal layer is deposited and patterned on the gate region of the functional layer and the first dielectric step to form an integrally connected gate and a first gate field plate.
[0037] Step S5: The source and drain are formed in the source region and the drain region, respectively.
[0038] In this invention, the first metal is a high-temperature resistant metal, such as titanium nitride, which can withstand the high temperatures during subsequent high-temperature annealing of the source and drain to form ohmic contacts. Furthermore, the gate and gate field plate are formed simultaneously in this invention, reducing multiple photolithography alignments and metal deposition processes, streamlining the fabrication process, and improving device fabrication efficiency. Moreover, the gate field plate in this invention extends unidirectionally from the gate to the drain side; neither the gate nor the gate field plate has structures extending towards the source side, nor are there unavoidable structures extending towards the source side such as metal vias, thereby effectively reducing Lgs. Therefore, this invention not only provides a gate field plate for effectively controlling the internal electric field distribution of the device, improving the breakdown performance and reliability of group III-V semiconductor devices, but also achieves the technical effect of reducing device area by reducing Lgs.
[0039] Example 1 Figure 3 This is a flowchart of the first part of the method for fabricating a semiconductor device according to Embodiment 1 of the present invention. Figure 4 This is a flowchart of the second part of the method for fabricating a semiconductor device according to Embodiment 1 of the present invention, combined with... Figure 3 and Figure 4 The method for fabricating the semiconductor device in this embodiment includes the following steps: Step S101: Provide a functional layer 100. The functional layer 100 includes, from bottom to top, a substrate 101, a buffer layer 102, and an epitaxial layer 103. The substrate 101 is made of materials such as intrinsic GaN, silicon (Si), silicon carbide (SiC), or sapphire (whose main component is Al2O3). In this embodiment, the substrate 101 is made of Si. The buffer layer 102 can be aluminum nitride (AlN), gallium nitride (GaN), or aluminum gallium nitride (Al2O3). X Ga (1-X) One or more of the following materials are used: GaN, Indium Gallium Nitride (InGaN), Indium Aluminum Nitride (AlInN), and Indium Aluminum Gallium Nitride (AlGaInN), to reduce the impact of differences in lattice constants and coefficients of thermal expansion between the substrate 101 and the epitaxial layer 103, effectively preventing cracking of the nitride epitaxial layer 103. The buffer layer 102 is an optional structure and can be a multilayer structure, with each layer composed of a different material. A nucleation layer (not shown) can also be introduced between the substrate 101 and the buffer layer 102 to avoid the melt-back effect. The epitaxial layer 103 includes a channel layer 1031 and a barrier layer 1032. The material of the channel layer 1031 is, for example, GaN, and the material of the barrier layer 1032 is, for example, Al. X Ga(1-X) N (abbreviated as AlGaN in the figure), the channel layer 1031 and the barrier layer 1302 constitute a heterojunction, in which a two-dimensional carrier gas is provided, such as the two-dimensional electron gas (2DEG) in this embodiment. Of course, depending on the channel layer 1031 and the barrier layer 1032, the two-dimensional carrier gas can also be a two-dimensional hole gas (2DHG). The materials of the channel layer 1031 and the barrier layer 1032 constituting the heterojunction can also be other group III-V semiconductor materials, such as AlN, GaN, InN and compounds of these materials, such as AlGaN, InGaN, AlInGaN, etc. The surface region of the functional layer 100 in this invention includes an adjacent gate region 110 and a gate field plate region 120, a source region 130 adjacent to the gate region 110, and a drain region 140 adjacent to the gate field plate region 120.
[0040] In step S102, a gate dielectric layer 201 is provided on the functional layer. The material of the gate dielectric layer 201 is, for example, silicon nitride, aluminum oxide, etc.
[0041] In step S103, a first dielectric layer 210 is provided on the gate dielectric layer 201. The material of the first dielectric layer 210 is, for example, silicon nitride, silicon oxide, or a high-k dielectric (such as aluminum oxide, aluminum nitride, etc.).
[0042] In step S104, the first dielectric layer 210 is patterned to form a first dielectric step 211 on the gate field plate region. At least the first dielectric layer 210 of the gate region 110 is etched away to expose the gate dielectric layer 201 of the gate region 110. During the etching of the first dielectric layer 210 of the gate region 110, a first dielectric step 211 comprising a longitudinal first surface and a transverse surface is formed. However, it is understood that during the patterning of the first dielectric layer 210, part or all of the first dielectric layer 210 in both the source region 130 and the drain region 140 may also be etched away simultaneously, as shown by the dashed line next to the first dielectric step 211 in the figure. As can be seen in the figure, the first dielectric step 211 extends from the gate region 110 to the drain region 140.
[0043] Step S105: Grow a first metal layer 310 on the current structure.
[0044] Step S106: The first metal layer 310 is patterned to form an integrally connected gate 40 and a first gate field plate 411.
[0045] Specifically, a gate structure 400 is obtained by depositing and patterning a first metal layer 310 on the gate region 110 of the functional layer and the dielectric step structure. The portion above the gate region 110 constitutes the gate 40, and the portion above the gate field plate region 120 constitutes the first gate field plate 411.
[0046] Step S107: Deposit a second dielectric layer 220 on the current structure.
[0047] Step S108: Etching the second dielectric layer 220. Specifically, a source contact hole 511 is etched downwards from the second dielectric layer 220 to form a portion of the source region 130, and a drain contact hole 611 is etched downwards from the second dielectric layer 220 to form a portion of the drain region 140. In this embodiment, the source contact hole 511 and the drain contact hole 611 extend into the barrier layer.
[0048] Step S109: Grow a second metal layer 320 on the current structure.
[0049] In step S110, the second metal layer 320 is patterned to form the source 50 and the drain 60. For example, the second metal layer is removed except for the source region 130 and the drain region 140. The second metal inside the source contact hole 511 and the metal on the surface of the source region 130 outside the hole constitute the source 50, and the second metal inside the drain contact hole 611 and the metal on the surface of the drain region 140 outside the hole constitute the drain 60.
[0050] Step S111, then passivation layer 230 is prepared and passivation layer 230 is etched to obtain dielectric hole 231 that communicates with source 50, drain 60 and first gate field plate 411.
[0051] Step S112 involves growing and patterning a pad metal layer to obtain individual electrode pads, such as source pad 52, gate pad 42, and drain pad 62 as shown in the figure. Specifically, a pad metal layer is first grown and patterned on the surface of passivation layer 230 to obtain primary pads located on the surface of passivation layer 230 at appropriate positions. Each primary pad is electrically connected to its corresponding electrode through pad metal within a dielectric via. Then, another passivation layer is deposited at an appropriate location in the current structure, covering part of the primary pads and exposing the remaining primary pads. The exposed primary pads form the pads of the final semiconductor device.
[0052] When depositing various dielectric layers in the aforementioned corresponding steps, such as gate dielectric layer 201, first dielectric layer 210, second dielectric layer 220 and passivation layer 230, they can be deposited by chemical vapor deposition (CVD), atomic layer deposition (ALD) and other methods.
[0053] The various metal layers in the aforementioned steps can be generated by electron beam evaporation or sputtering, and the metal layers can be single metal layers or composite metal layers of multiple metals. For example, the integrally connected gate 40 and the first gate field plate 411 can be single-layer high-temperature resistant metals, such as titanium nitride or tantalum nitride, or they can be a metal composite structure of titanium, aluminum, and titanium nitride.
[0054] In this embodiment, the second metal layer 320 is used to form the source and drain. It can be a multilayer Ti / Al / Ni / Au metal sequence evaporated by electron beam evaporation process, and the thickness of each layer depends on the specific requirements.
[0055] Furthermore, the aforementioned steps for etching and patterning various dielectric layers include, for example, firstly, using photoresist as a mask to define the locations to be etched, and then using a high selectivity etching method. Dry etching or wet etching can be used. For instance, when patterning the first dielectric layer 210 to form the first dielectric step 211, photoresist is used to define the first dielectric step 211, and then CF4, SF6, or other F-based gases or F-based mixed gases are used to etch away other parts of the first dielectric layer 210, thereby obtaining the first dielectric step 211. As another example, after patterning the second metal layer 320, a rapid high-temperature annealing process is performed on the second metal within the source contact hole 511 and drain contact hole 611 to form ohmic contacts between the drain / source and the semiconductor, thereby ensuring the stability of the source 50 and drain 60.
[0056] In addition, the aforementioned steps may also include some conventional processes in semiconductor fabrication, such as mechanical planarization after each semiconductor layer deposition to obtain a semiconductor layer with a flat surface. These conventional processes will not be described in detail in this invention.
[0057] Combination Figure 3 and Figure 4As can be seen, the semiconductor device in this embodiment includes at least a functional layer and electrodes. The functional layer 100 in this embodiment includes a substrate 101, a buffer layer 102, a channel layer 1031, and a barrier layer 1032. A 2DEG is formed in the channel layer 1031 near the barrier layer 1032. The functional layer includes an adjacent gate region 110 and a gate field plate region 120, a source region 130 adjacent to the gate region 110, and a drain region 140 adjacent to the gate field plate region 120. A gate dielectric layer 201 is formed on the barrier layer 1032. A first dielectric step 211 is formed above the gate field plate region 120, extending from the gate region 110 to the drain region 140. An integrally connected gate 40 and a first gate field plate 411 are formed above the gate dielectric layer 201 and the first dielectric step 211 on the gate region 110. A second dielectric layer 220 is formed above the integrally connected gate 40 and the first gate field plate 411. The bottoms of the source 50 and drain 60 extend into the barrier layer 1032. The source 50 is isolated from the gate 40 through the second dielectric layer 220, and the drain 60 is isolated from the first gate field plate 411 through the first dielectric layer 210 and the second dielectric layer 220. A passivation layer 230 covers the source 50, drain 60, and the second dielectric layer 220. Pads are formed on the passivation layer 230, and the pads are electrically connected to the respective electrodes through metal in the dielectric vias 231. The source pad 52, gate pad 42, and drain pad 62 are shown in the figure. In this embodiment, the semiconductor device is in the ON state under zero gate voltage conditions; that is, the semiconductor device is a D-Mode device.
[0058] In this embodiment, before fabricating the source and drain of the semiconductor device, an integrally connected gate and its field plate are fabricated first, simplifying the fabrication process and improving the fabrication efficiency of the semiconductor device. Furthermore, since this embodiment does not fabricate the gate by growing metal within dielectric vias, it avoids the problems that occur in other embodiments. Figure 1 The metal cladding shown solves the problem of hindering the reduction of the gate-source spacing, and thus provides space for further reduction of the gate-source spacing.
[0059] Example 2 Figure 5 This is a flowchart of the first part of the method for fabricating a semiconductor device according to Embodiment 2 of the present invention. Figure 6 This is a flowchart of the second part of the method for fabricating a semiconductor device according to Embodiment 2 of the present invention.
[0060] Step S201, provide functional layer 100.
[0061] Step S202: A gate dielectric layer 201 is provided on the functional layer 100.
[0062] In step S203, multiple first dielectric sublayers 2101 are provided on the gate dielectric layer 201, and the multiple first dielectric sublayers 2101 constitute the first dielectric layer 210. The semiconductor materials of the multiple first dielectric sublayers 2101 may be the same or different.
[0063] Step S204: Pattern the first dielectric layer 210 to form a plurality of first dielectric steps 211 on the gate field plate region 120. For example... Figure 5 As shown, a total of four first dielectric steps 211 are formed. In this embodiment, the longitudinal first surface of the first dielectric step 211 is an inclined plane, and the angle α between it and the lower surface is an obtuse angle. The longitudinal inclined plane can be etched by adjusting the photoresist coating speed, baking temperature, gas during etching, and reducing the anisotropy of etching.
[0064] Step S205: Grow a first metal layer 310 on the current structure.
[0065] Step S206: The first metal layer 310 is patterned to form an integrally connected gate 40 and a first gate field plate 411. The first gate field plate 411 is a multi-level field plate, and the angle α formed by each level of the field plate and its underlying metal layer is an obtuse angle. In this embodiment, the gate 40 extends to the drain 60 with multiple levels of field plates, modulating the electric field peaks between the gate and drain into multiple peaks. Furthermore, the obtuse angles between the field plates reduce the steepness of the electric field peaks, soften the electric field peaks, and further increase the modulation effect on the electric field.
[0066] Step S207: Deposit a second dielectric layer 220 on the current structure.
[0067] Step S208: Etching the second dielectric layer 220. Specifically, for a portion of the source region 130, source contact holes 511 are etched downwards from the second dielectric layer 220; for a portion of the drain region 140, drain contact holes 611 are etched downwards from the second dielectric layer 220. In this embodiment, the source contact holes 511 and drain contact holes 611 extend into the barrier layer. For a portion of the first gate field plate 411, etching is performed downwards from the second dielectric layer 220 until a portion of the first gate field plate 411 is exposed to obtain the first dielectric trench 2201.
[0068] Step S209: Grow a second metal layer 320 on the current structure.
[0069] Step S210: The second metal layer 320 is patterned, wherein at least the second metal in the source contact hole 511 is retained to form a source 50 in the source region 130, at least the second metal in the drain contact hole 611 is retained to form a drain 60 in the drain region 140, and at least the second metal in the first dielectric trench 2201 is retained to form a gate interconnect metal 412 electrically connected to the first gate field plate 411.
[0070] In step S211, a passivation layer 230 is deposited and etched to obtain a dielectric via 231 that communicates with the source 50, the drain 60 and the first gate field plate 411.
[0071] Step S212: Grow and pattern the pad metal layer to obtain source pad 52, gate pad 42 and drain pad 62 respectively.
[0072] A D-mode group III-V semiconductor device, such as a HEMT, was fabricated using the aforementioned method. In this embodiment, the gate field plate is a multi-level field plate with obtuse angles at the steps, which increases the modulation effect of the electric field. Furthermore, the first gate field plate 411 is electrically connected to the second metal used to fabricate the source and drain electrodes via the first dielectric trench 2201, thereby reducing the gate resistance and minimizing the impact of the high resistance of the high-temperature metal on device performance.
[0073] Example 3 See Figure 7 , Figure 7 This is a schematic diagram of the structural principle of a semiconductor device according to Embodiment 3 of the present invention. The fabrication process of the semiconductor device in this embodiment is partially the same as that in the previous embodiments, so the identical processes will not be repeated; only the different steps will be described below. In this embodiment, a P-type GaN layer 202 is provided on the functional layer 100 corresponding to the gate region 110. For example, it is a GaN layer with a doping concentration of 5E19 and a magnesium (Mg) doping element. The 2DEG in the channel layer 1031 corresponding to the gate 40 in the gate region 110 is depleted. The semiconductor device in this embodiment is in a turned-off state under zero gate voltage conditions; that is, the semiconductor device in this embodiment is an E-Mode device. In a specific embodiment, the source-drain breakdown voltage of the E-Mode device is 650V, and the gate turn-on voltage is 1.5V.
[0074] To improve the etching accuracy of the dielectric steps, in this embodiment, when depositing the first dielectric sublayer 2101, an etch stop layer 2102 is deposited first, followed by the first dielectric sublayer 2101, so that there is an etch stop layer 2102 under each first dielectric sublayer 2101. The etch stop layer 2102 has a high etching ratio with the first dielectric sublayer 2101. Therefore, when etching the dielectric steps, when etching downwards into the first dielectric sublayer 2101, the etching can be considered to have stopped when reaching the etch stop layer 2102, thus ensuring the precise height of the first dielectric step 211. In this embodiment, three first dielectric sublayers 2101 are deposited, and three levels of first dielectric steps 211 extending from the gate region 110 to the drain region 140 are etched.
[0075] In this embodiment, when patterning the second metal layer 320, the second metal extending from the gate interconnect metal 412 to the drain region 140 on the upper surface of the second dielectric layer 220 is also retained, thereby forming the second gate field plate 413, which further improves the electric field modulation effect on the region between the gate and drain.
[0076] In this embodiment, when etching the second dielectric layer 220 to obtain the source contact hole 511, see [link to previous section]. Figure 8 , Figure 8 This is a partial structural schematic diagram of the source contact hole 511 obtained by etching the second dielectric layer 220 according to Embodiment 3 of the present invention. The source contact hole 511 includes two sections: the lower section has a small diameter and extends into the barrier layer 1032; the upper section has a wide diameter and is located above the gate 40 of the gate region 110, with a shallow depth, and is separated from the gate 40 below by a second dielectric layer of a certain thickness. When the second metal layer 320 is grown and patterned in the etched second dielectric layer 220, a field plate 51 overlapping the gate 40 longitudinally is formed on the top of the source 50 formed in the source contact hole 511. Figure 7 As can be seen, in this embodiment, the gate 40 and the source 50 have a certain overlapping area in the longitudinal direction, and the two are isolated by a second dielectric. Therefore, this embodiment can reduce the device area by reducing the gate-source pitch Lgs, thereby achieving device miniaturization and reducing production costs.
[0077] In another embodiment, a second dielectric layer 220 is etched in the source region 130 near the gate 40 to obtain a source contact hole 511 close to the gate 40. When the second metal layer 320 is patterned to form the source 50, a portion of the second metal on the second dielectric layer above the gate 40 is retained, that is, a portion of the source overlaps onto the gate 40. Since the gate 40 is isolated from the source 50 by the second dielectric layer, the influence of metal vias on the reduction of Lgs in the process is avoided, and the requirement to reduce Lgs to reduce the device area is also met.
[0078] Example 4 See Figure 9 , Figure 9 This is a partial flowchart of a method for fabricating a semiconductor device according to Embodiment 4 of the present invention. In this embodiment, the method for fabricating the semiconductor device includes the following steps: Step S301, provide functional layer 100.
[0079] In step S302, a first dielectric layer 210 is provided on the functional layer 100, and two first dielectric steps 211 are graphically obtained.
[0080] Step S303: A first metal layer 310 is grown and patterned on the current structure to obtain a gate structure 400 integrally connected, including a gate 40 and a first gate field plate 411. In this embodiment, the gate 40 and the semiconductor layer are Schottky contacts. For example, the semiconductor device in this invention is a D-Mode device with a source-drain breakdown voltage of 650V and a gate voltage of -10V that is turned off.
[0081] Step S304: Deposit and pattern the second dielectric layer 220 on the current structure. Specifically, for a portion of the source region 130 and the gate region 110, etch downwards from the second dielectric layer 220. When there is a certain height from the gate 40, reduce the etching range to within the source region 130 until the etching reaches the barrier layer 1032. This yields the source contact hole 511. For a portion of the drain region 140, etch downwards from the second dielectric layer 220 to obtain the drain contact hole 611. For a portion of the first gate field plate 411, etch downwards from the second dielectric layer 220 until a portion of the first gate field plate 411 is exposed to obtain the first dielectric trench 2201. In this embodiment, when etching the first dielectric trench 2201, a step position is first defined on the upper surface of the second dielectric layer 220 near the drain region 140. Then, the second dielectric layer 220 is etched downwards. During the etching process, the etching conditions are adjusted to obtain the longitudinal slope of the step. After reaching the preset depth, the etching range is reduced until the bottom first gate field plate 411 is exposed, thereby obtaining a first dielectric trench 2201 with a second dielectric step 221 facing the drain region 140 on the sidewall.
[0082] In step S305, a second metal layer is grown and patterned to obtain a source 50 and a source field plate 51, a gate interconnect metal 412 electrically connected to the first gate field plate 411, a second gate field plate 413 extending from the gate interconnect metal 412 to the drain region, and a drain 60.
[0083] Step S306, followed by depositing a passivation layer 230, etching dielectric holes, and growing a pad metal layer, etc.
[0084] In this embodiment, the semiconductor device includes two multi-level gate field plates extending unidirectionally toward the drain region, which further enhances the modulation effect of the electric field; and the source field plate 51 is formed by utilizing the dielectric space above the gate 40, which can effectively reduce the gate-source spacing, thereby effectively reducing the device area and reducing the manufacturing cost.
[0085] Example 5 Figure 10 This is a schematic diagram of the structure of a semiconductor device according to Embodiment 5 of the present invention. The difference between this embodiment and Embodiment 4 is that, during the etching of the first dielectric layer 210, the first dielectric layer 210 is etched downwards in the gate region 110 until it reaches the barrier layer 1032. Since the remaining barrier layer 1032 is sufficiently thin, the polarization charge density in the channel layer 1031 corresponding to this location is small, preventing the formation of a 2DEG. Alternatively, the entire barrier layer 1032 corresponding to the gate 40 can be etched away. The second dielectric layer is etched in the source region 130 near the gate 40 to generate source contact holes. During the growth and patterning of the second metal layer, because the gate 40 and source 50 are very close (e.g., 1µm), a portion (1µm) of the metal via (e.g., 2µm) outside the source contact hole is located on the second dielectric layer above the gate 40, forming an overlap with the gate 40 in the longitudinal direction. This invention can meet the precision requirements of lithography machines and shorten the gate-source spacing without being limited by the metal via, thereby reducing the device area. The other preparation processes are the same as in Example 4, and will not be repeated here.
[0086] Alternatively, an E-Mode semiconductor device can be obtained by implanting ions into the barrier layer 1032 corresponding to the gate 40 or the channel layer 1301 to counteract the polarization charge in the channel layer 1031. For example, when the channel layer 1031 is GaN and the barrier layer 1302 is AlGaN, F ions are implanted into the barrier layer 1032. The corresponding semiconductor device is, for example, an E-Mode device with a drain-source breakdown voltage of 650V and a gate voltage of 0.7V for activation.
[0087] Although the first dielectric trench 2201 in the foregoing embodiment is formed in the gate field plate region 120, it can be understood that it can also be formed above the gate region 110, that is, the gate interconnect metal 412 in the first dielectric trench 2201 can also be electrically connected to the gate 40.
[0088] The semiconductor device fabrication method provided by this invention obtains the gate and a gate field plate extending unidirectionally towards the drain in a single process step. This achieves the purpose of preparing the gate field plate to modulate the electric field, simplifies the fabrication process, and improves the fabrication efficiency of the semiconductor device. Furthermore, this invention can utilize the dielectric space above the gate to define the source in the gate region 110, thereby achieving extreme compression of device size, miniaturization of the device, and reduction of production costs.
[0089] The above embodiments are for illustrative purposes only and are not intended to limit the invention. Those skilled in the art can make various changes and modifications without departing from the scope of the invention. Therefore, all equivalent technical solutions should also fall within the scope of the invention.
Claims
1. A method for fabricating a semiconductor device, characterized in that, The method includes: A functional layer is provided, the functional layer comprising at least a channel layer and a barrier layer composed of group III–V compounds, wherein a two-dimensional carrier gas is formed in the channel layer near the barrier layer; the functional layer includes an adjacent gate region and a gate field plate region, a source region adjacent to the gate region, and a drain region adjacent to the gate field plate region. A first dielectric layer is provided at least in the gate field plate region of the functional layer; The first dielectric layer is patterned to form one or more first dielectric steps extending from the gate region to the drain region in a low-to-high manner on the gate field plate region. A first metal layer is deposited and patterned on the gate region and the first dielectric step of the functional layer to form an integrally connected gate and a first gate field plate; and The source and drain are formed in the source region and the drain region, respectively.
2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The gate formed on the gate region of the functional layer forms a Schottky contact with the functional layer.
3. The method for fabricating a semiconductor device according to claim 1, characterized in that, Further includes: A gate control structure is provided at least on the gate region of the functional layer. Correspondingly, a first metal layer is deposited and patterned on the gate control structure in the gate region and on the first dielectric step to form an integrally connected gate and a first gate field plate.
4. The method for fabricating a semiconductor device according to claim 3, characterized in that, The gate control structure is a gate dielectric layer or a P-type III-V semiconductor layer. When the gate control structure is a gate dielectric layer, there is a continuous two-dimensional carrier gas in the channel layer of the corresponding gate region. When the gate control structure is a P-type III-V semiconductor layer, the two-dimensional carriers in the channel layer of the corresponding gate region are depleted.
5. The method for fabricating a semiconductor device according to claim 1, characterized in that, Further includes: Etching the barrier layer of the gate region or injecting ions into the barrier layer depletes the two-dimensional carrier gas in the channel layer of the corresponding gate region.
6. The method for fabricating a semiconductor device according to claim 1, characterized in that, When a first dielectric layer is provided on the gate field plate region of the functional layer, one or more first dielectric sublayers are sequentially formed to constitute the first dielectric layer.
7. The method for fabricating a semiconductor device according to claim 6, characterized in that, Before forming each first dielectric sublayer, a corresponding etch stop layer is formed; correspondingly, when the first dielectric layer is patterned, the first dielectric sublayer is etched to the corresponding etch stop layer to form the corresponding dielectric step.
8. The method for fabricating a semiconductor device according to claim 1, characterized in that, When the first dielectric layer is patterned, the angle between the longitudinal first surface of the first dielectric step and the lower semiconductor layer is an obtuse angle.
9. The method for fabricating a semiconductor device according to claim 1, characterized in that, After forming an integrally connected gate and gate field plate, the following is further included: Deposit a second dielectric layer on the current structure; For a portion of the gate and the first gate field plate that are integrally connected, the second dielectric layer is etched downwards until a portion of the first metal layer is exposed to obtain the first dielectric trench. For a portion of the source region, corresponding source contact holes are etched downwards from the second dielectric layer; for a portion of the drain region, corresponding drain contact holes are etched downwards from the second dielectric layer. A second metal layer is deposited and patterned on the current structure; wherein at least the second metal in the source contact hole is retained to form a source in the source region, at least the second metal in the drain contact hole is retained to form a drain in the drain region, and at least the second metal in the first dielectric trench is retained to form a gate interconnect metal electrically connected to the gate or the first gate field plate.
10. The method for fabricating a semiconductor device according to claim 9, characterized in that, When patterning the second metal layer, a portion of the second metal layer that is electrically connected to the gate interconnect metal and extends toward the drain region on the second dielectric layer is also retained to obtain the second gate field plate.
11. The method for fabricating a semiconductor device according to claim 10, characterized in that, During the etching of the first dielectric tank, one or more second dielectric steps extending from low to high are formed on the sidewall of the first dielectric tank towards the drain region. Correspondingly, when patterning the second metal layer, the second metal layer on the second dielectric step electrically connected to the gate interconnect metal is retained to obtain one or more levels of the second gate field plate.
12. The method for fabricating a semiconductor device according to claim 9, characterized in that, When patterning the second metal layer, a portion of the second metal layer on the second dielectric layer above the gate, which is integrally connected to the second metal in the source contact hole, is also retained to form the source.
13. A semiconductor device, the semiconductor device comprising at least a functional layer and electrodes, the functional layer comprising at least a channel layer and a barrier layer made of a group III–V compound, wherein a two-dimensional carrier gas is formed in a region of the channel layer near the barrier layer; the functional layer comprising an adjacent gate region and a gate field plate region, a source region adjacent to the gate region, and a drain region adjacent to the gate field plate region; Its features are, The gate field plate region of the functional layer includes one or more first dielectric steps extending from the gate region to the drain region in a low-to-high manner, and a first gate field plate covering the first dielectric steps. The electrode includes a gate formed in the gate region, a source formed in the source region, and a drain formed in the drain region; The gate is integrally connected to the first gate field plate, and the gate is adjacent to the source and isolated by a dielectric.
14. The semiconductor device according to claim 13, characterized in that, The gate also includes a gate control structure.
15. The semiconductor device according to claim 14, characterized in that, The gate control structure is a gate dielectric layer or a P-type III-V semiconductor layer. When the gate control structure is a gate dielectric layer, there is a continuous two-dimensional carrier gas in the channel layer of the corresponding gate region. When the gate control structure is a P-type III-V semiconductor layer, the two-dimensional carriers in the channel layer of the corresponding gate region are depleted.
16. The semiconductor device according to claim 13, characterized in that, The barrier layer includes a gate recess, the bottom region of which is the gate region, and the two-dimensional carrier gas in the channel layer corresponding to the gate region is depleted; or, the barrier layer region corresponding to the gate region is an ion implantation region, and the two-dimensional carrier gas in the channel layer corresponding to the gate region is depleted.
17. The semiconductor device according to claim 13, characterized in that, The first dielectric step includes one or more first dielectric sublayers; or, the first dielectric step includes one or more first dielectric sublayers, with an etch barrier layer beneath each first dielectric sublayer.
18. The semiconductor device according to claim 13, characterized in that, The angle between the longitudinal first surface of the first dielectric step and the lower semiconductor layer is an obtuse angle.
19. The semiconductor device according to claim 13, characterized in that, The device further includes a second dielectric layer covering the upper and side surfaces of an integral structure that covers the gate and the first gate field plate. A first dielectric trench is formed in the second dielectric layer above the connection structure of the gate and the first gate field plate. The first dielectric trench includes gate interconnect metal electrically connected to the gate or the first gate field plate. Correspondingly, the gate is isolated from the source through the second dielectric layer.
20. The semiconductor device according to claim 19, characterized in that, It further includes a second gate field plate that is integrally connected to the gate interconnect metal on the second dielectric layer and extends toward the drain region.
21. The semiconductor device according to claim 20, characterized in that, The first dielectric trench sidewall is a first-level or multiple-level second dielectric steps extending towards the drain region from low to high, and the second gate field plate covers the first-level or multiple-level second dielectric steps and is integrally connected with the gate interconnect metal.
22. The semiconductor device according to claim 19, characterized in that, The source includes metal extending over at least a portion of the upper surface of a second dielectric layer.