Method of manufacturing a silicon carbide mos device and device

Abstract

The application provides a manufacturing method and a device of a silicon carbide MOS device, and comprises the following steps: providing a silicon carbide substrate with an N-type silicon carbide epitaxial layer; forming a P-type channel region in the N-type silicon carbide epitaxial layer; performing nitrogen ion implantation on the P-type channel region; performing a high-temperature annealing step to activate the implanted nitrogen atoms; forming a gate oxide layer on the P-type channel region and forming a gate electrode; forming a source region and a drain region in the P-type channel region on both sides of the gate electrode. By introducing activated nitrogen atoms into the surface lattice of the silicon carbide in advance before oxidation, the nitrogen atoms actively participate in the interface reaction in the subsequent thermal oxidation process, which fundamentally inhibits the generation of carbon-related defects. Compared with the "post-passivation" method of the prior art, the effect is more essential and more complete, and the double action of "source inhibition" of carbon defects and "passivation" of residual defects by nitrogen atoms itself can greatly reduce the trap density of the silicon carbide and silicon dioxide interface.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device manufacturing technology, specifically, it relates to a method and device for manufacturing a silicon carbide MOS device. Background Technology

[0002] Silicon carbide metal-oxide-semiconductor field-effect transistors (SiCMOSFETs) have broad application prospects in new energy vehicles, photovoltaic power generation, and rail transportation due to their excellent characteristics such as high voltage withstand, low loss, and high operating frequency. However, the performance of SiCMOSFETs has long been constrained by a core technological bottleneck: the interface quality between the gate oxide layer (usually silicon dioxide) and the silicon carbide substrate.

[0003] In traditional silicon carbide thermal oxidation processes, due to incomplete oxidation and escape of carbon atoms, numerous carbon-related defects, such as carbon clusters, carbon interstices, and silicon-carbon dangling bonds, remain near the interface between silicon carbide and silicon dioxide. These defects introduce a large number of trap levels into the semiconductor bandgap, forming a high-density interface state that severely traps and scatters charge carriers in the channel. This results in low channel mobility, high on-resistance, unstable threshold voltage, and reduced long-term reliability of the gate oxide layer.

[0004] To address this issue, existing technologies have proposed several interface passivation methods. A common approach is to grow or anneal the gate oxide layer in a nitrogen-containing atmosphere (e.g., nitric oxide or nitrous oxide). These methods passivate existing carbon-related defects by introducing nitrogen atoms into silicon dioxide or at the interface, thus improving interface quality to some extent. However, this approach is essentially a "post-treatment" strategy; it addresses existing defects without fundamentally preventing their formation. Furthermore, achieving good passivation sometimes requires introducing high concentrations of nitrogen, which can adversely affect device electrical parameters (such as threshold voltage) and increase the complexity of process control. Therefore, finding a method that is compatible with existing processes and highly controllable to suppress the formation of carbon-related defects during silicon carbide thermal oxidation at its source is a key technical challenge for further improving the performance and reliability of silicon carbide MOSFETs. Summary of the Invention

[0005] In view of the deficiencies in the prior art, the purpose of this invention is to provide a method for manufacturing a silicon carbide MOS device and the device itself.

[0006] A method for manufacturing a silicon carbide MOS device according to the present invention includes the following steps: A silicon carbide substrate with an N-type silicon carbide epitaxial layer is provided; A P-type channel region is formed in the N-type silicon carbide epitaxial layer; Nitrogen ion implantation is performed on the P-type channel region; A high-temperature annealing step is performed to activate the injected nitrogen atoms; A gate oxide layer is formed on the P-type channel region to form a gate electrode; Within the P-type channel region, a source region and a drain region are formed on both sides of the gate electrode.

[0007] In a preferred embodiment, a P-well is formed in the N-type silicon carbide epitaxial layer.

[0008] In a preferred embodiment, the high-temperature annealing step is performed at a temperature of 1500°C to 1600°C.

[0009] In a preferred embodiment, the high-temperature annealing step is performed under an inert gas protective atmosphere.

[0010] In a preferred embodiment, the high-temperature annealing step includes the following steps: The first annealing step is performed at the first temperature; A second annealing step is performed in a nitrogen-containing atmosphere at a second temperature lower than the first temperature.

[0011] In a preferred embodiment, the nitrogen ion implantation dose is 1E12-1E13 cm⁻¹. - ².

[0012] A silicon carbide MOS device according to the present invention includes: silicon carbide substrate; An N-type silicon carbide epitaxial layer is formed on the silicon carbide substrate; A P-type channel region formed in the N-type silicon carbide epitaxial layer; An N-type source region and an N-type drain region are formed within the P-type channel region and separated by a portion of the P-type channel region; A gate oxide layer formed on the P-type channel region; and a gate electrode formed on the gate oxide layer; At the interface between the P-type channel region and the gate oxide layer, activated nitrogen atoms, introduced through ion implantation and high-temperature annealing, are distributed within the silicon carbide lattice of the P-type channel region. The implantation dose of these nitrogen atoms is 1E12-1E13 cm⁻¹. - ².

[0013] In a preferred embodiment, the P-type channel region is a P-well.

[0014] In a preferred embodiment, the silicon carbide MOS device is planar or trench type.

[0015] In a preferred embodiment, the silicon carbide MOS device is a trench type, which includes a trench formed in the silicon carbide substrate, and the P-type channel region is formed on the sidewall of the trench.

[0016] Compared with the prior art, the present invention has the following beneficial effects: 1. This invention introduces activated nitrogen atoms into the surface lattice of silicon carbide before oxidation, enabling them to actively participate in the interfacial reaction during subsequent thermal oxidation, thereby fundamentally suppressing the generation of carbon-related defects. Compared with the existing "post-passivation" method, this invention is more effective and thorough.

[0017] 2. This invention can significantly reduce the trap density at the silicon carbide-silicon dioxide interface by "suppressing" carbon defects at the source and by "passivating" residual defects by nitrogen atoms themselves.

[0018] 3. By reducing the interface state density, this invention reduces Coulomb scattering and trapping of channel carriers, thereby significantly improving the channel mobility of the device and effectively reducing the on-resistance of the device.

[0019] 4. The present invention uses low-dose implantation to form dispersed interface doping, which avoids adverse effects on key electrical parameters such as the threshold voltage of the device. Attached Figure Description

[0020] Other features, objects, and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings: Figure 1 This is a schematic diagram of a cross-sectional structure of a silicon carbide MOS unit in the prior art, which is the main feature of this invention. Figure 2 This is a schematic diagram illustrating the nitrogen ion implantation step, which is the main feature of this invention. Figure 3 This is a microscopic schematic diagram illustrating the changes in the silicon carbide lattice before and after nitrogen ion implantation, which is the main feature of this invention. Detailed Implementation

[0021] The present invention will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present invention, but do not limit the invention in any way. It should be noted that those skilled in the art can make several changes and improvements without departing from the concept of the present invention. These all fall within the protection scope of the present invention.

[0022] Example 1 like Figures 1 to 3As shown, this embodiment provides a method for manufacturing a silicon carbide MOS device and illustrates the device structure formed using this method. This method aims to suppress the generation of carbon-related defects during thermal oxidation at the source by performing precise interface pretreatment on the channel region before the formation of the gate oxide layer, thereby significantly improving the electrical performance and reliability of the device.

[0023] The process includes the following steps: providing a silicon carbide substrate having an N-type silicon carbide epitaxial layer; forming a P-type channel region in the N-type silicon carbide epitaxial layer; performing nitrogen ion implantation on the P-type channel region; performing a high-temperature annealing step to activate the implanted nitrogen atoms; forming a gate oxide layer on the P-type channel region to form a gate electrode; and forming a source region and a drain region on both sides of the gate electrode within the P-type channel region.

[0024] Specifically, a heavily N-type doped 4H-SiC single-crystal substrate is provided, on which a lightly N-type doped silicon carbide epitaxial layer is epitaxially grown. This silicon carbide epitaxial layer will serve as the main body of the active region of the device. In some applications, this silicon carbide substrate can serve as the drain of the final device.

[0025] Step S10 is executed to form a P-type channel region. In this embodiment, the P-type channel region is specifically a P-well structure. Specifically, the process includes: firstly, cleaning the surface of the silicon carbide epitaxial wafer using a standard cleaning process to remove surface particles and organic contaminants; then, uniformly coating a layer of photoresist onto the wafer surface using spin coating, and using ultraviolet lithography, exposing and developing the photoresist with a pre-designed P-well mask to open a window in the predetermined area for forming the P-well; subsequently, using the photoresist as a mask, placing the wafer in an ion implanter, and implanting P-type dopants, such as aluminum ions or boron ions, into the exposed silicon carbide epitaxial layer region. The implantation energy and dose are precisely calculated to form a P-well with a specific junction depth and doping concentration. After implantation, the remaining photoresist is removed by plasma ashing or chemical solvent stripping. Figure 1 The diagram schematically illustrates the cross-sectional structure of the device cell after the formation of the P-well (PW), which will serve as the channel body for subsequent MOS devices.

[0026] After the P-well is formed and before the gate oxide layer is formed, nitrogen ion implantation and high-temperature annealing are performed sequentially.

[0027] like Figure 2As shown, step S20 is performed to perform low-dose nitrogen ion implantation. After completing step S10 and removing the P-well implantation mask, the entire wafer is fed back into the ion implanter. This time, no additional mask is needed; a low-dose, shallow nitrogen ion implantation is performed on the entire wafer surface, particularly the surface region of the previously formed P-well, using the nitrogen ion implantation source. In this embodiment, the nitrogen ion implantation energy is set to a low value, such as 30 kiloelectron volts, to ensure that the implanted nitrogen ions are mainly distributed in a very shallow region below the silicon carbide surface layer, with a projected range of approximately tens of nanometers. Simultaneously, by precisely controlling the ion beam intensity and scanning time during the implantation process, the total implantation dose is precisely controlled at 1 × 10¹² cm⁻¹. - ². It should be noted that this dosage is in the low-dose range. Its purpose is not to change the P-type conductivity of the P-well, nor to form a continuous nitride material layer, but to introduce a controlled number of dispersed nitrogen atoms into the silicon carbide lattice where the interface is about to be formed.

[0028] After nitrogen ion implantation, step S30 is performed for high-temperature annealing. The wafer is removed from the ion implanter and placed in a high-temperature annealing furnace. A high-purity inert gas (e.g., argon) is introduced into the annealing furnace to create a protective atmosphere, preventing unnecessary oxidation or surface decomposition of the wafer at high temperatures. The furnace temperature is then rapidly increased to 1500°C and maintained at this temperature for 30 minutes. This high-temperature annealing step serves a dual purpose: firstly, to repair damage to the silicon carbide lattice caused during P-well implantation and nitrogen ion implantation, restoring lattice integrity; and secondly, to provide sufficient thermal energy to the implanted nitrogen atoms, enabling them to migrate within the lattice and enter electrically active sites.

[0029] like Figure 3 The diagram shows a microscopic representation of the changes in the silicon carbide lattice before and after nitrogen ion implantation. During high-temperature annealing, the implanted nitrogen atoms (N), which were originally interstitial atoms, preferentially replace the carbon atoms (C) in the silicon carbide lattice, forming a lower-energy and more stable silicon-nitrogen bond. This is because nitrogen and carbon atoms have similar atomic radii, and the bond energy of the silicon-nitrogen bond is higher than that of the silicon-carbon bond. Through this step, the implanted nitrogen atoms (N) are no longer lattice defects but become part of the silicon carbide lattice, stably "buried" in the surface region of the P-well, preparing for the subsequent gate oxidation step. The annealing temperature of 1500°C and the inert gas protective atmosphere used in this step correspond to the preferred temperature range and atmosphere conditions described in the dependent claims, respectively.

[0030] After high-temperature annealing, i.e., nitrogen atom activation and lattice repair, step S40 is performed to form the gate oxide layer. The wafer treated as described above undergoes standard pre-gate oxide cleaning and is then sent into an oxidation furnace. In this embodiment, a dry oxygen thermal oxidation process is used, in which the wafer is heat-treated at 1200°C in a pure oxygen atmosphere, causing the silicon carbide on its surface to react with oxygen to grow a 50-nanometer-thick layer of silicon dioxide as the gate oxide layer of the device.

[0031] In this crucial oxidation process, the technical solution of this application plays a core role. Since activated nitrogen atoms (N) that have replaced carbon sites are pre-existing in the silicon carbide lattice of the surface region of the P-well (i.e., the future channel region), these nitrogen atoms actively participate in and regulate the pathway of the interfacial reaction during the high-temperature oxidation reaction (SiC + O2 → SiO2 + C). They can effectively capture or occupy carbon vacancies that may form due to incomplete carbon atom oxidation, or directly form stable silicon-nitrogen bonds with surrounding silicon atoms. This thermodynamically and kinetically inhibits the aggregation of carbon atoms near the interface to form carbon clusters and reduces the generation of unstable silicon-carbon dangling bonds. In other words, the method of this application does not passivate after defects form, but rather prevents the formation of major interfacial defects at the source.

[0032] Next, step S50 is executed to complete the subsequent MOS process. A layer of polysilicon is deposited on the formed gate oxide layer using methods such as low-pressure chemical vapor deposition, and the polysilicon is doped to reduce its resistivity. Then, the polysilicon layer is patterned using photolithography and etching processes to form the device gate. Next, using the formed gate as a mask, an N-type heavily doped ion implantation, such as phosphorus ions, is performed to self-align the N+ source and N+ drain regions within the P-wells on both sides of the gate (the drain region is not shown separately from the source region in the two-dimensional cross-sectional view). Simultaneously, a P-type heavily doped implantation is performed to form the P+ body contact region P+ for P-well potential extraction. After implantation, an activation annealing is performed to activate the dopants in the source, drain, and body contact regions. Subsequently, standard back-end processes such as interlayer dielectric deposition, contact hole etching, metallization (forming the source, drain, gate, and body electrodes), and passivation layer deposition are performed sequentially to finally complete the fabrication of the entire planar silicon carbide MOS device.

[0033] The final device comprises: a silicon carbide substrate (with an epitaxial layer), a P-well formed on the substrate, an N+ source region within the P-well, a gate oxide layer covering the P-well channel region, and a gate on top of the gate oxide layer. The fundamental difference from conventional devices lies in the presence of a nitrogen-containing interface region on the silicon carbide side at the interface between the P-well and the gate oxide layer. This nitrogen-containing interface region is not an independent material layer, but rather refers to the stable distribution of activated nitrogen atoms that have replaced lattice positions within the surface silicon carbide lattice of the P-well due to the pre-gate nitrogen ion implantation and high-temperature annealing process described in this application. The areal density of these nitrogen atoms corresponds to an initial implantation density of 1 × 10¹² cm⁻¹. - ² dosage.

[0034] By employing the method of this embodiment, the silicon carbide MOS device fabricated exhibits a significantly lower interface state density at the silicon dioxide / silicon carbide interface compared to devices without this method. Because the Coulomb scattering and trap-emission effects of interface traps on channel carriers (electrons) are greatly weakened, the channel mobility of the device is significantly improved, thereby effectively reducing the on-resistance of the device. Correspondingly, a more perfect interface structure reduces electric field concentration and trap-assisted tunneling in the gate oxide layer, improving the long-term reliability of the gate oxide layer, such as the stability of time-dependent dielectric breakdown lifetime and threshold voltage.

[0035] Example 2 This embodiment provides an optimized annealing process to illustrate that the core concept of "gate pre-injection + annealing" can be flexibly combined with various specific annealing schemes to meet higher requirements for interface quality. This embodiment is also based on the fabrication of planar MOS.

[0036] The preliminary steps of the manufacturing process are similar to those in Example 1, including providing an N-type epitaxial wafer and forming a P-well by ion implantation.

[0037] After the P-trap is formed, a nitrogen ion implantation step is performed (corresponding to step S20). In this embodiment, a dose value in the middle of a preferred range is selected, for example, the nitrogen ion implantation dose is set to 5 × 10¹² cm⁻¹. - ².

[0038] The feature of this embodiment is the high-temperature annealing step S30, which employs a two-step annealing process that combines the advantages of different temperatures and atmospheres.

[0039] The two-step annealing process includes: Step 1, Activation Annealing. The wafer is placed in an annealing furnace, and under an inert gas atmosphere such as argon, the temperature is rapidly raised to a high first temperature, for example, 1600°C, and held for 15 minutes. The main purpose of this step is to utilize sufficiently high thermal energy to efficiently repair lattice damage caused by ion implantation and drive the implanted nitrogen atoms into substitution sites in the silicon carbide lattice to achieve full electrical activation. Step 2, Passivation Annealing. After completing Step 1 annealing, the wafer is not removed, but the temperature is lowered to a relatively low second temperature in the furnace, for example, 1150°C. Simultaneously, the gas environment in the furnace is switched from an inert gas to a nitrogen-containing weak oxidizing atmosphere, such as nitrous oxide, and held under these conditions for 60 minutes. The purpose of this step is to use a nitrogen-containing atmosphere at a lower temperature to perform a gentle chemical passivation on the very few dangling bonds or other defects that may still remain on the outermost layer after high-temperature activation. This is equivalent to adding a delicate "repair" process on top of "source suppression."

[0040] Understandably, this two-step process, which includes a first annealing at a first temperature and a second annealing at a second temperature below the first temperature in a nitrogen-containing atmosphere, constitutes a preferred implementation of the basic high-temperature annealing step.

[0041] After this composite annealing process is completed, the subsequent gate oxide layer formation (step S40) and the remaining MOS device manufacturing steps (step S50) are performed, which are the same as those described in Example 1.

[0042] The final device exhibits a nitrogen-containing interface region formed as a result of the synergistic effect of high-temperature activation and low-temperature passivation. Compared to a single-step annealing process, the two-step annealing process in this embodiment promises to achieve ultimate optimization of interface quality, potentially resulting in lower interface state density and superior long-term device reliability. The results of this embodiment demonstrate that the core technical concept of this application possesses strong process flexibility and can be combined with different annealing schemes (single-step or multi-step, different atmosphere combinations) according to specific performance targets and process platform conditions to achieve optimal technical results.

[0043] In the description of this application, it should be understood that the terms "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0044] Specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various changes or modifications within the scope of the claims, which do not affect the essence of the present invention. Unless otherwise specified, the embodiments and features described in this application can be arbitrarily combined with each other.

Claims

1. A method for manufacturing a silicon carbide MOS device, characterized in that, Includes the following steps: A silicon carbide substrate with an N-type silicon carbide epitaxial layer is provided; A P-type channel region is formed in the N-type silicon carbide epitaxial layer; Nitrogen ion implantation is performed on the P-type channel region; A high-temperature annealing step is performed to activate the injected nitrogen atoms; A gate oxide layer is formed on the P-type channel region to form a gate electrode; Within the P-type channel region, a source region and a drain region are formed on both sides of the gate electrode.

2. The method for manufacturing a silicon carbide MOS device according to claim 1, characterized in that, A P-well is formed in the N-type silicon carbide epitaxial layer.

3. The method for manufacturing a silicon carbide MOS device according to claim 1, characterized in that, The high-temperature annealing step is carried out at a temperature of 1500°C to 1600°C.

4. The method for manufacturing a silicon carbide MOS device according to claim 1, characterized in that, The high-temperature annealing step is carried out under an inert gas protective atmosphere.

5. The method for manufacturing a silicon carbide MOS device according to claim 1, characterized in that, The high-temperature annealing step includes the following steps: The first annealing step is performed at the first temperature; A second annealing step is performed in a nitrogen-containing atmosphere at a second temperature lower than the first temperature.

6. The method for manufacturing a silicon carbide MOS device according to claim 1, characterized in that, The nitrogen ion implantation dose is 1E12-1E13 cm⁻¹. - ².

7. A silicon carbide MOS device, manufactured using the method for manufacturing a silicon carbide MOS device according to any one of claims 1 to 6, characterized in that, include: silicon carbide substrate; An N-type silicon carbide epitaxial layer is formed on the silicon carbide substrate; A P-type channel region formed in the N-type silicon carbide epitaxial layer; An N-type source region and an N-type drain region are formed within the P-type channel region and separated by a portion of the P-type channel region; A gate oxide layer is formed on the P-type channel region; and the gate electrode formed on the gate oxide layer, At the interface between the P-type channel region and the gate oxide layer, activated nitrogen atoms, introduced through ion implantation and high-temperature annealing, are distributed within the silicon carbide lattice of the P-type channel region. The implantation dose of these nitrogen atoms is 1E12-1E13 cm⁻¹. - ².

8. The silicon carbide MOS device according to claim 7, characterized in that, The P-type channel region is a P-well.

9. The silicon carbide MOS device according to claim 7, characterized in that, The silicon carbide MOS device is either planar or trench type.

10. The silicon carbide MOS device according to claim 7, characterized in that, The silicon carbide MOS device is a trench type, which includes a trench formed in the silicon carbide substrate, and the P-type channel region is formed on the sidewall of the trench.

Images