A method for manufacturing an SGTMOS device and the SGTMOS device itself.

Abstract

The application relates to the technical field of semiconductors, in particular to a manufacturing method of an SGT MOS device and the SGT MOS device. The method comprises the following steps: forming an epitaxial layer on a substrate; forming a first cell region and a second cell region on the epitaxial layer, the first cell region and the second cell region are in a parallel structure; the first cell region comprises a first recess, a first isolation layer, a first shielding gate region and a first control gate region; the first control gate region comprises a first control gate and a first gate oxide layer, the first gate oxide layer is filled between the first control gate and the sidewall in the first recess; the second control gate region of the second cell region comprises a second control gate, a second gate oxide layer and a sacrifice oxide layer; the sacrifice oxide layer is located between the second gate oxide layer and the sidewall in the second recess, and the second gate oxide layer is located between the second control gate and the sacrifice oxide layer. The device manufactured by the method has the characteristics of reducing the zero temperature coefficient point and optimizing the expansion of the safe working area of the device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for manufacturing an SGT MOS device and the SGT MOS device itself. Background Technology

[0002] SGT MOSFET devices (Shielded Gate Trench Metal Oxide Semiconductor Field-Effect Transistor, or SGT MOS for short) are a new generation of power semiconductor devices with core advantages such as low on-resistance, low switching losses, high frequency characteristics, and excellent high-temperature stability. Due to their superior performance, SGT MOSFET devices are widely used in consumer electronics fast charging, new energy vehicles, industrial power supplies, energy storage systems, and motor drives. The widespread application of hot-swappable technology has placed higher demands on the safe operating area of ​​SGT MOSFET devices in harsh environments (such as automotive environments). This requires SGT MOSFET devices to operate in linear mode for milliseconds or longer under high voltage and high current conditions.

[0003] However, in pursuit of lower on-resistance, existing SGT MOSFET devices continuously shrink their cell size, further increasing power density and raising the zero-temperature coefficient point. This inevitably leads to positive thermoelectric coupling, deteriorating the safe operating area and potentially causing device burnout. Therefore, existing SGT MOSFET devices suffer from the problem of deterioration of the safe operating area due to the increased zero-temperature coefficient point. Summary of the Invention

[0004] This application provides a method for manufacturing an SGT MOS device and an SGT MOS device, which solves the technical problem in the prior art where the safe operating area of ​​the SGT MOSFET device deteriorates due to the increase of the zero temperature coefficient point. It achieves the technical effects of reducing the zero temperature coefficient point of the SGT MOSFET device, optimizing and expanding the safe operating area of ​​the device, and improving the reliability and stability of the device.

[0005] In a first aspect, embodiments of the present invention provide a method for manufacturing an SGT MOS device, comprising: An epitaxial layer is formed on the substrate; A first cell region and a second cell region are formed on the epitaxial layer, and the first cell region and the second cell region are in a parallel structure; The first cell region includes: a first groove, and a first isolation layer, a first shielding gate region, and a first control gate region located within the first groove; within the first groove, the first control gate region and the first shielding gate region are arranged in an upper and lower structure, and the first isolation layer is located between the first control gate region and the first shielding gate region; the first control gate region includes: a first control gate and a first gate oxide layer, and the first gate oxide layer fills the space between the first control gate and the sidewall within the first groove. The second cell region includes: a second groove, and a second isolation layer, a second shielding gate region, and a second control gate region located within the second groove; within the second groove, the second control gate region and the second shielding gate region are arranged in an upper and lower structure, and the second isolation layer is located between the second control gate region and the second shielding gate region; the second control gate region includes: a second control gate, a second gate oxide layer, and a sacrificial oxide layer; the sacrificial oxide layer is located between the second gate oxide layer and the sidewall within the second groove, and the second gate oxide layer is located between the second control gate and the sacrificial oxide layer.

[0006] Optionally, the width of the sacrificial oxide layer ranges from 200 Å to 400 Å.

[0007] Optionally, the proportion of the second cell region is between 30% and 50%.

[0008] Optionally, forming the first cell region and the second cell region on the epitaxial layer includes: After forming the first shielding gate region in the first groove, the first isolation layer is formed in the first groove and above the first shielding gate region; and after forming the second shielding gate region in the second groove, the second isolation layer is formed in the second groove and above the second shielding gate region. The sacrificial oxide layer is formed on the sidewall of the first groove and above the first isolation layer, and the sacrificial oxide layer is formed on the sidewall of the second groove and above the second isolation layer. Photoresist is provided to cover the sacrificial oxide layer in the second groove, and the sacrificial oxide layer in the first groove is removed by dry etching process. After removing the photoresist, a first gate oxide layer is formed on the sidewall inside the first groove and above the first isolation layer, and a second gate oxide layer is formed on the sacrificial oxide layer inside the second groove and above the second isolation layer. The first control gate is formed between the first gate oxide layers within the first groove, and the second control gate is formed between the second gate oxide layers within the second groove.

[0009] Optional, also includes: Doped regions are formed on both sides of the first cell region and on both sides of the second cell region. The doped regions include P-well regions and N-well regions. The P-well regions are located on the epitaxial layer, and the N-well regions are located on the P-well regions. The upper surface of the N-well regions and the upper surface of the epitaxial layer are located on the same horizontal plane.

[0010] Optional, also includes: An ILD dielectric layer is formed on the doped region, on the first cell region, and on the second cell region.

[0011] Optional, also includes: A contact hole is etched through the ILD dielectric layer and the N-well region, with the bottom of the contact hole located in the P-well region; A P+ contact area is formed at the bottom of the contact hole; Metal is filled into the contact hole and above the P+ contact area to obtain a contact electrode, and thus an electrode area.

[0012] Optionally, it may also include forming a source metal layer on the ILD dielectric layer and on the electrode region.

[0013] Optionally, it may also include forming a drain metal layer under the substrate.

[0014] Based on the same inventive concept, in a second aspect, the present invention provides an SGT MOS device, which is manufactured by the manufacturing method of the SGT MOS device described in the first aspect. The device includes: a substrate, an epitaxial layer, a first cell region, and a second cell region. The epitaxial layer is located on the substrate; The first cell region and the second cell region are located on the epitaxial layer, and the first cell region and the second cell region are in a parallel structure; The first cell region includes: a first groove, and a first isolation layer, a first shielding gate region, and a first control gate region located within the first groove; within the first groove, the first control gate region and the first shielding gate region are arranged in an upper and lower structure, and the first isolation layer is located between the first control gate region and the first shielding gate region; the first control gate region includes: a first control gate and a first gate oxide layer, and the first gate oxide layer fills the space between the first control gate and the sidewall within the first groove. The second cell region includes: a second groove, and a second isolation layer, a second shielding gate region, and a second control gate region located within the second groove; within the second groove, the second control gate region and the second shielding gate region are arranged in an upper and lower structure, and the second isolation layer is located between the second control gate region and the second shielding gate region; the second control gate region includes: a second control gate, a second gate oxide layer, and a sacrificial oxide layer; the sacrificial oxide layer is located between the second gate oxide layer and the sidewall within the second groove, and the second gate oxide layer is located between the second control gate and the sacrificial oxide layer.

[0015] One or more technical solutions in the embodiments of the present invention have at least the following technical effects or advantages: During the formation of the first and second cell regions on the epitaxial layer above the substrate, the first cell region has a first control gate region and a first shielding gate region arranged vertically. The first control gate region of the first cell region includes a first control gate and a first gate oxide layer, with the first gate oxide layer filling the space between the first control gate and the sidewalls within the first trench. The second cell region also has a second control gate region and a second shielding gate region arranged vertically. The second control gate region of the second cell region includes a second control gate, a second gate oxide layer, and a sacrificial oxide layer, with the sacrificial oxide layer located between the second gate oxide layer and the sidewalls within the second trench, and the second gate oxide layer located between the second control gate and the sacrificial oxide layer. This forms a parallel cell structure with different gate oxide thicknesses. At a low gate-source voltage Vgs, the channel of the first cell region is in the open state, and the channel of the second cell region is in the closed state, effectively reducing the current density and power consumption of the entire device, i.e., reducing the zero temperature coefficient (ZTC) point. At high gate-source voltage Vgs, all cell channels are open, meaning both the channels in the first and second cell regions are in the open state, resulting in a slight impact on the device's on-resistance Rdson. This widens the safe operating area of ​​the SGT MOS device, improving its stability, reliability, and practicality, and effectively reduces the zero temperature coefficient point while maintaining high power density. Attached Figure Description

[0016] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings: Figure 1 A schematic flowchart of the manufacturing method of the SGT MOS device in an embodiment of the present invention is shown; Figure 2A schematic diagram of the structure of the SGT MOS device in an embodiment of the present invention is shown; Figure 3 This diagram illustrates a structure in an embodiment of the present invention in which an epitaxial layer and a groove are formed on a substrate. Figure 4 This diagram illustrates a structural schematic of forming a field oxide layer within a groove in an embodiment of the present invention. Figure 5 This diagram illustrates a structure in which polycrystalline silicon material is filled within the recessed space of the field oxide layer in an embodiment of the present invention. Figure 6 This diagram illustrates a structure for etching polycrystalline silicon material within the recessed space of the field oxide layer in an embodiment of the present invention. Figure 7 A schematic diagram of the structure in which an isolation layer is formed in a groove is shown in an embodiment of the present invention; Figure 8 A schematic diagram of a structure in which a sacrificial oxide layer is formed in a groove (i.e., a first groove and a second groove) is shown in an embodiment of the present invention; Figure 9 A schematic diagram of the sacrificial oxide layer in the etched first groove is shown in an embodiment of the present invention; Figure 10 This diagram illustrates a structure in an embodiment of the present invention in which a first gate oxide layer and a second gate oxide layer are formed in a first groove and a second groove, respectively. Figure 11 A schematic diagram of the transmission characteristic curve of the comparative device in an embodiment of the present invention is shown; Figure 12 A schematic diagram of the transfer characteristic curves of SGT MOS devices with different gate oxide combinations in embodiments of the present invention is shown. In the attached figures, 201 is the substrate; 202 is the epitaxial layer; 210 is the first cell region; 220 is the second cell region; 203 is the P-well region; 204 is the N-well region; 205 is the ILD dielectric layer; 230 is the electrode region; 206 is the source metal layer; 207 is the drain metal layer; and 208 is the photoresist. 211, First groove; 212, First isolation layer; 213, First shielded gate region; 214, First control gate region; 2131, First shielded gate; 2132, First field oxide layer; 2141, First control gate; 2142, First gate oxide layer; 221. Second groove; 222. Second isolation layer; 223. Second shielded gate region; 224. Second control gate region; 2231. Second shielded gate; 2232. Second field oxide layer; 2241. Second control gate; 2242. Second gate oxide layer; 2243. Sacrificial oxide layer; 231. Contact hole; 232. P+ contact area; 233. Contact electrode. Detailed Implementation

[0017] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0018] Example 1 The first embodiment of the present invention provides a method for manufacturing an SGT MOS device, such as... Figure 1 and Figure 2 As shown, it includes: S101, an epitaxial layer 202 is formed on the substrate 201; S102, a first cell region 210 and a second cell region 220 are formed on the epitaxial layer 202. The first cell region 210 and the second cell region 220 are in a parallel structure, that is, the first cell region 210 and the second cell region 220 are connected in parallel. The first cell region 210 includes: a first groove 211, and a first isolation layer 212, a first shielding gate region 213, and a first control gate region 214 located within the first groove 211; within the first groove 211, the first control gate region 214 and the first shielding gate region 213 are arranged in an upper and lower structure, and the first isolation layer 212 is located between the first control gate region 214 and the first shielding gate region 213; the first control gate region 214 includes: a first control gate 2141 and a first gate oxide layer 2142, and the first gate oxide layer 2142 fills the space between the first control gate 2141 and the sidewall within the first groove 211; The second cell region 220 includes: a second groove 221, and a second isolation layer 222, a second shielding gate region 223, and a second control gate region 224 located within the second groove 221; within the second groove 221, the second control gate region 224 and the second shielding gate region 223 are arranged in an upper and lower structure, and the second isolation layer 222 is located between the second control gate region 224 and the second shielding gate region 223; the second control gate region 224 includes: a second control gate 2241, a second gate oxide layer 2242, and a sacrificial oxide layer 2243; the sacrificial oxide layer 2243 is located between the second gate oxide layer 2242 and the sidewall within the second groove 221, and the second gate oxide layer 2242 is located between the second control gate 2241 and the sacrificial oxide layer 2243.

[0019] It should be noted that in this embodiment, the first cell region 210 is a cell region without the sacrificial oxide layer 2243, and the second cell region 220 is a cell region with the sacrificial oxide layer 2243. Figure 2Only the simplest parallel structure of the first cell region 210 and the second cell region 220 is shown. In an actual chip, several cell regions can be divided into sections, with each cell region of one section designated as the first cell region 210 and each cell region of another section designated as the second cell region 220. Alternatively, a portion of the cell regions in the chip can be designated as the second cell region 220, and the remaining cell regions as the first cell regions 210. The specific arrangement of the cell regions is not limited. In this embodiment, structures marked with "first" refer to the structure of the first cell region 210, i.e., the cell region without the sacrificial oxide layer 2243. Structures marked with "second" refer to the structure of the second cell region 220, i.e., the cell region with the sacrificial oxide layer 2243.

[0020] In this embodiment, during the formation of the first cell region 210 and the second cell region 220 on the epitaxial layer 202 above the substrate 201, the first cell region 210 has a first control gate region 214 and a first shielding gate region 213 arranged vertically. The first control gate region 214 of the first cell region 210 includes a first control gate 2141 and a first gate oxide layer 2142, with the first gate oxide layer 2142 filling between the first control gate 2141 and the sidewalls within the first recess 211. The second cell region 220 also has a second control gate region 224 and a second shielding gate region 223 arranged vertically. The second control gate region 224 of the second cell region 220 includes a second control gate 2241, a second gate oxide layer 2242, and a sacrificial oxide layer 2243, with the sacrificial oxide layer 2243 located between the second gate oxide layer 2242 and the sidewalls within the second recess 221, and the second gate oxide layer 2242 located between the second control gate 2241 and the sacrificial oxide layer 2243. This creates a parallel cell structure with different gate oxide thicknesses. At low gate-source voltage Vgs, the channel of the first cell region 210 is in the open state, while the channel of the second cell region 220 is in the closed state, effectively reducing the overall device current density and power consumption, i.e., lowering the zero temperature coefficient (ZTC) point. At high gate-source voltage Vgs, all cell channels are open, meaning both the channels of the first cell region 210 and the second cell region 220 are in the open state, resulting in a slight impact on the device's on-resistance Rdson. This widens the safe operating area of ​​the SGT MOS device, improving its stability, reliability, and practicality, while effectively lowering the zero temperature coefficient point while maintaining high power density.

[0021] Below, in conjunction with Figure 1 and Figure 2 This embodiment details the specific implementation steps of the SGT MOS device manufacturing method and the specific structure of the SGT MOS device: First, step S101 is performed to form an epitaxial layer 202 on the substrate 201. Specifically, as shown... Figure 2 and 3 As shown, substrate 201 is an N-type silicon substrate, and epitaxial layer 202 is an N-type epitaxial layer. The thickness of epitaxial layer 202 can be set according to actual needs.

[0022] Next, step S102 is executed to form a first cell region 210 and a second cell region 220 on the epitaxial layer 202. The first cell region 210 and the second cell region 220 are arranged in parallel. The first cell region 210 includes a first recess 211, and a first isolation layer 212, a first shielding gate region 213, and a first control gate region 214 located within the first recess 211. Within the first recess 211, the first control gate region 214 and the first shielding gate region 213 are arranged vertically, with the first isolation layer 212 located between the first control gate region 214 and the first shielding gate region 213. The first control gate region 214 includes a first control gate 2141 and a first gate oxide layer 2142, with the first gate oxide layer 2142 filling the space between the first control gate 2141 and the sidewalls within the first recess 211. The first shielding gate region 213 includes a first shielding gate 2131 and a first field oxide layer 2132. The upper surface of the first shielding grid 2131 is in contact with the lower surface of the first isolation layer 212. The first field oxide layer 2132 fills the space between the first shielding grid 2131 and the sidewalls and bottom wall of the first groove 211.

[0023] The second cell region 220 includes a second recess 221, and a second isolation layer 222, a second shielding gate region 223, and a second control gate region 224 located within the second recess 221. Within the second recess 221, the second control gate region 224 and the second shielding gate region 223 are arranged vertically, with the second isolation layer 222 located between the second control gate region 224 and the second shielding gate region 223. The second control gate region 224 includes a second control gate 2241, a second gate oxide layer 2242, and a sacrificial oxide layer 2243. The sacrificial oxide layer 2243 is located between the second gate oxide layer 2242 and the sidewall within the second recess 221, and the second gate oxide layer 2242 is located between the second control gate 2241 and the sacrificial oxide layer 2243. The second shielding gate region 223 includes a second shielding gate 2231 and a second field oxide layer 2232. The upper surface of the second shielding gate 2231 is in contact with the lower surface of the second isolation layer 222. The second oxide layer 2232 is filled between the sidewalls and bottom wall of the second shielding grid 2231 and the second groove 221.

[0024] The first cell region 210 has a first control gate region 214 and a first shield gate region 213 arranged vertically. Specifically, the first shield gate region 213 is located at the bottom of the first groove 211, and the first isolation layer 212 is located in the first groove 211 and above the first shield gate region 213, with the bottom surface of the first isolation layer 212 contacting the top surface of the first shield gate region 213. The first control gate region 214 is located in the first groove 211 and above the first isolation layer 212, with the top surface of the first isolation layer 212 contacting the bottom surface of the first control gate region 214. The second cell region 220 also has a second control gate region 224 and a second shield gate region 223 arranged vertically. The specific structural arrangement principle of the second control gate region 224 and the second shield gate region 223 of the second cell region 220 is consistent with the specific structural arrangement principle of the first control gate region 214 and the first shield gate region 213 of the first cell region 210, and will not be described again.

[0025] Specifically, such as Figure 3 As shown, photolithography is performed on the epitaxial layer 202 using a first mask, followed by etching of the epitaxial layer 202. A first groove 211 is formed at a first designated location on the epitaxial layer 202, and a second groove 221 is formed at a second designated location on the epitaxial layer 202. The depth and width of the first groove 211 and the second groove 221 are determined based on the process capability and the voltage withstand design of the device.

[0026] like Figure 4 As shown, the process of forming the first shielding gate region 213 in the first groove 211 and the process of forming the second shielding gate region 223 in the second groove 221 involves forming a field oxide layer in each groove (i.e., the first groove 211 and the second groove 221) and along the bottom and sidewalls of the groove using a thermal growth process. This results in the subsequent first field oxide layer 2132 and second field oxide layer 2232. This field oxide layer is used to surround the source polysilicon in subsequent process steps and withstands reverse voltage. The thickness of the field oxide layer can be set according to actual needs. The material of the field oxide layer includes, but is not limited to, silicon dioxide (SiO2) and silicon nitride (SiN).

[0027] like Figure 5 As shown, polycrystalline silicon material is deposited in the recessed space formed by the field oxide layer in the groove, and the polycrystalline silicon is dry-etched back to the surface of the epitaxial layer 202.

[0028] like Figure 6As shown, photoresist covers and protects the terminal region of the device (not shown in the figure), leaving the cell region open, i.e., the photoresist does not cover the cell region. Photolithography is then performed using a second mask to dry-etch the polysilicon material of each cell region, forming the first shielding gate 2131 in the first groove 211 and the second shielding gate 2231 in the second groove 221. The field oxide layer is then etched to form the first field oxide layer 2132 in the first groove 211 and the second field oxide layer 2232 in the second groove 221. Thus, the first shielding gate region 213 in the first groove 211 and the second shielding gate region 223 in the second groove 221 are obtained. The specific structure of the device's terminal region can be set according to actual needs and is not limited here.

[0029] like Figure 7 As shown, after forming a first shielding gate region 213 in the first groove 211 and a second shielding gate region 223 in the second groove 221, an HDP (High-Density Plasma Oxide) layer is deposited on the shielding gate regions within the grooves (i.e., the first shielding gate region 213 in the first groove 211 and the second shielding gate region 223 in the second groove 221). The HDP oxide layer is then chemically and mechanically polished down to the upper surface of the epitaxial layer 202 using CMP (Chemical Mechanical Polishing). Next, the HDP oxide layer is wet- or dry-etched back to form isolation layers, namely, the first isolation layer 212 in the first groove 211 and the second isolation layer 222 in the second groove 221. Finally, the photoresist is removed.

[0030] It should be noted that the formation processes of the first groove 211 and the second groove 221 are consistent, as are the formation processes of the first shielding gate region 213 in the first groove 211 and the second shielding gate region 223 in the second groove 221, and the formation processes of the first isolation layer 212 and the second isolation layer 222 are consistent. Figures 3-7 Only one groove and the formation diagram of the shielding gate region within the groove are shown.

[0031] like Figure 8 As shown, a sacrificial oxide layer 2243 is formed on the sidewall within the first groove 211 and over the first insulating layer 212, and a sacrificial oxide layer 2243 is formed on the sidewall within the second groove 221 and over the second insulating layer 222. Furthermore, as... Figure 9As shown, photoresist 208 is used to cover the sacrificial oxide layer 2243 within the second groove 221. The sacrificial oxide layer 2243 within the first groove 211 is removed by dry etching. The dry etching process of the sacrificial oxide layer 2243 smooths the sidewalls within the first groove 211, improving the morphology and quality of the subsequent growth of the first gate oxide layer 2142. By retaining the sacrificial oxide layer 2243, the second groove 221 thickens the gate oxide thickness of the second cell region 220, achieving cell structures with different thresholds and increasing the threshold voltage of the second cell region 220.

[0032] The width of the sacrificial oxide layer 2243 ranges from 200 Å to 400 Å. If the sacrificial oxide layer 2243 is too thin, the threshold differences between individual cells are not significant, resulting in poor effectiveness in reducing the zero temperature coefficient point. If the sacrificial oxide layer 2243 is too thick, the on-resistance of the device will increase significantly.

[0033] like Figure 10 As shown, after removing the photoresist 208, a first gate oxide layer 2142 is formed on the sidewall of the first groove 211 and above the first isolation layer 212, and a second gate oxide layer 2242 is formed on the sacrificial oxide layer 2243 in the second groove 221 and above the second isolation layer 222. Thus, the gate oxide thickness in the second groove 221 is the width of the sacrificial oxide layer 2243 plus the width of the second gate oxide layer 2242. The gate oxide thickness in the first groove 211 is only the width of the first gate oxide layer 2142. The width of the gate oxide layers (i.e., the first gate oxide layer 2142 / second gate oxide layer 2242) ranges from 500 Å to 800 Å.

[0034] like Figure 2 As shown, a first control gate 2141 is formed between first gate oxide layers 2142 within a first groove 211, and a second control gate 2241 is formed between second gate oxide layers 2242 within a second groove 221. Specifically, gate polysilicon is deposited between the first gate oxide layers 2142 within the first groove 211, and the gate polysilicon is etched back to obtain the first control gate 2141. Similarly, gate polysilicon is deposited between the second gate oxide layers 2242 within the second groove 221, and the gate polysilicon is etched back to obtain the second control gate 2241.

[0035] like Figure 2As shown, doped regions are formed on both sides of the first cell region 210 and both sides of the second cell region 220. The doped regions include a P-well region 203 and an N-well region 204. The P-well region 203 is located on the epitaxial layer 202, and the N-well region 204 is located on the P-well region 203. The upper surface of the N-well region 204 and the upper surface of the epitaxial layer 202 are on the same horizontal plane. Specifically, on both sides of each cell region, P-type impurities are implanted and bonded on the epitaxial layer 202 to form the P-well region 203, and then N-type impurities are implanted and bonded on the P-well region 203 to form the N-well region 204.

[0036] Next, an ILD (Interlayer Dielectric) dielectric layer 205 is formed over the doped region, the first cell region 210, and the second cell region 220. The ILD dielectric layer 205 serves as an insulating isolation layer, responsible for insulation, capacitance reduction, and structural support. Then, a contact hole 231 is etched through the ILD dielectric layer 205 and the N-well region 204, with the bottom of the contact hole 231 located in the P-well region 203. A P+ contact region 232 is formed at the bottom of the contact hole 231. A filler metal is deposited within the contact hole 231 and over the P+ contact region 232 to obtain a contact electrode 233, thereby obtaining an electrode region 230. The electrode region 230 includes the contact hole 231, the P+ contact region 232, and the contact electrode 233. Finally, a source metal layer 206 is formed over the ILD dielectric layer 205 and the electrode region 230, and a drain metal layer 207 is formed under the substrate 201.

[0037] Furthermore, the proportion of the second cell region 220 ranges from 30% to 50%, meaning that the number of second cell regions 220 accounts for 30% to 50% of the total number of cell regions on the device. If the proportion of the second cell region 220 is too small, the effect of reducing the zero temperature coefficient point will be poor. If the proportion of the second cell region 220 is too large, the on-resistance of the device will increase significantly.

[0038] To more clearly illustrate the principle of the SGT MOS device in this embodiment, the principle of existing SGT MOS devices will first be explained: The existing SGT MOS device serves as a comparative device in this embodiment. The structure of the comparative device is identical to the device structure of this embodiment, which only has the first cell region 210. For example... Figure 11 The transfer characteristic curves of the comparative device are shown, with the horizontal axis representing the gate-source voltage and the vertical axis representing the drain current. The solid line represents the transfer characteristic curve of the comparative device at 25°C, and the dashed line represents the transfer characteristic curve of the comparative device at 150°C. Figure 11In the diagram, the intersection of the two curves is the zero temperature coefficient (ZTC) point, i.e., dI / dT = 0, where I is the drain current and T is the temperature. When the gate-source voltage is below the ZTC point, the drain current increases with increasing temperature. When the gate-source voltage is above the ZTC point, the drain current decreases with increasing temperature. Therefore, when the gate-source voltage is below the ZTC point, the positive temperature characteristic of the drain current generates a positive thermoelectric coupling effect, thereby deteriorating the safe operating area of ​​the device and leading to device burnout. Furthermore, the pursuit of lower on-resistance and continuous reduction in device cell size further increases the power density, leading to an increase in the zero temperature coefficient point of the device, further exacerbating the positive thermoelectric coupling effect, deteriorating the safe operating area, and ultimately causing device burnout.

[0039] Through the manufacturing method and structural arrangement of the SGT MOS device in this embodiment, when removing the sacrificial oxide layer 2243 before the growth of the first gate oxide layer 2142 in the first cell region 210, a photomask is used to photolithographically etch and remove the sacrificial oxide layer 2243 in the first groove 211, while retaining the sacrificial oxide layer 2243 in the second groove 221. Then, a gate oxide layer is grown on this basis, resulting in the first gate oxide layer 2142 in the first groove 211 and the gate oxide layer in the second groove 221, thereby forming a parallel cell structure with different gate oxide thicknesses (i.e., different threshold voltages). Under low gate-source voltage, the channel in the second cell region 220 remains in the off state, while only the channel in the first cell region 210 is in the on state, effectively reducing current density and power consumption, i.e., lowering the zero temperature coefficient (ZTC) point. At high gate-source voltages, all cell channels are on, meaning the channels of the first cell region 210 and the second cell region 220 are in the on-state, resulting in a slight impact on the device's on-resistance. This widens the safe operating area of ​​the SGT MOS device, improving its stability, reliability, and usability, and effectively reduces the zero-temperature coefficient point while maintaining high power density.

[0040] exist Figure 12In the diagram, the horizontal axis X represents the gate-source voltage, and the vertical axis Y represents the drain current. Curve La represents the transport characteristic curve of an SGT MOS device with a gate oxide thickness of 600 Å in the first cell region 210 and 600 Å in the second cell region 220 at 150°C. Curve La' represents the transport characteristic curve of the same SGT MOS device at 25°C. Curve Lb represents the transport characteristic curve of an SGT MOS device with a gate oxide thickness of 600 Å in the first cell region 210 and 650 Å in the second cell region 220 at 150°C. Curve Lb' represents the transport characteristic curve of the same SGT MOS device at 25°C. Curve Lc represents the transport characteristics of an SGT MOS device with a gate oxide thickness of 600 Å in the first cell region 210 and 700 Å in the second cell region 220 at 150 °C. Curve Lc' represents the transport characteristics of the same SGT MOS device at 25 °C. Curve Ld represents the transport characteristics of the same SGT MOS device with a gate oxide thickness of 600 Å in the first cell region 210 and 750 Å in the second cell region 220 at 150 °C. Curve Ld' represents the transport characteristics of the same SGT MOS device at 25 °C. Curve Le represents the transport characteristics of an SGT MOS device with a gate oxide thickness of 600 Å in the first cell region 210 and 800 Å in the second cell region 220 at 150 °C, and curve Le' represents the transport characteristics of an SGT MOS device with a gate oxide thickness of 600 Å in the first cell region 210 and 800 Å in the second cell region 220 at 25 °C. Figure 12 The points highlighted in the box represent the zero temperature coefficient points of each device. From Figure 12 As can be seen, the zero temperature coefficient point of each device is significantly reduced, thereby widening the safe operating area of ​​the SGTMOS device, improving the stability, reliability and practicality of the device, and also ensuring the high power density of the device.

[0041] Combination Figure 12As shown in Table 1, there are five groups of SGT MOS devices in this embodiment with different gate oxide combinations. Group 1: SGT MOS devices with a gate oxide thickness of 600 Å in the first cell region 210 and 600 Å in the second cell region 220; Group 2: SGT MOS devices with a gate oxide thickness of 600 Å in the first cell region 210 and 650 Å in the second cell region 220; Group 3: SGT MOS devices with a gate oxide thickness of 600 Å in the first cell region 210 and 700 Å in the second cell region 220; Group 4: SGT MOS devices with a gate oxide thickness of 600 Å in the first cell region 210 and 750 Å in the second cell region 220; Group 5: SGT MOS devices with a gate oxide thickness of 600 Å in the first cell region 210 and 800 Å in the second cell region 220. ΔTox represents the gate oxide thickness difference between the first cell region 210 and the second cell region 220, which is close to the thickness of the sacrificial oxide layer 2243. ZTC represents the ZTC point formed by the gate-source voltage and drain current corresponding to each SGT MOS device. BV is the breakdown voltage of each SGT MOS device. Ron is the on-resistance of each SGT MOS device. Vth is the threshold voltage of each SGT MOS device. Coss is the output capacitance of each SGT MOS device. Ciss is the input capacitance of each SGT MOS device. Crss is the Miller capacitance of each SGT MOS device. Qg is the total gate charge.

[0042] Table 1 from Figure 12 As can be clearly seen from Table 1, the manufacturing method and structural configuration of the SGT MOS device in this embodiment significantly reduce the zero temperature coefficient point of the device, with minimal impact on the on-resistance Rdson. This widens the safe operating area of ​​the SGT MOS device, improves its stability, reliability, and practicality, and effectively reduces the zero temperature coefficient point while maintaining high power density.

[0043] One or more technical solutions in the embodiments of the present invention have at least the following technical effects or advantages: During the formation of the first and second cell regions on the epitaxial layer above the substrate, the first cell region has a first control gate region and a first shielding gate region arranged vertically. The first control gate region of the first cell region includes a first control gate and a first gate oxide layer, with the first gate oxide layer filling the space between the first control gate and the sidewalls within the first trench. The second cell region also has a second control gate region and a second shielding gate region arranged vertically. The second control gate region of the second cell region includes a second control gate, a second gate oxide layer, and a sacrificial oxide layer, with the sacrificial oxide layer located between the second gate oxide layer and the sidewalls within the second trench, and the second gate oxide layer located between the second control gate and the sacrificial oxide layer. This forms a parallel cell structure with different gate oxide thicknesses. At a low gate-source voltage Vgs, the channel of the first cell region is in the open state, and the channel of the second cell region is in the closed state, effectively reducing the current density and power consumption of the entire device, i.e., reducing the zero temperature coefficient (ZTC) point. At high gate-source voltage Vgs, all cell channels are open, meaning both the channels in the first and second cell regions are in the open state, resulting in a slight impact on the device's on-resistance Rdson. This widens the safe operating area of ​​the SGT MOS device, improving its stability, reliability, and practicality, and effectively reduces the zero temperature coefficient point while maintaining high power density.

[0044] Example 2 Based on the same inventive concept, the second embodiment of the present invention also provides an SGT MOS device, such as... Figure 2 As shown, the SGT MOS device is manufactured by the manufacturing method of Embodiment 1. The device includes: a substrate 201, an epitaxial layer 202, a first cell region 210, and a second cell region 220. Epitaxial layer 202 is located on substrate 201; The first cell region 210 and the second cell region 220 are located on the epitaxial layer 202, and the first cell region 210 and the second cell region 220 are in a parallel structure. The first cell region 210 includes: a first groove 211, and a first isolation layer 212, a first shielding gate region 213, and a first control gate region 214 located within the first groove 211; within the first groove 211, the first control gate region 214 and the first shielding gate region 213 are arranged in an upper and lower structure, and the first isolation layer 212 is located between the first control gate region 214 and the first shielding gate region 213; the first control gate region 214 includes: a first control gate 2141 and a first gate oxide layer 2142, and the first gate oxide layer 2142 fills the space between the first control gate 2141 and the sidewall within the first groove 211; The second cell region 220 includes: a second groove 221, and a second isolation layer 222, a second shielding gate region 223, and a second control gate region 224 located within the second groove 221; within the second groove 221, the second control gate region 224 and the second shielding gate region 223 are arranged in an upper and lower structure, and the second isolation layer 222 is located between the second control gate region 224 and the second shielding gate region 223; the second control gate region 224 includes: a second control gate 2241, a second gate oxide layer 2242, and a sacrificial oxide layer 2243; the sacrificial oxide layer 2243 is located between the second gate oxide layer 2242 and the sidewall within the second groove 221, and the second gate oxide layer 2242 is located between the second control gate 2241 and the sacrificial oxide layer 2243.

[0045] Since the SGT MOS device described in this embodiment is manufactured using the manufacturing method of the SGT MOS device in Embodiment 1 of this application, those skilled in the art can understand the specific implementation and various variations of the SGT MOS device in this embodiment based on the manufacturing method of the SGT MOS device described in Embodiment 1 of this application. Therefore, how the SGT MOS device is implemented using the method in Embodiment 1 of this application will not be described in detail here. Any SGT MOS device manufactured by those skilled in the art using the manufacturing method of the SGT MOS device in Embodiment 1 of this application falls within the scope of protection of this application.

[0046] Those skilled in the art will understand that although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the invention.

[0047] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A method for manufacturing an SGT MOS device, characterized in that, include: An epitaxial layer is formed on the substrate; A first cell region and a second cell region are formed on the epitaxial layer, and the first cell region and the second cell region are in a parallel structure; The first cell region includes: a first groove, and a first isolation layer, a first shielding gate region, and a first control gate region located within the first groove; within the first groove, the first control gate region and the first shielding gate region are arranged in an upper and lower structure, and the first isolation layer is located between the first control gate region and the first shielding gate region; the first control gate region includes: a first control gate and a first gate oxide layer, and the first gate oxide layer fills the space between the first control gate and the sidewall within the first groove. The second cell region includes: a second groove, and a second isolation layer, a second shielding gate region, and a second control gate region located within the second groove; within the second groove, the second control gate region and the second shielding gate region are arranged in an upper and lower structure, and the second isolation layer is located between the second control gate region and the second shielding gate region; the second control gate region includes: a second control gate, a second gate oxide layer, and a sacrificial oxide layer; the sacrificial oxide layer is located between the second gate oxide layer and the sidewall within the second groove, and the second gate oxide layer is located between the second control gate and the sacrificial oxide layer.

2. The method for manufacturing the SGT MOS device as described in claim 1, characterized in that, The width of the sacrificial oxide layer ranges from 200 Å to 400 Å.

3. The method for manufacturing the SGT MOS device as described in claim 2, characterized in that, The proportion of the second cell region ranges from 30% to 50%.

4. The method for manufacturing the SGT MOS device as described in claim 3, characterized in that, The formation of the first cell region and the second cell region on the epitaxial layer includes: After forming the first shielding gate region in the first groove, the first isolation layer is formed in the first groove and above the first shielding gate region; and after forming the second shielding gate region in the second groove, the second isolation layer is formed in the second groove and above the second shielding gate region. The sacrificial oxide layer is formed on the sidewall of the first groove and above the first isolation layer, and the sacrificial oxide layer is formed on the sidewall of the second groove and above the second isolation layer. Photoresist is provided to cover the sacrificial oxide layer in the second groove, and the sacrificial oxide layer in the first groove is removed by dry etching process. After removing the photoresist, a first gate oxide layer is formed on the sidewall inside the first groove and above the first isolation layer, and a second gate oxide layer is formed on the sacrificial oxide layer inside the second groove and above the second isolation layer. The first control gate is formed between the first gate oxide layers within the first groove, and the second control gate is formed between the second gate oxide layers within the second groove.

5. The method for manufacturing the SGT MOS device according to any one of claims 1 to 4, characterized in that, Also includes: Doped regions are formed on both sides of the first cell region and on both sides of the second cell region. The doped regions include P-well regions and N-well regions. The P-well regions are located on the epitaxial layer, and the N-well regions are located on the P-well regions. The upper surface of the N-well regions and the upper surface of the epitaxial layer are located on the same horizontal plane.

6. The method for manufacturing the SGT MOS device as described in claim 5, characterized in that, Also includes: An ILD dielectric layer is formed on the doped region, on the first cell region, and on the second cell region.

7. The method for manufacturing the SGT MOS device as described in claim 6, characterized in that, Also includes: A contact hole is etched through the ILD dielectric layer and the N-well region, with the bottom of the contact hole located in the P-well region; A P+ contact area is formed at the bottom of the contact hole; Metal is filled into the contact hole and above the P+ contact area to obtain a contact electrode, and thus an electrode area.

8. The method for manufacturing the SGT MOS device as described in claim 7, characterized in that, Also includes: A source metal layer is formed on the ILD dielectric layer and on the electrode region.

9. The method for manufacturing the SGT MOS device as described in claim 7, characterized in that, Also includes: A drain metal layer is formed beneath the substrate.

10. An SGT MOS device, characterized in that, The SGTMOS device is manufactured by the manufacturing method of any one of claims 1-9, and the device comprises: a substrate, an epitaxial layer, a first cell region, and a second cell region; The epitaxial layer is located on the substrate; The first cell region and the second cell region are located on the epitaxial layer, and the first cell region and the second cell region are in a parallel structure; The first cell region includes: a first groove, and a first isolation layer, a first shielding gate region, and a first control gate region located within the first groove; within the first groove, the first control gate region and the first shielding gate region are arranged in an upper and lower structure, and the first isolation layer is located between the first control gate region and the first shielding gate region; the first control gate region includes: a first control gate and a first gate oxide layer, and the first gate oxide layer fills the space between the first control gate and the sidewall within the first groove. The second cell region includes: a second groove, and a second isolation layer, a second shielding gate region, and a second control gate region located within the second groove; within the second groove, the second control gate region and the second shielding gate region are arranged in an upper and lower structure, and the second isolation layer is located between the second control gate region and the second shielding gate region; the second control gate region includes: a second control gate, a second gate oxide layer, and a sacrificial oxide layer; the sacrificial oxide layer is located between the second gate oxide layer and the sidewall within the second groove, and the second gate oxide layer is located between the second control gate and the sacrificial oxide layer.

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