Gallium nitride high electron mobility transistor
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- INNOSCIENCE (SUZHOU) SEMICON CO LTD
- Filing Date
- 2026-06-10
- Publication Date
- 2026-07-14
Smart Images
Figure CN122395985A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor device technology, and in particular to a gallium nitride high electron mobility transistor. Background Technology
[0002] High Electron Mobility Transistors (HEMTs) are widely used due to their advantages such as fast switching speed and low on-resistance. An HEMT may include multiple ohmic contact electrodes arranged in the transistor device region. These ohmic contact electrodes are configured as source and drain electrodes arranged alternately along a first direction, and each ohmic contact electrode extends along a second direction.
[0003] In some gallium nitride high electron mobility transistors, there are shape change locations in the transistor device region. At these shape change locations, the lengths of two adjacent ohmic contact electrodes are significantly different, with one being the source and the other the drain. At the moment of turn-off of the gallium nitride high electron mobility transistor, there is a significant risk of breakdown at these shape change locations. Summary of the Invention
[0004] This application provides a gallium nitride high electron mobility transistor, which reduces the risk of breakdown at the location of shape change in the transistor device region during turn-off.
[0005] This application provides a gallium nitride high electron mobility transistor, comprising: an epitaxial layer group, the epitaxial layer group including a substrate, a channel layer, and a barrier layer, the channel layer being located on the substrate, the barrier layer being located on the side of the channel layer away from the substrate, and a two-dimensional electron gas being formed between the channel layer and the barrier layer; the epitaxial layer group having a transistor device region, the transistor device region including a first sub-region and a second sub-region adjacent along a first direction, the length of the first sub-region in a second direction being greater than the length of the second sub-region in the second direction, the second direction being perpendicular to the first direction; and a plurality of ohmic contact electrodes arranged along the first direction in the transistor device region, each of the ohmic contact electrodes extending along the second direction, the plurality of ohmic contact electrodes... The contact electrodes are configured as source and drain electrodes arranged alternately along the first direction, wherein the plurality of ohmic contact electrodes include: a first electrode, which is the ohmic contact electrode within the first sub-region and closest to the second sub-region, and the first electrode includes a first sub-electrode and a second sub-electrode spaced apart from each other along the second direction; and a second electrode, which is the ohmic contact electrode within the second sub-region and closest to the first electrode, and the projection of the second electrode and the first sub-electrode overlaps along the first direction; and a first electrical isolation member disposed at the interval between the first sub-electrode and the second sub-electrode, the first electrical isolation member being used to interrupt the two-dimensional electron gas between the first sub-electrode and the second sub-electrode.
[0006] According to some of the foregoing embodiments of this application, the projection overlap length between the second electrode and the first sub-electrode along the first direction is greater than the projection overlap length between the second electrode and the second sub-electrode along the first direction.
[0007] According to some of the foregoing embodiments of this application, the projections of the second electrode and the second sub-electrode along the first direction do not overlap.
[0008] According to some of the foregoing embodiments of this application, in the second direction, the ratio of the length of the first sub-electrode to the length of the second electrode is between 0.8 and 1.2.
[0009] According to some of the foregoing embodiments of this application, the first sub-electrode and the second electrode are of equal length and are aligned in the second direction.
[0010] According to some of the foregoing embodiments of this application, the gallium nitride high electron mobility transistor further includes: a second electrical isolation element, which electrically isolates the source and drain of the plurality of ohmic contact electrodes when the transistor is in the off state.
[0011] According to some of the foregoing embodiments of this application, the first electrical isolation element and at least a portion of the second electrical isolation element are disposed in the same layer and are made of the same material.
[0012] According to some of the foregoing embodiments of this application, the first electrical isolation element includes a first depletion layer located on the epitaxial layer group, the first depletion layer being used to deplete the two-dimensional electron gas in the covered area.
[0013] According to some of the foregoing embodiments of this application, the first depletion layer comprises a p-doped III-V group nitride semiconductor material.
[0014] According to some of the foregoing embodiments of this application, the first electrical isolation device includes a first ion implantation isolation region, which is configured to eliminate the two-dimensional electron gas in the corresponding region by ion implantation.
[0015] According to some of the foregoing embodiments of this application, the first ion implantation isolation region is configured to eliminate the two-dimensional electron gas in the corresponding region by fluorine ion implantation.
[0016] According to some of the foregoing embodiments of this application, the second electrical isolation element includes a second depletion layer located on the epitaxial layer group, the second depletion layer being used to deplete the two-dimensional electron gas in the covered area.
[0017] According to some of the foregoing embodiments of this application, the second depletion layer comprises a p-doped III-V group nitride semiconductor material.
[0018] According to some of the foregoing embodiments of this application, the second depletion layer is disposed around each of the sources and / or around each of the drains.
[0019] According to some of the foregoing embodiments of this application, the second electrical isolation device further includes a second ion implantation isolation region disposed around the transistor device region, and the second depletion layer includes depletion units located between every two adjacent ohmic contact electrodes, with each depletion unit connected to the second ion implantation isolation region at opposite ends along the second direction.
[0020] According to some of the foregoing embodiments of this application, each of the source electrodes is provided with the depletion unit on both sides along the second direction; and / or each of the drain electrodes is provided with the depletion unit on both sides along the second direction.
[0021] According to some of the foregoing embodiments of this application, the gallium nitride high electron mobility transistor further includes: a gate located on the side of the second depletion layer away from the epitaxial layer group, and the gate is located between two adjacent ohmic contact electrodes.
[0022] According to some of the foregoing embodiments of this application, both the first electrical isolation device and the second electrical isolation device include p-doped III-V group nitride semiconductor materials, and the p-doped III-V group nitride semiconductor materials included in the first electrical isolation device and the p-doped III-V group nitride semiconductor materials included in the second electrical isolation device are formed simultaneously in the same process.
[0023] According to some of the foregoing embodiments of this application, the gallium nitride high electron mobility transistor is an enhancement-mode device.
[0024] According to some of the foregoing embodiments of this application, the plurality of ohmic contact electrodes further includes: a third electrode, the third electrode being the ohmic contact electrode located within the first sub-region and closest to the first electrode, wherein the opposite ends of the first electrode along the second direction are aligned with the opposite ends of the third electrode along the second direction.
[0025] According to some of the foregoing embodiments of this application, both the first sub-region and the second sub-region are rectangular.
[0026] According to some of the foregoing embodiments of this application, the number of the first electrical isolation elements is two or more, and the two or more first electrical isolation elements are arranged at intervals along the second direction.
[0027] According to some of the foregoing embodiments of this application, the transistor device region further includes a third sub-region adjacent to the second sub-region along the first direction, the third sub-region being located on the side of the second sub-region away from the first sub-region, and the length of the third sub-region in the second direction being greater than the length of the second sub-region in the second direction; the plurality of ohmic contact electrodes further includes: a fourth electrode, the fourth electrode being the ohmic contact electrode within the third sub-region and closest to the second sub-region, the fourth electrode including a third sub-electrode and a fourth sub-electrode spaced apart from each other along the second direction; and a fifth electrode, the fifth electrode being the ohmic contact electrode within the second sub-region and closest to the fourth electrode, and the projection of the fifth electrode and the third sub-electrode overlaps along the first direction; the gallium nitride high electron mobility transistor further includes: a third electrical isolation element disposed at the interval between the third sub-electrode and the fourth sub-electrode, the third electrical isolation element being used to interrupt the two-dimensional electron gas between the third sub-electrode and the fourth sub-electrode.
[0028] According to some of the foregoing embodiments of this application, the transistor device region further includes a fourth sub-region adjacent to the second sub-region along the first direction, the fourth sub-region being located on the side of the second sub-region away from the first sub-region, and the length of the fourth sub-region in the second direction being less than the length of the second sub-region in the second direction; the plurality of ohmic contact electrodes further includes: a sixth electrode, the sixth electrode being the ohmic contact electrode within the second sub-region and closest to the fourth sub-region, the sixth electrode including a fifth sub-electrode and a sixth sub-electrode spaced apart from each other along the second direction; and a seventh electrode, the seventh electrode being the ohmic contact electrode within the fourth sub-region and closest to the sixth electrode, and the projection of the seventh electrode and the fifth sub-electrode overlaps along the first direction; the gallium nitride high electron mobility transistor further includes: a fourth electrical isolation element disposed at the interval between the fifth sub-electrode and the sixth sub-electrode, the fourth electrical isolation element being used to interrupt the two-dimensional electron gas between the fifth sub-electrode and the sixth sub-electrode.
[0029] According to an embodiment of the gallium nitride high electron mobility transistor of this application, the transistor device region includes a first sub-region and a second sub-region adjacent to each other along a first direction. The length of the first sub-region in the second direction is greater than the length of the second sub-region in the second direction. Therefore, the boundary between the first and second sub-regions of the transistor device region is a shape change location. A plurality of ohmic contact electrodes are arranged along the first direction in the transistor device region, each ohmic contact electrode extending along a second direction. The plurality of ohmic contact electrodes are configured as source and drain electrodes alternately arranged along the first direction. The plurality of ohmic contact electrodes include a first electrode and a second electrode. The first electrode is the ohmic contact electrode within the first sub-region and closest to the second sub-region, and the second electrode is the ohmic contact electrode within the second sub-region and closest to the first electrode. That is, the first electrode and the second electrode are two adjacent ohmic contact electrodes at the shape change location. In traditional solutions, the first and second electrodes are each integral structures of different lengths, making alignment impossible in the second direction. At the moment the gallium nitride high electron mobility transistor (GaN HMT) is turned off, the electron flow direction between the first and second electrodes is significantly tilted relative to the first direction, resulting in an uneven electric field between them at the moment of turn-off. This easily leads to electric field breakdown at the shape change location. In the solution of the above embodiment, the first electrode includes a first sub-electrode and a second sub-electrode spaced apart along the second direction, with the projections of the second electrode and the first sub-electrode overlapping along the first direction. A first electrical isolator is disposed at the interval between the first and second sub-electrodes, and is used to interrupt the two-dimensional electron gas between them. At the moment the GaN HMT is turned off, the electric field at the first and second electrodes is effectively controlled, forming a more uniform electric field between them, thereby reducing the risk of breakdown at the shape change location. Furthermore, in conventional solutions, the first and second electrodes are each integral structures with different lengths. At the moment the gallium nitride high electron mobility transistor (GaN HMT) is turned on, the difference in length causes an uneven electric field between the two electrodes, leading to electron accumulation at the shape change location and increasing the risk of thermal failure. In the solution described in this application, the first electrode is configured to include a first sub-electrode and a second sub-electrode spaced apart from each other. A first electrical isolation element is placed at the interval between the first and second sub-electrodes. This first electrical isolation element breaks the two-dimensional electron gas between the first and second sub-electrodes, and the projections of the second electrode and the first sub-electrode overlap along a first direction. At the moment the GaN HMT is turned on, a uniform electric field can be formed between the first and second sub-electrodes, reducing the risk of thermal failure at the shape change location, thereby improving the dynamic resistance characteristics of the transistor and enhancing its hard-start capability. Attached Figure Description
[0030] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.
[0031] Figure 1 This is a top view schematic diagram of a first embodiment of a gallium nitride high electron mobility transistor according to this application; Figure 2 yes Figure 1 Schematic diagram of the cross section along the AA direction; Figure 3 This is a top view schematic diagram of a second embodiment of a gallium nitride high electron mobility transistor according to this application; Figure 4 yes Figure 3 Schematic diagram of the cross section along the BB direction; Figure 5 This is a top view schematic diagram of a third embodiment of a gallium nitride high electron mobility transistor according to this application; Figure 6 This is a top view schematic diagram of a fourth embodiment of a gallium nitride high electron mobility transistor according to this application; Figure 7 This is a top view schematic diagram of the fifth embodiment of the gallium nitride high electron mobility transistor according to this application; Figure 8 This is a top view schematic diagram of a sixth embodiment of a gallium nitride high electron mobility transistor according to this application. Detailed Implementation
[0032] The technical solutions in the embodiments (or "implementations") of this application will be clearly and completely described herein with reference to the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements.
[0033] If the embodiments of this application contain terms relating to directional indications or positional relationships (such as up, down, left, right, front, back, inside, outside, top, bottom, center, vertical, horizontal, longitudinal, transverse, length, width, counterclockwise, clockwise, axial, radial, circumferential, etc.), such terms are only used to explain the relative positional relationships and movement of the components in a specific posture (as shown in the attached figures); if the specific posture changes, the directional indications or positional relationships will also change accordingly. Furthermore, the terms "first" and "second" used in the embodiments of this application are only for descriptive convenience and should not be construed as indicating or implying relative importance.
[0034] Figure 1 This is a top view schematic diagram of a first embodiment of a gallium nitride high electron mobility transistor according to this application. Figure 2 yes Figure 1 Schematic diagram of the cross section along the AA direction. Figure 1 To clearly illustrate some of the structures of a gallium nitride (GaN) high electron mobility transistor (HEMT), some layer structures are omitted. The GaN high electron mobility transistor 100 includes an epitaxial layer group 110, multiple ohmic contact electrodes 120, and a first electrical isolation element 130.
[0035] In some embodiments, the epitaxial layer group 110 has a two-dimensional electron gas. In some embodiments, the epitaxial layer group 110 includes a substrate 111, a channel layer 112, and a barrier layer 113, wherein the channel layer 112 is located on the substrate 111, the barrier layer 113 is located on the side of the channel layer 112 away from the substrate 111, and a two-dimensional electron gas is formed between the channel layer 112 and the barrier layer 113.
[0036] Substrate 111 may comprise, but is not limited to, semiconductor substrate materials such as silicon (Si), doped Si, silicon carbide (SiC), germanium silicide (SiGe), and gallium arsenide (GaAs). Substrate 111 may comprise, but is not limited to, sapphire, silicon-on-insulator (SOI), or other suitable substrate materials. Channel layer 112 and barrier layer 113 may comprise, but are not limited to, gallium nitride (GaN), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), and indium aluminum gallium nitride (InAlGaN). The band gap (i.e., band width) of barrier layer 113 is larger than that of channel layer 112, which allows electron affinity to differ between them, forming a heterojunction. In this embodiment, the example is a GaN layer for channel layer 112 and an AlGaN layer for barrier layer 113; in this case, the transistor is, for example, a GaN-based HEMT. A triangular well potential is generated at the interface between the barrier layer 113 and the channel layer 112, which causes electrons to accumulate in the triangular well, thereby generating a two-dimensional electron gas (2DEG) near the heterojunction. That is, a 2DEG can be formed near the interface between the channel layer 112 and the barrier layer 113.
[0037] In some other embodiments, the epitaxial layer group 110 may also include other functional layers such as buffer layer 114, which is located between the substrate 111 and the channel layer 112. The material of buffer layer 114 may include, but is not limited to, gallium nitride (GaN), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), indium aluminum gallium nitride (InAlGaN), or combinations thereof.
[0038] The epitaxial layer group 110 has a transistor device region TA for forming transistors. The transistor device region TA includes a first sub-region SA1 and a second sub-region SA2 adjacent along a first direction X. The length of the first sub-region SA1 in the second direction Y is greater than the length of the second sub-region SA2 in the second direction Y. The second direction Y is perpendicular to the first direction X. Figure 1The boundaries of the transistor device region TA and the boundaries of each subregion of the transistor device region TA are shown by dashed lines.
[0039] In some embodiments, the transistor device region TA has a shape similar to that of the gallium nitride high electron mobility transistor 100. The gallium nitride high electron mobility transistor 100 may have a shape that includes the first sub-region SA1 and the second sub-region SA2 due to the shape of its side boundary having a shape change similar to the first sub-region SA1 and the second sub-region SA2.
[0040] In some embodiments, the transistor device region TA has a shape dissimilar to that of the gallium nitride high electron mobility transistor 100, which can have any desired shape. The transistor device region TA is located within the gallium nitride high electron mobility transistor 100 and forms the shape described above, including the first sub-region SA1 and the second sub-region SA2. For example, the gallium nitride high electron mobility transistor 100 may also include other functional regions located outside the transistor device region TA and occupying some area within the gallium nitride high electron mobility transistor 100, such that the transistor device region TA is formed in the shape described above, including the first sub-region SA1 and the second sub-region SA2.
[0041] In some embodiments, each ohmic contact electrode 120 is electrically connected to at least the barrier layer 113.
[0042] Multiple ohmic contact electrodes 120 are arranged along a first direction X in the transistor device region TA, and each ohmic contact electrode 120 extends along a second direction Y. The multiple ohmic contact electrodes 120 are configured as source SE and drain DE arranged alternately along the first direction X. In some embodiments, the ohmic contact electrode 120 may include multiple sub-layers, and each ohmic contact electrode 120 forms an ohmic contact with the source SE region of the epitaxial layer group 110, or forms an ohmic contact with the drain DE region of the epitaxial layer group 110.
[0043] like Figure 1 In the first embodiment, the plurality of ohmic contact electrodes 120 are arranged in an alternating order from right to left: source SE, drain DE, source SE, drain DE... In other embodiments, the positions of source SE and drain DE can be interchanged.
[0044] In this embodiment, the plurality of ohmic contact electrodes 120 include a first electrode 120a and a second electrode 120b. The first electrode 120a is the ohmic contact electrode 120 within the first sub-region SA1 and closest to the second sub-region SA2, and includes a first sub-electrode 121 and a second sub-electrode 122 spaced apart along the second direction Y. The second electrode 120b is the ohmic contact electrode 120 within the second sub-region SA2 and closest to the first electrode 120a, and the projections of the second electrode 120b and the first sub-electrode 121 overlap along the first direction X. A first electrical isolator 130 is disposed at the interval between the first sub-electrode 121 and the second sub-electrode 122, and the first electrical isolator 130 is used to interrupt the two-dimensional electron gas between the first sub-electrode 121 and the second sub-electrode 122.
[0045] According to the gallium nitride high electron mobility transistor 100 of this application embodiment, the transistor device region TA includes a first sub-region SA1 and a second sub-region SA2 adjacent along a first direction X. The length of the first sub-region SA1 in the second direction Y is greater than the length of the second sub-region SA2 in the second direction Y. Therefore, the boundary between the first sub-region SA1 and the second sub-region SA2 of the transistor device region TA is a shape change location. A plurality of ohmic contact electrodes 120 are arranged along the first direction X in the transistor device region TA, and each ohmic contact electrode 120 extends along the second direction Y. The plurality of ohmic contact electrodes 120 are configured as source electrodes SE and drain electrodes DE alternately arranged along the first direction X. Multiple ohmic contact electrodes 120 include a first electrode 120a and a second electrode 120b. The first electrode 120a is the ohmic contact electrode 120 within the first sub-region SA1 and closest to the second sub-region SA2. The second electrode 120b is the ohmic contact electrode 120 within the second sub-region SA2 and closest to the first electrode 120a. That is, the first electrode 120a and the second electrode 120b are two adjacent ohmic contact electrodes 120 at the shape change location. In conventional schemes, the first electrode and the second electrode are each a single structure with different lengths, and they cannot be aligned in the second direction. At the instant the gallium nitride high electron mobility transistor is turned off, the electron flow direction between the first electrode and the second electrode is significantly tilted relative to the first direction, resulting in an uneven electric field between the first electrode and the second electrode at the instant of turn-off, which can easily lead to electric field breakdown at the shape change location. In the above-described embodiment of this application, the first electrode 120a includes a first sub-electrode 121 and a second sub-electrode 122 spaced apart along the second direction Y, and the projections of the second electrode 120b and the first sub-electrode 121 along the first direction X overlap. A first electrical isolation member 130 is disposed at the interval between the first sub-electrode 121 and the second sub-electrode 122, and the first electrical isolation member 130 is used to interrupt the two-dimensional electron gas between the first sub-electrode 121 and the second sub-electrode 122. At the instant the gallium nitride high electron mobility transistor 100 is turned off, the electric field at the first electrode 120a and the second electrode 120b is effectively controlled, and a relatively uniform electric field can be formed between the first sub-electrode 121 and the second electrode 120b, thereby reducing the risk of breakdown at the shape change location.
[0046] In traditional solutions, the first electrode and the second electrode are each a single, continuous structure with different lengths. When the gallium nitride high electron mobility transistor is turned on, the electric field between the first electrode and the second electrode is uneven due to the difference in length. Electrons tend to accumulate at the location of the shape change, which can easily lead to thermal failure of the device at that location. According to the gallium nitride high electron mobility transistor 100 of the present application, by configuring the first electrode 120a to include a first sub-electrode 121 and a second sub-electrode 122 spaced apart from each other, and providing a first electrical isolation member 130 at the interval between the first sub-electrode 121 and the second sub-electrode 122, the first electrical isolation member 130 interrupts the two-dimensional electron gas between the first sub-electrode 121 and the second sub-electrode 122, and the projection of the second electrode 120b and the first sub-electrode 121 along the first direction X overlaps, a uniform electric field can be formed between the first sub-electrode 121 and the second electrode 120b at the moment when the gallium nitride high electron mobility transistor 100 is turned on, reducing the risk of device thermal failure at the shape change position, thereby improving the dynamic resistance characteristics of the transistor and improving the hard-turn capability of the transistor device.
[0047] In this embodiment, the second direction Y is perpendicular to the first direction X, and both the first sub-region SA1 and the second sub-region SA2 are rectangular, making the transistor device region TA L-shaped. In other embodiments, the first sub-region SA1 and the second sub-region SA2 can be other shapes, with different lengths in the second direction Y, allowing the transistor device region TA to have other irregular shapes.
[0048] In some embodiments, the projected overlap length of the second electrode 120b and the first sub-electrode 121 along the first direction X is greater than the projected overlap length of the second electrode 120b and the second sub-electrode along the first direction X. At the instant the gallium nitride high electron mobility transistor 100 is turned off, a more uniform electric field can be formed between the first sub-electrode 121 and the second electrode 120b, thereby reducing the risk of breakdown at the shape change location.
[0049] In some embodiments, the projections of the second electrode 120b and the second sub-electrode 122 along the first direction X do not overlap. The projections of the second electrode 120b and the first sub-electrode 121 along the first direction X overlap. A first electrical isolation element 130 that interrupts the two-dimensional electron gas is provided at the interval between the first sub-electrode 121 and the second sub-electrode 122. At the instant the gallium nitride high electron mobility transistor 100 is turned off, a further uniform electric field can be formed between the first sub-electrode 121 and the second electrode 120b, thereby further reducing the breakdown risk at the shape change location.
[0050] In some embodiments, in the second direction Y, the ratio of the length of the first sub-electrode 121 to the length of the second electrode 120b is between 0.8 and 1.2, ensuring that a relatively uniform electric field can be formed between the first sub-electrode 121 and the second electrode 120b at the moment when the gallium nitride high electron mobility transistor 100 is turned off and at the moment when the gallium nitride high electron mobility transistor 100 is turned on.
[0051] In some embodiments, the first sub-electrode 121 and the second electrode 120b are of equal length and aligned in the second direction Y. This further ensures that a uniform electric field can be formed between the first sub-electrode 121 and the second electrode 120b at the moment the gallium nitride high electron mobility transistor 100 is turned off and at the moment the gallium nitride high electron mobility transistor 100 is turned on. This reduces the risk of breakdown at the shape change location at the moment the gallium nitride high electron mobility transistor 100 is turned off and reduces the risk of device thermal failure at the shape change location at the moment the gallium nitride high electron mobility transistor 100 is turned on.
[0052] like Figure 1 In some embodiments, the plurality of ohmic contact electrodes 120 further includes a third electrode 120c. The third electrode 120c is the ohmic contact electrode 120 within the first sub-region SA1 and closest to the first electrode 120a. The opposite ends of the first electrode 120a along the second direction Y are aligned with the opposite ends of the third electrode 120c along the second direction Y, thereby effectively controlling the electric field within the first sub-region SA1.
[0053] In some embodiments, the gallium nitride high electron mobility transistor 100 further includes a second electrical isolation element 140, which electrically isolates the source SE and drain DE of the plurality of ohmic contact electrodes 120 from each other when the transistor is in the off state.
[0054] In some embodiments, the first electrical isolation element 130 and at least a portion of the second electrical isolation element 140 are disposed in the same layer and are made of the same material. The first electrical isolation element 130 and at least a portion of the second electrical isolation element 140 can be formed simultaneously in the same process, thereby eliminating the need for additional process steps to form the second electrical isolation element 140, which helps to maintain the high manufacturing efficiency of the gallium nitride high electron mobility transistor 100.
[0055] In some embodiments, the first electrical isolation element 130 includes a first depletion layer 131 located on the epitaxial layer group 110, the first depletion layer 131 being used to deplete the two-dimensional electron gas of the covered area.
[0056] In this embodiment, the first depletion layer 131 comprises a p-doped III-V group nitride semiconductor material, such as p-type GaN, p-type AlGaN, p-type InN, p-type AlInN, p-type InGaN, p-type AlInGaN, or a combination thereof. In this embodiment, the channel layer 112 is, for example, a GaN layer, the barrier layer 113 is, for example, an AlGaN layer, and the first depletion layer 131 is, for example, a p-type GaN layer. The first depletion layer 131 causes the 2DEG in its covered region to form a depletion region, thereby blocking the 2DEG in the covered region.
[0057] In the above embodiments, the first electrical isolator 130 includes a first depletion layer 131, which achieves electrical isolation by depleting the two-dimensional electron gas in the covered area. In other embodiments, the first electrical isolator 130 can be other electrical isolators that simply block the two-dimensional electron gas in the corresponding area.
[0058] In some embodiments, the epitaxial layer group 110 has a two-dimensional electron gas. In some embodiments, the second electrical isolation member 140 includes a second depletion layer 141 located on the epitaxial layer group 110, the second depletion layer 141 being used to deplete the two-dimensional electron gas in the covered area.
[0059] In this embodiment, the second depletion layer 141 comprises a p-doped III-V group nitride semiconductor material, such as p-type GaN, p-type AlGaN, p-type InN, p-type AlInN, p-type InGaN, p-type AlInGaN, or a combination thereof. In this embodiment, the second depletion layer 141 is, for example, a p-type GaN layer. The second depletion layer 141 causes the 2DEG in its covered region to form a depletion region, thereby blocking the 2DEG in the covered region.
[0060] In some embodiments, the second depletion layer 141 is disposed around each source SE and / or around each drain DE. For example, in this embodiment, the second depletion layer 141 surrounds each source SE and the second depletion layer 141 surrounds each drain DE. In some other embodiments, the second depletion layer 141 may surround each source SE but not the drain DE; or in some other embodiments, the second depletion layer 141 may surround each drain DE but not the source SE.
[0061] In some embodiments, both the first electrical isolator 130 and the second electrical isolator 140 comprise p-doped III-V group nitride semiconductor materials, and the p-doped III-V group nitride semiconductor materials included in the first electrical isolator 130 and the second electrical isolator 140 are formed simultaneously in the same process. For example, in this embodiment, the first electrical isolator 130 includes a first depletion layer 131 comprising p-doped III-V group nitride semiconductor materials, and the second electrical isolator 140 includes a second depletion layer 141 comprising p-doped III-V group nitride semiconductor materials. The simultaneous formation of the p-doped III-V group nitride semiconductor materials in the first electrical isolator 130 and the second electrical isolator 140 in the same process facilitates improved manufacturing efficiency of the gallium nitride high electron mobility transistor 100.
[0062] In some embodiments, the gallium nitride high electron mobility transistor 100 further includes a gate GE, which is located on the side of the second depletion layer 141 away from the epitaxial layer group 110 and between two adjacent ohmic contact electrodes 120. The gate GE may be made of metal.
[0063] In this embodiment, the gate GE is located on the side of the second depletion layer 141 away from the epitaxial layer group 110. The gallium nitride high electron mobility transistor 100 is an enhancement-mode device, and it is normally off when the gate GE is at approximately zero bias. That is, when no voltage is applied to the gate GE or the voltage applied to the gate GE is less than the threshold voltage, the second depletion layer 141 at the gate GE depletes the 2DEG in the corresponding covered area, and the 2DEG is blocked. At this time, no current flows between the source SE and the drain DE.
[0064] like Figure 2 In some embodiments, the gallium nitride high electron mobility transistor 100 further includes a passivation layer 150 located on the side of the barrier layer 113 and the gate GE away from the substrate 111, and an ohmic contact electrode 120 penetrating the passivation layer 150.
[0065] like Figure 1 , Figure 2 In the first embodiment, along the first direction X, the distance between the source SE and the second depletion layer 141 is different from the distance between the drain DE and the second depletion layer 141; or, along the first direction X, the distance between the source SE and the gate GE is different from the distance between the drain DE and the gate GE. For example, as Figure 1 , Figure 2In the first embodiment, the distance between the source SE and the gate GE along the first direction X is less than the distance between the drain DE and the gate GE. In other embodiments, the spacing between the source SE, drain DE, and gate GE is not limited to the example of the first embodiment described above.
[0066] Figure 3 This is a top view schematic diagram of a second embodiment of a gallium nitride high electron mobility transistor according to this application. Figure 4 yes Figure 3 A cross-sectional diagram along the BB direction. Some structures in the second embodiment are the same as in the first embodiment; the following will mainly describe the differences between the two.
[0067] like Figure 3 , Figure 4 In the second embodiment, along the first direction X, the distance between the source SE and the second depletion layer 141 is equal to the distance between the drain DE and the second depletion layer 141; or, along the first direction X, the distance between the source SE and the gate GE is equal to the distance between the drain DE and the gate GE. That is, in some embodiments, the distance between the source SE and the gate GE may be the same as the distance between the drain DE and the gate GE.
[0068] like Figure 1 , Figure 2 In the aforementioned first embodiment, the first electrode 120a includes a first sub-electrode 121 and a second sub-electrode 122 spaced apart from each other along the second direction Y. The first electrical isolation member 130 is disposed at the interval between the first sub-electrode 121 and the second sub-electrode 122. In the first embodiment, it is described by taking the provision of one first electrical isolation member 130 between the first sub-electrode 121 and the second sub-electrode 122 as an example. In some other embodiments, other numbers of first electrical isolation members 130 may be provided between the first sub-electrode 121 and the second sub-electrode 122.
[0069] Figure 5 This is a top view schematic diagram of a third embodiment of a gallium nitride high electron mobility transistor according to this application. Parts of the structure of the third embodiment are the same as those of the first embodiment; the differences between the two will be mainly described below.
[0070] In some embodiments, the number of first electrical isolators 130 is two or more, and the two or more first electrical isolators 130 are arranged at intervals along the second direction Y. Each first electrical isolator 130 is used to interrupt the two-dimensional electron gas between the first sub-electrode 121 and the second sub-electrode 122. Figure 5For example, in the third embodiment, there are two first electrical isolation elements 130, which are spaced apart along the second direction Y between the first sub-electrode 121 and the second sub-electrode 122. In other embodiments, the number of first electrical isolation elements 130 can be three, four, five, or other numbers. Since there are two or more first electrical isolation elements 130 between the first sub-electrode 121 and the second sub-electrode 122, the electrical isolation effect between the first sub-electrode 121 and the second sub-electrode 122 in the epitaxial layer group 110 can be further improved, and the breakdown risk at the junction of the first sub-region SA1 and the second sub-region SA2 at the moment of turn-off of the gallium nitride high electron mobility transistor 100 can be further reduced.
[0071] In the above embodiments, the second electrical isolator 140 includes a second depletion layer 141, which achieves electrical isolation by depleting the two-dimensional electron gas in the covered area. In other embodiments, the second electrical isolator 140 may include other electrical isolators that can block the two-dimensional electron gas in the corresponding area.
[0072] Figure 6 This is a top view schematic diagram of the fourth embodiment of the gallium nitride high electron mobility transistor according to this application. Figure 6 To clearly illustrate some of the structures of the gallium nitride high electron mobility transistor 100, some layer structures are omitted. Parts of the structure of the fourth embodiment are the same as those of the first embodiment; the following will mainly describe the differences between the two.
[0073] The gallium nitride high electron mobility transistor 100 includes an epitaxial layer group 110, a plurality of ohmic contact electrodes 120, and a first electrical isolation element 130. The epitaxial layer group 110 has a two-dimensional electron gas. In some embodiments, the epitaxial layer group 110 includes a substrate 111, a channel layer 112, and a barrier layer 113. The channel layer 112 is located on the substrate 111, and the barrier layer 113 is located on the side of the channel layer 112 away from the substrate 111. A two-dimensional electron gas is formed between the channel layer 112 and the barrier layer 113. The epitaxial layer group 110 has a transistor device region TA. The transistor device region TA includes a first sub-region SA1 and a second sub-region SA2 adjacent along a first direction X. The length of the first sub-region SA1 in a second direction Y is greater than the length of the second sub-region SA2 in the second direction Y, and the second direction Y is perpendicular to the first direction X. Figure 6 The boundaries of the transistor device region TA and the boundaries of each subregion of the transistor device region TA are shown by dashed lines.
[0074] Multiple ohmic contact electrodes 120 are arranged along a first direction X in the transistor device region TA, and each ohmic contact electrode 120 extends along a second direction Y. The multiple ohmic contact electrodes 120 are configured as source SE and drain DE arranged alternately along the first direction X.
[0075] The plurality of ohmic contact electrodes 120 include a first electrode 120a and a second electrode 120b. The first electrode 120a is the ohmic contact electrode 120 within a first sub-region SA1 and closest to a second sub-region SA2. The first electrode 120a includes a first sub-electrode 121 and a second sub-electrode 122 spaced apart along a second direction Y. The second electrode 120b is the ohmic contact electrode 120 within the second sub-region SA2 and closest to the first electrode 120a. The projections of the second electrode 120b and the first sub-electrode 121 along a first direction X overlap. Further, in one example, the first sub-electrode 121 and the second electrode 120b are of equal length and aligned in position along the second direction Y. A first electrical isolator 130 is disposed at the interval between the first sub-electrode 121 and the second electrode 122.
[0076] In this embodiment, the example is given where both the first sub-region SA1 and the second sub-region SA2 are rectangles.
[0077] like Figure 6 In some embodiments, the plurality of ohmic contact electrodes 120 further includes a third electrode 120c. The third electrode 120c is the ohmic contact electrode 120 within the first sub-region SA1 and closest to the first electrode 120a. The opposite ends of the first electrode 120a along the second direction Y are aligned with the opposite ends of the third electrode 120c along the second direction Y, thereby effectively controlling the electric field within the first sub-region SA1.
[0078] The gallium nitride high electron mobility transistor 100 further includes a second electrical isolator 140 that electrically isolates the source SE and drain DE of the plurality of ohmic contact electrodes 120 from each other when the transistor is in the off state. The epitaxial layer group 110 has a two-dimensional electron gas. In some embodiments, the second electrical isolator 140 includes a second depletion layer 141 located on the epitaxial layer group 110, the second depletion layer 141 being used to deplete the two-dimensional electron gas in the covered region. In some embodiments, the second depletion layer 141 comprises a p-doped III-V group nitride semiconductor material.
[0079] In the fourth embodiment, the second electrical isolation element 140 further includes a second ion implantation isolation region 142. The second ion implantation isolation region 142 is disposed around the transistor device region TA. The second depletion layer 141 includes depletion units 141s located between every two adjacent ohmic contact electrodes 120, and each depletion unit 141s is connected to the second ion implantation isolation region 142 at opposite ends along the second direction Y.
[0080] In this embodiment, the second ion implantation isolation region 142 refers to an electrically isolated region obtained by eliminating the conductive channel formed by the two-dimensional electron gas in the corresponding region through ion implantation. In one example, the second ion implantation isolation region 142 is configured to eliminate the two-dimensional electron gas in the corresponding region through fluorine ion implantation.
[0081] In this embodiment, the transistor device region TA may have a different shape from the gallium nitride high electron mobility transistor 100. The second ion implantation isolation region 142 encloses the transistor device region TA, or the second ion implantation isolation region 142 defines the transistor device region TA.
[0082] In some embodiments, the gallium nitride high electron mobility transistor 100 may further include other functional regions located outside the transistor device region TA and occupying some area within the gallium nitride high electron mobility transistor 100. For example... Figure 6 For example, the gallium nitride high electron mobility transistor 100 also includes an electrostatic discharge (ESD) protection region XA located outside the transistor device region TA. The gallium nitride high electron mobility transistor 100 also includes an electrostatic discharge (ESD) circuit 190 disposed within the ESD protection region XA. In some other embodiments, the gallium nitride high electron mobility transistor 100 is not limited to including an additional functional region, and even if it does include an additional functional region, it is not limited to the ESD protection region XA for arranging the ESD circuit 190; it could also be another functional region for arranging other circuits.
[0083] In some embodiments, each source SE is provided with depletion units 141s on both sides of the second direction Y; and / or each drain DE is provided with depletion units 141s on both sides of the second direction Y.
[0084] For example, in this embodiment, each source SE has depletion units 141s on both sides along the second direction Y. Each source SE may have one depletion unit 141s on each side, or two or more depletion units 141s may be provided on each side. In some other embodiments, each drain DE may have depletion units 141s on both sides along the second direction Y.
[0085] In some embodiments, the gallium nitride high electron mobility transistor 100 further includes a gate GE, which is located on the side of the second depletion layer 141 away from the epitaxial layer group 110 and is located between two adjacent ohmic contact electrodes 120.
[0086] The epitaxial layer group 110 contains a two-dimensional electron gas. For example... Figure 6In some embodiments, the first electrical isolation element 130 includes a first ion implantation isolation region 132, which is configured to eliminate the two-dimensional electron gas in the corresponding region by ion implantation. That is, in some embodiments, the first electrical isolation element 130 is not limited to the first depletion layer 131, but can also be the first ion implantation isolation region 132.
[0087] In one example, the first ion implantation isolation region 132 is configured to eliminate the two-dimensional electron gas in the corresponding region by fluorine ion implantation.
[0088] In this embodiment, the first electrical isolation device 130 includes a first ion implantation isolation region 132, and the second electrical isolation device 140 includes a second ion implantation isolation region 142. The first ion implantation isolation region 132 and the second ion implantation isolation region 142 can be formed simultaneously in the same ion implantation step, thereby improving the manufacturing efficiency of the gallium nitride high electron mobility transistor 100.
[0089] Figure 7 This is a top view schematic diagram of the fifth embodiment of the gallium nitride high electron mobility transistor according to this application. Figure 7 To clearly show some of the structures of the gallium nitride high electron mobility transistor 100, some layer structures are hidden. Figure 7 The boundaries of the transistor device region TA and its sub-regions are shown by dashed lines. Parts of the structure in the fifth embodiment are the same as in the first embodiment; the differences will be mainly described below.
[0090] In the fifth embodiment, the transistor device region TA further includes a third sub-region SA3 adjacent to the second sub-region SA2 along the first direction X. The third sub-region SA3 is located on the side of the second sub-region SA2 away from the first sub-region SA1. The length of the third sub-region SA3 in the second direction Y is greater than the length of the second sub-region SA2 in the second direction Y.
[0091] In the fifth embodiment, the plurality of ohmic contact electrodes 120 further include a fourth electrode 120d and a fifth electrode 120e.
[0092] The fourth electrode 120d is an ohmic contact electrode 120 located within the third sub-region SA3 and closest to the second sub-region SA2. The fourth electrode 120d includes a third sub-electrode 123 and a fourth sub-electrode 124 spaced apart from each other along the second direction Y.
[0093] The fifth electrode 120e is the ohmic contact electrode 120 within the second sub-region SA2 and closest to the fourth electrode 120d, and the projection of the fifth electrode 120e and the third sub-electrode 123 overlaps along the first direction X.
[0094] In the fifth embodiment, the gallium nitride high electron mobility transistor 100 further includes a third electrical isolation element 160, which is disposed at the interval between the third sub-electrode 123 and the fourth sub-electrode 124. The third electrical isolation element 160 is used to interrupt the two-dimensional electron gas between the third sub-electrode 123 and the fourth sub-electrode 124.
[0095] In the above embodiment, the transistor device region TA further includes a third sub-region SA3 adjacent to the second sub-region SA2 along the first direction X. The third sub-region SA3 is located on the side of the second sub-region SA2 away from the first sub-region SA1. The length of the third sub-region SA3 in the second direction Y is greater than the length of the second sub-region SA2 in the second direction Y. Therefore, the boundary between the second sub-region SA2 and the third sub-region SA3 of the transistor device region TA is also a shape change location. The plurality of ohmic contact electrodes 120 also include a fourth electrode 120d and a fifth electrode 120e. The fourth electrode 120d is the ohmic contact electrode 120 within the third sub-region SA3 and closest to the second sub-region SA2. The fifth electrode 120e is the ohmic contact electrode 120 within the second sub-region SA2 and closest to the fourth electrode 120d. That is, the fourth electrode 120d and the fifth electrode 120e are also two adjacent ohmic contact electrodes 120 at the shape change location. The fourth electrode 120d includes a third sub-electrode 123 and a fourth sub-electrode 124 spaced apart along the second direction Y. The projection of the fifth electrode 120e onto the third sub-electrode 123 along the first direction X overlaps with the projection of the fifth electrode 120e onto the third sub-electrode 123. The third electrical isolation member 160 is disposed at the interval between the third sub-electrode 123 and the fourth sub-electrode 124. The third electrical isolation member 160 is used to break the two-dimensional electron gas between the third sub-electrode 123 and the fourth sub-electrode 124, thereby effectively controlling the electric field at the fourth electrode 120d and the fifth electrode 120e, reducing the risk of breakdown at the shape change position when the gallium nitride high electron mobility transistor 100 is turned off, reducing the risk of device thermal failure at the shape change position when the gallium nitride high electron mobility transistor 100 is turned on, further improving the dynamic resistance characteristics of the transistor, and improving the hard-turn capability of the transistor device.
[0096] In some embodiments, the projected overlap length of the fifth electrode 120e and the third sub-electrode 123 along the first direction X is greater than the projected overlap length of the fifth electrode 120e and the fourth sub-electrode 124 along the first direction X. At the instant the gallium nitride high electron mobility transistor 100 is turned off, a more uniform electric field can be formed between the third sub-electrode 123 and the fifth electrode 120e, thereby reducing the risk of breakdown at the shape change location.
[0097] In some embodiments, the projections of the fifth electrode 120e and the fourth sub-electrode 124 along the first direction X do not overlap.
[0098] In some embodiments, in the second direction Y, the ratio of the length of the third sub-electrode 123 to the length of the fifth electrode 120e is between 0.8 and 1.2, ensuring that a relatively uniform electric field can be formed between the third sub-electrode 123 and the fifth electrode 120e at the moment when the gallium nitride high electron mobility transistor 100 is turned off and at the moment when the gallium nitride high electron mobility transistor 100 is turned on.
[0099] Furthermore, in one example, the third sub-electrode 123 and the fifth electrode 120e are of equal length and aligned in the second direction Y. This further ensures that a uniform electric field can be formed between the third sub-electrode 123 and the fifth electrode 120e at the moment the gallium nitride high electron mobility transistor 100 is turned off and at the moment the gallium nitride high electron mobility transistor 100 is turned on. This reduces the risk of breakdown at the shape change location at the moment the gallium nitride high electron mobility transistor 100 is turned off and reduces the risk of device thermal failure at the shape change location at the moment the gallium nitride high electron mobility transistor 100 is turned on.
[0100] Figure 8 This is a top view schematic diagram of the sixth embodiment of the gallium nitride high electron mobility transistor according to this application. Figure 8 To clearly show some of the structures of the gallium nitride high electron mobility transistor 100, some layer structures are hidden. Figure 8 The boundaries of the transistor device region TA and its sub-regions are indicated by dashed lines. Parts of the structure in the sixth embodiment are the same as in the first embodiment; the differences will be mainly described below.
[0101] In the sixth embodiment, the transistor device region TA further includes a fourth sub-region SA4 adjacent to the second sub-region SA2 along the first direction X. The fourth sub-region SA4 is located on the side of the second sub-region SA2 away from the first sub-region SA1. The length of the fourth sub-region SA4 in the second direction Y is less than the length of the second sub-region SA2 in the second direction Y.
[0102] In the sixth embodiment, the plurality of ohmic contact electrodes 120 further include a sixth electrode 120f and a seventh electrode 120g.
[0103] The sixth electrode 120f is an ohmic contact electrode 120 located within the second sub-region SA2 and closest to the fourth sub-region SA4. The sixth electrode 120f includes a fifth sub-electrode 125 and a sixth sub-electrode 126 spaced apart from each other along the second direction Y.
[0104] The seventh electrode 120g is the ohmic contact electrode 120 that is closest to the sixth electrode 120f in the fourth sub-region SA4, and the projection of the seventh electrode 120g and the fifth sub-electrode 125 overlaps along the first direction X.
[0105] In the sixth embodiment, the gallium nitride high electron mobility transistor 100 further includes a fourth electrical isolation element 170, which is disposed at the interval between the fifth sub-electrode 125 and the sixth sub-electrode 126. The fourth electrical isolation element 170 is used to interrupt the two-dimensional electron gas between the fifth sub-electrode 125 and the sixth sub-electrode 126.
[0106] In the above embodiment, the transistor device region TA further includes a fourth sub-region SA4 adjacent to the second sub-region SA2 along the first direction X. The fourth sub-region SA4 is located on the side of the second sub-region SA2 away from the first sub-region SA1. The length of the fourth sub-region SA4 in the second direction Y is less than the length of the second sub-region SA2 in the second direction Y. Therefore, the boundary between the second sub-region SA2 and the fourth sub-region SA4 of the transistor device region TA is also a shape change location. The plurality of ohmic contact electrodes 120 also include a sixth electrode 120f and a seventh electrode 120g. The sixth electrode 120f is the ohmic contact electrode 120 within the second sub-region SA2 and closest to the fourth sub-region SA4. The seventh electrode 120g is the ohmic contact electrode 120 within the fourth sub-region SA4 and closest to the sixth electrode 120f. That is, the sixth electrode 120f and the seventh electrode 120g are also two adjacent ohmic contact electrodes 120 at the shape change location. The sixth electrode 120f includes a fifth sub-electrode 125 and a sixth sub-electrode 126 spaced apart along the second direction Y. The seventh electrode 120g overlaps with the projection of the fifth sub-electrode 125 along the first direction X. The third electrical isolation member 160 is disposed at the interval between the fifth sub-electrode 125 and the sixth sub-electrode 126. The fourth electrical isolation member 170 is used to break the two-dimensional electron gas between the fifth sub-electrode 125 and the sixth sub-electrode 126, thereby effectively controlling the electric field at the sixth electrode 120f and the seventh electrode 120g, reducing the risk of breakdown at the shape change position when the gallium nitride high electron mobility transistor 100 is turned off, reducing the risk of device thermal failure at the shape change position when the gallium nitride high electron mobility transistor 100 is turned on, further improving the dynamic resistance characteristics of the transistor, and improving the hard-turn capability of the transistor device.
[0107] In some embodiments, the projected overlap length of the seventh electrode 120g and the fifth sub-electrode 125 along the first direction X is greater than the projected overlap length of the seventh electrode 120g and the sixth sub-electrode 126 along the first direction X. At the instant the gallium nitride high electron mobility transistor 100 is turned off, a more uniform electric field can be formed between the fifth sub-electrode 125 and the seventh electrode 120g, thereby reducing the risk of breakdown at the shape change location.
[0108] In some embodiments, the projections of the seventh electrode 120g and the sixth sub-electrode 126 along the first direction X do not overlap.
[0109] In some embodiments, in the second direction Y, the length ratio of the fifth sub-electrode 125 to the seventh electrode 120g is between 0.8 and 1.2, ensuring that a relatively uniform electric field can be formed between the fifth sub-electrode 125 and the seventh electrode 120g at the moment when the gallium nitride high electron mobility transistor 100 is turned off and at the moment when the gallium nitride high electron mobility transistor 100 is turned on.
[0110] Furthermore, in one example, the fifth sub-electrode 125 and the seventh electrode 120g are of equal length and aligned in the second direction Y. This further ensures that a uniform electric field can be formed between the fifth sub-electrode 125 and the seventh electrode 120g at the moment the gallium nitride high electron mobility transistor 100 is turned off and at the moment the gallium nitride high electron mobility transistor 100 is turned on. This reduces the risk of breakdown at the shape change location at the moment the gallium nitride high electron mobility transistor 100 is turned off and reduces the risk of device thermal failure at the shape change location at the moment the gallium nitride high electron mobility transistor 100 is turned on.
[0111] It should be noted that the technical solutions or features described in the above embodiments can be combined or supplemented with each other without conflict. The scope of protection of this application is not limited to the precise structures described in the above embodiments and shown in the accompanying drawings; all modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.
Claims
1. A gallium nitride high electron mobility transistor, characterized in that, include: An epitaxial layer group, the epitaxial layer group including a substrate, a channel layer and a barrier layer, the channel layer being located on the substrate, the barrier layer being located on the side of the channel layer away from the substrate, and a two-dimensional electron gas being formed between the channel layer and the barrier layer; The epitaxial layer group has a transistor device region, which includes a first sub-region and a second sub-region adjacent to each other along a first direction. The length of the first sub-region in the second direction is greater than the length of the second sub-region in the second direction. The second direction is perpendicular to the first direction. A plurality of ohmic contact electrodes are arranged along a first direction in the transistor device region, each of the ohmic contact electrodes extending along a second direction, and the plurality of ohmic contact electrodes are configured as source and drain electrodes alternately arranged along the first direction, wherein the plurality of ohmic contact electrodes include: A first electrode, wherein the first electrode is the ohmic contact electrode located within the first sub-region and closest to the second sub-region, the first electrode comprising a first sub-electrode and a second sub-electrode spaced apart from each other along the second direction; and a second electrode, wherein the second electrode is the ohmic contact electrode located within the second sub-region and closest to the first electrode, and the projection of the second electrode and the first sub-electrode overlaps in the first direction; and A first electrical isolator is disposed at the interval between the first sub-electrode and the second sub-electrode, and the first electrical isolator is used to interrupt the two-dimensional electron gas between the first sub-electrode and the second sub-electrode.
2. The gallium nitride high electron mobility transistor according to claim 1, characterized in that, The projection overlap length between the second electrode and the first sub-electrode along the first direction is greater than the projection overlap length between the second electrode and the second sub-electrode along the first direction.
3. The gallium nitride high electron mobility transistor according to claim 2, characterized in that, The projections of the second electrode and the second sub-electrode along the first direction do not overlap.
4. The gallium nitride high electron mobility transistor according to claim 1, characterized in that, In the second direction, the ratio of the length of the first sub-electrode to the length of the second electrode is between 0.8 and 1.
2.
5. The gallium nitride high electron mobility transistor according to claim 1, characterized in that, The first sub-electrode and the second electrode are of equal length and are aligned in the second direction.
6. The gallium nitride high electron mobility transistor according to claim 1, characterized in that, Also includes: A second electrical isolator electrically isolates the source and drain of the plurality of ohmic contact electrodes when the transistor is in the off state.
7. The gallium nitride high electron mobility transistor according to claim 6, characterized in that, The first electrical isolator and at least a portion of the second electrical isolator are disposed in the same layer and are made of the same material.
8. The gallium nitride high electron mobility transistor according to any one of claims 1 to 6, characterized in that, The first electrical isolation element includes a first depletion layer located on the epitaxial layer group, the first depletion layer being used to deplete the two-dimensional electron gas over the covered area.
9. The gallium nitride high electron mobility transistor according to claim 8, characterized in that, The first depletion layer comprises a p-doped III-V group nitride semiconductor material.
10. The gallium nitride high electron mobility transistor according to any one of claims 1 to 6, characterized in that, The first electrical isolation device includes a first ion implantation isolation region, which is configured to eliminate the two-dimensional electron gas in the corresponding region by ion implantation.
11. The gallium nitride high electron mobility transistor according to claim 10, characterized in that, The first ion implantation isolation region is configured to eliminate the two-dimensional electron gas in the corresponding region by fluorine ion implantation.
12. The gallium nitride high electron mobility transistor according to claim 6, characterized in that, The second electrical isolation element includes a second depletion layer located on the epitaxial layer group, the second depletion layer being used to deplete the two-dimensional electron gas in the covered area.
13. The gallium nitride high electron mobility transistor according to claim 12, characterized in that, The second depletion layer comprises a p-doped III-V group nitride semiconductor material.
14. The gallium nitride high electron mobility transistor according to claim 12, characterized in that, The second depletion layer is disposed around each of the sources and / or around each of the drains.
15. The gallium nitride high electron mobility transistor according to claim 12, characterized in that, The second electrical isolation device further includes a second ion implantation isolation region disposed around the transistor device region, and the second depletion layer includes depletion units located between every two adjacent ohmic contact electrodes, with each depletion unit connected to the second ion implantation isolation region at opposite ends along the second direction.
16. The gallium nitride high electron mobility transistor according to claim 15, characterized in that, Each of the source electrodes has the depletion unit on both sides along the second direction; and / or Each of the drains is provided with the depletion cells on both sides along the second direction.
17. The gallium nitride high electron mobility transistor according to claim 12, characterized in that, Also includes: The gate is located on the side of the second depletion layer away from the epitaxial layer group, and the gate is located between two adjacent ohmic contact electrodes.
18. The gallium nitride high electron mobility transistor according to claim 6, characterized in that, Both the first and second electrical isolation devices include p-doped III-V group nitride semiconductor materials, and the p-doped III-V group nitride semiconductor materials included in the first and second electrical isolation devices are formed simultaneously in the same process.
19. The gallium nitride high electron mobility transistor according to claim 1, characterized in that, The gallium nitride high electron mobility transistor is an enhancement device.
20. The gallium nitride high electron mobility transistor according to claim 1, characterized in that, The plurality of ohmic contact electrodes also include: The third electrode is the ohmic contact electrode located within the first sub-region and closest to the first electrode, wherein the opposite ends of the first electrode along the second direction are aligned with the opposite ends of the third electrode along the second direction.
21. The gallium nitride high electron mobility transistor according to claim 1, characterized in that, Both the first sub-region and the second sub-region are rectangular.
22. The gallium nitride high electron mobility transistor according to claim 1, characterized in that, The number of the first electrical isolation element is two or more, and the two or more first electrical isolation elements are arranged at intervals along the second direction.
23. The gallium nitride high electron mobility transistor according to claim 1, characterized in that, The transistor device region further includes a third sub-region adjacent to the second sub-region along the first direction, the third sub-region being located on the side of the second sub-region away from the first sub-region, and the length of the third sub-region in the second direction being greater than the length of the second sub-region in the second direction; The plurality of ohmic contact electrodes also include: A fourth electrode, wherein the fourth electrode is the ohmic contact electrode located within the third sub-region and closest to the second sub-region, the fourth electrode comprising a third sub-electrode and a fourth sub-electrode spaced apart from each other along the second direction; and The fifth electrode is the ohmic contact electrode located in the second sub-region and closest to the fourth electrode, and the projection of the fifth electrode overlaps with that of the third sub-electrode along the first direction; The gallium nitride high electron mobility transistor also includes: A third electrical isolator is disposed at the interval between the third sub-electrode and the fourth sub-electrode, and the third electrical isolator is used to interrupt the two-dimensional electron gas between the third sub-electrode and the fourth sub-electrode.
24. The gallium nitride high electron mobility transistor according to claim 1, characterized in that, The transistor device region further includes a fourth sub-region adjacent to the second sub-region along the first direction, the fourth sub-region being located on the side of the second sub-region away from the first sub-region, and the length of the fourth sub-region in the second direction being less than the length of the second sub-region in the second direction; The plurality of ohmic contact electrodes also include: The sixth electrode, which is the ohmic contact electrode located within the second sub-region and closest to the fourth sub-region, comprises a fifth sub-electrode and a sixth sub-electrode spaced apart from each other along the second direction; and The seventh electrode is the ohmic contact electrode located within the fourth sub-region and closest to the sixth electrode, and the projection of the seventh electrode onto the fifth sub-electrode along the first direction overlaps with the projection of the fifth sub-electrode. The gallium nitride high electron mobility transistor also includes: A fourth electrical isolator is disposed at the interval between the fifth sub-electrode and the sixth sub-electrode, and the fourth electrical isolator is used to interrupt the two-dimensional electron gas between the fifth sub-electrode and the sixth sub-electrode.