Enhanced gallium nitride high electron mobility transistor device based on p-type cap layer
By using an arrayed multi-gate p-GaN structure, the problems of low threshold voltage and increased capacitance in p-GaN HEMT devices are solved, improving the device's withstand voltage and electrical performance, maintaining switching frequency characteristics, and achieving higher operating stability and lower power consumption.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Filing Date
- 2026-06-15
- Publication Date
- 2026-07-14
AI Technical Summary
Existing p-GaN enhancement-mode GaN HEMT devices have low threshold voltages and weak gate control capabilities, making them susceptible to gate voltage fluctuations. This leads to false triggering, increased power consumption, reduced signal drive, and decreased circuit stability. Furthermore, the use of field-plate termination structures increases capacitance and reduces switching frequency characteristics.
The arrayed multi-gate p-GaN structure includes parallel strip p-GaN and gate electrodes, which are fabricated by photolithography and etching processes or photolithography and secondary epitaxial processes. There is a gap between the source and drain electrodes and the strip p-GaN. The gate electrode is composed of gate pins and gate bridges, which improves the device's breakdown voltage and threshold voltage.
It improves the voltage withstand rating and operational stability of the device, enhances electrical performance, maintains switching frequency characteristics, reduces load effects, and improves etching uniformity and production line yield.
Smart Images
Figure CN122395987A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of power electronics, specifically to an enhanced gallium nitride high electron mobility transistor device based on a p-type cap layer and including an array of multiple gates. Background Technology
[0002] Power electronics technology is a key enabling technology for moving towards a fully electrified society. Whether it is the grid interface for data center power supply, the ultra-fast electric vehicle charging pile, or the intelligent motor drive in industrial automation, power electronic systems are now ubiquitous and will become even more widespread in the future.
[0003] Traditional silicon-based power electronic devices are increasingly failing to meet the demands of power electronics. The superior advantages of silicon carbide (SiC), gallium nitride (GaN), and other wide-bandgap semiconductors are leading to their adoption in power electronics. Compared to Si-based power electronic devices, GaN-based heterojunction transistors (GaN HEMTs) with p-type caps (p-GaN Caps) exhibit high two-dimensional electron gas concentration and mobility, significantly improving the performance and reliability of power electronic systems and reducing power consumption. Therefore, they offer significant advantages in fabricating high-performance power semiconductor devices, particularly high-speed, low-power, and high / medium-voltage power electronic devices. Furthermore, p-GaN bidirectional GaN HEMT technology plays a crucial role in power management systems.
[0004] However, on the one hand, due to the characteristics of the principle and process of p-GaN enhancement-mode GaN HEMT devices, they have obvious drawbacks, namely, low threshold voltage, typically around 0.5V, and weak gate control capability. GaN HEMT devices also face inherent circuit problems, such as false triggering and increased power consumption due to gate voltage fluctuations, reduced switching reliability due to decreased signal drive, and decreased circuit stability due to signal reflection and electromagnetic interference. On the other hand, typical GaN HEMT power electronic devices use field-plate termination structures to improve voltage withstand capability, but this introduces a large capacitance into the device, thereby reducing its switching frequency characteristics. Summary of the Invention
[0005] The purpose of this invention is to provide an enhanced gallium nitride high electron mobility transistor device based on a p-type cap layer, which improves the withstand voltage level, power density and efficiency, and electrical performance.
[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows: An enhancement-mode gallium nitride high electron mobility transistor device based on a p-type cap layer includes an epitaxial layer, a gate electrode, a source electrode, and a drain electrode, and further includes an arrayed multi-gate p-GaN structure. The arrayed multi-gate p-GaN structure comprises several strip p-GaNs, each strip p-GaN being formed by a p-GaN cap layer in the epitaxial layer or formed on the epitaxial layer, with each strip p-GaN arranged parallel to the length direction to form an array layout. Both the source electrode and the drain electrode are strip-shaped, and the length directions of the source electrode and the drain electrode are parallel to the length direction of the strip-shaped p-GaN. The arrayed multi-gate p-GaN structure is disposed between the source electrode and the drain electrode, and there are gaps between two adjacent strip-shaped p-GaNs, between the strip-shaped p-GaN and the source electrode, and between the strip-shaped p-GaN and the drain electrode. The gate electrode includes gate pins that correspond one-to-one with the strip-shaped p-GaN and a gate bridge connecting each of the gate pins.
[0007] A preferred embodiment is that each of the said strip p-GaN has an equal length, each of the said strip p-GaN has an equal width, and each of the said intervals has an equal width.
[0008] Preferably, the strip-shaped p-GaN is prepared by photolithography and etching processes, or by photolithography and secondary epitaxial processes.
[0009] According to embodiments of the present invention, the epitaxial layer includes any multiple layers selected from a substrate, a buffer layer, a channel layer, a barrier layer, and a p-GaN layer; the substrate is made of silicon, sapphire, or silicon carbide; the buffer layer is made of GaN, AlGaN, or AlN; the channel layer is made of GaN, AlGaN, or AlN; and the barrier layer is made of AlGaN or AlN.
[0010] Furthermore, the interval is filled with insulating material.
[0011] Furthermore, the insulating material is SiO2, Al2O3, or SiC.
[0012] In one embodiment, the length of the gate pin is equal to the length of the strip p-GaN, and the width of the gate pin is equal to the width of the strip p-GaN.
[0013] Preferably, the source electrode and the drain electrode are made of Ti, Al, Ni, or Au. The gate electrode is made of Ni or Au.
[0014] Due to the application of the above technical solutions, the present invention has the following advantages compared with the prior art: The present invention, through the array multi-gate p-GaN structure, can share the withstand voltage capability of the device, thereby improving the overall withstand voltage level of the device, increasing the power density and efficiency of the system; improving the overall threshold voltage of the device, improving the operating stability and safety of the device, improving the electrical performance of the device, and maintaining the switching frequency characteristics of the device. Attached Figure Description
[0015] Appendix Figure 1 This is a cross-sectional schematic diagram of the enhanced gallium nitride high electron mobility transistor device based on a p-type cap layer according to the present invention.
[0016] Appendix Figure 2 This is a schematic diagram of the gate electrode in the enhanced gallium nitride high electron mobility transistor device based on a p-type cap layer according to the present invention.
[0017] Appendix Figure 3 This is a schematic diagram of the gate electrode structure in the enhanced gallium nitride high electron mobility transistor device based on a p-type cap layer according to the present invention.
[0018] Appendix Figure 4 This is a schematic diagram of step 0 of the manufacturing method of the enhanced gallium nitride high electron mobility transistor device based on the p-type cap layer of the present invention.
[0019] Appendix Figure 5 This is a schematic diagram of step 1 of the manufacturing method of the enhanced gallium nitride high electron mobility transistor device based on the p-type cap layer of the present invention.
[0020] Appendix Figure 6 This is a schematic diagram of step 2 of the manufacturing method of the enhanced gallium nitride high electron mobility transistor device based on the p-type cap layer of the present invention.
[0021] Appendix Figure 7 This is a schematic diagram of step 3 of the manufacturing method of the enhanced gallium nitride high electron mobility transistor device based on the p-type cap layer of the present invention.
[0022] Appendix Figure 8 This is a schematic diagram of step 4 of the manufacturing method of the enhanced gallium nitride high electron mobility transistor device based on the p-type cap layer of the present invention.
[0023] In the above figures: 1. Gate electrode; 2. Source electrode; 3. Drain electrode; 4. Interconnect metal; 5. Gate metal pad; 6. Source metal pad; 7. Drain metal pad; 8. Substrate; 9. Buffer layer; 10. Channel layer; 11. Barrier layer; 12. p-GaN layer; 13. Strip p-GaN; 14. Spacer; 15. Gate pin; 16. Gate bridge; 17. Device isolation; 18. Passivation layer; 19. Protective layer; 20. Two-dimensional electron gas. Detailed Implementation
[0024] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.
[0025] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.
[0026] Example: As attached Figure 1 As shown, an enhanced gallium nitride high electron mobility transistor device based on a p-type cap layer includes an epitaxial layer, a gate electrode 1, a source electrode 2, a drain electrode 3, an interconnect metal 4, a gate metal pad 5, a source metal pad 6, a drain metal pad 7, and an array of multi-gate p-GaN structures.
[0027] The epitaxial layer structure, from bottom to top, generally includes any multiple layers such as substrate 8, buffer layer 9, channel layer 10, barrier layer 11, and p-GaN layer 12 (p-GaN cap layer). The substrate 8 is made of silicon (Si), sapphire, silicon carbide (SiC), or other materials; the buffer layer 9 is made of GaN, AlGaN, AlN, or other materials; the channel layer 10 is made of GaN, AlGaN, AlN, or other materials; and the barrier layer 11 is made of AlGaN, AlN, or other materials.
[0028] The arrayed multi-gate p-GaN structure includes several strip-shaped p-GaN13s, which are elongated cuboid structures composed of p-GaN. These strip-shaped p-GaN13s are formed from p-GaN cap layers in an epitaxial layer, or from p-GaN formed on an epitaxial layer. Specifically, when the substrate 8 includes a p-GaN layer 12, the p-GaN layer 12 is processed to form individual strip-shaped p-GaN13s; when the substrate 8 does not include a p-GaN layer 12, the individual strip-shaped p-GaN13s are formed on the epitaxial layer through processing. Here, the strip-shaped p-GaN13s can be formed on either the upper surface of the epitaxial layer or the lower surface of the epitaxial layer after the substrate 8 has been removed. The length directions of the individual strip-shaped p-GaN13s are parallel to form an array layout, and typically, the length and width of each strip-shaped p-GaN13 are equal. Figure 1 In the diagram, the length direction of the p-GaN13 bar corresponds to the direction perpendicular to the plane, and the width direction of the p-GaN13 bar corresponds to the left-right direction.
[0029] Simultaneously, the source electrode 2 and drain electrode 3 disposed on the substrate 8 are also strip-shaped, and the length directions of the source electrode 2 and drain electrode 3 are parallel to the length directions of the strip-shaped p-GaN 13. Thus, an array of multi-gate p-GaN structures is disposed between the source electrode 2 and the drain electrode 3. Furthermore, there is a gap 14 between adjacent two strip-shaped p-GaN 13s, between the strip-shaped p-GaN 13 closest to the source electrode 2 and the source electrode 2, and between the strip-shaped p-GaN 13 closest to the drain electrode 3 and the drain electrode 3. The width of each gap 14 is equal, and the width direction of the gap 14 also corresponds to the adjacent... Figure 1 The left and right directions are shown in the diagram. The space within 14 is usually filled with insulating material, such as SiO2, Al2O3, or SiC.
[0030] As attached Figure 2 and attached Figure 3 As shown, the gate electrode 1 includes multiple gate pins 15 and a gate bridge 16. Each gate pin 15 is correspondingly positioned above and connected to a strip of p-GaN 13, forming a p-GaN gate, i.e., gate electrode 1. The gate bridge 16 connects to each gate pin 15 above it. The gate pins 15 are also strip-shaped, with a length and width equal to the length and width of the strip of p-GaN 13. The gate bridge 16 and the gate pins 15 are actually integrally fabricated and completed simultaneously. (See attached diagram) Figure 2 For ease of structural demonstration, the gate bridge 16 and gate foot 15 are separated. (The remaining text appears to be incomplete and requires further context.) Figure 3 In order to facilitate the demonstration of the arrayed multi-gate p-GaN structure, the gate bridge 16 has been made transparent.
[0031] The aforementioned strip-shaped p-GaN13 is prepared by photolithography and etching processes (when the substrate 8 includes a p-GaN layer 12), or by photolithography and secondary epitaxial processes (when the substrate 8 does not include a p-GaN layer 12).
[0032] In the aforementioned multi-gate p-GaN array structure, the width of the strip p-GaN13 / gate pin 15 (i.e., the width of the p-GaN gate) and the width of the spacing 14 are related to the device's voltage withstand capability. In a specific embodiment, the width Wg of a single strip p-GaN13 is 1 μm, and the width Pitch of the spacing 14 is 4 μm. One strip p-GaN13 and one spacing 14 form a withstand voltage cycle, with a withstand voltage cycle T = 5 μm. At a withstand voltage of 1200V, the multi-gate p-GaN array structure includes 5 cycles 5T. In each cycle T, the p-GaN gate bears a voltage of 1200V / 5. The total width Lsj of the multi-gate p-GaN array structure is at least 25 μm, and the peak voltage Vpeak is changed from being borne by a single p-GaN gate in the prior art to being shared by 5 p-GaN gates, greatly improving the reliability of the gate being able to break down. The number of strip p-GaN13s in the multi-gate p-GaN array structure is determined through calculation and experimentation. For example, if Wg = 0.5 μm, Pitch = 2.5 μm, and the peak voltage withstand capability of one cycle T = 100V, then the array size required to design a 600V device is 6T, and Lsj = 6 × (0.5 + 2.5) = 18 μm. When designing the device, based on the peak voltage the device needs to withstand, combined with the peak voltage withstand capability of a unit width interval 14, the total width of the required interval 14 can be calculated. This leads to the width of a single interval 14 after dividing the device into multiple intervals. Combining this with the width of a single strip of p-GaN13, the width of the withstand voltage cycle is obtained. Finally, the device width is determined based on the width of the withstand voltage cycle and the number of cycles.
[0033] The following describes the manufacturing process of the aforementioned enhanced gallium nitride high electron mobility transistor device based on a p-type cap layer.
[0034] Step 0 is as follows Figure 4 As shown: Preparation of epitaxial wafers.
[0035] The epitaxial layer structure of GaN HEMT devices, from bottom to top, generally includes a substrate (8), a nucleation layer, a superlattice layer, a buffer layer (9), a channel layer (10), a spacer layer, a charge supply layer, a barrier layer (11), and a cap layer. The specific structure and its composition vary depending on the performance and cost requirements of the GaN HEMT device.
[0036] Because this solution targets arrayed multi-gate p-GaN structures, and does not involve the epitaxy, structure, or fabrication process of specific GaN HEMT devices, the realization of arrayed multi-gate p-GaN structures can be achieved either by etching the topmost p-GaN layer of the epitaxial wafer, or by patterning an epitaxial wafer without a p-GaN layer and then performing a second epitaxial growth of p-GaN. Furthermore, the number, type, and thickness of the metal stacks for the source / drain ohmic contact electrodes include, but are not limited to, the conventional Ti / Al / Ni / Au = 20 / 160 / 55 / 45nm, and are not limited to specific process parameters achieved due to differences in equipment technology or device performance.
[0037] In this embodiment, an epitaxial layer structure with a p-GaN layer 12 is used as an example to illustrate the concept of this scheme. The epitaxial layer includes, from bottom to top, a substrate 8, a buffer layer 9, a channel layer 10, a barrier layer 11, and a p-GaN layer 12. Further, it includes a silicon (Si) or sapphire or silicon carbide (SiC) substrate 8, a GaN buffer layer 9, a GaN channel layer 10, an AlGaN barrier layer 11, and a p-GaN cap layer.
[0038] Step 1 is attached. Figure 5 As shown: Device fabrication, specifically including the fabrication of an array of multi-gate p-GaN structures and device isolation 17.
[0039] ① Using a photolithography machine (stepper photolithography machine) to perform photolithography process, patterning of each strip of p-GaN13 of the array multi-gate p-GaN structure is fabricated on the surface of p-GaN layer 12; ② Etching (IPC etching) of p-GaN layer 12 completes the fabrication of the arrayed multi-gate p-GaN structure; ③ For device isolation 17, a photolithography process is performed using a photolithography machine (stepper photolithography machine), and ion implantation is used to complete the fabrication of device isolation 17 on the upper half of AlGaN barrier layer 11, GaN channel layer 10 and GaN buffer layer 9.
[0040] Step 2 is attached. Figure 6 As shown: Device fabrication, specifically including the fabrication of source / drain ohmic contact electrodes.
[0041] ① Photolithography is performed on the source / drain ohmic contact electrodes (i.e., source electrode 2 and drain electrode 3) using a photolithography machine (stepper photolithography machine); ②Etch (IPC etching) AlGaN barrier layer 11, and further etch into GaN channel layer 10, so that the etching depth reaches the depth of two-dimensional electron gas (2EDG) 20 (shown by the red dashed line in the figure); ③ The source / drain ohmic contact electrodes (i.e., source electrode 2 and drain electrode 3) are fabricated using E-beam evaporation, stripping, and annealing processes (800~900℃, 30s).
[0042] Alternatively, step ② can be skipped and step ③ can be performed directly to complete the fabrication of the source / drain ohmic contact electrodes. The positions of the source / drain ohmic contact electrodes can be interchanged.
[0043] The metal types and thicknesses of the source electrode 2 and drain electrode 3 include, but are not limited to, Ti / Al / Ni / Au = 20 / 160 / 55 / 45nm.
[0044] Step 3 is attached. Figure 7 As shown: Device fabrication, specifically including the fabrication of arrayed Schottky contact electrodes.
[0045] ① For the gate Schottky contact electrode (gate electrode 1), a photolithography process is performed using a photolithography machine (stepper photolithography machine); ② The gate Schottky contact electrode (gate electrode 1) is fabricated on the p-GaN layer 12 by E-beam evaporation and stripping.
[0046] The metal type and thickness of the gate Schottky contact electrode (gate electrode 1) include, but are not limited to, Ni / Au = 45 / 220 nm.
[0047] Step 4 is attached. Figure 8 As shown: Device fabrication, specifically including the fabrication of interconnect metal 4 and various metal terminals.
[0048] ① A passivation layer 18 is grown using low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD) technology. The material of the passivation layer 18 is Si3N4 or SiO2 or other film materials, or it can be a composite layer. ② For interconnect metal 4 (interconnect metal 4 is used to connect gate electrode 1 to gate metal terminal block 5, source electrode 2 to source metal terminal block 6, drain electrode 3 to drain metal terminal block 7, etc.), a photolithography process is performed using a photolithography machine (stepper photolithography machine); ③ Etch (RIE etching) the passivation layer 18 to create openings at the required locations on the interconnect metal 4 (such as the top of the gate electrode 1, the top of the source electrode 2, the top of the drain electrode 3, etc.); ④ The interconnect metals 4 are fabricated using E-beam evaporation and stripping. The types and thicknesses of the interconnect metals 4 include, but are not limited to, Ti / Au = 20 / 400 nm. ⑤ After coating with polyimide to complete the device protective layer 19, the metal terminal block is patterned by photolithography using a photolithography machine (stepper photolithography machine). ⑥ On the protective layer 19, the gate metal terminal block 5, the source metal terminal block 6, and the drain metal terminal block 7 are sputtered and electroplated.
[0049] Compared to conventional GaN-enhanced HEMT bidirectional devices, the aforementioned p-type cap-based enhancement-mode gallium nitride high electron mobility transistor (HMT) devices have the following advantages: 1) From the perspective of device structure, on the one hand, the arrayed multi-gate p-GaN structure can distribute the device's withstand voltage, thereby improving the overall withstand voltage level, increasing system power density and efficiency, and expanding the device's application to medium and high voltage fields. On the other hand, the arrayed multi-gate p-GaN structure increases the overall threshold voltage of the device, improving its operational stability and safety, while also reducing off-state leakage current and improving its electrical performance. Furthermore, it avoids the drawback of introducing large capacitance due to the use of a field-plate termination structure, thus maintaining the device's switching frequency characteristics. 2) From the perspective of process fabrication, the etching of the array multi-gate p-GaN structure reduces the loading effect, thereby improving the etching uniformity. This not only improves the stability of electrical properties such as withstand voltage and threshold voltage, but also improves the production line yield.
[0050] The above embodiments are only for illustrating the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They should not be construed as limiting the scope of protection of the present invention. All equivalent changes or modifications made in accordance with the spirit and essence of the present invention should be covered within the scope of protection of the present invention.
Claims
1. An enhancement-mode gallium nitride high electron mobility transistor device based on a p-type cap layer, comprising an epitaxial layer, a gate electrode, a source electrode, and a drain electrode, characterized in that: It also includes arrayed multi-gate p-GaN structures: The arrayed multi-gate p-GaN structure comprises several strip p-GaNs, each strip p-GaN being formed by a p-GaN cap layer in the epitaxial layer or formed on the epitaxial layer, with each strip p-GaN arranged parallel to the length direction to form an array layout. Both the source electrode and the drain electrode are strip-shaped, and the length directions of the source electrode and the drain electrode are parallel to the length direction of the strip-shaped p-GaN. The arrayed multi-gate p-GaN structure is disposed between the source electrode and the drain electrode, and there are gaps between two adjacent strip-shaped p-GaNs, between the strip-shaped p-GaN and the source electrode, and between the strip-shaped p-GaN and the drain electrode. The gate electrode includes gate pins that correspond one-to-one with the strip-shaped p-GaN and a gate bridge connecting each of the gate pins.
2. The enhanced gallium nitride high electron mobility transistor device based on a p-type cap layer according to claim 1, characterized in that: Each of the stated strip p-GaN has the same length and the same width.
3. The enhanced gallium nitride high electron mobility transistor device based on a p-type cap layer according to claim 1, characterized in that: The widths of all the intervals are equal.
4. The enhanced gallium nitride high electron mobility transistor device based on a p-type cap layer according to claim 1, characterized in that: The strip-shaped p-GaN is prepared by photolithography and etching processes, or by photolithography and secondary epitaxial processes.
5. The enhanced gallium nitride high electron mobility transistor device based on a p-type cap layer according to claim 1, characterized in that: The epitaxial layer includes any multiple layers selected from a substrate, a buffer layer, a channel layer, a barrier layer, and a p-GaN layer; the substrate is made of silicon, sapphire, or silicon carbide; the buffer layer is made of GaN, AlGaN, or AlN; the channel layer is made of GaN, AlGaN, or AlN; and the barrier layer is made of AlGaN or AlN.
6. The enhanced gallium nitride high electron mobility transistor device based on a p-type cap layer according to claim 1, characterized in that: The interval is filled with insulating material.
7. The enhanced gallium nitride high electron mobility transistor device based on a p-type cap layer according to claim 6, characterized in that: The insulating material is SiO2, Al2O3 or SiC.
8. The enhanced gallium nitride high electron mobility transistor device based on a p-type cap layer according to claim 1, characterized in that: The length of the gate pin is equal to the length of the strip p-GaN, and the width of the gate pin is equal to the width of the strip p-GaN.
9. The enhanced gallium nitride high electron mobility transistor device based on a p-type cap layer according to claim 1, characterized in that: The source electrode and the drain electrode are made of Ti, Al, Ni or Au metals.
10. The enhanced gallium nitride high electron mobility transistor device based on a p-type cap layer according to claim 1, characterized in that: The gate electrode uses either Ni or Au metal.