Shielded gate trench device and method of manufacturing the same

Abstract

The present application provides a shield gate trench device and a manufacturing method thereof. The method comprises: depositing a first polysilicon material in a trench with a field dielectric layer and performing a first etching process to preliminarily determine a step angle; depositing a second polysilicon material again and performing a second etching process to form a shield gate; and then forming an inter-electrode dielectric layer and a control gate above the shield gate. By controlling the first etching process mode (such as DRC or DRP combination) and cooperating with the polysilicon re-deposition process, the precise control of the step field dielectric layer angle is realized. The present application can make the intermediate electric field distribution in the device more uniform, avoid the electric field concentration effect at the step thickness mutation, and thus significantly improve the breakdown voltage and working reliability of the device. The device manufactured by the present disclosure has an optimized field dielectric topography, effectively improves the electrical performance and improves the process manufacturing window.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit manufacturing, and in particular to a shielded gate trench device and its manufacturing method. Background Technology

[0002] With the increasing demands on device performance from modern high-efficiency power conversion systems, shielded gate trench MOSFETs have become core devices in the power semiconductor field due to their excellent characteristics such as low on-resistance, low gate charge, and high switching frequency.

[0003] In the structural design of SGT devices, a shielding gate polysilicon (Poly1) is typically placed at the bottom of the trench, and an inter-electrode dielectric layer (IPO) is placed between the shielding gate polysilicon and the control gate polysilicon. In this type of structure, the morphology of the polysilicon and the angle of the adjacent step field oxide layer have a crucial influence on the electric field distribution and breakdown voltage (BV) inside the device.

[0004] In traditional manufacturing processes, the etching process for shielding gate polysilicon is relatively simple, but it is often difficult to precisely control the step angle of the field oxide layer. If the field oxide layer angle is inappropriate, it will lead to uneven electric field distribution during device operation, which can easily generate electric field concentration effect, thereby reducing the breakdown voltage and long-term reliability of the device.

[0005] Especially in medium-voltage (MV) SGT device applications, how to achieve a better electric field distribution balance through process optimization is a key issue that urgently needs to be solved in current semiconductor manufacturing processes. Summary of the Invention

[0006] The technical problem to be solved by this invention is how to accurately control the angle of the stepped field dielectric layer in the shielded gate trench device in order to optimize the internal electric field distribution of the device and improve the breakdown voltage and long-term operational reliability.

[0007] Shielding trench devices include:

[0008] Substrate, with trenches;

[0009] The field medium layer is located on the sidewall of the trench and has a stepped structure;

[0010] The shielding gate is located at the bottom of the trench, and the sidewall of the shielding gate is attached to the stepped structure of the field dielectric layer;

[0011] Inter-electrode dielectric layer, located above the shielding gate;

[0012] The control gate is located above the inter-electrode dielectric layer.

[0013] Preferably, the field dielectric layer includes a field oxide layer.

[0014] Preferably, the shielding gate has a structure formed by stacking two layers of polycrystalline silicon material.

[0015] Preferably, the stepped structure of the field medium layer is located in the middle of the trench sidewall.

[0016] Preferably, the inter-electrode dielectric layer includes an inter-electrode oxide layer.

[0017] Preferably, the stepped structure has a preset stepped angle value.

[0018] A method for manufacturing a shielded trench device includes the following steps:

[0019] Step 1: Provide a substrate, form trenches in the substrate, and form a field dielectric layer on the inner wall of the trenches and the surface of the substrate;

[0020] Step 2: Deposit the first shielding gate material in the trench;

[0021] Step 3: Perform a first etching process on the first shielding gate material, and adjust the morphology of the field dielectric layer by controlling the etching mode, thereby determining the step field dielectric layer angle.

[0022] Step 4: Deposit a second shielding gate material again on the surface of the first shielding gate material after the first etching process;

[0023] Step 5: Perform a second etching process on the second shielding gate material to form the shielding gate;

[0024] Step 6: Etch the field dielectric layer and form an inter-electrode dielectric layer above the shielding gate;

[0025] Step 7: Deposit control gate material in the trench and etch to form the control gate.

[0026] Preferably, in step one, the field dielectric layer includes a field oxide layer.

[0027] Preferably, in step three, the first etching process includes a multi-stage etching process.

[0028] Preferably, in step three, the multi-stage etching process includes a combination of plasma dry etching and plasma reaction treatment.

[0029] Preferably, in step three, the first etching process is performed by performing at least two consecutive plasma dry etching processes.

[0030] Preferably, in step three, the first etching process is performed by sequentially performing plasma reaction treatment and plasma dry etching.

[0031] Preferably, in step three, the first etching process is performed by plasma reaction alone.

[0032] Preferably, in step six, the inter-electrode dielectric layer includes an inter-electrode oxide layer.

[0033] As described above, the shielding trench device and its manufacturing method of the present invention have the following beneficial effects:

[0034] This invention achieves precise adjustment of the stepped field dielectric layer angle by introducing a re-deposition process combined with multi-stage etching. This smoothing of the morphology reduces electric field jumps caused by abrupt changes in step thickness, allowing electric field lines to be distributed more evenly on the trench sidewalls, eliminating localized high electric field points caused by excessively steep steps in traditional processes. This effectively improves the device's breakdown voltage and avalanche withstand capability, and reduces leakage current risk. Simultaneously, the gentler angle improves the coverage integrity of the inter-electrode dielectric layer, enhances gate reliability in high-temperature applications, eliminates the risk of gate oxide failure due to tip discharge, and achieves synergistic optimization of power device performance. Attached Figure Description

[0035] Figure 1 The diagram shows a process flow diagram of the method for manufacturing the shielded trench device of the present invention;

[0036] Figure 2 This is a schematic diagram of the initial structure during the manufacturing process of the shielding trench device of the present invention;

[0037] Figure 3 The diagram shows the structure of the first etching stage of the present invention, which employs a two-stage plasma dry etching process.

[0038] Figure 4 The diagram shows a stage structure of the re-deposition of polycrystalline silicon material using a two-stage plasma dry etching process according to the present invention.

[0039] Figure 5 The diagram shows a schematic representation of the shielding gate formation stage of the present invention using a two-stage plasma dry etching process.

[0040] Figure 6 The diagram shows the structural stage of forming the inter-electrode dielectric layer using a two-stage plasma dry etching process according to the present invention.

[0041] Figure 7 The diagram shows a schematic representation of the control gate formation stage of the present invention using a two-stage plasma dry etching process.

[0042] Figure 8 The diagram shown is a schematic diagram of the first etching stage of the present invention using plasma reaction processing technology.

[0043] Figure 9 The diagram shows a stage structure of the re-deposition of polycrystalline silicon material using a plasma reaction processing technology according to the present invention.

[0044] Figure 10 The diagram shows a schematic representation of the shielding gate formation stage using a plasma reaction processing technology according to the present invention.

[0045] Figure 11 The diagram shows a staged structure of the inter-electrode dielectric layer using plasma reaction processing technology according to the present invention.

[0046] Figure 12 The diagram shows a schematic representation of the control gate formation stage using a plasma reaction processing technology according to the present invention.

[0047] Figure 13 The diagram shows the changes in electric field distribution and the simulation of device structure before and after optimization using plasma reaction processing technology according to the present invention. Detailed Implementation

[0048] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0049] This disclosure provides a shielded trench device and its manufacturing method, which are described below in conjunction with... Figures 1 to 13 The embodiments are described in detail below. Figure 1 The process flow of the method for manufacturing a shielded trench device is shown. Figure 2 The initial structure during the manufacturing process is shown. Figures 3 to 7 The different stages of the structure are shown, which employ two plasma dry etching processes in the first etching process. Figures 8 to 12 The different stages of the plasma reaction process used in the first etching process are shown. Figure 13 The simulation comparison shows the changes in electric field distribution and device structure before and after optimization using plasma reaction processing technology.

[0050] Shielding trench devices include:

[0051] Substrate 101 has trenches;

[0052] The field medium layer 102 is located on the sidewall of the trench and has a stepped structure;

[0053] The shielding gate is located at the bottom of the trench, and the sidewall of the shielding gate is attached to the stepped structure of the field dielectric layer 102.

[0054] An inter-electrode dielectric layer 105 is located above the shielding gate;

[0055] The control gate is located above the inter-electrode dielectric layer 105.

[0056] In some embodiments, substrate 101 is made of a semiconductor material, which may include single-crystal silicon. Substrate 101 may also be made of other suitable semiconductor structures. Besides bulk silicon wafers, substrate 101 may also be composed of silicon carbide, gallium nitride, gallium arsenide, indium phosphide, silicon germanium, or combinations thereof. Substrate 101 may have a multilayer structure, such as a uniformly doped layer or polarization gradient layer formed on a single-crystal semiconductor by an epitaxial process, the epitaxial layer thickness and doping concentration of which can be adjusted according to the breakdown voltage level of the device design. Furthermore, substrate 101 may also be made of silicon-on-insulator (SOI), germanium-on-insulator (GOI), or a semiconductor wafer with a strain distribution. Substrate 101 typically has a predefined conductivity type, such as an N-type structure containing phosphorus or arsenic, or a P-type structure containing boron, gallium, or aluminum. Trenches can be formed downwards in substrate 101 using a photolithographic mask in conjunction with anisotropic reactive ion etching, and their height-to-width ratio can be flexibly customized according to the power handling capacity of the device.

[0057] In some embodiments, the field dielectric layer 102 includes a field oxide layer. In some embodiments, the field dielectric layer 102 may include silicon dioxide, silicon nitride, silicon oxynitride, fluorosilicone glass, phosphosilicate glass, borosilicate glass, or a dielectric material with a low dielectric constant. To improve interface quality, the field dielectric layer 102 may also employ a combination of high dielectric constant dielectric materials such as hafnium oxide, zirconium oxide, aluminum oxide, lanthanum oxide, or yttrium oxide. The field dielectric layer 102 can be formed by a thermal oxidation process, such as in-situ steam generation, dry oxidation, or wet oxidation; the field dielectric layer 102 can also be formed by chemical vapor deposition, plasma-enhanced chemical vapor deposition, high-density plasma chemical vapor deposition, high-gain plasma deposition, or atomic layer deposition. Employing a high-quality thermal oxidation process ensures a low interface state density between the field dielectric layer 102 and the trench sidewalls of the substrate 101. The field dielectric layer 102 has a preset thickness value, which can gradually increase from the trench depth direction towards the bottom or remain constant to maintain stable potential isolation between the shielding gate and the drift region.

[0058] In some embodiments, the shielding gate has a structure formed by stacking two layers of polycrystalline silicon material. This structure is jointly formed by a first polycrystalline silicon material 103 and a second polycrystalline silicon material 104 through staged deposition and subsequent etching. Besides polycrystalline silicon, the shielding gate can also be made of amorphous silicon or a low-resistivity metal material. These metal materials can include titanium, titanium nitride, tantalum, tantalum nitride, tungsten, tungsten nitride, tungsten silicide, cobalt, cobalt silicide, nickel, nickel silicide, aluminum, copper, or alloys thereof. The shielding gate can be filled in the lower part of the trench using a low-pressure chemical vapor deposition process. During formation, the shielding gate can be in-situ doped with impurities such as phosphorus, arsenic, or boron to adjust its work function. Using a staged deposition process allows for better filling integrity at the stepped corner positions of the shielding gate, eliminating internal stress points that may be caused by high aspect ratio filling.

[0059] In some embodiments, the stepped structure of the field dielectric layer 102 is located in the middle of the trench sidewall. This location can serve as a transition region between the shielding electric field and the gate electric field. By placing the stepped structure in the middle of the trench sidewall, the equipotential line distribution inside the trench can be more uniformly dispersed, and the electric field peak can be moved away from the critical interface where breakdown is likely to occur. The vertical depth of this location can be precisely defined by adjusting the time and mode of the first etching process to allow for topology adaptation between product platforms of different voltage levels.

[0060] In some embodiments, the inter-electrode dielectric layer 105 includes an inter-electrode oxide layer. The inter-electrode dielectric layer 105 can also employ a silicon oxide-silicon nitride-silicon oxide composite structure, silicon nitride, or the aforementioned high-dielectric-constant dielectric materials. The inter-electrode dielectric layer 105 can be formed by plasma-enhanced chemical vapor deposition, atomic layer deposition, or a process involving a combination of chemical vapor deposition and thermal oxidation. Using a high-dielectric-constant material can significantly enhance the shielding effectiveness of the control gate on the shield gate and improve insulation capability without increasing physical thickness.

[0061] In some embodiments, the stepped structure has a preset step angle value. (Reference) Figure 13 Specific etching processes can improve the distribution of the intermediate electric field. The optimized stepped structure, with its gentle angular transition, broadens the electric field lines that originally converged at the right-angled steps. This morphological modification avoids charge accumulation in the thinner regions of the field dielectric layer 102, enabling the device to smoothly distribute potential energy under reverse bias, thereby improving the device's breakdown voltage and long-term operational stability.

[0062] The method for manufacturing shielded gate trench devices includes the following steps, with polysilicon as an example of the gate material:

[0063] Step 1: Provide a substrate 101, form a trench in the substrate 101, and form a field dielectric layer 102 on the inner wall of the trench and the surface of the substrate 101.

[0064] The substrate 101 can be a silicon or composite semiconductor substrate. The trench formation process typically involves forming a sacrificial oxide layer and a hard mask layer on the surface of the substrate 101, followed by defining the trench profile using a dry etching process based on fluorine- or chlorine-based gases. The formation of the field dielectric layer 102 can be achieved using high-temperature thermal oxidation in a furnace tube, or by chemical vapor deposition containing silane and nitrous oxide precursors. To optimize high aspect ratio filling, a flowable chemical vapor deposition process combined with steam annealing can also be used.

[0065] In some embodiments, in step one, the field dielectric layer 102 includes a field oxide layer. The field oxide layer can be grown under a preset pressure range, and the high density of the field oxide layer is ensured by controlling the oxygen flow rate and ambient pressure.

[0066] Step 2: Deposit the first polycrystalline silicon material 103 in the trench. (e.g.) Figure 2 As shown, a first polycrystalline silicon material 103 is filled using a low-pressure chemical vapor deposition (LPCVD) process. Dichlorosilane can be used as the primary silicon source during the deposition process. The deposition thickness must be sufficient to fill the entire trench and cover the upper surface of the field dielectric layer 102 to provide adequate material margin for subsequent etch-back processes.

[0067] Step 3: Perform a first etching process on the first polycrystalline silicon material 103. By controlling the etching mode, adjust the morphology of the field dielectric layer 102, and thus determine the stepped field dielectric layer angle. The first etching process thins the first polycrystalline silicon material 103 in a plasma etching chamber, reducing its upper surface to a preset stepped height. During this process, by adjusting the gas composition and energy distribution in the subreactor, the exposed upper contour of the field dielectric layer 102 is simultaneously corrected using physical bombardment.

[0068] In some embodiments, step three, the first etching process includes a multi-stage etching process. The multi-stage etching process can achieve gradual fine-tuning of the gradient of the field dielectric layer 102 by switching the etching gas ratio during the thinning process of the first polysilicon material 103.

[0069] In some embodiments, in step three, the multi-stage etching process includes a combination of dry plasma etching (DRC) and reactive plasma processing (DRP).

[0070] In some embodiments, plasma dry etching (DRC) can employ an inductively coupled plasma (ICP) source or a capacitively coupled plasma (CCP) source. DRC can utilize a mixture containing hydrogen bromide, chlorine, oxygen, and nitrogen to provide highly anisotropic etching. In some embodiments, the etching process can employ a pulsed plasma mode. By adjusting the pulse frequency and duty cycle, the concentration ratio of reactive radicals to oriented ions can be independently controlled, thereby maintaining consistency of the step angle in trenches with different aspect ratios.

[0071] In some embodiments, plasma reactive processing (DRP) can employ a remote plasma source. DRP utilizes the reactive radicals of nitrogen trifluoride or sulfur hexafluoride with hydrogen to isotropically chemically modify the bends of the field dielectric layer 102, making its edges smoother. The combination of these two methods can obtain a step with a specific angle of inclination. In this way, charged particles can be deactivated before entering the reaction chamber, and a purely chemical reaction can be achieved between neutral reactive radicals and the field dielectric layer 102, thus achieving isotropic correction of the step's sharp corners.

[0072] In some embodiments, in step three, the first etching process is performed by continuously performing at least two plasma dry etching operations. (See reference...) Figures 3 to 7 The morphology can be adjusted stepwise by performing two plasma dry etching processes (DRC+DRC). In the first stage, most of the polysilicon is removed using the main etching gas. In the second stage, the height of the remaining first polysilicon material 103 is precisely determined using over-etching conditions, and the angle of the field dielectric layer 102 is finally shaped. Segmented operation can reduce process deviations caused by differences in pattern density, resulting in excellent consistency of the step angle between the wafer center and the edge.

[0073] In some embodiments, in step three, the first etching process is performed sequentially by plasma reactive processing (DRP) and plasma dry etching (DRC). First, the exposed dielectric surface is pre-modified using plasma reactive processing (DRP), and then the polysilicon is etched back down using plasma dry etching (DRC). This sequence helps to make the stepped surface of the field dielectric layer 102 smoother while ensuring the etching selectivity.

[0074] In some embodiments, in step three, the first etching process is performed as a separate plasma reaction process. (See reference...) Figure 8 In a specific process configuration, plasma reactive processing (DRP) alone can significantly etch back the first polysilicon material 103 and spontaneously form a gentler gradient step using free radical reactions. This method can maximize the protection of the substrate 101 from excessive physical bombardment.

[0075] In some embodiments, the first etching process can also employ atomic layer etching (ALE). ALE achieves atomic-level depth control through cyclic surface saturation modification followed by controlled physical stripping. This process provides extremely high etch selectivity, precisely defining the opening profile of the stepped structure while protecting the bottom surface of the underlying field dielectric layer 102. In some embodiments, the first etching process can also be combined with chemical downstream etching (CDE) to obtain a uniform stepped slope gradient across the wafer using a flow field distribution gradient. The etching pressure can be maintained at a preset pressure value. This multi-process synergistic etching approach ensures that the bonding accuracy between the shielded gate and the stepped surface of the field dielectric layer 102 meets preset design tolerances, thereby synergistically improving the blocking characteristics of the shielded gate trench device.

[0076] Step 4: Deposit a second polysilicon material 104 again on the residual surface of the first polysilicon material 103 after the first etching process. (Reference) Figure 4 and Figure 10 The re-deposition process repairs localized roughness caused by etching and refills the conductive layer above the steps within the trench. The second polysilicon material 104 can be polysilicon, amorphous silicon, or a doped silicon composite containing metallic impurities. The purpose of re-deposition is to eliminate stress points or microcracks that may be left on the steps of the field dielectric layer 102 by a single etching. The deposition conditions can be referenced from those of the first polysilicon material 103.

[0077] Step 5: Perform a second etching process on the second polysilicon material 104 to form a shielding gate. For example... Figure 5 and Figure 11 As shown, the polysilicon upper surface is adjusted to a set height through a second etching process. The second etching process utilizes an endpoint detection system to control the etch depth, ensuring that the final shielding gate sidewalls perfectly conform to the inclined surface of the stepped structure. Through this complex alternating deposition and etching process, the angle of the stepped field dielectric layer is significantly optimized, achieving a gentler slope than traditional single-particle etching.

[0078] Step Six: Etch the field dielectric layer 102 and form an inter-electrode dielectric layer 105 above the shielding gate. This step involves removing the excessively thick dielectric layer in the upper half of the trench to reserve sidewall space for the subsequent gate system. Unwanted portions of the field dielectric layer 102 can be removed using diluted hydrofluoric acid or a vapor phase method. The inter-electrode dielectric layer 105 is then formed using materials generated by oxidation of the shielding gate surface or grown through chemical phase deposition. This forms a... Figure 6 and Figure 11 The structure shown.

[0079] In some embodiments, in step six, the inter-electrode dielectric layer 105 includes an inter-electrode oxide layer. The thickness of the inter-electrode oxide layer can be controlled according to the threshold voltage requirements of the device, and the fabrication process can incorporate an in-situ vapor generation process to enhance the dielectric strength within the oxide layer.

[0080] Step 7: Deposit a third polysilicon material 106 in the trench and etch it to form the control gate. (Example: ...) Figure 7 and Figure 12 As shown, a third polysilicon material 106 fills the remaining space in the trench and is formed on the inter-electrode dielectric layer 105. The third polysilicon material 106 can be doped polysilicon with a specific crystal orientation, or a metal gate material can be used to reduce resistance. Subsequently, chemical mechanical polishing is used to remove excess polysilicon from the top of the substrate 101 to ensure that the control gate has a flat upper surface.

[0081] In some embodiments, in steps three to five, the electric field distribution inside the device tends to be uniform through the synergistic optimization of the first etching process, the deposition of the second polysilicon material 104, and the second etching process. (Reference) Figure 13 Through this multi-step etch-back and re-deposition process, the angle of the stepped field oxide layer is significantly reduced (the step FOX is more slanted). Simulated electric field models show that at the optimized stepped structure, the internal electric field peak changes from a concentrated state to a uniformly distributed band. This electric field balancing eliminates local high-pressure stress regions, significantly reducing the probability of hot carrier injection, thereby directly improving the device's bias withstand capability and cycle switching lifetime. Furthermore, the smoothing of the step angle also improves the consistency of the subsequent inter-electrode dielectric layer 105 film, preventing the risk of insulating layer breakage due to deformation. This synergistic optimization scheme achieves a significant enhancement of the electrical performance of power devices by fine-tuning the micro-geometry.

[0082] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0083] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A shielding trench device, characterized in that, include: Substrate, with trenches; The field medium layer is located on the sidewall of the trench and has a stepped structure; The shielding gate is located at the bottom of the trench, and the sidewall of the shielding gate is attached to the stepped structure of the field dielectric layer; Inter-electrode dielectric layer, located above the shielding gate; The control gate is located above the inter-electrode dielectric layer.

2. The shielding trench device according to claim 1, characterized in that: The field dielectric layer includes the field oxide layer.

3. The shielding trench device according to claim 1, characterized in that: The shielding gate has a structure formed by stacking two layers of polycrystalline silicon material.

4. The shielding trench device according to claim 1, characterized in that: The stepped structure of the field medium layer is located in the middle of the trench sidewall.

5. The shielding trench device according to claim 1, characterized in that: The inter-electrode dielectric layer includes the inter-electrode oxide layer.

6. The shielding trench device according to claim 1, characterized in that: The stepped structure has a preset step angle value.

7. A method for manufacturing a shielded trench device, characterized in that, include: Step 1: Provide a substrate, form trenches in the substrate, and form a field dielectric layer on the inner wall of the trenches and the surface of the substrate; Step 2: Deposit the first shielding gate material in the trench; Step 3: Perform a first etching process on the first shielding gate material, and adjust the morphology of the field dielectric layer by controlling the etching mode, thereby determining the step field dielectric layer angle. Step 4: Deposit a second shielding gate material again on the surface of the first shielding gate material after the first etching process; Step 5: Perform a second etching process on the second shielding gate material to form the shielding gate; Step 6: Etch the field dielectric layer and form an inter-electrode dielectric layer above the shielding gate; Step 7: Deposit control gate material in the trench and etch to form the control gate.

8. The method for manufacturing the shielding trench device according to claim 7, characterized in that: In step one, the field dielectric layer includes a field oxide layer.

9. The method for manufacturing the shielding trench device according to claim 7, characterized in that: In step three, the first etching process includes a multi-stage etching process.

10. The method for manufacturing the shielding trench device according to claim 9, characterized in that: In step three, the multi-stage etching process includes a combination of plasma dry etching and plasma reaction treatment.

11. The method for manufacturing the shielding trench device according to claim 7, characterized in that: In step three, the first etching process is performed by performing at least two consecutive plasma dry etching processes.

12. The method for manufacturing the shielding trench device according to claim 7, characterized in that: In step three, the first etching process involves sequentially performing plasma reaction treatment and plasma dry etching.

13. The method for manufacturing the shielding trench device according to claim 7, characterized in that: In step three, the first etching process is performed by plasma reaction alone.

14. The method for manufacturing the shielding trench device according to claim 7, characterized in that: In step six, the inter-electrode dielectric layer includes an inter-electrode oxide layer.

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