Semiconductor device, method of manufacture, power module, conversion circuit and vehicle

Abstract

The application discloses a semiconductor device, a preparation method, a power module, a conversion circuit and a vehicle. The semiconductor device comprises a semiconductor body comprising a first region and a well region, which are sequentially away from a first surface and are respectively arranged as a first conductive type and a second conductive type; the first surface is provided with a gate trench and a source trench comprising at least one sub-trench; further comprising a plurality of third regions and a plurality of fourth regions, which are respectively arranged as the first and second conductive types; the third regions are arranged on the slot walls of the source trench; the fourth regions are coated on the outer surfaces of the third regions, and the two ends thereof are connected to the slot walls of the source trench, and the two fourth regions coated on adjacent third regions are arranged at intervals; a first dielectric layer covers the sidewalls of the at least one sub-trench; a source contact structure is located in the source trench; the application can ensure high current density and low on-resistance of the device, suppress the electric field concentration near the gate, and improve the reverse recovery characteristics of the parasitic diode.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more particularly to a semiconductor device, a fabrication method, a power module, a conversion circuit, and a vehicle. Background Technology

[0002] Among power devices, SiC MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) are one of the most closely watched key devices. Their technological development has evolved from planar gate structures to trench gate structures. In planar SiC MOSFETs, current flows parallel to the substrate surface; while in trench structures, by embedding the gate electrode in an etched trench, current flows perpendicular to the substrate surface. This shift significantly reduces cell size, increases current density, and helps reduce on-resistance, thereby further improving device performance.

[0003] However, trench structures also introduce new technical challenges. At the bottom of the trench and its corners (trench corners), high local electric fields are easily generated due to the effects of geometry and electric field concentration. This high electric field can subject the gate insulating layer (such as the oxide layer) covering the trench surface to excessive electric field stress, potentially leading to degradation or even breakdown of the insulating layer under long-term operation, severely impacting the long-term reliability of the device. To mitigate these problems, reference... Figure 1 Existing technologies propose forming a semi-enclosed P+ region 01 on the sidewall and part of the bottom region of one side of the gate trench through ion implantation, serving as an electric field shielding structure. This structure aims to reduce the electric field strength borne by the gate insulating layer 02 by modulating the electric field distribution near the trench.

[0004] Nevertheless, the existing solutions still have the following obvious shortcomings: 1. The electric field at the bottom of the gate is still high, which limits reliability: Even with the introduction of P+ region shielding, the problem of electric field concentration in the central region at the bottom of the trench and at the corner of the trench has not been completely solved. The gate insulating layer still faces a high risk of breakdown, which affects the long-term reliability of the device under high voltage.

[0005] 2. Poor performance of the parasitic diode: When the device is reverse-biased, its body diode (parasitic diode) will participate in the operation. In the existing structure, the reverse recovery charge of this parasitic diode is relatively large, which leads to increased switching losses and poor reverse recovery capability, thus restricting the efficiency and performance of the device in high-frequency switching applications.

[0006] Therefore, how to further optimize the device structure of trench SiC MOSFETs, while maintaining their advantages of high current density and low on-resistance, effectively suppress electric field concentration near the gate, enhance gate oxide reliability, and improve the reverse recovery characteristics of parasitic diodes, has become a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0007] This application provides a semiconductor device, fabrication method, power module, conversion circuit, and vehicle that, while maintaining the advantages of high current density and low on-resistance, effectively suppress electric field concentration near the gate, enhance gate oxide reliability, and improve the reverse recovery characteristics of parasitic diodes.

[0008] According to one aspect of this application, a semiconductor device is provided, comprising: A semiconductor body, configured with a first conductivity type, includes a first surface and a second surface disposed opposite to each other; the semiconductor body further includes a well region and a first region; the first region is configured with a first conductivity type and located on the first surface, the well region is configured with a second conductivity type and located on the side of the first region away from the first surface, the first conductivity type and the second conductivity type are different; the first surface is provided with a gate trench and a source trench located on at least one side of the gate trench, the source trench including at least one sub-trench; the semiconductor body further includes a plurality of third regions and a plurality of fourth regions, the third regions are configured with a first conductivity type, the fourth regions are configured with a second conductivity type; the third regions are disposed on the trench wall of the source trench; the fourth regions cover the outer surface of the third regions, and their two ends are connected to the trench wall of the source trench, wherein the trench wall of the source trench includes a trench bottom and a sidewall, and the two fourth regions covering adjacent third regions are spaced apart; The gate is located in the gate trench; A first dielectric layer is located in the source trench and covers the sidewall of at least one sub-trench; A source contact structure is located in the source trench; The source electrode is located on the first surface; The drain electrode is located on the second surface.

[0009] Optionally, the source contact structure is electrically connected to the first region, and the potential of the source contact structure is equal to the potential of the first region; The thickness of the fourth region located on the sidewall of the sub-trench is less than the thickness of the well region.

[0010] Optionally, the source contact structure includes: An ohmic contact layer is located on the bottom surface of each sub-trench and on the surface of each first dielectric layer away from the sidewall of the sub-trench. A conductive filling layer is located in the source trench; the conductive filling layer is electrically connected to the source.

[0011] Optionally, the orthographic projection of the source trench on the second surface extends along a first direction; in the first direction, the source trench is formed by alternating arrangement of at least one first segment trench and at least one second segment trench. In the first section of the trench, the bottom and sidewalls of the sub-trench are provided with the third region; the surface of the last sub-trench near the second surface and the outer surface of each third region are respectively provided with a fourth region; In the second section of the trench, the fourth region is provided on the bottom and sidewalls of the sub-trench.

[0012] Optionally, the semiconductor body further includes a current spreading region and a drift region; The current extension region is configured with a first conductivity type and is located on the side of the well region away from the first surface; the drift region is configured with a first conductivity type and is located on the side of the current extension region away from the first surface; the ion doping concentration of the current extension region is greater than the ion doping concentration of the drift region. Both the gate trench and the source trench extend from the first surface to the second surface into the current extension region; and the depth of the source trench is greater than the depth of the gate trench.

[0013] Optionally, the semiconductor body further includes: The fifth region is configured as the second conductivity type and is located on the side of the source trench closer to the second surface; the surface of the fifth region away from the second surface is in contact with the fourth region.

[0014] Optionally, the semiconductor body further includes: The sixth region, configured as the second conductivity type, is located on the side of the fifth region closer to the second surface; the surface of the sixth region away from the second surface is in contact with the fifth region; The thickness of the sixth region is greater than the thickness of the fifth region.

[0015] Optionally, the semiconductor body further includes: Substrate: The first epitaxial layer, configured with a first conductivity type, is located on one side of the substrate; The second epitaxial layer, configured as a first semiconductor type, is located on the side of the first epitaxial layer away from the substrate; the ion doping concentration of the second epitaxial layer is greater than that of the first epitaxial layer. The drift region, the fifth region, and the sixth region are disposed in the first epitaxial layer; the current extension region, the first region, the well region, the third region, and the fourth region are disposed in the second epitaxial layer.

[0016] According to another aspect of this application, a method for fabricating a semiconductor device is provided, for fabricating the semiconductor device described in any embodiment of this application; comprising, A semiconductor body is formed, and a source trench and a gate trench are formed on a first surface of the semiconductor body. The semiconductor body is configured with a first conductivity type and includes a first surface and a second surface disposed opposite to each other. The semiconductor body also includes a well region and a first region. The first region is configured with a first conductivity type and is located on the first surface, and the well region is configured with a second conductivity type and is located on the side of the first region away from the first surface. The first conductivity type and the second conductivity type are different. The source trench includes at least one sub-trench. The semiconductor body also includes a plurality of third regions and a plurality of fourth regions. The third regions are configured with a first conductivity type, and the fourth regions are configured with a second conductivity type. The third regions are disposed on the trench wall of the source trench. The fourth regions cover the outer surface of the third regions, and their two ends are connected to the trench wall of the source trench. The trench wall of the source trench includes a trench bottom and a sidewall. The two fourth regions covering adjacent third regions are spaced apart. A gate is formed in the gate trench; A first dielectric layer is formed on the sidewall of at least one sub-trench in the source trench; A source contact structure is formed in the source trench; A source electrode is formed on the first surface; A drain electrode is formed on the second surface.

[0017] Optionally, forming a semiconductor body and forming a source trench and a gate trench on a first surface of the semiconductor body includes: Provide substrate; A first epitaxial layer is formed on one side of the substrate; the first epitaxial layer is configured with a first conductivity type; A second epitaxial layer is formed on the side of the first epitaxial layer away from the substrate; the second epitaxial layer is configured with a first conductivity type; the ion doping concentration of the second epitaxial layer is greater than that of the first epitaxial layer; At least two source trenches are formed on the surface of the second epitaxial layer away from the substrate; A first region is formed on the surface of the second epitaxial layer away from the substrate, and a well region is formed on the side of the first region close to the substrate; A third region is provided on the corner sidewall between each adjacent sub-groove, and a fourth region is formed on the outer surface of the third region. A source trench is formed on the surface of the second epitaxial layer away from the substrate; Gate trenches are formed between adjacent source trenches.

[0018] Optionally, at least two source trenches are formed on the surface of the second epitaxial layer away from the substrate, including: A first mask layer is formed on the side of the second epitaxial layer away from the substrate, and the first mask layer is patterned; the patterned first mask layer includes at least two first openings extending along a first direction and arranged along a second direction, the first openings exposing the surface of the second epitaxial layer; Based on the patterned first mask layer, at least two sub-grooves extending in the first direction and arranged in the second direction are formed in the region of the second epitaxial layer adjacent to the first epitaxial layer. Using the patterned first mask layer as a mask, multiple etching processes are performed sequentially within the second epitaxial layer to form multiple interconnected sub-trenches; wherein, before each etching process, a first barrier layer with a preset thickness is formed on the sidewall of the existing sub-trench to define a new etching area; Remove the first mask layer and the first barrier layer.

[0019] Optionally, forming a first region on the surface of the second epitaxial layer away from the substrate and forming a well region on the side of the first region closer to the substrate includes: An initial well region is formed on the surface of the second epitaxial layer on the side away from the substrate; A first region is formed on the surface of the initial well region on the side away from the substrate; the region outside the first region in the initial well region is used to form the well region. The third region is provided on the corner sidewall between each adjacent sub-groove, and a fourth region is formed on the outer surface of the third region, including: An initial fourth region is formed on the surface of the last-level sub-groove near the second surface and in the corner region between each adjacent sub-groove. A second barrier layer is formed on all the walls of the last-level sub-groove and on the sidewalls of each sub-groove on opposite sides outside the last-level sub-groove, and the second barrier layer located on the sidewalls covers the corners and part of the bottom surface of the sub-groove. Based on the second barrier layer, the third region is formed in the initial fourth region; the region outside the third region in the initial fourth region is used to form the fourth region.

[0020] Optionally, the orthographic projection of the source trench on the second surface extends along a first direction; in the first direction, the source trench includes at least one first segment trench and at least one second segment trench. An initial fourth region is formed on the surface of the last-level sub-groove near the second surface and at the corners between each adjacent sub-groove, including: The initial fourth region is formed by the surface of the last sub-groove in the first section of the trench near the second surface and the corner area between each adjacent sub-groove. The initial fourth region is formed by the surface of the last sub-groove in the first section of the trench near the second surface and the corner areas between each adjacent sub-groove, and also includes: The fourth region is formed by the surface of the last sub-groove in the second section trench near the second surface and the corner area between each adjacent sub-groove.

[0021] Optionally, before forming the gate in the gate trench, the method further includes: A second dielectric layer is formed on the trench wall of the gate trench; After forming the gate in the gate trench, the method further includes: An interlayer insulating layer is formed on the side of the gate away from the second surface; The first dielectric layer is formed on the sidewall of at least one sub-trench in the source trench, comprising: While forming a second dielectric layer on the wall of the gate trench, a first dielectric layer is formed on the wall of the source trench. Remove the first dielectric layer located at the bottom of each sub-trench; The formation of the source contact structure in the source trench includes: An ohmic contact layer is formed on the bottom surface of each sub-trench and on the surface of each first dielectric layer away from the sidewall of the sub-trench. A conductive filling layer is formed in the source trench, and the ohmic contact layer is located between the conductive filling layer and the trench wall of the source trench; the conductive filling layer is electrically connected to the source.

[0022] According to another aspect of this application, a power module is provided, including a substrate and at least one semiconductor device as described in any embodiment of this application, the substrate being used to support the semiconductor device.

[0023] According to another aspect of this application, a power conversion circuit is provided, which is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device as described in any embodiment of this application, the semiconductor device being electrically connected to the circuit board.

[0024] According to another aspect of this application, a vehicle is provided, including a load and a power conversion circuit as described in any embodiment of this application, the power conversion circuit being used to convert alternating current to direct current, convert alternating current to alternating current, convert direct current to direct current, or convert direct current to alternating current and then input the converted direct current to the load.

[0025] The technical solution provided in this application provides that the source trench includes at least one sub-trench, and a fourth region is provided on the sidewall and bottom of the source trench. This enables the fourth region to achieve a deeper vertical masking effect, thereby significantly reducing the electric field concentration at the corner of the gate trench and improving the reliability of the gate insulating layer. Furthermore, by setting a source contact structure in the source trench, setting a third region covered by a fourth region on the trench wall of the sub-trench, and forming a first dielectric layer on the sidewall of at least one sub-trench, at least one MCD (MOS Channel Diode) is integrated in the semiconductor device. Since the barrier of the MCD is smaller than that of the PN junction of the body diode, the on-state voltage drop (V_F) of the MCD is much lower than the voltage drop when the body diode (PN junction) is turned on. Therefore, during the freewheeling process, the MCD provides a low-resistance electronic current path in parallel with the body diode, forcing the freewheeling current to be mainly completed through the channel electron flow of the unipolar MCD, avoiding the injection and recombination of a large number of minority carriers (such as holes), effectively suppressing bipolar degradation; and when the diode is turned off, almost no or only a very small number of minority carriers need to be removed, thus significantly reducing the reverse recovery time. Furthermore, a fourth region is provided on the sidewall and bottom of the source trench. Since the conductivity type of the fourth region is different from that of the semiconductor body (drift region and / or current spread region) on the side of the gate trench near the second surface, the fourth region can reduce the concentration of the drift region and / or current spread region, thereby increasing the width of the depletion layer, thereby reducing the depletion capacitance, and further reducing the Miller capacitance (gate-drain capacitance Cgd) of the device, and reducing switching losses.

[0026] Based on this, the source contact structure is further configured to be electrically connected to the first region, and the potential of the source contact structure is equal to that of the first region. The thickness of the fourth region located on the sidewall of the sub-trench is less than the thickness of the well region, so that the MCD can also conduct when the semiconductor device is turned on, thereby allowing current shunting at the sidewall of the multi-level trench and reducing the total on-resistance of the device.

[0027] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in the prior art; Figure 2 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application; Figure 3 This is a top view of a portion of the structure of a semiconductor device provided in an embodiment of this application; Figure 4 yes Figure 3 A schematic diagram of the cross-sectional structure along line BB1 ​​shown. Figure 5 This is a schematic diagram of the structure of another semiconductor device provided in an embodiment of this application; Figure 6 This is a schematic diagram of the structure of another semiconductor device provided in an embodiment of this application; Figure 7 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of this application; Figure 8 This is a cross-sectional structural diagram corresponding to step S120 in a method for fabricating a semiconductor device provided in this application embodiment; Figure 9 This is a schematic cross-sectional view of the structure after a fifth region is formed on the surface of the first epitaxial layer in a method for fabricating a semiconductor device according to an embodiment of this application. Figure 10 This is a cross-sectional structural diagram corresponding to step S130 in a method for fabricating a semiconductor device provided in this application embodiment; Figure 11 This is a schematic cross-sectional view of step S1420 in a method for fabricating a semiconductor device provided in this application embodiment; Figures 12-13 This is a schematic cross-sectional view of step S1430 in a method for fabricating a semiconductor device provided in this application embodiment; Figure 14 This is a schematic cross-sectional view of step S1440 in a method for fabricating a semiconductor device provided in this application embodiment; Figure 15 This is a schematic cross-sectional view of step S1510 in a method for fabricating a semiconductor device provided in this application embodiment; Figure 16A schematic cross-sectional view of step S1530 in a method for fabricating a semiconductor device provided in this application embodiment; Figure 17 A schematic cross-sectional view of step S160 in a method for fabricating a semiconductor device provided in this application embodiment; Figure 18 This application provides a cross-sectional view of a semiconductor device fabrication method after forming a second dielectric layer and a gate in a gate trench. Figure 19 This application provides a cross-sectional view of a semiconductor device fabrication method after forming an interlayer insulating layer on the side of the gate away from the second surface. Figure 20 This application provides a schematic diagram of the cross-sectional structure of a semiconductor device fabrication method after a first dielectric layer is formed on the sidewalls and corners of each sub-trench in the source trench. Figure 21 This application provides a schematic cross-sectional view of a semiconductor device fabrication method after forming a source contact structure in a gate trench. Detailed Implementation

[0030] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0031] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0032] This application provides a semiconductor device. Figure 2 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application, with reference to... Figure 2 Semiconductor devices include: The semiconductor body 1, configured as a first conductivity type, includes a first surface 11 and a second surface 12 disposed opposite to each other. The semiconductor body 1 also includes a well region QJ and a first region Q1. The first region Q1 is configured as a first conductivity type and located on the first surface 11, while the well region QJ is configured as a second conductivity type and located on the side of the first region Q1 away from the first surface 11. The first conductivity type and the second conductivity type are different. The first surface 11 is provided with a gate trench and a source trench located on at least one side of the gate trench. The source trench includes at least one sub-trench. The semiconductor body 1 also includes a plurality of third regions Q3 and a plurality of fourth regions Q4. The third regions Q3 are configured as a first conductivity type, and the fourth regions Q4 are configured as a second conductivity type. The third regions Q3 are disposed on the trench wall of the source trench. The fourth regions Q4 cover the outer surface of the third regions Q3, and their two ends are connected to the trench wall of the source trench 80. The trench wall of the source trench includes a trench bottom and sidewalls. The two fourth regions Q4 covering adjacent third regions Q3 are spaced apart. Figure 2 As illustrated in the embodiments, the source trench is a multi-level trench including multiple sub-trenches, and a third region Q3 is correspondingly provided on the corner sidewall between each adjacent sub-trench; Gate G is located in the gate trench; The first dielectric layer 51 is located in the source trench and covers the sidewall of at least one sub-trench; The source contact structure 40 is located in the source trench; The source electrode S is located on the first surface 11; The drain electrode D is located on the second surface 12.

[0033] The technical solution provided in this application embodiment configures the source trench 80 to include at least one sub-trench, and provides a fourth region Q4 on the sidewall and bottom of the source trench 80. This design enables the fourth region Q4 to achieve a deeper vertical masking effect, thereby significantly reducing the electric field concentration at the corner of the gate trench and improving the reliability of the gate insulating layer. When the source trench is configured as a multi-level trench, a deeper vertical masking effect can be achieved, further improving the reliability of the gate insulating layer 50. Furthermore, by setting a source contact structure 40 in the source trench, setting a third region Q3 covered by a fourth region Q4 on the trench wall between the sub-trenches, and forming a first dielectric layer 51 on the sidewall of at least one sub-trench, at least one MCD is integrated in the semiconductor device. Since the barrier of the MCD is smaller than that of the PN junction of the body diode, the on-state voltage drop (V_F) of the MCD is much lower than the voltage drop when the body diode (PN junction) is turned on. Therefore, during the freewheeling process, the MCD provides a low-resistance electronic current path in parallel with the body diode, forcing the freewheeling current to be completed mainly through the channel electron flow of the unipolar MCD, avoiding the injection and recombination of a large number of minority carriers (such as holes), and effectively suppressing bipolar degradation. Moreover, when the diode is turned off, there are almost no or only a very small number of minority carriers that need to be removed, so the reverse recovery time can be greatly reduced. Figure 2 In the structure shown, a third region Q3 covered by a fourth region Q4 is provided in the corner region of each sub-trench, and a first dielectric layer 51 is formed on the sidewalls on opposite sides of each sub-trench, thereby integrating multiple MCDs in the semiconductor device, which can further suppress bipolar degradation and reduce reverse recovery time.

[0034] Furthermore, a fourth region Q4 is provided on the sidewall and bottom of the source trench. Since the conductivity type of the fourth region Q4 is different from that of the semiconductor body 1 (drift region 21 and / or current extension region 31) on the side of the gate trench 70 near the second surface 12, the fourth region Q4 can reduce the concentration of the drift region 21 and / or current extension region 31, thereby increasing the width of the depletion layer, reducing the depletion capacitance, and further reducing the Miller capacitance (gate-drain capacitance Cgd) of the device, thus reducing switching losses.

[0035] The above are the core inventive points of this application. The structure of the semiconductor device will be described in detail below with reference to the accompanying drawings.

[0036] The semiconductor body 1 can be formed by a single epitaxial layer or by multiple epitaxial layers. That is, the semiconductor body 1 can be a single semiconductor epitaxial layer or a stacked structure formed by multiple semiconductor epitaxial layers. The semiconductor body 1 may also include a substrate 10, that is, the semiconductor body 1 includes a substrate 10 and at least one semiconductor epitaxial layer formed on one side of the substrate 10.

[0037] The material of the substrate 10 can be the same as the material of the semiconductor epitaxial layer, or the material of the substrate 10 can be different from the material of the semiconductor epitaxial layer. In a specific embodiment of this application, both the material of the semiconductor epitaxial layer and the material of the substrate 10 can be SiC. Compared with silicon, SiC has a larger bandgap and advantages such as high breakdown electric field, high thermal conductivity, high electron saturation velocity, and strong radiation resistance. Therefore, semiconductor devices made of SiC can not only operate stably at higher temperatures, but are also suitable for high-voltage and high-frequency applications.

[0038] The semiconductor body 1 includes a first surface 11 and a second surface 12 disposed opposite to each other. When the semiconductor body 1 includes a substrate 10 and at least one semiconductor epitaxial layer, the second surface 12 is the surface of the substrate 10 away from the semiconductor epitaxial layer, and the first surface 11 is the surface of the semiconductor epitaxial layer that is furthest from the substrate 10 away from the substrate 10. Figure 2 The semiconductor body 1 in the structure shown includes: a substrate 10; a first epitaxial layer 20, configured as a first conductivity type, located on one side of the substrate 10; a second epitaxial layer 30, configured as a first semiconductor type, located on the side of the first epitaxial layer 20 away from the substrate 10; a second surface 12, which is the surface of the substrate 10 away from the semiconductor epitaxial layer; and a first surface 11, which is the surface of the second epitaxial layer 30 away from the substrate 10. The first region Q1, the well region QJ, the fourth region Q4, and the third region Q3 are all disposed on the second epitaxial layer 30.

[0039] Furthermore, the doping concentration of the first conductivity type doped ions in the second epitaxial layer 30 can be greater than the doping concentration of the first conductivity type ions in the first epitaxial layer 20. By setting the doping concentration of the first conductivity type ions to increase layer by layer, the on-resistance of the device can be further reduced. The semiconductor body 1 in this embodiment also includes a drift region 21 and a current extension region 31; the current extension region 31 is configured as the first conductivity type and is located on the side of the well region QJ away from the first surface 11; the drift region 21 is configured as the first conductivity type and is located on the side of the current extension region 31 away from the first surface 11; the ion doping concentration of the current extension region 31 is greater than the ion doping concentration of the drift region 21. The drift region 21 is disposed in the first epitaxial layer 20, and the current extension region 31 is disposed in the second epitaxial layer 30. Both the gate trench and the source trench extend from the first surface 11 to the second surface 12 into the current extension region 31, and the gap region of the first conductivity type between two adjacent fourth regions Q4 is the current extension region 31. Setting the depth of the source trench 80 to be greater than the depth of the gate trench 70 allows for a deeper vertical masking effect in the fourth region Q4, thereby significantly reducing the electric field concentration at the corner of the gate trench 70 and improving gate oxide reliability. In other embodiments of this application, the doping concentration of the first conductivity type doped ions in the second epitaxial layer 30 can also be equal to the doping concentration of the first conductivity type ions in the first epitaxial layer 20, in which case the region where the current extension region 31 is located in the second epitaxial layer 20 is replaced by a drift region.

[0040] The first conductivity type can be N-type and the second conductivity type can be P-type; or, the first conductivity type can be P-type and the second conductivity type can be N-type. Figure 2 In the structure shown, the semiconductor body 11 has an N-type conductivity. Therefore, the first region Q1 has an N-type conductivity and is located on the first surface 11; the first region Q1 is a heavily doped region. The well region QJ has a P-type conductivity and is located on the side of the first region Q1 away from the first surface 11. The current extension region 31 has an N-type conductivity and is located on the side of the well region QJ away from the first surface 11; the current extension region 31 can also be a heavily doped region. The drift region 21 has an N-type conductivity and is located on the side of the current extension region 31 away from the first surface 11; the drift region 21 can be a lightly doped region. The third region Q3 has an N-type conductivity and is located on the corner sidewall between each adjacent sub-trench; the third region Q3 is a heavily doped region, and its doping concentration can be the same as that of the first region Q1. The fourth region Q4 has a P-type conductivity and covers the outer surface of the third region Q3, with both ends extending to the trench walls covering the source trench 80; the doping concentration of the fourth region Q4 can be the same as that of the well region QJ. Optional, see reference Figure 2A fourth region Q4 can also be set on the side of the last-stage sub-trench near the second surface 12, thereby further increasing the depth of the fourth region Q4 in the device and enabling the fourth region Q4 to achieve a deeper longitudinal masking effect.

[0041] The first epitaxial layer 20 is an N-type semiconductor epitaxial layer, doped with N-type dopant ions. The second epitaxial layer 30 is also an N-type semiconductor epitaxial layer, doped with N-type dopant ions. The well region QJ and the fourth region Q4 are formed by implanting P-type dopant ions into the second epitaxial layer 30; the first region Q1 and the third region Q3 are formed by implanting N-type dopant ions into the second epitaxial layer 30. In semiconductors, when the same region is simultaneously doped with N-type dopant ions (donor dopant ions, such as phosphorus) and P-type dopant ions (acceptor dopant ions, such as boron), their effects interact through a "compensation effect." Specifically, the charge carriers (electrons and holes) of N-type and P-type dopant ions cancel each other out. Free electrons provided by N-type dopant ions fill the holes generated by P-type dopant ions, and ultimately the conductivity type of the material depends on the dopant concentration of the higher dopant. If the donor concentration (N-type dopant concentration) is greater than the acceptor concentration (P-type dopant concentration), the material behaves as an N-type semiconductor, with the remaining electrons being the majority carriers; if the acceptor concentration (P-type dopant concentration) is greater than the donor concentration (N-type dopant concentration), the material behaves as a P-type semiconductor, with the remaining holes being the majority carriers; if the two dopant concentrations are equal (perfectly compensated), the material will approach an intrinsic semiconductor with extremely low conductivity.

[0042] The gate trench contains a second dielectric layer 52 (i.e., a gate insulating layer) and a gate G. The second dielectric layer 52 can be made of silicon oxide, and the gate G can be made of polysilicon. The source trench contains a first dielectric layer 51 and a source contact structure 40. The first dielectric layer 51 can be made of silicon oxide, and the source contact structure 40 can be made of metal, for electrically connecting the source S and the third region Q3.

[0043] In this embodiment, the semiconductor device integrates a MOSFET, a body diode, and an MCD. The MOSFET consists of a first region Q1, a well region QJ, a current extension region 31, a drift region 21, a gate G, a source S, and a drain D within the semiconductor device. The body diode is a PN junction formed by the well region QJ and the current extension region 31 within the semiconductor device, with the anode at the source S and the cathode at the drain D. The MCD consists of a fourth region Q4, a third region Q3, a source contact structure, a first dielectric layer 51, a source S, and a drain D on the sidewalls of each sub-trench.

[0044] The forward conduction and reverse cutoff of the MCD and body diode depend on the MOSFET's operating state and the voltage polarity between the source and drain. When the MOSFET is fully off (gate-source voltage V...),... GS When the voltage is ≤ 0, the MOSFET's conductive channel is not formed, and the current (freewheeling current) can only conduct through the MCD. The forward conduction condition of the MCD is: when the source (S) voltage is higher than the drain (D) voltage, the body diode is forward biased, and the source voltage turns on the MCD. Because the barrier of the MCD is smaller than the barrier of the body diode's PN junction, the forward voltage drop (V_F) of the MCD is much lower than the voltage drop when the body diode (PN junction) is on. Therefore, during freewheeling, the MCD provides a low-resistance electron current path in parallel with the body diode, forcing the freewheeling current to mainly complete through the unipolar channel electron flow of the MCD, avoiding the injection and recombination of a large number of minority carriers (holes), effectively suppressing bipolar degradation. The reverse cutoff condition of the MCD and body diode is: when the drain (D) voltage is higher than the source (S) voltage, i.e., V_F... DS >0, the MCD is reverse-biased off, and the body diode is reverse-biased. When the MCD is reverse-biased off, almost no or only a very small number of minority carriers need to be removed, thus significantly reducing the reverse recovery time.

[0045] In trench-type MOS transistors, the gate-drain capacitance Cgd is typically composed of two parts connected in series: the gate oxide capacitance and the depletion capacitance. The gate oxide capacitance is determined by the thickness and dielectric constant of the gate oxide layer, connecting the gate G (polysilicon) to the underlying semiconductor surface. The depletion capacitance (barrier capacitance) is essentially the capacitive effect exhibited by the change in internal charge due to the change in the width of the depletion layer with voltage. A fourth region Q4 is provided on the sidewalls and bottom of the source trench. Since the conductivity type of the fourth region Q4 is different from that of the semiconductor body 1 (drift region 21 and / or current extension region 31) near the second surface 12 of the gate trench, the fourth region Q4 can reduce the concentration of the drift region 21 and / or current extension region 31, thereby increasing the width of the depletion layer, reducing the depletion capacitance, and consequently reducing the gate-drain capacitance Cgd of the device, thus reducing switching losses.

[0046] Based on the above embodiments, refer to Figure 2 Optionally, the two fourth regions Q4 covering adjacent third regions Q3 are isolated by a current spreading region 31 at the corner of the sub-trench. In other embodiments of this application, if the semiconductor body 1 does not have a current spreading region 31, the two fourth regions Q4 covering adjacent third regions Q3 are isolated by a drift region 21 at the corner of the sub-trench. Additionally, Figure 2The illustrated structure exemplifies the source trench 80, which includes three sub-trenches with gradually decreasing widths in the Z direction from the first surface 11 to the second surface 12. A third region Q3 is correspondingly provided on the corner sidewall between the first-level sub-trench and the second-level sub-trench, and on the corner sidewall between the second-level sub-trench and the third-level sub-trench.

[0047] Based on the above embodiments, optionally, the source contact structure 40 is electrically connected to the first region Q1, and the potential of the source contact structure 40 is equal to the potential of the first region Q1; the thickness of the fourth region Q4 located on the sidewall of the sub-trench is less than the thickness of the well region QJ.

[0048] Specifically, the source contact structure 40 is shorted to the first region Q1, making the potential of the source contact structure 40 equal to the potential of the first region Q1. When the MOSFET in the semiconductor device is turned on, since the potential of the first region Q1 relative to the source S is a small positive value, and the potential of the source contact structure 40 is equal to the potential of the first region Q1, the potential of the source contact structure 40 relative to the source S is also a small positive value. Moreover, since the thickness of the fourth region Q4 located on the sidewall of the sub-trench is less than the thickness of the well region QJ, the small positive potential on the source contact structure 40 can also cause the portion of the fourth region Q4 near the first dielectric layer 51 to form a reverse layer, i.e., form a channel, turn on the MCD, thereby allowing current shunting at the multi-level trench sidewalls and reducing the total on-resistance of the device. The method of shorting the source contact structure 40 to the first region Q1 is not limited in this application, as long as the potential of the source contact structure 40 is equal to the potential of the first region Q1.

[0049] Based on the above embodiments, refer to Figure 2 Optionally, the source contact structure 40 includes: Ohmic contact layer 41 is located on the bottom surface of each sub-trench and on the surface of each first dielectric layer 51 away from the sub-trench sidewall. The conductive filling layer 42 is located in the source trench 80; the conductive filling layer 42 is electrically connected to the source S.

[0050] Specifically, the materials of the ohmic contact layer 41 include, but are not limited to, nickel (Ni); the materials of the conductive filling layer 42 include, but are not limited to, tungsten (W). The key advantage of using nickel in the ohmic contact layer 41 is its ability to form a low-resistivity silicide with the semiconductor body 1 at the bottom of the sub-trench at low temperatures. This not only establishes excellent ohmic contact at all contact interfaces but also facilitates its coverage of the trench walls of each sub-trench level. The primary advantage of using tungsten in the conductive filling layer 42 is its excellent step coverage and high aspect ratio trench filling capability, enabling it to completely fill the complex multi-stage stepped source trench 80 without gaps, forming a dense and uniform bulk conductor. Tungsten has a high melting point and excellent electromigration resistance, allowing the filling layer to maintain long-term stability under high current density and high-temperature operating conditions, avoiding reliability degradation caused by metal electromigration.

[0051] Based on the above embodiments, Figure 3 This is a top view of a portion of the structure of a semiconductor device provided in an embodiment of this application. Figure 4 yes Figure 3 The diagram shows a cross-sectional view of the structure along line BB1. Figure 3 The cross-sectional view of the structure shown along line AA1 can be referenced. Figure 2 ,refer to Figures 2-4 Optionally, the orthographic projection of the source trench 80 on the second surface 12 extends along the first direction X; in the first direction X, the source trench 80 includes at least one first segment trench 81 and at least one second segment trench 82. In the first section trench 81, a third region Q3 is provided on the bottom and sidewalls of the sub-trench. When the source trench is a multi-stage trench, refer to... Figure 2 A third region Q3 is provided on the corner sidewall between each adjacent sub-groove; a fourth region Q4 is provided on the surface of the last sub-groove near the second surface 12 and on the outer surface of each third region Q3. In the second section trench 82, the bottom and sidewalls of the sub-trench are provided with the fourth region Q4, and adjacent fourth regions Q4 are continuously arranged. In the case of a multi-level source trench, refer to... Figure 4 A fourth region Q4 is provided on the surface of the last sub-groove near the second surface 12 and at the corner area between each adjacent sub-groove. In the second section trench 82 and the first section trench 81, the fourth region Q4 on the sub-trench at the same relative position can be set as a single unit.

[0052] Specifically, the third region Q3 located on the corner sidewall between every two adjacent sub-trenches is discontinuously arranged in the first direction X. This can be understood as follows: in the first direction X, the corner sidewall between every two adjacent sub-trenches includes multiple spaced-apart third regions Q3, and the region between two adjacent third regions Q3 is designated as the fourth region Q4. In the second segment trench 82 and the first segment trench 81, the fourth region Q4 on the same sidewall of the same level sub-trench is integrally formed. This can be understood as the fourth region Q4 on the sub-trenches in the second segment trench 82 and the first segment trench 81 at the same relative position being formed synchronously, thereby reducing the fabrication difficulty of semiconductor devices.

[0053] The technical solution provided in this application embodiment, by setting the third region Q3 on the bottom and sidewall of the sub-trench in the first segment trench 81, and the fourth region Q4 correspondingly set on the outer surface of each third region Q3, and the two fourth regions Q4 covering adjacent third regions Q3 are not discontinuously arranged; in the second segment trench 82, the surface of the last sub-trench near the second surface 12 and the corner area between each adjacent sub-trench are correspondingly set with a fourth region Q4, and the adjacent fourth regions Q4 can be continuously arranged or discontinuously arranged, so that at least one MCD is integrated at the bottom of the source trench 80 in some segments, which plays the role of shunting and improving the reverse recovery characteristics of parasitic diodes. The bottom of the source trench 80 in some segments is completely covered by the P+ region (fourth region Q4), thereby further enhancing the effect of weakening the electric field at the corner of the gate trench 70 and improving the reliability of the gate G insulating layer.

[0054] Based on the above embodiments, refer to Figures 2-4 Optionally, the semiconductor body 11 also includes: The fifth region Q5 is configured as the second conductivity type and is located on the side of the source trench close to the second surface 12; the surface of the fifth region Q5 away from the second surface 12 is in contact with the fourth region Q4.

[0055] Specifically, the fifth region Q5 can be disposed on the first epitaxial layer 20. The fifth region Q5 is disposed on the side of the last sub-trench near the second surface 12, and the surface of the fifth region Q5 away from the second surface 1212 contacts the fourth region Q4. The conductivity type of the fifth region Q5 is the same as that of the fourth region Q4. The fifth region Q5 can achieve a deeper vertical masking effect, thereby significantly reducing the electric field concentration at the corner of the gate trench 70 and improving the reliability of the gate insulating layer.

[0056] Based on the above embodiments, refer to Figure 5 and Figure 6Optionally, the semiconductor body 1 further includes multiple sixth regions Q6, configured as second conductivity types and located in the first epitaxial layer 20; the thickness of the sixth region Q6 is greater than the thickness of the fifth region Q5, and the sixth region Q6 is used to form a superjunction structure or a semi-superjunction structure. Figure 5 An example is shown where the sixth region Q6 is used to form a semi-superjunction structure. Figure 6 An exemplary illustration shows a sixth region Q6 used to form a superjunction structure, where Q6 is a heavily doped P+ region. The sixth region Q6 extends along direction Z. In the superjunction structure, Q6 extends throughout the entire drift region 21; in the semi-superjunction structure, Q6 extends from the fourth region Q4 towards the substrate 10, with a distance greater than zero from the substrate 10. By forming a semi-superjunction or superjunction structure in the first epitaxial layer 20, the breakdown voltage of the semiconductor device can be further improved. Furthermore, the contact between the sixth region Q6 and the fifth region Q5 can achieve a deeper vertical masking effect, thereby significantly reducing the electric field concentration at the corner of the gate trench 70 and improving the reliability of the gate G insulating layer.

[0057] Based on the above embodiments, refer to Figures 2-6 Optionally, the semiconductor device also includes an interlayer insulating layer 60 located between the source S and the gate G for electrically isolating the source S and the gate G.

[0058] This application also provides a method for fabricating a semiconductor device, used to prepare the semiconductor device described in any embodiment of this application. Figure 7 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of this application, see reference. Figure 7 The methods for fabricating semiconductor devices include: S10. A semiconductor body is formed, and a source trench and a gate trench are formed on a first surface of the semiconductor body. The semiconductor body is configured with a first conductivity type and includes a first surface and a second surface disposed opposite to each other. The semiconductor body also includes a well region and a first region. The first region is configured with a first conductivity type and is located on the first surface, and the well region is configured with a second conductivity type and is located on the side of the first region away from the first surface. The first conductivity type and the second conductivity type are different. The source trench includes at least one sub-trench. The semiconductor body also includes a plurality of third regions and a plurality of fourth regions. The third regions are configured with a first conductivity type, and the fourth regions are configured with a second conductivity type. The third regions are disposed on the trench wall of the source trench. The fourth regions cover the outer surface of the third regions, and their two ends are connected to the trench wall of the source trench. The trench wall of the source trench includes a trench bottom and a sidewall. The two fourth regions covering adjacent third regions are spaced apart.

[0059] S20. A gate is formed in the gate trench.

[0060] S30. A first dielectric layer is formed on the sidewall of at least one sub-trench in the source trench.

[0061] S40. A source contact structure is formed in the source trench.

[0062] S50, a source electrode is formed on the first surface.

[0063] S60, a drain electrode is formed on the second surface.

[0064] The technical solution provided in this application embodiment sets the source trench 80 to include at least one sub-trench, and sets a fourth region Q4 on the sidewall and bottom of the source trench 80. This design enables the fourth region Q4 to achieve a deeper vertical masking effect, thereby significantly reducing the electric field concentration at the corner of the gate trench 70 and improving the reliability of the gate G insulating layer. Furthermore, by providing a source contact structure 40 in the source trench 80, providing a third region Q3 covered by a fourth region Q4 on the trench wall of the sub-trench, and forming a first dielectric layer 51 on the sidewall of at least one sub-trench, at least one MCD is integrated in the semiconductor device. Since the barrier of the MCD is smaller than that of the PN junction of the body diode, the on-state voltage drop (V_F) of the MCD is much lower than the voltage drop when the body diode (PN junction) is turned on. Therefore, during the freewheeling process, the MCD provides a low-resistance electronic current path in parallel with the body diode, forcing the freewheeling current to be mainly completed through the channel electron flow of the unipolar MCD, avoiding the injection and recombination of a large number of minority carriers (such as holes), effectively suppressing bipolar degradation; and when the diode is turned off, almost no or only a very small number of minority carriers need to be removed, thus significantly reducing the reverse recovery time. Furthermore, a fourth region Q4 is provided on the sidewall and bottom of the source trench 80. Since the conductivity type of the fourth region Q4 is different from that of the semiconductor body 1 (drift region 21 and / or current extension region 31) on the side of the gate trench 70 near the second surface 12, the fourth region Q4 can reduce the concentration of the drift region 21 and / or current extension region 31, thereby increasing the width of the depletion layer, reducing the depletion capacitance, and further reducing the gate drain capacitance Cgd of the device, thus reducing the switching loss.

[0065] Step S10: Forming a semiconductor body, and forming a source trench and a gate trench on the first surface of the semiconductor body, including: S110, providing substrate 10.

[0066] S120, A first epitaxial layer 20 is formed on one side of the substrate 10; the first epitaxial layer 20 is configured as a first conductivity type.

[0067] For details, please refer to Figure 8The material of the substrate 10 and the material of the first epitaxial layer 20 may be the same or different. In the embodiments of this application, both the material of the substrate 10 and the material of the first epitaxial layer 20 may be SiC. The conductivity type of the first epitaxial layer 20 is the same as that of the substrate 10, for example, both are N-type. The N-type first epitaxial layer 20 is used to form the drift region 21 of the device.

[0068] Furthermore, the semiconductor body 1 also includes a fifth region Q5, configured as a second conductivity type and located on the side of the last-stage sub-trench near the second surface 12. (See reference) Figure 9 After forming the first epitaxial layer 20 on one side of the substrate 10, the method further includes forming a fifth region Q5 on the surface of the first epitaxial layer 20.

[0069] S130, a second epitaxial layer 30 is formed on the side of the first epitaxial layer 20 away from the substrate 10; the second epitaxial layer 30 is configured with a first conductivity type; the ion doping concentration of the second epitaxial layer 30 is greater than the ion doping concentration of the first epitaxial layer 20.

[0070] For details, please refer to Figure 10 The material of the second epitaxial layer 30 may be the same as or different from the material of the first epitaxial layer 20. In the embodiments of this application, the material of the second epitaxial layer 30 and the first epitaxial layer 20 are both SiC. The conductivity type of the first epitaxial layer 20 is the same as that of the second epitaxial layer 30. The concentration of N-type dopant ions in the second epitaxial layer 30 is greater than the concentration of N-type dopant ions in the first epitaxial layer 20.

[0071] S140, at least two source trenches 80 are formed on the surface of the second epitaxial layer 30 on the side away from the substrate 10.

[0072] Optionally, the step of forming at least two source trenches 80 on the surface of the second epitaxial layer 30 away from the substrate 10 includes: S1410, a first mask layer is formed on the side of the second epitaxial layer 30 away from the substrate 10, and the first mask layer is patterned; the patterned first mask layer includes at least two first openings extending along the first direction X and arranged along the second direction Y, the first openings exposing the surface of the second epitaxial layer 30, and the first direction X and the second direction Y intersect each other.

[0073] S1420. Based on the patterned first mask layer, at least two sub-grooves extending along the first direction X and arranged along the second direction Y are formed on the surface of the second epitaxial layer 30 away from the substrate 10.

[0074] For details, please refer to Figure 11The material of the first mask layer 100 can be silicon dioxide or silicon nitride. A plurality of first openings are formed in the first mask layer by an etching process. Based on the patterned first mask layer 100, at least two first-level sub-trenches 801 extending along the first direction X and arranged along the second direction Y are formed on the surface of the second epitaxial layer 30 away from the substrate 10 by an etching process.

[0075] S1430, using the patterned first mask layer 100 as a mask, multiple etching operations are performed in the second epitaxial layer 30 to form a source trench 80 with multiple interconnected sub-trenches; wherein, before each etching operation, a first barrier layer 91 with a preset thickness is formed on the sidewall of the existing sub-trench to define a new etching area.

[0076] For details, please refer to Figure 12 and Figure 13 An exemplary illustration shows two etching operations performed within the second epitaxial layer 30, using a patterned first mask layer 100 as a mask, to form a source trench 80 with three sub-trenches. (See reference...) Figure 12 Before forming the second-level sub-trench 802, a first barrier layer 91 of a predetermined thickness is formed on the sidewall of the first-level sub-trench 801, thereby defining the etching region of the second-level sub-trench 802; Reference Figure 13 Before forming the third-level sub-trench 803, a first barrier layer 91 with a predetermined thickness is formed on the sidewall of the second-level sub-trench 802, thereby defining the etching region of the third-level sub-trench 803. The material of the first barrier layer 91 can be silicon dioxide or silicon nitride.

[0077] S1440, Remove the first mask layer and the first barrier layer.

[0078] For details, please refer to Figure 14 The first mask layer 100 and the first barrier layer 91 can be removed by a wet etching process.

[0079] S150, a first region Q1 is formed on the surface of the second epitaxial layer 30 away from the substrate 10, and a well region QJ is formed on the side of the first region Q1 close to the substrate 10; a third region Q3 is formed on the corner sidewall between each adjacent sub-trench, and a fourth region Q4 is formed on the outer surface of each third region Q3 and on the side of the last sub-trench close to the second surface 12.

[0080] Optional, see reference Figure 15 and Figure 16Forming a first region Q1 on the surface of the second epitaxial layer 30 away from the substrate 10 and forming a well region QJ on the side of the first region Q1 close to the substrate 10 includes: forming an initial well region QJ0 on the surface of the second epitaxial layer 30 away from the substrate 10; forming a first region Q1 on the surface of the initial well region QJ0 away from the substrate 10; and using the region outside the first region Q1 in the initial well region QJ0 to form the well region QJ.

[0081] Optional, see reference Figure 15 and Figure 16 A third region Q3 is formed on the corner sidewall between each adjacent sub-groove, and a fourth region Q4 is formed on the outer surface of each third region Q3 and on the side of the last-level sub-groove near the second surface 12. This includes: forming an initial fourth region Q40 on the surface of the last-level sub-groove near the second surface 12 and in the corner region between each adjacent sub-groove; forming a second barrier layer 92 on all the groove walls of the last-level sub-groove and on the sidewalls of each sub-groove on opposite sides outside the last-level sub-groove, with the second barrier layer 92 on the sidewalls covering the groove corners and part of the bottom surface of the sub-groove; forming a third region Q3 in the initial fourth region Q40 based on the second barrier layer 92; and using the area outside the third region Q3 in the initial fourth region Q40 to form the fourth region Q4.

[0082] Optionally, the initial well region QJ0 and the initial fourth region Q40 can be formed simultaneously; the first region Q1 and the third region Q3 can be formed simultaneously. Therefore, step S150 specifically includes: S1510. An initial well region QJ0 is formed on the surface of the second epitaxial layer 30 away from the substrate 10 using an ion implantation process. Simultaneously, an initial fourth region Q40 is formed on the surface of the last-stage sub-trench near the second surface 12 and at the corner regions between each adjacent sub-trench. (Reference) Figure 15 ) S1520, A second barrier layer 92 is formed on all the walls of the last-level sub-groove and on the sidewalls of each sub-groove on opposite sides outside the last-level sub-groove, and the second barrier layer 92 located on the sidewalls covers the corners and part of the bottom surface of the sub-groove.

[0083] S1530, a first region Q1 is formed on the surface of the initial well region QJ0 away from the substrate 10, and a third region Q3 is formed in the initial fourth region Q40 based on the second barrier layer 92.

[0084] For details, please refer to Figure 16In the initial fourth region Q40 of the P-type structure, an N-type dopant ion is implanted to form a third region Q3. Because the implantation of the N-type dopant ions cancels out the charge carriers in the initial fourth region Q40, the initial fourth region Q40 located at the corner of the sub-trench shrinks inward towards the N-type dopant ion implantation region, thus breaking it off. This results in the fourth region Q4 being discontinuously positioned at the corner of the sub-trench. By utilizing the compensation and diffusion effects of the N-type dopant ions, multiple fourth regions Q4 are spaced apart, thereby simplifying the formation of an MCD in a semiconductor device.

[0085] Furthermore, regarding such Figure 3 The structure shown has a source trench 80 whose orthographic projection on the second surface 12 extends along the first direction X. In the first direction X, the source trench 80 is formed by alternating arrangement of at least one first segment trench 81 and at least one second segment trench 82. In the first segment trench 81, a third region Q3 is correspondingly provided on the corner sidewall between each adjacent sub-trench, and a fourth region Q4 is correspondingly provided on the surface of the last sub-trench near the second surface 12 and on the outer surface of each third region Q3. In the second segment trench 82, a fourth region Q4 is correspondingly provided on the surface of the last sub-trench near the second surface 12 and on the corner region between each adjacent sub-trench, and adjacent fourth regions Q4 are continuously arranged. In step S1510, an initial fourth region Q40 is formed on the surface of the last-stage sub-groove near the second surface 12 and at the corners between each adjacent sub-groove, including: The surface of the last sub-groove in the first section trench 81 near the second surface 12 and the corner areas between each adjacent sub-groove form the initial fourth region Q40; it also includes: The fourth region Q4 is formed by the last sub-groove in the second section 82 on the side near the second surface 12 and the corner area between each adjacent sub-groove.

[0086] In step S1530, forming a third region Q3 in the initial fourth region Q40 includes: forming a third region Q3 on the corner sidewall of an adjacent sub-ditch located in the first section trench 81.

[0087] S160, A gate trench 70 is formed between adjacent source trenches 80. (Reference) Figure 17 ) Optionally, before forming the gate G in the gate trench 70, step S20 further includes forming a second dielectric layer 52 on the sidewalls and bottom surface of the gate trench 70; the material of the second dielectric layer 52 may be silicon oxide. (Reference) Figure 18 ) After forming the gate G in the gate trench 70, step S20 further includes forming an interlayer insulating layer 60 on the surface of the gate G away from the substrate 10; the material of the interlayer insulating layer 60 may be silicon oxide. (Reference) Figure 19 ) Optionally, step S30 involves forming a first dielectric layer 51 on the sidewall of at least one sub-trench in the source trench 80, including: While a second dielectric layer 52 is formed on the wall of the gate trench 70, a first dielectric layer 51 is formed on the wall of the source trench 80; (Reference) Figure 17 ) After removing the polysilicon material from the source trench 80, the first dielectric layer 51 located at the bottom surface of each sub-trench is removed. (Reference) Figure 20 ) Optional, see reference Figure 21 Step S40, which involves forming the source contact structure 40 in the source trench 80, includes: An ohmic contact layer 41 is formed on the bottom surface of each sub-trench and on the surface of each first dielectric layer 51 away from the sub-trench sidewall; the material of the ohmic contact layer 41 includes Ni. A conductive filling layer 42 is formed in the source trench 80, and an ohmic contact layer 41 is located between the conductive filling layer 42 and the trench wall of the source trench 80; the material of the conductive filling layer 42 includes tungsten.

[0088] Embodiments of this application also provide a power module, including a substrate and at least one semiconductor device as described in any embodiment of this application, wherein the substrate is used to support the semiconductor device. It has the same technical effects and will not be described again here.

[0089] According to another aspect of this application, a power conversion circuit is provided, which is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device as described in any embodiment of this application, wherein the semiconductor device is electrically connected to the circuit board. It has the same technical effects and will not be described again here.

[0090] According to another aspect of this application, a vehicle is provided, including a load and a power conversion circuit as described in any embodiment of this application, the power conversion circuit being used to convert alternating current to direct current, convert alternating current to alternating current, convert direct current to direct current, or convert direct current to alternating current and then input the converted direct current to the load. It has the same technical effects and will not be described again here.

[0091] Note that the above are merely preferred embodiments and the technical principles employed in this application. Those skilled in the art will understand that this application is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of this application. Therefore, although this application has been described in detail through the above embodiments, this application is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of this application, the scope of which is determined by the scope of the appended claims.

Claims

1. A semiconductor device, characterized in that, include: A semiconductor body, configured with a first conductivity type, includes a first surface and a second surface disposed opposite to each other; the semiconductor body further includes a well region and a first region; the first region is configured with a first conductivity type and is located on the first surface, the well region is configured with a second conductivity type and is located on the side of the first region away from the first surface, and the first conductivity type and the second conductivity type are different; The first surface is provided with a gate trench and a source trench, wherein the source trench includes at least one sub-trench; The semiconductor body further includes a plurality of third regions and a plurality of fourth regions, wherein the third regions are configured with a first conductivity type and the fourth regions are configured with a second conductivity type; the third regions are disposed on the trench wall of the source trench; the fourth regions cover the outer surface of the third regions and their two ends are connected to the trench wall of the source trench, wherein the trench wall of the source trench includes a trench bottom and a sidewall, and the two fourth regions covering adjacent third regions are spaced apart. The gate is located in the gate trench; A first dielectric layer is located in the source trench and covers the sidewall of at least one sub-trench; A source contact structure is located in the source trench; The source electrode is located on the first surface; The drain electrode is located on the second surface.

2. The semiconductor device according to claim 1, characterized in that, The source contact structure is electrically connected to the first region, and the potential of the source contact structure is equal to the potential of the first region; The thickness of the fourth region located on the sidewall of the sub-trench is less than the thickness of the well region.

3. The semiconductor device according to claim 1, characterized in that, The source contact structure includes: An ohmic contact layer is located on the bottom surface of each sub-trench and on the surface of each first dielectric layer away from the sidewall of the sub-trench. A conductive filling layer is located in the source trench; the conductive filling layer is electrically connected to the source.

4. The semiconductor device according to claim 1, characterized in that, The orthographic projection of the source trench on the second surface extends along a first direction; in the first direction, the source trench includes at least one first segment trench and at least one second segment trench. In the first section of the trench, the third region is provided on the bottom and sidewalls of the sub-trench; In the second section of the trench, the fourth region is provided on the bottom and sidewalls of the sub-trench.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that, The semiconductor body also includes a current spreading region and a drift region; The current extension region is configured with a first conductivity type and is located on the side of the well region away from the first surface; the drift region is configured with a first conductivity type and is located on the side of the current extension region away from the first surface; the ion doping concentration of the current extension region is greater than the ion doping concentration of the drift region. Both the gate trench and the source trench extend from the first surface to the second surface into the current extension region; and the depth of the source trench is greater than the depth of the gate trench.

6. The semiconductor device according to claim 5, characterized in that, The semiconductor body also includes: The fifth region is configured as the second conductivity type and is located on the side of the source trench closer to the second surface; the surface of the fifth region away from the second surface is in contact with the fourth region.

7. The semiconductor device according to claim 6, characterized in that, The semiconductor body also includes: The sixth region, configured as the second conductivity type, is located on the side of the fifth region closer to the second surface; the surface of the sixth region away from the second surface is in contact with the fifth region; The thickness of the sixth region is greater than the thickness of the fifth region.

8. The semiconductor device according to claim 7, characterized in that, The semiconductor body also includes: Substrate: The first epitaxial layer, configured with a first conductivity type, is located on one side of the substrate; The second epitaxial layer, configured as a first semiconductor type, is located on the side of the first epitaxial layer away from the substrate; the ion doping concentration of the second epitaxial layer is greater than that of the first epitaxial layer. The drift region, the fifth region, and the sixth region are disposed in the first epitaxial layer; the current extension region, the first region, the well region, the third region, and the fourth region are disposed in the second epitaxial layer.

9. A method for fabricating a semiconductor device, characterized in that, Used to prepare the semiconductor device according to any one of claims 1 to 8; include, A semiconductor body is formed, and a source trench and a gate trench are formed on a first surface of the semiconductor body. The semiconductor body is configured with a first conductivity type and includes a first surface and a second surface disposed opposite to each other. The semiconductor body also includes a well region and a first region. The first region is configured with a first conductivity type and is located on the first surface, and the well region is configured with a second conductivity type and is located on the side of the first region away from the first surface. The first conductivity type and the second conductivity type are different. The source trench includes at least one sub-trench. The semiconductor body also includes a plurality of third regions and a plurality of fourth regions. The third regions are configured with a first conductivity type, and the fourth regions are configured with a second conductivity type. The third regions are disposed on the trench wall of the source trench. The fourth regions cover the outer surface of the third regions, and their two ends are connected to the trench wall of the source trench. The trench wall of the source trench includes a trench bottom and a sidewall. The two fourth regions covering adjacent third regions are spaced apart. A gate is formed in the gate trench; A first dielectric layer is formed on the sidewall of at least one sub-trench in the source trench; A source contact structure is formed in the source trench; A source electrode is formed on the first surface; A drain electrode is formed on the second surface.

10. The method for fabricating a semiconductor device according to claim 9, characterized in that, The process of forming a semiconductor body and forming a source trench and a gate trench on a first surface of the semiconductor body includes: Provide substrate; A first epitaxial layer is formed on one side of the substrate; the first epitaxial layer is configured with a first conductivity type; A second epitaxial layer is formed on the side of the first epitaxial layer away from the substrate; the second epitaxial layer is configured with a first conductivity type; the ion doping concentration of the second epitaxial layer is greater than that of the first epitaxial layer; At least two source trenches are formed on the surface of the second epitaxial layer away from the substrate; A first region is formed on the surface of the second epitaxial layer away from the substrate, and a well region is formed on the side of the first region close to the substrate; A third region is provided on the corner sidewall between each adjacent sub-groove, and a fourth region is formed on the outer surface of the third region. A source trench is formed on the surface of the second epitaxial layer away from the substrate; Gate trenches are formed between adjacent source trenches.

11. The method for fabricating a semiconductor device according to claim 10, characterized in that, At least two source trenches are formed on the surface of the second epitaxial layer on the side away from the substrate, including: A first mask layer is formed on the side of the second epitaxial layer away from the substrate, and the first mask layer is patterned; the patterned first mask layer includes at least two first openings extending along a first direction and arranged along a second direction, the first openings exposing the surface of the second epitaxial layer; Based on the patterned first mask layer, at least two sub-grooves extending in the first direction and arranged in the second direction are formed in the region of the second epitaxial layer adjacent to the first epitaxial layer. Using the patterned first mask layer as a mask, multiple etching processes are performed sequentially within the second epitaxial layer to form multiple interconnected sub-trenches; wherein, before each etching process, a first barrier layer with a preset thickness is formed on the sidewall of the existing sub-trench to define a new etching area; Remove the first mask layer and the first barrier layer.

12. The method for fabricating a semiconductor device according to claim 10, characterized in that, The formation of a first region on the surface of the second epitaxial layer away from the substrate and the formation of a well region on the side of the first region closer to the substrate include: An initial well region is formed on the surface of the second epitaxial layer on the side away from the substrate; A first region is formed on the surface of the initial well region on the side away from the substrate; the region outside the first region in the initial well region is used to form the well region. The third region is provided on the corner sidewall between each adjacent sub-groove, and a fourth region is formed on the outer surface of the third region, including: An initial fourth region is formed on the surface of the last-level sub-groove near the second surface and in the corner region between each adjacent sub-groove. A second barrier layer is formed on all the walls of the last-level sub-groove and on the sidewalls of each sub-groove on opposite sides outside the last-level sub-groove, and the second barrier layer located on the sidewalls covers the corners and part of the bottom surface of the sub-groove. Based on the second barrier layer, the third region is formed in the initial fourth region; the region outside the third region in the initial fourth region is used to form the fourth region.

13. The method for fabricating a semiconductor device according to claim 12, characterized in that, The orthographic projection of the source trench on the second surface extends along a first direction; in the first direction, the source trench includes at least one first segment trench and at least one second segment trench. An initial fourth region is formed on the surface of the last-level sub-groove near the second surface and at the corners between each adjacent sub-groove, including: The initial fourth region is formed by the surface of the last sub-groove in the first section of the trench near the second surface and the corner area between each adjacent sub-groove. The initial fourth region is formed by the surface of the last sub-groove in the first section of the trench near the second surface and the corner areas between each adjacent sub-groove, and also includes: The fourth region is formed by the surface of the last sub-groove in the second section trench near the second surface and the corner area between each adjacent sub-groove.

14. The method for fabricating a semiconductor device according to claim 13, characterized in that, Before forming the gate in the gate trench, the method further includes: A second dielectric layer is formed on the trench wall of the gate trench; After forming the gate in the gate trench, the method further includes: An interlayer insulating layer is formed on the side of the gate away from the second surface; The first dielectric layer is formed on the sidewall of at least one sub-trench in the source trench, comprising: While forming a second dielectric layer on the wall of the gate trench, a first dielectric layer is formed on the wall of the source trench. Remove the first dielectric layer located at the bottom of each sub-trench; The formation of the source contact structure in the source trench includes: An ohmic contact layer is formed on the bottom surface of each sub-trench and on the surface of each first dielectric layer away from the sidewall of the sub-trench. A conductive filling layer is formed in the source trench, and the ohmic contact layer is located between the conductive filling layer and the trench wall of the source trench; the conductive filling layer is electrically connected to the source.

15. A power module, characterized in that, It includes a substrate and at least one semiconductor device as described in any one of claims 1 to 8, wherein the substrate is used to support the semiconductor device.

16. A power conversion circuit, characterized in that, The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device as described in any one of claims 1 to 8, wherein the semiconductor device is electrically connected to the circuit board.

17. A vehicle, characterized in that, The device includes a load and a power conversion circuit as described in claim 16, the power conversion circuit being used to convert AC power to DC power, convert AC power to AC power, convert DC power to DC power, or convert DC power to AC power and then input it to the load.

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