A high voltage MOS device and a method of manufacturing the same

Abstract

A high-voltage MOS device and a manufacturing method thereof, the device comprising: a semiconductor substrate having a first conductivity type; a gate structure on the semiconductor substrate; a source region and a drain region in the semiconductor substrate on two sides of the gate structure along a first direction, the source region and the drain region having a second conductivity type opposite to the first conductivity type; a first well region in the semiconductor substrate below the gate structure, the first well region having the first conductivity type, the first well region being spaced apart from at least one of the source region and the drain region to form a low-doped region between the first well region and the source region and / or between the first well region and the drain region, the low-doped region being composed of the semiconductor substrate. The application can simplify the manufacturing process while ensuring the withstand voltage.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically to a high-voltage MOS device and its manufacturing method. Background Technology

[0002] With the widespread application of embedded flash memory technology in microcontrollers, automotive electronics, and secure storage, flash memory chips, in addition to low-voltage logic devices, also need to integrate high-voltage MOS devices for memory cell programming, erasing, and high-voltage signal transmission. These high-voltage MOS devices typically need to operate under high drain-source voltage conditions, thus placing high demands on their voltage withstand performance.

[0003] In existing technologies, to increase the breakdown voltage of high-voltage MOS devices, taking high-voltage NMOS devices as an example, a high-voltage N-type drift region is typically introduced between the channel region and the source / drain. This high-voltage drift region can effectively extend the depletion region width and reduce the local electric field peak at the drain, thereby improving the device's breakdown voltage capability. However, the introduction of HV NDrift often requires customized additional photomasks and corresponding photolithography, ion implantation, and other process steps, which not only increases manufacturing costs but also makes the process flow more complex.

[0004] Furthermore, the voltage withstand requirements of flash memory devices for high-voltage MOS transistors typically have well-defined application boundaries. For example, in programming and erasing operations, only specific high-voltage reliability requirements need to be met, and higher breakdown voltages are not necessarily pursued. Therefore, how to reduce the number of photomasks and process flows required in the manufacturing process of high-voltage MOS transistors while meeting the voltage withstand performance requirements of flash memory high-voltage operations, thereby reducing manufacturing costs, is a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0005] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. This summary section is not intended to limit the key and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0006] To address the existing problems, this application provides a high-voltage MOS device, comprising: A semiconductor substrate having a first conductivity type; The gate structure located on the semiconductor substrate; A source region and a drain region are disposed on both sides of the gate structure in the semiconductor substrate along a first direction, and the source region and the drain region have a second conductivity type, which is opposite to the first conductivity type; A first well region located in the semiconductor substrate below the gate structure, the first well region having the first conductivity type, the first well region being spaced apart from at least one of the source region and the drain region to form a low-doped region between the first well region and the source region and / or between the first well region and the drain region, the low-doped region being formed by the semiconductor substrate.

[0007] In one embodiment, the dimension of the first well region along the first direction is 45%-65% of the dimension of the gate structure along the first direction.

[0008] In one embodiment, the first well region is spaced apart from the source region and the drain region, and the distance between the first well region and the source region is equal to the distance between the first well region and the drain region.

[0009] In one embodiment, the first well region is located near the source region and is spaced apart from the drain region.

[0010] In one embodiment, the source region and / or the drain region are spaced apart from the gate structure.

[0011] In one embodiment, the high-voltage MOS device further includes: A shallow trench isolation structure is disposed in the semiconductor substrate, the shallow trench isolation structure being used to isolate adjacent high-voltage MOS devices; A second well region is disposed below the shallow trench isolation structure, the second well region having the first conductivity type.

[0012] In one embodiment, the high-voltage MOS device does not include a drift region located between the source region or the drain region and the channel region.

[0013] Another aspect of this application provides a method for manufacturing a high-voltage MOS device, the method comprising: A semiconductor substrate is provided, the semiconductor substrate having a first conductivity type; Ion implantation of a first conductivity type is performed on the semiconductor substrate to form a first well region in the semiconductor substrate; A gate structure is formed on the semiconductor substrate, the gate structure being located above the first well region; The semiconductor substrate is subjected to ion implantation of a second conductivity type to form a source region and a drain region disposed on both sides of the gate structure along a first direction in the semiconductor substrate. The second conductivity type is opposite to the first conductivity type. At least one of the source region and the drain region is spaced apart from the first well region to form a low-doped region between the first well region and the source region and / or between the first well region and the drain region, wherein the low-doped region is formed by the semiconductor substrate.

[0014] In one embodiment, the first well region is spaced apart from the source region and the drain region, and the distance between the first well region and the source region is equal to the distance between the first well region and the drain region.

[0015] In one embodiment, the first well region is located near the source region and is spaced apart from the drain region.

[0016] In one embodiment, the source region and / or the drain region are spaced apart from the gate structure.

[0017] In one embodiment, prior to ion implantation of the semiconductor substrate of a first conductivity type, the method further includes: A shallow trench isolation structure is formed in the semiconductor substrate, the shallow trench isolation structure being used to isolate adjacent high-voltage MOS devices; The first type of conductivity ion implantation is also used to form a second well region below the shallow trench isolation structure, the depth of the second well region being less than the depth of the first well region.

[0018] According to the high-voltage MOS device and its manufacturing method provided in the embodiments of this application, by setting the first well region and the source region and / or drain region separately, the low-doped region composed of semiconductor substrate is depleted under high voltage bias, effectively expanding the width of the lateral depletion region, reducing the electric field peak of the overlapping area between the gate edge and the source region and / or drain region, thereby enabling the breakdown voltage to meet the high-voltage operation requirements of flash memory without the need to add additional photomasks and injection processes, while reducing manufacturing costs and process steps. Attached Figure Description

[0019] The following drawings, which are incorporated herein by reference and are used to understand this application, illustrate embodiments of the invention and their descriptions to explain the principles of the invention.

[0020] In the attached image: Figure 1 A cross-sectional view of a high-voltage MOS device in the related art is shown; Figure 2 A schematic flowchart illustrating a method for manufacturing a high-voltage MOS device according to an embodiment of this application is shown; Figures 3A-3D A cross-sectional view of a high-voltage MOS device during the implementation of a manufacturing method for a high-voltage MOS device according to an embodiment of this application is shown. Figures 4-6 A cross-sectional view of a high-voltage MOS device according to an embodiment of this application is shown; Figure 7 The following is a simulation comparison diagram of the breakdown voltage of high-voltage MOS devices according to the embodiments of this application and those of the prior art; Figure 8 The diagram shows the leakage current characteristic curves between adjacent high-voltage MOS devices in an embodiment of this application. Detailed Implementation

[0021] The following description provides numerous specific details to offer a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described to avoid confusion with this application.

[0022] It should be understood that this application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of this application to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0023] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0024] Spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0025] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0026] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solutions proposed in this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0027] like Figure 1 As shown, a high-voltage MOS device structure of the related technology is illustrated. The high-voltage MOS device includes: a P-type semiconductor substrate (Psub) 100; a P-type well region (PW) 101 covering the active region; a gate structure 102 located above the P-type well region 101; an N-type doped source region (S) 103 and a drain region (D) 104 respectively disposed on both sides of the gate structure 102; and a high-voltage N-type drift region (HV NDrift) 105 located between the channel region and the source region 103 and the drain region 104.

[0028] The high-voltage N-type drift region 105 improves the device's breakdown voltage by expanding the depletion region width and reducing the peak local electric field at the drain end. However, the introduction of the high-voltage N-type drift region 105 requires customized additional masks and corresponding photolithography, ion implantation, and other process steps, which not only increases manufacturing costs but also makes the process flow more complex.

[0029] For flash memory devices, high-voltage operation has clear application boundaries for voltage withstand performance (e.g., typically requiring no less than 11.5V), and higher breakdown voltage is not necessarily pursued. Therefore, how to reduce the number of photomasks, simplify the process flow, and reduce manufacturing costs while meeting the high-voltage operation withstand requirements of flash memory has become an urgent technical problem to be solved in this field.

[0030] To address the aforementioned issues, this application provides a high-voltage MOS device and its manufacturing method. It should be noted that in semiconductor devices, NMOS devices use electrons as charge carriers, while PMOS devices use holes. Since electron mobility is much higher than hole mobility, NMOS devices can provide a larger drive current under the same size conditions; or, for the same drive current requirement, NMOS devices are smaller, thus saving chip area. Furthermore, in embedded flash memory processes, NMOS devices have better compatibility with standard CMOS logic processes and superior conduction characteristics. Therefore, the high-voltage MOS device of this application is preferably a high-voltage NMOS device. In this case, the first conductivity type is defined as P-type, corresponding to the conductivity type of the semiconductor substrate, the first well region, and the second well region; the second conductivity type is defined as N-type, corresponding to the conductivity type of the source and drain regions. The following embodiments are described using this conductivity type correspondence. It should be noted that this application also applies to high-voltage PMOS devices; in this case, only the first and second conductivity types need to be interchanged.

[0031] Below, first refer to Figure 2 and Figures 3A to 3D The fabrication method of the high-voltage MOS device in this embodiment is described in detail.

[0032] First, execute step S201, such as Figure 3A As shown, a semiconductor substrate 300 is provided, which has a first conductivity type.

[0033] The semiconductor substrate 300 can be a silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, or a compound semiconductor substrate (such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, etc.). In this embodiment, the semiconductor substrate 300 is a p-type single-crystal silicon substrate.

[0034] Next, a shallow trench isolation structure 301 is formed in the semiconductor substrate 300. The shallow trench isolation structure 301 is used to isolate adjacent high-voltage MOS devices, and it is located between the source region of one high-voltage MOS device and the drain region of another high-voltage MOS device.

[0035] For example, firstly, a thin pad oxide layer is formed on the surface of the semiconductor substrate 300 using a thermal oxidation process to alleviate stress between the subsequently deposited silicon nitride layer and the substrate. Then, a pad silicon nitride layer is deposited on the pad oxide layer using a low-pressure chemical vapor deposition (LPCVD) process as a stop layer for subsequent chemical mechanical polishing (CMP). A shallow trench isolation structure (STI) pattern is defined on the pad silicon nitride layer using a photolithography process, i.e., using photoresist as a mask to expose the areas where isolation trenches need to be formed. Then, a reactive ion etching (RIE) process is used to sequentially etch the pad silicon nitride layer, the pad oxide layer, and the semiconductor substrate to form trenches in the semiconductor substrate.

[0036] Next, after removing the photoresist, an insulating material, preferably silicon dioxide, is deposited in the trenches and on the entire substrate surface using high-density plasma chemical vapor deposition (HDP-CVD). HDP-CVD allows for simultaneous deposition and etching, enabling void-free trench filling. Then, the deposited insulating material is planarized using chemical mechanical polishing (CMP), with a silicon nitride layer as a stop layer, to remove the insulating material outside the trenches, leaving only the insulating material inside the trenches.

[0037] Finally, the pad silicon nitride layer is removed by wet etching (e.g., using a hot phosphoric acid solution), and then the pad oxide layer is removed by dilute hydrofluoric acid (DHF) solution, exposing the active region surface of the semiconductor substrate 300, forming the final shallow trench isolation structure 301. At this point, the top of the shallow trench isolation structure 301 can be slightly higher than the surface of the semiconductor substrate 300, or it can be flush with the surface of the semiconductor substrate 300.

[0038] Next, proceed to step S202, as follows: Figure 3B As shown, ion implantation of a first conductivity type is performed on the semiconductor substrate 300 to form a first well region 302 in the semiconductor substrate.

[0039] In this embodiment, the first well region 302 does not cover the entire active region as in the prior art. Instead, the opening size of the mask is optimized so that its size along the first direction is smaller than the size of the active region along the first direction. This creates a low-doped region between the first well region 302 and the subsequently formed source region and / or between the first well region 302 and the subsequently formed drain region. This low-doped region is composed of the semiconductor substrate 300, and its doping concentration is equal to the original doping concentration of the semiconductor substrate 300, significantly lower than the doping concentration of the first well region 302.

[0040] When the high-voltage MOS device is operating, a high voltage is applied to the drain region 306, while the source region 305 is grounded. The low-doped region between the first well region 302 and the drain region 306 forms a PN junction with the drain region (N+), which is reverse biased. Due to the extremely low doping concentration in the low-doped region, the depletion region expands significantly in this region, effectively increasing the width of the lateral depletion region. The increased width of the lateral depletion region makes the electric field distribution from the drain region to the channel direction more gradual, effectively reducing the peak electric field in the overlapping area between the gate edge and the drain region, thereby improving the breakdown voltage of the device.

[0041] In such Figure 1 In the prior art shown, to improve the withstand voltage performance, an additional dedicated ion implantation process is required between the channel region and the source or drain region to form a high-voltage N-type drift region (HV NDrift) 105. This requires adding a dedicated photomask and corresponding photolithography and implantation steps, increasing manufacturing costs and process complexity. However, the embodiments of this application achieve a withstand voltage performance sufficient to meet design requirements without introducing any N-type drift region.

[0042] like Figure 7 As shown in the simulation, the breakdown voltage of the high-voltage MOS device using the embodiment of this application can reach about 11.9V. Although it is lower than that of the high-voltage MOS device with HV NDrift, it can stably meet the design requirement of high voltage operation of flash memory devices for withstand voltage performance of not less than 11.5V. In contrast, the breakdown voltage of the device that simply removes HV NDrift but does not optimize the PW structure is only 10.6V, which cannot meet the requirements.

[0043] For example, in a practical layout, adjacent high-voltage MOS devices are typically isolated only by a shallow trench isolation structure 301. During operation, when a voltage is applied to the drain of one of the high-voltage NMOS devices, the electric field may extend to adjacent devices through the semiconductor region beneath the shallow trench isolation structure 301, thereby introducing parasitic leakage paths. To address this problem, the ion implantation process of this embodiment simultaneously forms a second well region 303 beneath the shallow trench isolation structure 301. The second well region 303 can form an effective depletion isolation region under high-voltage conditions, thereby suppressing leakage between adjacent high-voltage MOS devices and improving the isolation performance between devices.

[0044] Figure 8 The diagram shows the IV characteristic curves between adjacent high-voltage NMOS devices after a second well region 303 is introduced below the shallow trench isolation structure 301. The curves demonstrate that the second well region 303 significantly suppresses leakage current between adjacent NMOS devices, achieving effective isolation between high-voltage devices.

[0045] For example, since the shallow trench isolation structure 301 and the non-shallow trench isolation structure 301 have different blocking capabilities for ion implantation, the shallow trench isolation structure 301 has a stronger ion blocking capability, resulting in the depth of the second well region 303 being less than the depth of the first well region 302.

[0046] In this step, boron (B) is used as the P-type dopant ion. The boron ion implantation dose and energy can be designed based on the target well depth and doping concentration. For example, the ion implantation energy is 250 keV and the implantation dose is 1.0 × 10⁻⁶. 12 cm -2 Up to 3.0×10 13 cm -2 The implantation dose and doping concentration are less than those in the source / drain regions. The implantation angle is perpendicular to the surface of the semiconductor substrate at 30°. Multiple ion implantations with decreasing doping concentration and implantation dose can be performed to form a uniform doping distribution. After implantation, annealing can be performed to activate the implanted impurity ions and repair lattice damage.

[0047] Next, proceed to step S203, as follows: Figure 3C As shown, a gate structure 304 is formed on the surface of a semiconductor substrate. The gate structure 304 is located above a first well region 302. The dimension of the gate structure 304 along a first direction is larger than the dimension of the first well region 302 along the first direction, and the first direction is perpendicular to the extension direction of the gate structure 304. For example, the dimension of the first well region 302 along the first direction is 45%-65% of the dimension of the gate structure 304 along the first direction.

[0048] For example, the method of forming the gate structure 304 includes: firstly forming a gate dielectric layer 3041 on a semiconductor substrate. The gate dielectric layer 3041 can be formed by thermal oxidation process, chemical vapor deposition process or atomic layer deposition process, and its material can be silicon oxide, silicon oxynitride or high-k dielectric material.

[0049] Then, a gate electrode layer 3042 is formed on the gate dielectric layer 3041. Specifically, a polysilicon layer, a metal layer, or a combination thereof is deposited, and a patterned mask layer is formed thereon. The gate electrode layer 3042 and the gate dielectric layer 3041 are etched using the patterned mask layer as a mask. Afterward, the patterned mask layer is removed.

[0050] Next, a gate sidewall 3043 is formed on the sidewalls of the gate electrode layer 3042 and the gate dielectric layer 3041. Specifically, a sidewall material layer, such as silicon oxide, silicon nitride, or a combination thereof, is first deposited. Then, the sidewall material layer is anisotropically etched to remove the horizontal sidewall material, leaving only the sidewall material layer on the sidewalls to form the gate sidewall 3043. The gate sidewall 3043 can be a single-layer structure or a multi-layer structure (such as a three-layer structure of silicon oxide-silicon nitride-silicon oxide). In this embodiment, the gate sidewall 3043 is a stacked structure of silicon oxide and silicon nitride.

[0051] Next, proceed to step S204, as follows: Figure 3D As shown, ion implantation of a second conductivity type is performed on the semiconductor substrate 300 to form a source region 305 and a drain region 306 disposed on both sides of the gate structure 304 along a first direction in the semiconductor substrate 300. The second conductivity type is opposite to the first conductivity type. At least one of the source region 305 and the drain region 306 is spaced apart from the first well region 302 to form a low-doped region between the first well region 302 and the source region 305 and / or between the first well region 302 and the drain region 306. The low-doped region is formed by the semiconductor substrate 300.

[0052] Specifically, the impurities implanted into the source and drain are preferably arsenic (As) or phosphorus (P). Arsenic has a low diffusion coefficient, making it suitable for forming shallow junctions; phosphorus has a high diffusion coefficient, making it suitable for forming deeper junctions or for adjusting the implantation depth. The source and drain regions have a second conductivity type (N-type) and are heavily doped (N+), with a doping concentration higher than that of the first well region 302, to form good ohmic contacts. For example, the implantation conditions for source and drain ion implantation are: implantation energy of 20 keV to 80 keV and implantation dose of 1 × 10⁻⁶. 15 cm -2 Up to 5×10 15 cm -2 .

[0053] After ion implantation, high-temperature annealing is performed to activate the implanted impurity ions and repair implantation damage. Annealing processes can include rapid thermal annealing (RTA), spike annealing, or laser annealing.

[0054] The first well region 302 in this embodiment does not cover the entire active region, but is located between the source region 305 and the drain region 306, and is spaced apart from at least one of the source region 305 and the drain region 306. Figure 4 In the example, the first well region 302 is spaced apart from the source region 305 and the drain region 306, and the distance between the first well region 302 and the source region 305 is equal to the distance between the first well region 302 and the drain region 306. That is, the source region 305 and the drain region 306 are symmetrically arranged on both sides of the first well region 302.

[0055] The advantage of using a symmetrical structure is that the source and drain regions can be used interchangeably, the layout is flexible, it is compatible with standard CMOS processes, no additional mask adjustments are required, and it is suitable for applications that require bidirectional signal transmission.

[0056] In another embodiment, such as Figure 5 As shown, the first well region 302 is disposed near the source region 305 and spaced apart from the drain region 306, forming a low-doped region between the first well region 302 and the drain region 306. The source region 305 can be located within the first well region 302 or at a small distance from it. Since the drain region 306 bears a high voltage, biasing the first well region 302 toward the source region 305 allows for a wider low-doped region on the drain side, enabling the depletion region to expand sufficiently within this region. This effectively reduces the peak electric field on the drain side and improves the breakdown voltage.

[0057] In yet another embodiment, such as Figure 6 As shown, the lateral distance between the source region 305 and / or the drain region 306 and the gate edge can be further widened, so that the source region 305 and / or the drain region 306 and the gate structure 304 are spaced apart, thereby improving the electric field distribution of the source region 305 and / or the drain region 306 and the gate edge region, thereby further improving the breakdown voltage of the high voltage MOS device. This has certain practical value in application scenarios with higher requirements for withstand voltage performance and relatively relaxed area requirements.

[0058] In summary, the manufacturing method of the high-voltage MOS device in this application embodiment effectively expands the width of the lateral depletion region by setting the first well region and the source region and / or drain region separately, and utilizing the low-doped region composed of the semiconductor substrate to deplete under high voltage bias. This reduces the electric field peak value in the overlapping area between the gate edge and the source region and / or drain region, thereby enabling the breakdown voltage to meet the high-voltage operation requirements of flash memory without the need for additional photomasks and injection processes, while reducing manufacturing costs and process steps.

[0059] This application also provides a high-voltage MOS device, which can be prepared by the method in the aforementioned embodiment one, but is not limited thereto.

[0060] Below, for reference Figures 4-6 The high-voltage MOS device of this application is described in detail. It is worth mentioning that, in order to avoid repetition, only a brief description is given for the same components and structures as in the foregoing embodiments. For specific explanations and descriptions, please refer to the descriptions in the foregoing embodiments.

[0061] Specifically, such as Figure 4 As shown, the high-voltage MOS device in this embodiment includes: The semiconductor substrate 300 has a first conductivity type (P-type in this embodiment). The semiconductor substrate 300 can be a silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, or a compound semiconductor substrate (such as silicon carbide, gallium arsenide, etc.).

[0062] A shallow trench isolation structure (STI) 301 is disposed in a semiconductor substrate 300 to isolate adjacent high-voltage MOS devices. The shallow trench isolation structure 301 is located between the source or drain region of one high-voltage MOS device and the source or drain region of another high-voltage MOS device. A second well region 303 is disposed below the shallow trench isolation structure 301. The second well region 303 has a first conductivity type (P-type), and optionally, its depth is less than the depth of the first well region 302. The second well region 303 is used to form a depletion isolation region under operating conditions to suppress leakage current between adjacent high-voltage MOS devices.

[0063] A first well region 302 is disposed in the semiconductor substrate 300, below the gate structure 304, and has a first conductivity type (P-type), i.e., a P-type well region (PW). The first well region 302 does not cover the entire active region, but is located between the source region 305 and the drain region 306, spaced apart from at least one of the source region 305 and the drain region 306. This spacing creates a low-doped region between the first well region 302 and the source region 305 and / or between the first well region 302 and the drain region 306. This low-doped region is formed by the semiconductor substrate 300, and its doping concentration is equal to the original doping concentration of the semiconductor substrate 300, but lower than the doping concentration of the first well region 302.

[0064] A gate structure 304 is disposed on a semiconductor substrate 300 and located above a first well region 302. The gate structure 304 includes a gate dielectric layer 3041, a gate electrode layer 3042 located on the gate dielectric layer 3041, and gate sidewalls 3043 located on the sidewalls of the gate electrode layer 3042 and the gate dielectric layer 3041. The dimension of the gate structure 304 along a first direction is larger than the dimension of the first well region 302 along the first direction. For example, the dimension of the first well region 302 along the first direction is 45% to 65% of the dimension of the gate structure 304 along the first direction.

[0065] Source region (S) 305 and drain region (D) 306 are disposed in the semiconductor substrate 300 on both sides of the gate structure 304 along a first direction, and have a second conductivity type (N-type in this embodiment), which is opposite to the first conductivity type. Source region 305 and drain region 306 are heavily doped regions (N+), and their doping concentration is higher than that of the first well region 302. At least one of source region 305 and drain region 306 is disposed at a distance from the first well region 302.

[0066] In one embodiment of this application, such as Figure 4As shown, the first well region 302 is spaced apart from the source region 305 and the drain region 306, and the distance between the first well region 302 and the source region 305 is equal to the distance between the first well region 302 and the drain region 306. That is, the source region 305 and the drain region 306 are symmetrically arranged on both sides of the first well region 302. The advantage of this symmetrical structure is that the source region 305 and the drain region 306 can be used interchangeably, providing flexible layout, compatibility with standard CMOS processes, and eliminating the need for additional mask adjustments. This makes it suitable for applications requiring bidirectional signal transmission.

[0067] In another embodiment of this application, such as Figure 5 As shown, the first well region 302 is positioned close to the source region 305 and spaced apart from the drain region 306, forming a low-doped region between the first well region 302 and the drain region 306. The source region 305 can be located within the first well region 302 or at a small distance from it. The advantages of using an asymmetric structure are: since the drain region 306 typically withstands a high voltage, biasing the first well region 302 towards the source region 305 allows for a wider low-doped region on the drain side, enabling the depletion region to expand sufficiently within this region, effectively reducing the peak electric field on the drain side and increasing the breakdown voltage; simultaneously, the narrower spacing or direct contact on the source side helps reduce the on-resistance.

[0068] In yet another embodiment of this application, as Figure 6 As shown, the lateral distance between the source region 305 and / or the drain region 306 and the gate structure 304 can be widened to allow the source region 305 and / or the drain region 306 to be spaced apart from the gate structure 304, further improving the electric field distribution at the edge of the source region and / or drain region 306 and the gate, thereby increasing the breakdown voltage of the high-voltage MOS device. This solution has certain practical value in applications with higher withstand voltage requirements and relatively less stringent area requirements.

[0069] The high-voltage MOS device in this application embodiment does not include a high-voltage N-type drift region (HVNDrift) for increasing the withstand voltage, thereby saving the corresponding photomask and injection process and reducing manufacturing costs.

[0070] In summary, the high-voltage MOS device of this application, by spacing the first well region with the source region and / or drain region, utilizes the low-doped region formed by the semiconductor substrate to deplete under high voltage bias, effectively expanding the width of the lateral depletion region, reducing the electric field peak of the overlapping area between the gate edge and the source region and / or drain region, thereby enabling the breakdown voltage to meet the high-voltage operation requirements of flash memory without the need for additional photomasks and injection processes, while reducing manufacturing costs and process steps.

[0071] In another embodiment of this application, an electronic device is also provided, including the aforementioned high-voltage MOS device, which is prepared according to the aforementioned method.

[0072] The electronic devices in this embodiment include, but are not limited to, microcontrollers, automotive electronic control units, secure storage devices, embedded flash memory chips, and portable electronic devices such as mobile phones, tablets, and laptops. Due to the use of the aforementioned high-voltage MOS devices, the electronic devices in this embodiment have higher reliability and lower manufacturing costs.

[0073] This application has been described through the above embodiments. However, it should be understood that the above embodiments are for illustrative purposes only and are not intended to limit this application to the scope of the described embodiments. Furthermore, those skilled in the art will understand that this application is not limited to the above embodiments, and many more variations and modifications can be made based on the teachings of this application, all of which fall within the scope of protection claimed in this application. The scope of protection of this application is defined by the appended claims and their equivalents.

Claims

1. A high-voltage MOS device, characterized in that, include: A semiconductor substrate having a first conductivity type; A shallow trench isolation structure is disposed in the semiconductor substrate, the shallow trench isolation structure being used to isolate adjacent high-voltage MOS devices; The gate structure located on the semiconductor substrate; A source region and a drain region are disposed on both sides of the gate structure in the semiconductor substrate along a first direction, and the source region and the drain region have a second conductivity type, which is opposite to the first conductivity type; A first well region is located in the semiconductor substrate below the gate structure. The first well region has the first conductivity type. The first well region is spaced apart from the source region and the drain region to form a low-doped region between the first well region and the source region and between the first well region and the drain region. The low-doped region is formed by the semiconductor substrate. The doping concentration of the low-doped region is equal to the original doping concentration of the semiconductor substrate. A second well region is disposed below the shallow trench isolation structure, the second well region having the first conductivity type.

2. The high-voltage MOS device according to claim 1, characterized in that, The dimension of the first well region along the first direction is 45%-65% of the dimension of the gate structure along the first direction.

3. The high-voltage MOS device according to claim 1, characterized in that, The distance between the first well region and the source region is equal to the distance between the first well region and the drain region; Alternatively, the first well region may be located near the source region.

4. The high-voltage MOS device according to claim 1, characterized in that, The source region and / or the drain region are spaced apart from the gate structure.

5. The high-voltage MOS device according to claim 1, characterized in that, The high-voltage MOS device does not include the drift region located between the source region or the drain region and the channel region.

6. A method for manufacturing a high-voltage MOS device, characterized in that, The method includes: A semiconductor substrate is provided, the semiconductor substrate having a first conductivity type; A shallow trench isolation structure is formed in the semiconductor substrate, the shallow trench isolation structure being used to isolate adjacent high-voltage MOS devices; Ion implantation of a first conductivity type is performed on the semiconductor substrate to form a first well region in the semiconductor substrate, and a second well region is simultaneously formed below the shallow trench isolation structure; A gate structure is formed on the semiconductor substrate, the gate structure being located above the first well region; Ion implantation of a second conductivity type is performed on the semiconductor substrate to form a source region and a drain region disposed on both sides of the gate structure along a first direction in the semiconductor substrate. The second conductivity type is opposite to the first conductivity type. The source region and the drain region are both spaced apart from the first well region to form a low-doped region between the first well region and the source region and between the first well region and the drain region. The low-doped region is composed of the semiconductor substrate, and the doping concentration of the low-doped region is equal to the original doping concentration of the semiconductor substrate.

7. The manufacturing method according to claim 6, characterized in that, The distance between the first well region and the source region is equal to the distance between the first well region and the drain region; Alternatively, the first well region may be located near the source region.

8. The manufacturing method according to claim 6, characterized in that, The source region and / or the drain region are spaced apart from the gate structure.

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