A step-type trench SiC JFET device structure based on vertical ion implantation and a manufacturing method thereof

Abstract

This invention discloses a stepped trench SiC JFET device structure and its fabrication method based on vertical ion implantation. Through vertical ion implantation, sidewall gates and bottom gates are simultaneously constructed in a multi-step characteristic trench. Specifically, a second conductivity type sidewall gate region is formed in the sidewall of the first conductivity type channel layer and part of the first conductivity type current extension layer, and a second conductivity type bottom gate region is formed in the first conductivity type current extension layer, with the second conductivity type sidewall gate region and the second conductivity type bottom gate region overlapping. A second conductivity type highly doped bottom gate region is also formed on the surface of the first conductivity type current extension layer. This invention solves the problems of traditional trench SiC JFET devices requiring multiple tilted ion implantations to form sidewall gates and being sensitive to sidewall crystal orientation, reducing process complexity and improving device production yield.

Description

Technical Field

[0001] This invention relates to the field of power electronic device technology, and in particular to a stepped trench SiC JFET device structure based on vertical ion implantation and its manufacturing method. Background Technology

[0002] Silicon carbide junction field-effect transistors (SiC JFETs) eliminate the Metal-Oxide-Semiconductor (MOS) structure, offering advantages such as high operating temperature and strong current carrying capacity, making them particularly advantageous in protection circuits such as solid-state circuit breakers.

[0003] Trench-type SiC JFETs are the current mainstream technology, with smaller cell size and higher current density. However, traditional trench technology requires at least two tilting or rotating ion implantations to form symmetrical sidewall gates, which requires high precision in controlling the ion implantation angle and trench sidewall angle. Secondly, due to the anisotropy of SiC crystal, the crystal orientation of the trench sidewall affects the ion implantation distribution. Therefore, the trench layout of traditional trench SiC JFETs has limitations, especially when using polygonal cells such as squares and hexagons. Because the crystal orientation of the cell trench sidewall is different, different tilting ion implantation conditions are required to form a uniformly doped sidewall gate. Summary of the Invention

[0004] Technical Objective: To address the shortcomings of traditional trench SiC JFETs in existing technologies, this invention provides a stepped trench SiC JFET device structure and its manufacturing method based on vertical ion implantation. By using vertical ion implantation, the sidewall gate and bottom gate are simultaneously constructed in a multi-step characteristic trench, solving the problems of traditional trench SiC JFET devices requiring multiple tilted ion implantations to form the sidewall gate and being sensitive to the crystal orientation of the sidewalls. This reduces process complexity and provides a SiC JFET device structure and manufacturing method with a high process window; it simplifies the manufacturing process and improves device production yield.

[0005] Technical solution: To achieve the above technical objectives, the present invention adopts the following technical solution.

[0006] A method for fabricating a stepped trench SiC JFET device structure based on vertical ion implantation includes the following steps: Step 1: Sequentially grow the first conductivity type withstand voltage layer, the first conductivity type current spreading layer, and the first conductivity type channel layer material from bottom to top on the first conductivity type substrate; Step 2: Form a source region material of the first conductivity type on the channel layer material of the first conductivity type; Step 3: Form a mask on the source region material of the first conductivity type, and etch the source region material of the first conductivity type and part of the channel layer material of the first conductivity type based on the mask to form a feature trench and a source region of the first conductivity type located between adjacent feature trenches. Step 4: Form a first sacrificial dielectric sidewall located on the sidewall of the source region of the first conductivity type in the adjacent feature trench, and expose the channel layer material of the first conductivity type; Step 5: Using the mask and the first sacrificial dielectric sidewall as etching masking layers, etch the first conductive type channel layer material to form the first conductive type channel layer and feature trenches two located on both sides of the first conductive type channel layer. Feature trenches one and two on the same side of the first conductive type channel layer are connected to each other as feature trenches; remove the first sacrificial dielectric sidewall; the feature trenches are stepped trenches. Step 6: Using a mask as an ion implantation masking layer, a second conductivity type sidewall gate region is formed in the sidewall of the first conductivity type channel layer and part of the first conductivity type current extension layer by vertical ion implantation, and a second conductivity type bottom gate region is formed in the first conductivity type current extension layer, with the second conductivity type sidewall gate region and the second conductivity type bottom gate region overlapping. Step 7: Form a second sacrificial medium sidewall located on the sidewall of the feature trench; Step 8: Using the mask and the second sacrificial dielectric sidewall as the ion implantation masking layer, a second conductivity type highly doped bottom gate region is formed on the surface of the first conductivity type current extension layer by vertical ion implantation. The second conductivity type highly doped bottom gate region overlaps with the second conductivity type bottom gate region; remove the mask and the second sacrificial dielectric sidewall. Step 9: Form dielectric sidewalls on the sidewalls of the feature trench, exposing the source region of the first conductivity type and the bottom gate region of the second conductivity type; Step 10: Form a source alloy on the source region of the first conductivity type and form a gate alloy on the bottom gate region of the second conductivity type; Step 11: Form a passivation dielectric layer that fills the feature trenches; Step 12: Form a source metal electrode on the passivation dielectric layer and the source alloy; form a drain metal electrode at the bottom of the first conductivity type substrate.

[0007] Furthermore, the width of feature groove one ranges from 0.5μm to 3μm, and the depth ranges from 0.2μm to 1.0μm.

[0008] Furthermore, the width of the second feature groove ranges from 0.2 μm to 2.5 μm, and the depth ranges from 0.2 μm to 1.0 μm.

[0009] Furthermore, the depth of the overlapping region between the second conductivity type sidewall gate region and the second conductivity type bottom gate region is ΔY; ΔY ≥ 0.1 μm.

[0010] Furthermore, the second conductivity type sidewall gate region is buried in the sidewall of the first conductivity type channel layer, extends into the interior of the first conductivity type current extension layer, and is more than 0 μm away from the first conductivity type source region and less than 1 μm away.

[0011] Furthermore, in step 6, the implantation energy range for vertical ion implantation is 50 keV-1000 keV, and the implantation dose range is 5E12 / cm². 3 -1E14 / cm 3 .

[0012] Furthermore, in step 8, the implantation energy of vertical ion implantation is ≥30 keV, and the implantation dose range is 1E14 / cm². 3 -1E15 / cm 3 .

[0013] Furthermore, the source metal electrode, drain metal electrode, gate alloy, and source alloy are made of one or more combinations of Ti, Al, Ni, Pt, and Ag metals.

[0014] This invention also discloses a stepped trench SiC JFET device structure based on vertical ion implantation, manufactured according to any of the above-described methods for fabricating a stepped trench SiC JFET device structure based on vertical ion implantation, comprising: Drain metal electrode; A first conductivity type substrate located above the drain metal electrode; a first conductivity type withstand layer located above the first conductivity type substrate; a first conductivity type current spreading layer located above the first conductivity type withstand layer; A first conductivity type channel layer located above the first conductivity type current extension layer; a first conductivity type source region located above the first conductivity type channel layer; The feature trenches are symmetrically located on both sides of the source region of the first conductivity type and the channel layer of the first conductivity type. The feature trenches include a connected feature trench one and a feature trench two. Feature trench one is located on the sidewall of the source region of the first conductivity type and part of the sidewall of the channel layer of the first conductivity type. Feature trench two is located on part of the sidewall of the channel layer of the first conductivity type. The width of feature trench two is smaller than the width of feature trench one. The medium sidewall located on the sidewall of the characteristic trench; The second conductivity type sidewall gate region is located inside the dielectric sidewall, inside the two sidewalls of the feature trench, and extends into the first conductivity type current extension layer; The second conductivity type bottom gate region is located at the bottom of the feature trench and inside the first conductivity type current extension layer, and the second conductivity type bottom gate region overlaps with the second conductivity type sidewall gate region; A second conductivity type highly doped bottom gate region is located at the bottom of the feature trench and on the surface of the first conductivity type current extension layer; the second conductivity type highly doped bottom gate region overlaps with the second conductivity type bottom gate region; Source alloy located above the source region of the first conductivity type; Gate alloy located at the bottom of the feature trench, above the highly doped bottom gate region of the second conductivity type; Passivation medium filling feature trenches; A source metal electrode located on a passivation medium and a source alloy.

[0015] Beneficial effects: 1. This invention solves the problem of traditional trench SiC JFET devices requiring multiple tilted ion implantations to form sidewall gates and being sensitive to sidewall crystal orientation by simultaneously constructing sidewall gates and bottom gates in multi-step feature trenches through vertical ion implantation. It reduces process complexity and is a SiC JFET device structure and manufacturing method with a high process window, improving device production yield. 2. The sidewall gate region of the present invention is far from the high-concentration first conductivity type source region, thus achieving a higher gate-source breakdown voltage, increasing the rated gate-source voltage range of the device, widening the gate-source safe operating area, and improving device reliability. In contrast, traditional trench SiC JFET devices, due to the sidewall gate being formed by tilted ion implantation, have the sidewall gate directly overlapping with the high-concentration first conductivity type source region, reducing the gate-source breakdown voltage and resulting in a small gate-source safe operating area. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the structure of a trench SiC JFET device with symmetrical sidewall gates in the prior art; Figure 2 This is a schematic diagram of a stepped trench SiC JFET device structure based on vertical ion implantation according to an embodiment of the present invention; Figures 3-22 This is a schematic diagram of a manufacturing process for a stepped trench SiC JFET device structure based on vertical ion implantation, as an example. Wherein, 1. First conductivity type substrate; 2. First conductivity type withstand voltage layer; 3. First conductivity type current spread layer; 4. First conductivity type channel layer; 4'. First conductivity type channel layer material; 4-1. Feature trench; 4-1-1. Feature trench one; 4-1-2. Feature trench two; 5. First conductivity type source region; 5'. First conductivity type source region; 6. Mask; 7. First sacrificial dielectric sidewall; 8-1. Second conductivity type sidewall gate region; 8-2. Second conductivity type bottom gate region; 8-3. Second conductivity type highly doped bottom gate region; 9. Second sacrificial dielectric sidewall; 10'. Dielectric sidewall material; 10. Dielectric sidewall; 11-1. Source alloy; 11-2. Gate alloy; 12. Passivation dielectric; 13. Source metal electrode; 14. Drain metal electrode. Detailed Implementation

[0017] The present invention will be further explained and described below with reference to the accompanying drawings and embodiments.

[0018] The embodiments are for illustrative purposes only and do not constitute a limitation on the scope of the claims. Other alternative means that can be conceived by those skilled in the art are all within the scope of the claims of this invention.

[0019] Furthermore, in the description of this invention, it should be noted that the terms "central," "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. In addition, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Example

[0020] As attached Figure 3 -Appendix Figure 22 As shown, this invention discloses a method for fabricating a stepped trench SiC JFET device structure based on vertical ion implantation, comprising the following steps: Step 1: Sequentially grow the following layers on the first conductivity type substrate 1: first conductivity type withstand voltage layer 2, first conductivity type current spreading layer 3, and first conductivity type channel layer material 4' from bottom to top. like Figure 3 and Figure 4 As shown, a first conductivity type withstand voltage layer 2 is formed on a first conductivity type substrate 1 by epitaxial growth. The doping concentration range of the first conductivity type withstand voltage layer 2 is generally 1e14cm. -3 ~5e16cm -3The first conductivity type substrate 1 is a first conductivity type SiC substrate, and the first conductivity type withstand voltage layer 2 is a first conductivity type SiC epitaxial layer. The semiconductor material can be 3C-SiC, 4H-SiC, or 6H-SiC. Then, a first conductivity type current spreading layer 3 is formed by epitaxial growth of the first conductivity type withstand voltage layer 2. Its doping concentration is higher than that of the first conductivity type withstand voltage layer 2, and the range is generally 1e15cm. -3 ~1e17cm -3 The first conductivity type current spreading layer 3 is a first conductivity type SiC epitaxial layer, and the semiconductor material can be 3C-SiC, 4H-SiC, or 6H-SiC. Then, a first conductivity type channel layer material 4' is formed by epitaxial growth of the first conductivity type current spreading layer 3, and its doping concentration is lower than that of the first conductivity type current spreading layer 3, typically ranging from 1e14cm. -3 ~5e16cm -3 The first conductivity type channel layer 4 is a first conductivity type SiC epitaxial layer, and the semiconductor material can be 3C-SiC, 4H-SiC or 6H-SiC; Step 2: Form a first conductivity type source region material 5' on the first conductivity type channel layer material 4'; like Figure 5 As shown, on the surface of the SiC wafer prepared in step 1, a first conductivity type source region material 5' is formed on the surface of the first conductivity type channel layer material 4' by an ion implantation process, with a doping concentration ranging from 1e17cm. -3 ~ 1e19cm -3 .

[0021] Step 3: Form a mask 6 on the first conductivity type source region material 5', and etch the first conductivity type source region material 5' and part of the first conductivity type channel layer material 4' based on the mask 6 to form a feature trench and a first conductivity type source region 5 located between adjacent feature trenches. The first conductivity type source region 5 is columnar and its width is the same as the width of the mask 6. like Figure 6 As shown, on the surface of the SiC wafer prepared in step 2, a masking layer is grown by chemical vapor deposition. Then, the mask layer is patterned by photolithography and etching processes to form mask 6, which serves as an etching and implantation mask. Then, the exposed first conductivity type source region material 5' and part of the first conductivity type channel layer material 4' are etched by etching processes to form feature trench 4-1-1 and first conductivity type source region 5. Feature trench 4-1-1 consists of two adjacent trenches. The first conductivity type source region 5 is columnar and located between adjacent feature trench 4-1-1. The width of the first conductivity type source region 5 is the same as the width of mask 6. The width of feature trench 4-1-1 is generally 0.5μm-3μm, and the depth is generally 0.2μm-1.0μm. Step 4: Form a first sacrificial dielectric sidewall 7 located on the sidewall of the first conductivity type source region 5 in the adjacent feature trench 4-1-1, and expose the first conductivity type channel layer material 4'; like Figure 7 , Figure 8 As shown, on the surface of the SiC wafer prepared in step 3, a passivation dielectric layer is deposited by chemical vapor deposition, and then reverse etched by anisotropic etching process, leaving the first sacrificial dielectric sidewall 7 of the feature trench 4-1-1 sidewall, exposing the first conductive type channel layer material 4'; the first sacrificial dielectric sidewall 7 is also located on the sidewall of part of the mask 6.

[0022] Step 5: Using mask 6 and the first sacrificial dielectric sidewall 7 as etching masking layers, etch the first conductive type channel layer material 4' to form the first conductive type channel layer 4 and feature trenches 4-1-2 located on both sides of the first conductive type channel layer 4. Feature trenches 4-1-1 and 4-1-2 on the same side of the first conductive type channel layer 4 are connected. Feature trenches 4-1-1 and 4-1-2 together form feature trench 4-1; remove the first sacrificial dielectric sidewall 7. like Figure 9 , Figure 10 As shown, on the SiC wafer surface prepared in step 4, using the aforementioned mask 6 and the first sacrificial dielectric sidewall 7 as etching masking layers, the exposed first conductive type channel layer material 4' is etched through anisotropic etching process to form a feature trench 4-1 and a first conductive type channel layer 4 located between adjacent feature trenches 4-1. The trenches on both sides of the first conductive type channel layer 4 are feature trenches 4-1-2, and feature trenches 4-1-2 on the same side of the first conductive type channel layer 4 are connected to feature trench 4-1-1. Feature trenches 4-1-1 and 4-1-2 together constitute feature trench 4-1. The width of feature trench 4-1-2 is smaller than that of feature trench 4-1-1, and the width range of feature trench 4-1-2 is generally 0.2μm-2.5μm; the depth H2 range is generally 0.2μm-1.0μm. Then, the sacrificial dielectric sidewall 7 is removed by etching process. In this invention, feature groove 4-1, which is formed by feature groove 1 4-1-1 and feature groove 2 4-1-2, is a stepped groove, and the width of feature groove 2 4-1-2 is smaller than the width of feature groove 1 4-1-1. In other embodiments of this invention, the manufacturing method of feature groove 2 can be repeated to form feature groove 3, and even feature groove N. The width of feature groove N is smaller than that of feature groove N-1, generally 0.1μm-1μm smaller than feature groove N-1, and its depth has no special requirements, generally 0.2μm-1.0μm. Step 6: Using mask 6 as an ion implantation masking layer, a second conductivity type sidewall gate region 8-1 is formed in the sidewall of the first conductivity type channel layer 4 and part of the first conductivity type current extension layer 3 by vertical ion implantation, and a second conductivity type bottom gate region 8-2 is formed in the first conductivity type current extension layer 3, and the second conductivity type sidewall gate region 8-1 and the second conductivity type bottom gate region 8-2 overlap. like Figure 11 and Figure 12 As shown, on the SiC wafer surface prepared in step 5, the aforementioned mask 6 is used as an ion implantation masking layer. A second conductivity type sidewall gate region 8-1 is formed on the inner sidewall of the feature trench 4-1-2 by vertical ion implantation. At the same time, the second conductivity type sidewall gate region 8-1 is located in the sidewall of the first conductivity type channel layer 4 and part of the first conductivity type current extension layer 3. A second conductivity type bottom gate region 8-2 is formed at the bottom of the feature trench 4-1-2 and in the first conductivity type current extension layer 3. At the same time, the upper surface of the second conductivity type bottom gate region 8-2 is lower than the upper surface of the first conductivity type current extension layer 3, and the second conductivity type sidewall gate region 8-1 extends into the first conductivity type current extension layer 3, achieving overlapping contact with the second conductivity type bottom gate region 8-2. Since the second conductivity type sidewall gate region 8-1 and the second conductivity type bottom gate region 8-2 are formed simultaneously, their injection depths are the same. The distance between the upper surface of the second conductivity type sidewall gate region 8-1 and the upper surface of the first conductivity type channel layer 4 is defined as Y1, and the distance between the upper surface of the second conductivity type bottom gate region 8-2 and the upper surface of the first conductivity type current extension layer 3 is defined as Y1. The depth of the feature trench 4-1-2 is H2, the injection depth of the second conductivity type sidewall gate region 8-1 and the second conductivity type bottom gate region 8-2 is Y2, and the depth of the overlapping area of ​​the second conductivity type sidewall gate region 8-1 and the second conductivity type bottom gate region 8-2 is ΔY. To ensure the interconnection of gate regions in all parts of the device, the second conductivity type sidewall gate region 8-1 and the second conductivity type bottom gate region 8-2 must overlap, and considering process allowance, the overlap dimension ΔY ≥ 0.1 μm. According to... Figure 12 Since Y2 - Y1 = H2 + ΔY, the design constraint Y2 - Y1 - H2 ≥ 0.1 μm can be obtained. To meet this constraint, the ion implantation conditions for the second conductivity type sidewall gate region 8-1 and the second conductivity type bottom gate region 8-2 are generally as follows: implantation angle 0°, implantation energy range 50 keV-1000 keV, and implantation dose range 5E12 / cm². 2 -1E14 / cm 2 Multiple vertical ion implantations can be performed; when the second conductivity type is P-type, the implanted atom is aluminum; when the second conductivity type is N-type, the implanted atom is nitrogen or phosphorus. Step 7: Form the second sacrificial medium sidewall 9 located on the sidewall of the feature trench 4-1; like Figure 13 , Figure 14 As shown, on the surface of the SiC wafer prepared in step 6, a passivation dielectric layer is deposited by chemical vapor deposition, and then reverse etched by anisotropic etching process, leaving a second sacrificial dielectric sidewall 9 on the sidewall of the feature trench 4-1. The second sacrificial dielectric sidewall 9 covers part of the sidewall of the mask 6, the sidewall of the first conductivity type source region 5, part of the sidewall of the first conductivity type channel layer 4, part of the sidewall of the second conductivity type gate region 8-1, and part of the top of the first conductivity type current extension layer 3. Step 8: Using mask 6 and the second sacrificial dielectric sidewall 9 as ion implantation masking layers, a second conductivity type highly doped bottom gate region 8-3 located on the surface of the first conductivity type current extension layer 3 is formed by vertical ion implantation; then mask 6 and the second sacrificial dielectric sidewall 9 are removed. like Figure 15 As shown, on the SiC wafer surface prepared in step 7, using the aforementioned mask 6 and the second sacrificial dielectric sidewall 9 as an ion implantation masking layer, a second conductivity type highly doped bottom gate region 8-3 is formed at the bottom of feature trench 4-1 (i.e., the bottom of feature trench 4-1-2) and on the surface of the first conductivity type current extension layer 3 by vertical ion implantation. The upper surface of the second conductivity type highly doped bottom gate region 8-3 is flush with the upper surface of the first conductivity type current extension layer 3, and the lower surface of the second conductivity type highly doped bottom gate region 8-3 is lower than the upper surface of the second conductivity type bottom gate region 8-2. That is to say, the second conductivity type highly doped bottom gate region 8-3 overlaps with the second conductivity type bottom gate region 8-2. When the second conductivity type highly doped bottom gate region 8-3 is formed by vertical ion implantation, the implantation angle is 0°, the implantation energy is ≥30keV, and the implantation dose range is 1E14 / cm. 3 -1E15 / cm 3 Multiple vertical ion implantations can be performed; then the mask 6 and the second sacrificial medium sidewall 9 can be removed by an etching process. Step 9: Form a dielectric sidewall 10 on the sidewall of the feature trench 4-1, exposing the first conductivity type source region 5 and the second conductivity type bottom gate region 8-3; like Figure 16 , Figure 17 As shown, on the surface of the SiC wafer prepared in step 8, a passivation dielectric layer is deposited as a dielectric sidewall material 10' by chemical vapor deposition process, and then reverse etching is performed by anisotropic etching process to leave dielectric sidewall 10 with feature trench 4-1 sidewall, exposing the first conductivity type source region 5 and the second conductivity type bottom gate region 8-3, and the dielectric sidewall 10 masks the sidewall. Step 10: Form source alloy 11-1 on the source region 5 of the first conductivity type, and form gate alloy 11-2 on the bottom gate region 8-3 of the second conductivity type; like Figure 18 As shown, on the surface of the SiC wafer prepared in step 9, ohmic metal is deposited by sputtering or evaporation and then annealed. Metal silicides are formed in the exposed first conductivity type source region 5 and the second conductivity type highly doped bottom gate region 8-3, which are source alloy 11-1 and gate alloy 11-2, respectively. The dielectric sidewall 10 cannot form metal silicides with the ohmic metal. The ohmic metal that does not form metal silicides is removed by a wet process. Step 11: Form a passivation dielectric layer 12 that fills the feature trench; like Figure 19 , Figure 20 As shown, on the surface of the SiC wafer prepared in step 10, a passivation dielectric layer material is deposited by chemical vapor deposition to fill the feature trench 4-1. The thickness of the passivation dielectric layer material ranges from 0.4 μm to 5 μm. The passivation dielectric layer material is generally silicon nitride, silicon oxide, or a composite dielectric of silicon nitride and silicon oxide. Then, the passivation dielectric layer material is reverse-etched by anisotropic etching process, with an etching thickness of 1.1 to 1.5 times the thickness of the passivation dielectric layer material, exposing the source alloy 11-1 and forming the passivation dielectric layer 12. Step 12: Form a source metal electrode 13 on the passivation dielectric layer 12 and the source alloy 11-1; form a drain metal electrode 14 at the bottom of the first conductivity type substrate 1; like Figure 21 and Figure 22 As shown, on the surface of the SiC wafer prepared in step 11, a source metal electrode 13 is deposited by sputtering or evaporation; on the bottom layer of the SiC wafer prepared in step 11, i.e. the bottom of the first conductivity type substrate 1, an ohmic metal is deposited by sputtering or evaporation and then annealed to form a drain metal electrode 14.

[0023] In this embodiment, the source metal electrode 13, drain metal electrode 14, gate alloy and source alloy are made of one or more combinations of metals such as Ti, Al, Ni, Pt and Ag; the ohmic metal is made of a different material than the source metal electrode 13 and drain metal electrode 14, and is generally made of titanium, nickel, cobalt, platinum, tungsten or a combination thereof.

[0024] As attached Figure 2 As shown, this embodiment also discloses a stepped trench SiC JFET device structure based on vertical ion implantation, including: Drain metal electrode 14; A first conductivity type substrate 1 is located on the drain metal electrode 14; the first conductivity type substrate 1 is a first conductivity type SiC substrate. A first conductivity type withstand layer 2 is located on a first conductivity type substrate 1; the first conductivity type withstand layer 2 is a first conductivity type SiC epitaxial layer. A first conductivity type current spreading layer 3 is located on top of the first conductivity type withstand voltage layer 2; the first conductivity type current spreading layer 3 is a first conductivity type SiC epitaxial layer. A first conductivity type channel layer 4 located above the first conductivity type current extension layer 3; a first conductivity type source region 5 located above the first conductivity type channel layer 4; The feature trenches 4-1 are symmetrically located on both sides of the first conductivity type source region 5 and the first conductivity type channel layer 4. The feature trenches 4-1 include a connected feature trench 1 4-1-1 and a feature trench 2 4-1-2. Feature trench 1 4-1-1 is located on the side wall of the first conductivity type source region 5 and part of the side wall of the first conductivity type channel layer 4. Feature trench 2 4-1-2 is located on part of the side wall of the first conductivity type channel layer 4. The width of feature trench 2 4-1-2 is smaller than the width of feature trench 1 4-1-1. Medium sidewall 10 located on the sidewall of feature trench 4-1; Located inside the dielectric sidewall 10, inside the sidewall of the feature trench 4-1-2, and extending into the second conductivity type sidewall gate region 8-1 of the first conductivity type current extension layer 3; The second conductivity type bottom gate region 8-2 is located at the bottom of the feature trench 4-1 and inside the first conductivity type current extension layer 3, and the second conductivity type bottom gate region 8-2 overlaps with the second conductivity type sidewall gate region 8-1; Located at the bottom of the feature trench 4-1 and on the surface of the first conductivity type current extension layer 3, the second conductivity type highly doped bottom gate region 8-3 overlaps with the second conductivity type bottom gate region 8-2; Source alloy 11-1 located above source region 5 of the first conductivity type; Gate alloy 11-2 located at the bottom of feature trench 4-1 and above the highly doped bottom gate region 8-3 of the second conductivity type; Passivation medium 12 fills the feature trench 4-1; The source metal electrode 13 is located on the passivation medium 12 and the source alloy 11-1.

[0025] In this invention, the first conductivity type is N-type or P-type, and the second conductivity type is P-type or N-type. The cell arrangement can be in the form of bars, hexagons, squares, or atomic lattices, etc.

[0026] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for fabricating a stepped trench SiC JFET device structure based on vertical ion implantation, characterized in that: Includes the following steps: Step 1: Sequentially grow the first conductivity type withstand voltage layer, the first conductivity type current spreading layer, and the first conductivity type channel layer material from bottom to top on the first conductivity type substrate; Step 2: Form a source region material of the first conductivity type on the channel layer material of the first conductivity type; Step 3: Form a mask on the source region material of the first conductivity type, and etch the source region material of the first conductivity type and part of the channel layer material of the first conductivity type based on the mask to form a feature trench and a source region of the first conductivity type located between adjacent feature trenches. Step 4: Form a first sacrificial dielectric sidewall located on the sidewall of the source region of the first conductivity type in the adjacent feature trench, and expose the channel layer material of the first conductivity type; Step 5: Using the mask and the first sacrificial medium sidewall as etching masking layers, etch the first conductive type channel layer material to form the first conductive type channel layer and the second feature trench located on both sides of the first conductive type channel layer. The first feature trench on the same side of the first conductive type channel layer is connected to the second feature trench, which serves as the feature trench. Remove the first sacrificial medium sidewall; the characteristic trench is a stepped trench; Step 6: Using a mask as an ion implantation masking layer, a second conductivity type sidewall gate region is formed in the sidewall of the first conductivity type channel layer and part of the first conductivity type current extension layer by vertical ion implantation, and a second conductivity type bottom gate region is formed in the first conductivity type current extension layer, with the second conductivity type sidewall gate region and the second conductivity type bottom gate region overlapping. Step 7: Form a second sacrificial medium sidewall located on the sidewall of the feature trench; Step 8: Using the mask and the second sacrificial dielectric sidewall as ion implantation masking layers, a second conductivity type highly doped bottom gate region is formed on the surface of the first conductivity type current extension layer by vertical ion implantation. The second conductivity type highly doped bottom gate region overlaps with the second conductivity type bottom gate region; remove the mask and the second sacrificial dielectric sidewall. Step 9: Form dielectric sidewalls on the sidewalls of the feature trench, exposing the source region of the first conductivity type and the bottom gate region of the second conductivity type; Step 10: Form a source alloy on the source region of the first conductivity type and form a gate alloy on the bottom gate region of the second conductivity type; Step 11: Form a passivation dielectric layer that fills the feature trenches; Step 12: Form a source metal electrode on the passivation dielectric layer and the source alloy; form a drain metal electrode at the bottom of the first conductivity type substrate.

2. The method for manufacturing a stepped trench SiC JFET device structure based on vertical ion implantation according to claim 1, characterized in that: The width of feature groove one ranges from 0.5μm to 3μm, and the depth ranges from 0.2μm to 1.0μm.

3. The method for manufacturing a stepped trench SiC JFET device structure based on vertical ion implantation according to claim 1, characterized in that: The width of feature groove 2 ranges from 0.2μm to 2.5μm; the depth ranges from 0.2μm to 1.0μm.

4. The method for manufacturing a stepped trench SiC JFET device structure based on vertical ion implantation according to claim 1, characterized in that: The depth of the overlapping region between the sidewall gate region of the second conductivity type and the bottom gate region of the second conductivity type is ΔY; ΔY ≥ 0.1 μm.

5. The method for manufacturing a stepped trench SiC JFET device structure based on vertical ion implantation according to claim 1, characterized in that: The second conductivity type sidewall gate region is buried in the sidewall of the first conductivity type channel layer, extends into the interior of the first conductivity type current extension layer, and is more than 0 μm away from the first conductivity type source region and less than 1 μm away.

6. The method for manufacturing a stepped trench SiC JFET device structure based on vertical ion implantation according to claim 1, characterized in that: In step 6, the implantation energy range for vertical ion implantation is 50 keV-1000 keV, and the implantation dose range is 5E12 / cm². 3 -1E14 / cm 3 .

7. The method for manufacturing a stepped trench SiC JFET device structure based on vertical ion implantation according to claim 1, characterized in that: In step 8, the vertical ion implantation energy is ≥30 keV, and the implantation dose range is 1E14 / cm². 3 -1E15 / cm 3 .

8. The method for manufacturing a stepped trench SiC JFET device structure based on vertical ion implantation according to claim 1, characterized in that: The source metal electrode, drain metal electrode, gate alloy, and source alloy are made of one or more combinations of Ti, Al, Ni, Pt, and Ag metals.

9. A stepped trench SiC JFET device structure based on vertical ion implantation, manufactured by the method for fabricating a stepped trench SiC JFET device structure based on vertical ion implantation according to any one of claims 1-8, characterized in that, include: Drain metal electrode; A first conductivity type substrate located above the drain metal electrode; A first conductivity type withstand layer located on a first conductivity type substrate; A first conductivity type current spreading layer located above a first conductivity type withstand voltage layer; A first conductivity type channel layer located above a first conductivity type current extension layer; The first conductivity type source region is located above the first conductivity type channel layer; The feature trenches are symmetrically located on both sides of the source region of the first conductivity type and the channel layer of the first conductivity type. The feature trenches include a connected feature trench one and a feature trench two. Feature trench one is located on the sidewall of the source region of the first conductivity type and part of the sidewall of the channel layer of the first conductivity type. Feature trench two is located on part of the sidewall of the channel layer of the first conductivity type. The width of feature trench two is smaller than the width of feature trench one. The medium sidewall located on the sidewall of the characteristic trench; The second conductivity type sidewall gate region is located inside the dielectric sidewall, inside the two sidewalls of the feature trench, and extends into the first conductivity type current extension layer; The second conductivity type bottom gate region is located at the bottom of the feature trench and inside the first conductivity type current extension layer, and the second conductivity type bottom gate region overlaps with the second conductivity type sidewall gate region; A second conductivity type highly doped bottom gate region is located at the bottom of the feature trench and on the surface of the first conductivity type current extension layer; the second conductivity type highly doped bottom gate region overlaps with the second conductivity type bottom gate region; Source alloy located above the source region of the first conductivity type; Gate alloy located at the bottom of the feature trench, above the highly doped bottom gate region of the second conductivity type; Passivation medium filling feature trenches; A source metal electrode located on a passivation medium and a source alloy.

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