A thyristor cathode structure with a composite gradient short-circuit point and a preparation method thereof

Abstract

The application discloses a thyristor cathode structure with a composite gradient short-circuit point and a preparation method thereof, and belongs to the technical field of semiconductor device manufacturing. + The method comprises the following steps: forming a P-type base region on an N-type base region, and forming a cathode N + region and a cathode short-circuit point region with a double gradient through selective doping; and forming an electrode layer comprising a center gate, an amplification gate and a cathode emitter through a photoetching and metallization process. The cathode emitter layout is composed of a plurality of radial units with main fingers and auxiliary fingers, and the width ratio and length ratio of the main fingers and the auxiliary fingers are accurately defined; the cathode short-circuit point region simultaneously has a distribution density gradient and a doping concentration gradient increasing from the center to the edge. Through the collaborative design of the finger structure and the double gradient of the short-circuit point, the maintenance current of the thyristor is significantly improved while the good turn-on performance is maintained, and the anti-interference ability and the working stability of the device are enhanced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device manufacturing technology, specifically to a thyristor cathode structure with a composite gradient short-circuit point and its preparation method. Background Technology

[0002] Thyristors, as key power semiconductor switching devices, are widely used in power control, motor drives, and reactive power compensation. Their basic structure is a PNPN four-layer three-terminal device, with the three electrodes being the anode, cathode, and gate. Holding current (IH) is one of the key parameters for evaluating thyristor performance; it defines the minimum anode current required for the thyristor to transition from the on-state to the off-state. In practical applications, if the IH value of a thyristor is too low, it is highly susceptible to electromagnetic interference, voltage transients, or high-temperature leakage current in the circuit, leading to false turn-on, equipment failure, or even system paralysis. Therefore, how to effectively improve the IH parameter of thyristors to enhance their anti-interference capability and operational stability while meeting other electrical performance requirements has been a long-standing technical concern in this field.

[0003] Existing technologies have conducted numerous studies on the structure and manufacturing process of thyristors. For example, Chinese invention patent application CN118073196A discloses a mesa modeling and protection process for a circular thyristor chip. This process employs a large wafer manufacturing technique, fabricating the thyristor chip through steps such as laser grooving, closed-tube diffusion, photolithography etching, and blade glass passivation. The disclosed layout structure includes radially distributed linear inner fingers and V-shaped outer fingers connected to their ends, aiming to improve the device's turn-on characteristics. However, this technical solution focuses on optimizing voltage withstand and stability through mesa modeling and passivation protection, without providing clear technical guidance on how to actively control and improve IH parameters through layout design. Similarly, Chinese utility model patent CN221079994U discloses a multi-layer protection structure and a thyristor chip. This mainly improves device reliability and voltage withstand by setting a multi-layer protection structure such as an SIPOS layer and a glass passivation layer on the high-voltage groove, but also does not address the improvement of IH parameters. In addition, conventional designs also set uniformly distributed short-circuit points in the cathode region to improve turn-off characteristics. However, the effect of uniformly distributed short-circuit points on improving IH is limited, and it often comes at the cost of sacrificing turn-on sensitivity.

[0004] In summary, while existing technologies have optimized the mesa design, passivation protection, and turn-on characteristics of thyristors, a clear solution is still lacking for effectively improving the critical parameter of sustaining current (IH). Traditional layout designs (such as simple ring or interdigital structures combined with uniform short-circuit points) result in uneven current distribution during conduction, leading to a low current threshold required to maintain conduction and poor device anti-interference capabilities. Therefore, developing a thyristor cathode structure with composite gradient short-circuit points and its fabrication method can significantly improve the thyristor's IH parameter and enhance its operational stability, possessing significant engineering application value. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of existing technologies and provide a thyristor cathode structure with a composite gradient short-circuit point and its fabrication method. This invention achieves precise control over the internal current path and carrier distribution of the device in the on-state by synergistically optimizing the finger geometry of the cathode emitter and the composite gradient distribution of the short-circuit point. While ensuring good turn-on performance, it significantly improves the holding current of the thyristor, thereby enhancing the device's resistance to false triggering and operational stability.

[0006] To achieve the above objectives, the present invention provides the following technical solution: A thyristor cathode structure with a composite gradient short-circuit point includes: N-type semiconductor base region; A P-type semiconductor base region is formed on the upper surface of the N-type semiconductor base region; Multiple cathodes N + The regions are regularly arranged on the upper surface of the P-type semiconductor base region; Multiple cathode short-circuit point regions with composite gradient characteristics are distributed in the cathode N. + Between districts; An insulating dielectric layer covers the surface of the silicon wafer, in which contact holes are formed for defining the center gate, amplification gate, cathode emitter, and short-circuit point; A central gate metal electrode, an amplifying gate metal electrode, and a cathode emitter metal electrode are formed on the insulating dielectric layer and electrically connected to the corresponding area below through the contact hole.

[0007] A method for fabricating a thyristor cathode structure with a composite gradient short-circuit point includes the following steps: S1: Provide an N-type semiconductor base region, and form a P-type semiconductor base region on the upper surface of the N-type semiconductor base region by a diffusion process; S2: Multiple regularly arranged cathodes N are formed on the upper surface of the P-type semiconductor base region through selective diffusion or ion implantation processes. + The region and the distribution in the cathode N +Multiple cathode short-circuit point regions with composite gradient characteristics between zones; S3: An insulating dielectric layer is formed on the silicon wafer surface after step S2, and contact holes for defining the center gate, amplification gate, cathode emitter and short circuit point are opened in the insulating dielectric layer through photolithography and etching processes. S4: Deposit a metal layer on the silicon wafer surface after the contact hole is made, and pattern the metal layer through photolithography and etching processes to form mutually isolated center gate metal electrode, amplification gate metal electrode and cathode emitter metal electrode.

[0008] More preferably, the layout of the cathode emitter metal electrode is composed of a plurality of emitter units radially distributed around the central gate; each emitter unit includes at least one radially extending main finger and at least two secondary fingers respectively connected to the end of the main finger and extending to both sides, the width W1 of the main finger and the width W2 of the secondary fingers satisfy W1:W2=1.2:1 to 2.5:1, and the length L1 of the main finger and the length L2 of the secondary fingers satisfy L1:L2=0.6:1 to 1.5:1; one end of the main finger of the emitter unit extends into the annular region below the amplification gate metal electrode on the layout, and the two are completely isolated by the insulating dielectric layer and have no electrical connection; The cathode short-circuit point region with composite gradient characteristics also has dual gradient characteristics: its geometric distribution density gradually increases from the inner region near the central gate to the outer edge region away from the central gate; and the peak concentration of P-type doping inside it also gradually increases from the inner region to the outer edge region.

[0009] More preferably, in step S2, the geometric distribution density of the cathode short-circuit point region with composite gradient characteristics satisfies the following: the short-circuit point density ρ1 located in the first circular region with radius R1 centered on the center of the central gate, and the short-circuit point density ρ2 located in the second annular region with radius R1 to R2, satisfy ρ1:ρ2=1:1.5 to 1:4, where R2>R1; the P-type doping peak concentration of the cathode short-circuit point region with composite gradient characteristics satisfies the following: the average peak doping concentration C1 of the short-circuit points located in the first circular region, and the average peak doping concentration C2 of the short-circuit points located in the second annular region, satisfy C1:C2=1:1.2 to 1:2.5.

[0010] More preferably, the secondary finger strip has a V-shaped structure, which includes a first segment connected to the end of the main finger strip and a second segment extending outward from the end of the first segment, with the first segment and the second segment forming an angle of 120° to 150°.

[0011] More preferably, in step S4, the layout of the amplified gate metal electrode is a continuous or discontinuous ring located around the central gate metal electrode.

[0012] More preferably, the N-type semiconductor base region in step S1 is a single-crystal silicon wafer prepared by zone melting or Czochralski method, with a resistivity of 40 Ω·cm to 120 Ω·cm and a thickness of 200 μm to 600 μm; the junction depth of the P-type semiconductor base region is 20 μm to 80 μm, and the surface doping concentration is 1 × 10⁻⁶. 17 cm -3 Up to 5×10 18 cm -3 .

[0013] More preferably, the cathode N in step S2 + The junction depth is 10 μm to 30 μm, and the surface doping concentration is 5 × 10⁻⁶. 19 cm -3 Up to 2×10 20 cm -3 The peak concentration range of the P-type doping in the cathode short-circuit point region with composite gradient characteristics is 5 × 10⁻⁶. 17 cm -3 Up to 2×10 19 cm -3 .

[0014] More preferably, step S4 further includes: after forming the metal layer, performing an alloying annealing treatment at a nitrogen or argon protective atmosphere at 350°C to 480°C for 10 to 45 minutes to enable the metal layer to form good ohmic contact with the underlying silicon.

[0015] More preferably, the second segment of the secondary finger strip is further connected to at least one arc-shaped or straight end extension strip extending to both sides.

[0016] The first approach of this invention is to combine the "doping concentration gradient" and "geometric distribution density gradient" of the cathode short-circuit point to form a composite gradient design. In existing technologies, the short-circuit point only serves as a uniformly distributed carrier extraction channel. This invention has found that the carrier extraction demand during turn-off is spatially non-uniform. Near the chip periphery, due to the greater distance from the gate and weaker electric field, the carrier extraction efficiency is low, easily leading to residual current, which is a bottleneck limiting IH (Inductance Homogeneity). Therefore, this invention not only sets a higher density of short-circuit points (geometric gradient) at the periphery, but more importantly, it ensures that the peripheral short-circuit points have a higher P-type doping concentration (concentration gradient). A higher doping concentration means lower contact resistance and a shorter minority carrier lifetime, thus establishing an efficient and rapid "carrier extraction barrier" in the chip periphery at the moment of device turn-off. This forcibly confines the conduction maintenance region to the chip center, significantly increasing the anode current threshold required to maintain the entire device's conduction, i.e., IH.

[0017] The second approach of this invention achieves functional synergy between the "shunting-concentration" finger configuration and the "composite gradient" of short-circuit points. Specifically, the wider main finger creates a current "concentration" effect in the central region near the gate, ensuring the device's turn-on sensitivity and latch-up reliability, which is fundamental for maintaining normal operation. The relatively thinner sub-fingers connected to the ends of the main finger "shunt" the current to a wider cathode region. At this point, the "carrier extraction barrier" formed by the high density and high concentration of short-circuit points in the peripheral region begins to play a crucial role: they efficiently extract minority carriers from the ends and edge regions of the sub-fingers, causing these regions to be the first to exit conduction when the anode current decreases. However, because the current is concentrated below the main finger in the central region and there is a lack of high-concentration short-circuit points, this region can maintain conduction even at lower anode currents, forming a stable "maintenance core region." Only when the anode current decreases further, enough to cause the "maintenance core region" to collapse, will the device turn off. This design, which "forcefully" divides the space into "easy-to-turn-off" and "difficult-to-turn-off" regions through layout structure and doping engineering, makes the device's turn-off behavior more "steep" and controllable, and its IH value is significantly and stably improved due to the presence of the "difficult-to-turn-off" region.

[0018] The mechanism of this invention lies in the fact that the sustaining current IH of a thyristor is essentially the minimum current required to maintain positive feedback within the device. The magnitude of IH is closely related to the carrier concentration, lifetime, and geometry of the current path within the conduction region. This invention artificially constructs a high current density region (center) and a low current density region (edge) on the layout using a "master-slave bar configuration." During turn-off, the low current density region at the edge should be easily turned off, but in traditional structures, incomplete turn-off occurs due to low extraction efficiency. The "composite gradient" introduced in this invention at the short-circuit point, especially the high concentration of doping at the periphery, actively and efficiently extracts carriers from the edge region, enabling rapid and complete turn-off. This active "edge-forced turn-off" behavior completely places the burden of maintaining conduction on the central region. To maintain conduction in the high current density region of the center, a relatively higher anode current is required, ultimately resulting in a significant increase in the macroscopic IH value of the device.

[0019] The present invention has the following beneficial technical effects: (1) Significantly improves the sustaining current (IH): Through the spatial functional synergy of the "shunting-concentration" finger configuration and the short-circuit point "composite gradient" (dual gradient of geometric density and doping concentration), the thyristor chip prepared by the method of the present invention has a significantly improved sustaining current IH compared with the chip using the traditional uniform finger and uniform short-circuit point distribution, which greatly enhances the device's resistance to electromagnetic interference and voltage fluctuation.

[0020] (2) Good balance between turn-on characteristics and stability: This invention improves IH without sacrificing the turn-on performance of the device. The main finger bar in the central region and the low-concentration short-circuit point design ensure sufficient trigger sensitivity and current concentration effect near the gate, ensuring that the device can conduct quickly and reliably, achieving a balance between high stability and good dynamic characteristics.

[0021] (3) Good process compatibility: The technical solution of the present invention is based entirely on the existing thyristor planar manufacturing process. The composite gradient doping of the short-circuit point can be achieved by adjusting the pattern of the ion implantation mask or by using multiple implantation processes. No additional complex process steps are required. It is easy to implement on existing production lines and has the advantages of low cost and strong feasibility. Attached Figure Description

[0022] Figure 1 This is a cross-sectional schematic diagram of the thyristor cathode structure with a composite gradient short-circuit point in Embodiment 1 of the present invention.

[0023] Figure 2 This is a schematic diagram of the planar layout of the thyristor cathode structure with a composite gradient short-circuit point in Embodiment 1 of the present invention.

[0024] The names of the components shown in the diagram are as follows: Figure 1 In the middle, 11—N-type base region (N - ), 12—P-type base region (P), 13—cathode N + Zone 14 – Cathode short-circuit point region with composite gradient characteristics (P) + 15—Insulating dielectric layer (SiO2), 16—Central gate metal, 17—Amplification gate metal, 18—Cathode emitter metal, 19—Anode P + layer.

[0025] Figure 2 In the middle, 21—the cathode short-circuit point region with composite gradient characteristics (P) + ), 22 - central gate metal, 23 - amplification gate metal (ring), 24 - cathode emitter unit (main finger bar), 25 - cathode emitter unit (sub finger bar). The overlapping area between the end of the main finger bar (24) and the amplification gate metal ring (23) is isolated by an insulating dielectric layer and has no contact hole. Detailed Implementation

[0026] Before further describing specific embodiments of the present invention, it should be understood that the scope of protection of the present invention is not limited to the specific embodiments described below; it should also be understood that the terminology used in the embodiments of the present invention is for describing specific embodiments and not for limiting the scope of protection of the present invention. Test methods in the following embodiments that do not specify specific conditions are generally performed under conventional conditions or as recommended by the respective manufacturers.

[0027] When numerical ranges are given in the embodiments, it should be understood that, unless otherwise stated in this invention, both endpoints of each numerical range and any value between the two endpoints may be selected. Unless otherwise defined, all technical and scientific terms used in this invention have the same meaning as commonly understood by those skilled in the art. In addition to the specific methods, apparatus, and materials used in the embodiments, based on the knowledge of those skilled in the art and the description of this invention, any prior art methods, apparatus, and materials similar to or identical to those described in the embodiments of this invention may be used to implement this invention.

[0028] Unless otherwise stated, the test methods, detection methods and preparation methods disclosed in this invention all adopt conventional techniques in this technical field.

[0029] Example 1 This embodiment provides a method for fabricating a thyristor cathode structure with a composite gradient short-circuit point, the specific steps of which are as follows: S1: An N-type zone-melted single-crystal silicon wafer with a resistivity of 60 Ω·cm and a thickness of 400 μm was selected as the N-type base region 11. After cleaning, boron diffusion was performed at 1200℃ to form a junction with a depth of 50 μm and a surface doping concentration of 2 × 10⁻⁶ on the upper surface of the N-type base region 11. 18 cm -3 The P-type base region 12.

[0030] S2: The cathode N is defined by photolithography. + The diagram shows the regions 13 and the short-circuit point region. Then, selective phosphorus diffusion was performed to form a junction with a depth of 20 μm and a surface doping concentration of 1 × 10⁻⁶ at 1050 °C. 20 cm -3 Multiple cathodes N + Region 13. Simultaneously, a cathode short-circuit point region 14 (corresponding to) with composite gradient characteristics is formed through a stepwise ion implantation process. Figure 2 (21) First, using the first mask, perform a basic boron ion implantation on the short-circuit points of the entire chip area, with an implantation dose of 5 × 10⁻⁶. 14 cm -2 The energy was 60 keV; then, using a second mask, a second boron ion implantation was performed only on the area outside the chip center with a radius R1 = 3 mm, and the implantation dose was 8 × 10⁻⁶.14 cm -2 The energy is 80 keV; finally, all short-circuit point regions are activated by rapid thermal annealing. This forms a cathode short-circuit point region 14 with composite gradient characteristics (corresponding to...). Figure 2 In section 21), the geometric distribution density is sparser inside and denser outside (area ratio increases from 3% to 12%), and the doping peak concentration is lower inside and higher outside (from approximately 8 × 10⁻⁶). 18 cm -3 Increased to approximately 2×10 19 cm -3 ), to achieve composite gradients.

[0031] S3: A 1 μm thick silicon dioxide layer is grown on the silicon wafer surface as an insulating dielectric layer 15 by thermal oxidation. Subsequently, photolithography and buffered oxide etch (BOE) wet etching are performed to create the insulating dielectric layer 15 for defining the central gate metal 16, the amplifying gate metal 17, the cathode emitter metal 18, and the cathode short-circuit point region 14 with composite gradient characteristics (corresponding to...). Figure 2 The contact hole in (21) is provided; however, no contact hole is provided at the corresponding position where the main finger strip 24 extends to the area below the amplification gate metal ring 23, so as to ensure that the subsequent metal layer is isolated by the insulating dielectric layer 15 in this area.

[0032] S4: On the silicon wafer surface after the contact holes are formed, a 4 μm thick aluminum-silicon alloy (Al-1%Si) metal layer is deposited by magnetron sputtering. Then, photolithography and reactive ion etching (RIE) are performed to pattern the metal layer, forming mutually isolated central gate metal electrodes 16 (corresponding to...). Figure 2 22), Amplifying gate metal electrode 17 (corresponding to) Figure 2 23) and cathode emitter metal electrode 18. The metal at the end of the main finger strip 24 extends below the amplification gate metal ring 23, but is separated from the amplification gate metal electrode 17 by the insulating dielectric layer 15, and the two are not electrically connected. The layout of the cathode structure is as follows: Figure 2 As shown, the emitter unit consists of 12 emitter cells evenly distributed around the central gate metal 22. Each emitter cell includes a radially extending main finger 24 and two symmetrically connected V-shaped sub-fingers 25 extending to both sides from the ends of the main finger 24, with an included angle of 135° between the two segments of the sub-fingers 25. The width W1 of the main finger 24 is 80 μm, and the length L1 is 800 μm; the width W2 of the sub-fingers 25 is 50 μm, and the length L2 is 800 μm. At this point, W1:W2 = 1.6:1, and L1:L2 = 1:1. Finally, the metallized silicon wafer is annealed at 420°C in a nitrogen atmosphere for 20 minutes to form good ohmic contacts. In subsequent processes, an anode P will be formed on the back side of the silicon wafer. + Floor 19 (e.g.) Figure 1 (As shown).

[0033] Example 2 The thyristor cathode structure with a composite gradient short-circuit point in this embodiment and its fabrication method are basically the same as in Embodiment 1, except for the layout parameters. In step S4, the number of emitter units is 8, the width W1 of the main finger strip 24 is 100 μm, and the length L1 is 700 μm; the width W2 of the secondary finger strip 25 is 40 μm, and the length L2 is 900 μm. At this time, W1:W2=2.5:1, L1:L2≈0.78:1. The cathode short-circuit point region 14 with composite gradient characteristics (corresponding to...) Figure 2 The dual gradient parameters of (21) are the same as in Example 1. As in Example 1, the end of the main finger strip 24 extends below the amplification gate metal ring 23 but is electrically isolated from the amplification gate metal electrode 17 by the insulating dielectric layer 15.

[0034] Example 3 The preparation method in this embodiment is basically the same as that in Example 1, the only difference being the cathode short-circuit point region 14 (corresponding to) which has composite gradient characteristics. Figure 2 The dual gradient parameters of (21) are used. In step S2, the injection area of ​​the second mask is adjusted to be outside the radius R1 = 2.5 mm, and the injection dose is increased to 1 × 10⁻⁶. 15 cm -2 This results in a peak doping concentration of approximately 3 × 10⁻⁶ at the peripheral short-circuit point. 19 cm -3 The internal and external concentration ratio C1:C2 is close to 1:2.5. The finger strip configuration parameters (main finger strip 24 and sub-finger strip 25) are the same as in Example 1. As in Example 1, the end of the main finger strip 24 extends below the amplification gate metal ring 23, but is electrically isolated from the amplification gate metal electrode 17 by an insulating dielectric layer 15.

[0035] Comparative Example 1 This comparative example uses the exact same process steps as Example 1, but the cathode structure adopts a conventional uniform-width finger bar structure. Specifically, the cathode structure layout consists of 12 straight fingers, each 80 μm wide and 1200 μm long, radiating outward from the central gate metal 22, without distinguishing between the main fingers 24 and the sub-fingers 25. Meanwhile, the cathode short-circuit point region is located throughout the entire cathode N... + The doping concentration is uniformly distributed within region 13, with each region accounting for 7% of the area and having a peak doping concentration of 1×10⁻⁶. 19 cm -3 It does not have composite gradient characteristics. Similar to Example 1, the end of the finger extends below the amplification gate metal ring 23, but is electrically isolated from the amplification gate metal electrode 17 by an insulating dielectric layer 15.

[0036] Comparative Example 2 This comparative example uses the exact same process steps as Example 1, and employs the same main finger strip 24 and sub-finger strip 25 structure as Example 1 (W1=80μm, W2=50μm, L1=800μm, L2=800μm). (Same as Example 1, the end of the main finger strip 24 extends below the amplification gate metal ring 23, but is electrically isolated from the amplification gate metal electrode 17 by an insulating dielectric layer 15.) However, the cathode short-circuit point region is located throughout the entire cathode N... + The doping concentration is uniformly distributed within region 13, with each region accounting for 7% of the area and having a peak doping concentration of 1×10⁻⁶. 19 cm -3 This comparative example does not possess composite gradient characteristics and is used to illustrate the technical effect of using the finger strip configuration alone without combining it with the composite gradient at the short-circuit point.

[0037] Comparative Example 3 This comparative example uses the exact same process steps as Example 1, and employs the same cathode short-circuit point region 14 with a composite gradient as in Example 1 (corresponding to...). Figure 2 (21) Dual gradient distribution, but the cathode structure layout adopts the uniform width linear finger bar described in Comparative Example 1. This comparative example is used to illustrate the technical effect of using the short-circuit point composite gradient alone without combining the main and secondary finger bar configurations. Similar to Example 1, the finger bar ends extend below the amplification gate metal ring 23 but are electrically isolated from the amplification gate metal electrode 17 by an insulating dielectric layer 15.

[0038] Performance testing Performance testing was conducted according to IEC 60747-6 standard. Specifically, a Tektronix 371B transistor curve tracer was used at room temperature (25°C). First, a positive pulse current with a pulse width of 100 μs and an amplitude of 50 mA was applied between the gate and cathode to turn on the device under test (DUT). Then, the gate signal was removed. Next, the voltage between the anode and cathode was slowly increased in a linear ramp manner (scan rate approximately 10 V / s) while monitoring the anode current. The critical current value before the anode current suddenly drops from the stable on-state to the off-state was recorded; this value is the holding current IH. Each sample was measured 5 times, and the average value was taken.

[0039] Table 1. Test results of sustaining current (IH) of thyristor chip cathode structures in different embodiments and comparative examples. Performance Testing Description: The sustaining current (IH) of the thyristor cathode structures with composite gradient short-circuit points prepared in Examples 1-3 and Comparative Examples 1-3 above can be tested according to the semiconductor device testing methods commonly used in the art. The test conditions are as follows: at room temperature (25°C), using a transistor curve tracer, a pulse current sufficient to trigger the device to conduct is applied to the gate and then removed. Then, the voltage between the anode and cathode is slowly increased, and the change in anode current is monitored. When the anode current begins to suddenly drop from a stable conducting state to a turning-off state, the critical current value before this drop is the sustaining current IH. The test results qualitatively show that the sustaining current IH values ​​of Examples 1-3 are significantly higher than those of Comparative Examples 1-3. Specifically, compared with the conventional structure of Comparative Example 1, the IH of Example 1 is increased by more than 50%; compared with Examples 2 and 3, which only have a single feature, the IH value of Example 1, which has both a main and sub-finger configuration and a composite gradient, is also significantly higher. This directly proves that the various technical features of the present invention have a synergistic effect, achieving unexpected technical results.

[0040] In summary, this invention, through a unique cathode structure design, particularly by functionally coupling the "shunting-concentration" finger strip configuration with the composite gradient at the short-circuit point, achieves precise spatial control of the internal current distribution and carrier extraction behavior of the thyristor. While ensuring the device's turn-on performance, it significantly improves the holding current IH, enhancing the device's anti-interference capability and operational stability.

[0041] The above description is merely a preferred embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A method for fabricating a thyristor cathode structure with a composite gradient short-circuit point, characterized in that, Includes the following steps: S1: Provide an N-type semiconductor base region, and form a P-type semiconductor base region on the upper surface of the N-type semiconductor base region by a diffusion process; S2: Multiple regularly arranged cathodes N are formed on the upper surface of the P-type semiconductor base region through selective diffusion or ion implantation processes. + The region and the distribution in the cathode N + Multiple cathode short-circuit point areas between zones; S3: An insulating dielectric layer is formed on the silicon wafer surface after step S2, and contact holes for defining the center gate, amplification gate, cathode emitter and short circuit point are opened in the insulating dielectric layer through photolithography and etching processes. S4: Deposit a metal layer on the silicon wafer surface after the contact hole is made, and pattern the metal layer through photolithography and etching processes to form mutually isolated center gate metal electrode, amplification gate metal electrode and cathode emitter metal electrode.

2. The preparation method according to claim 1, characterized in that: The layout of the cathode-emitter metal electrode consists of multiple emitter units radially distributed around the central gate. Each emitter unit includes at least one radially extending main finger and at least two secondary fingers connected to the ends of the main finger and extending to both sides. The width W1 of the main finger and the width W2 of the secondary fingers satisfy W1:W2=1.2:1 to 2.5:1, and the length L1 of the main finger and the length L2 of the secondary fingers satisfy L1:L2=0.6:1 to 1.5:

1. One end of the main finger extends on the layout to below the annular region of the amplification gate metal electrode, and the two are electrically isolated by an insulating dielectric layer. The cathode short-circuit point region has dual gradient characteristics: its geometric distribution density gradually increases from the inner region near the central gate to the outer edge region away from the central gate; and the peak concentration of P-type doping inside it also gradually increases from the inner region to the outer edge region.

3. The preparation method according to claim 2, characterized in that: In step S2, the geometric distribution density of the cathode short-circuit point region satisfies the following: the short-circuit point density ρ1 in the first circular region with radius R1 centered on the center of the central gate, and the short-circuit point density ρ2 in the second annular region with radius R1 to R2, satisfy ρ1:ρ2=1:1.5 to 1:4, where R2>R1; the P-type doping peak concentration of the cathode short-circuit point region satisfies the following: the average peak doping concentration C1 of the short-circuit points in the first circular region, and the average peak doping concentration C2 of the short-circuit points in the second annular region, satisfy C1:C2=1:1.2 to 1:2.

5.

4. The preparation method according to claim 2, characterized in that: The secondary finger bar has a V-shaped structure, which includes a first straight segment connected to the end of the main finger bar and a second straight segment extending outward from the end of the first segment, with the first segment and the second segment forming an angle of 120° to 150°.

5. The preparation method according to claim 2, characterized in that: In step S4, the layout of the amplified gate metal electrode is a continuous or discontinuous ring located around the central gate metal electrode.

6. The preparation method according to claim 1, characterized in that: The N-type semiconductor base region in step S1 is a single-crystal silicon wafer prepared by zone melting or Czochralski method, with a resistivity of 40 Ω·cm to 120 Ω·cm and a thickness of 200 μm to 600 μm; the junction depth of the P-type semiconductor base region is 20 μm to 80 μm, and the surface doping concentration is 1 × 10⁻⁶. 17 cm -3 Up to 5×10 18 cm -3 .

7. The preparation method according to claim 1, characterized in that: Cathode N in step S2 + The junction depth is 10 μm to 30 μm, and the surface doping concentration is 5 × 10⁻⁶. 19 cm -3 Up to 2×10 20 cm -3 The peak concentration of P-type doping in the cathode short-circuit region ranges from 5 × 10⁻⁶. 17 cm -3 Up to 5×10 19 cm -3 Furthermore, the peak concentration of the P-type doping gradually increases from the inside to the outside.

8. The preparation method according to claim 1, characterized in that: Step S4 further includes: after forming the metal layer, performing an alloying annealing treatment at a nitrogen or argon protective atmosphere of 350°C to 480°C for 10 to 45 minutes to enable the metal layer to form good ohmic contact with the underlying silicon.

9. A thyristor chip, characterized in that: This includes cathode structures prepared using the method described in any one of claims 1 to 8.

Images